PCB Design and Module Placement Guide 1. Introduction The WT8266-S1 module is designed to be soldered to a host PCB. The placement of the module and antenna needs to adhere to our guidelines, in order to optimize the RF performance of the final product. This application note describes the recommended placement of the antenna on a host board to ensure optimal RF performance. 2. Module Placement The PCB antenna used on WT8266-S1 is a Meandered Inverted F Antenna (MIFA) for the 2.4G Wi-Fi band with an antenna gain of 1 dBi. Figure 1 shows six placement options that are commonly used; option 1 is used as a reference, and the measurements results show that option 2 and 3 have the best performances, while the other options are sub-optimal. / 2016.06 17 WT8266-S1
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PCB Design and Module Placement
Guide1. Introduction
The WT8266-S1 module is designed to be soldered to a host PCB. The placement of the module and antenna needs to adhere to our guidelines, in order to optimize the RF performance of the final product. This application note describes the recommended placement of the antenna on a host board to ensure optimal RF performance.
2. Module PlacementThe PCB antenna used on WT8266-S1 is a Meandered Inverted F Antenna (MIFA) for the 2.4G Wi-Fi band with an antenna gain of 1 dBi. Figure 1 shows six placement options that are commonly used; option 1 is used as a reference, and the measurements results show that option 2 and 3 have the best performances, while the other options are sub-optimal.
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WT8266-S1
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Figure 1.PCB Antenna Placement Options
↑Option 1. No host board under the module
↑Option 2. Placing at the edge with the antenna outside of the host board
↑Option 3. Placing at the edge with clearance area
↑Option 4. Placing at the edge with no copper trace below the antenna
↑Option 5. Placing in the center with clearance area
↑Option 6. Placing in the center with no clearance area
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3. Test ResultsWi-Fi transmit power and EVM parameters were measured for different channels of 802.11n OFDM (MCS1-7) to verify the RF performance of the PCB antenna in different locations. Higher power and lower EVM values indicate better signal quality.
Figure 2. Wi-Fi Power Values for Six Placement Options
• Placement options 1, 2 and 3 show basically unaffected RF performance as the antenna faces outward exposed to open space. It is recommended to provide a clearance area of at least 5.0 mm around the antenna in each direction.
• If the PCB antenna has to be mounted onto the host board, it is recommended to choose option 4 with no copper plane below the antenna, despite some loss of the RF performance.
• Placement option 6 delivers the worst RF performance as the transmission and reception of the RF signal is blocked by the host board.
4. Filtering and Noise ReductionA wireless communication chipset relies on accurate clock signals and a reliable power supply to function properly. Filtering and noise reduction techniques must be applied to the host PCB to ensure optimal power supply characteristics. It is recommended that the following guidelines be followed when designing the host PCB:
• Filter capacitors: A filter capacitor can be used to eliminate noise (low frequency) from the power supply section. The recommended value is 10uF or higher and the capacitor must be placed physically close to the regulator chip. Please consult the datasheet of the regulator device for the optimum value.
• Bypass capacitor: Critical for noise reduction, a bypass capacitor provides a low impedance path for high frequency variations on the power rails. Using multiple bypass capacitors is generally recommended. WT8266-S1 contains internal capacitors across the power rails and therefore, an external low-ESR bypass capacitor of over 10uF should suffice. Note that it must be placed as close to the module power pins as possible.
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• Critical traces such as reset line must be kept away from other signal traces by at least about 3 times the trace width to avoid false triggering and glitches. Routing reset trace close to a fixed-voltage plane such as ground is a good design practice.
• Trace width: It is recommended to route wider traces for the power net. WT8266-S1can draw significant amount of current during operation at full power and data rate.
5. Routing Peripheral Signal TracesIn this application note, the term signal trace refers to any trace carrying signals to/from digital peripherals connected to WT8266-S1. The module contains high speed peripheral interface such as HSPI and I2S. It is important to route the traces properly to control distortion and ensure signal integrity.
• Cross talk: Positioning signal traces very closely may cause inductive and capacitive coupling. A minimum trace separation distance of 2 times the trace width is recommended.For critical system signals such as reset and external interrupt lines, a minimum trace separation of 3 times the trace width is recommended.
• Trace length: The length of high frequency traces must be kept minimum to reduce their effect on other traces and also to minimize noise pick-up. It is good practice to keep the length of traces on a data bus approximately equal. For example, the SCK, MOSI and MISO lines of the SPI interface should be approximately equal in length.
• Trace bends: In case of right angled bends (especially in clock traces), the bend must be smoothened out over two 45o bends (or smoother). This is done in order to minimize signal reflection that occurs with 90o trace bends. Please refer to Figure 4 below for recommended trace routing.
Figure 4. Trace Bends
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• Vias: Vias on high speed clock traces should generally be avoided if possible.
• Return path: Return path of all signal traces should be kept as short as possible to realize a low EMI design.
• Switching noise control: WT8266-S1 has high speed GPIO and peripheral interfaceswhich can create severe switching noise. In applications where power consumption and EMI profile are important, it is recommended that a series resistor of 10-100 ohms be placed with digital I/O. This limits overshoot during switching and results in smoother transitions. A series resistor may also protect from ESD to some extents.
6. Ground Plane• Good practices: High speed signal traces must be routed over ground planes to minimize size of return loops in the host PCB. This ensures minimal radiation of electromagnetic noise from the PCB. Also, it is good practice to have large, uninterrupted ground planes on one layer of the host PCB. The pad on the bottom of WT8266-S1 must be provided sufficient plane contact for proper dissipation.
• Dual ground planes: If your design contains analog components or ADCs, it is recommended that the ground plane for digital and analog components be kept separate. This will ensure noise-free analog signal input for the internal ADC as well. However, note that the digital ground and analog ground should not be overlapped or interconnected directly. Both the ground planes should have a dedicated trace to the main power supply block ground for optimal grounding.
• Split ground planes: Split ground planes do not severely affect noise or EMI characteristics of the host PCB. However, running a trace over a split, unrelated ground plane creates large current loops and may result in EMI.
7. ConclusionIt is recommended that the module is mounted on the edge of the host PCB with the antenna exposed to free space. It is permitted for PCB material to be below the antenna structure of the module as long as no copper traces or planes are on the host PCB in that area. For best performance, place the module on the host PCB as shown in placement options 2 and 3 in Chapter 2.
These placement practices, along with good routing practices result in robust, reliable and effective system design with the WT8266-S1 module.
