ETAPS 2008 Budapest, Hungary April 6, 2008

Policies of System Level Pipeline Modeling

Ed HarcourtDept. Mathematics, Computer Science,

and StatisticsSt.Lawrence University

Workshop on Generative TechnologiesETAPS 2008,The European Conference on Theory and Practice of SoftwareBudapest, HungaryApril 2008

ETAPS 2008 Budapest, Hungary April 6, 2008

ETAPS 2008 Budapest, Hungary April 6, 2008

Overview

• Hardware Description Languages• SystemC, Briefly• Review Hardware Pipelining• Pipeline Policies• Reusable pipeline policy classes• Conclusions future work

ETAPS 2008 Budapest, Hungary April 6, 2008

Language Based Design• Hardware Description Languages (HDLs)• Verilog, VHDL• Discrete event simulation semantics• Circuit complexity growing exponentially• Poor abstraction mechanisms• System Design Languages

– SystemC, SystemVerilogHuman Spec

Architectural

RTL

Modeling gap[Sharad Malik]

SystemC enables …

Generic programmingGenerative programmingEmbedded DSLs

ETAPS 2008 Budapest, Hungary April 6, 2008

SystemC• C++ Library

– Block Structure, Ports– HW data types– Discrete Event Simulator– Communication/Concurrency

class Stage : public sc_module {public: sc_in<int> in; sc_out<int> out; Stage() { SC_METHOD(process); }

void process() { int v = in.read(); int tmp = f(v); out.write(tmp); }};

Stage2

Stage1

in

out

in

out

ETAPS 2008 Budapest, Hungary April 6, 2008

Hardware Pipelining2x2 + 4x - 7

Stage<F1> s1; Stage<F2> s2; Stage<F3> s3;Pipeline p = s1 >> s2 >> s3;

Human Spec

Architectural

RTL

321

3

2

21

pipeline

7.

4.

2.

sss

xxs

xxxs

xxs

ETAPS 2008 Budapest, Hungary April 6, 2008

Complex Pipelines

s1 s2 s3

Pipeline p1 = s1 >> s2 >> s3 >> s3;

Pipeline p2 = s1 >> s2 >> s3*2;

Pipeline p3 = s1 >> s2 >> s3 >> s1 >> s3*2 >> s1 >> s2;

p3 t1 t2 t3 t4 t5 t6 t7 t8

s1 X X X

s2 X X

s3 X X X

c1 c2 c3 c4

ETAPS 2008 Budapest, Hungary April 6, 2008

Policies for Modeling Pipelines

• Properties of Pipelines– Transaction– Route– Concurrency model– Communication model

• Properties of Stages – Function– Delay model

s1 s2 s3

ETAPS 2008 Budapest, Hungary April 6, 2008

class Stage1 : public sc_module {public: sc_fifo_in<Transaction *> in; sc_fifo_out<Transaction *> out;

Stage() { SC_THREAD(process); }

void process() { while (1) { Transaction * t = in.read(); t->data = t->data + 2 * sqr(t->orig); ::wait(1, SC_NS); t->advance(); out.write(t); } }};

Policies for Stages

s1 s2 s3

Communication

Concurrency

FunctionDelay Model

ETAPS 2008 Budapest, Hungary April 6, 2008

Generic Stagetemplate <class Transaction, class Function, class DelayModel, class PortInterface, class ConcurrencyModel>class Stage : public sc_module, public Function, public DelayModel, public PortInterface, public RunInterface {

Stage() { SC_THREAD(process); }

void run() { Transaction * t = in.read(); t->data = f(t->data); delay(1); t->advance(); out.write(t); } void process() { ConcurrencyModel::run(this); }};

ETAPS 2008 Budapest, Hungary April 6, 2008

Example Policy Classestemplate <typename T>struct Transaction { T data; void advance() { curr++; } private: static Route *r; Route::iterator curr;};

template<typename T>struct S1Func { static inline T f(T p) { … } };

struct TimedPolicy { static void delay(int x) { wait(x, SC_NS); }};struct UntimedPolicy { static void delay(int) { }};

template< class Transaction, template <class> class InPort, template <class> class OutPort >struct PortInterface { InPort<Transaction *> in; OutPort<Transaction *> out; };

struct Threading { static void run( RunInterface *r) { while(1) r->run(); }};

struct Method { static void run( RunInterface *r) { r->run(); }};

ETAPS 2008 Budapest, Hungary April 6, 2008

Controllers

• Transaction routers• Transactions keep track of location• Controllers have

– arbitrary number input/output ports– routing table

• Route transactions to next stage

s1 s2 s3c1 c2 c3 c4

ETAPS 2008 Budapest, Hungary April 6, 2008

ElaborationPipeline p3 = s1 >> s2 >> s3 >> s1 >> s3*2 >> s1 >> s2;

s1 s2 s3c1 c2 c3 c4

Elaboration

• Depth-first the AST for the pipeline expression• If encounter a new stage

• Instantiate stage• Instantiate controllers if necessary• Instantiate channels (FIFOs or wires), update map

• If stage is already instantiated• Instantiate channel, update map

ETAPS 2008 Budapest, Hungary April 6, 2008

Putting it all togethertypedef pair<double,double> Data;

typedef Transaction<Data> MyTransaction;

typedef PortInterface< MyTransaction, sc_fifo_in, sc_fifo_out> FIFOInterface;

Stage<MyTransaction, S1Func<Data>, TimedPolicy, FIFOInterface, Threading> s1;

Stage<MyTransaction, S2Func<Data>, TimedPolicy, FIFOInterface, Threading> s2;

Stage<MyTransaction, S3Func<Data>, TimedPolicy, FIFOInterface, Threading> s3;

Pipeline p = s1 >> s2 >> s3*3 >> s1 >> s3;

ETAPS 2008 Budapest, Hungary April 6, 2008

Conclusions and Future Work

• Generic/Generative programming +– Modeling gap

• C++ expertise• Prototype more complex pipelines• Use lambda library for function• Beef up the pipeline expression language

– Handle dynamic pipelines– Multi-function pipelines

• Lots of clean up – redundant template parameters– More compile time genericity