EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ …€¦ · UG-884...

EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide

UG-884 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the AD7770, AD7771, and AD7779 8-Channel, 24-Bit, Simultaneous

Sampling, Sigma-Delta ADCs with Power Scaling

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. B | Page 1 of 32

FEATURES Full featured evaluation board for the AD7770, AD7771, and

AD7779 PC control in conjunction with the Analog Devices, Inc.,

SDP, EVAL-SDP-CH1Z PC software control and data analysis Time and frequency domain Standalone hardware capability

ONLINE RESOURCES Evaluation Kit Contents

EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ EVAL-AD7779FMCZ evaluation board

AD777x evaluation software Documents Needed

AD7770, AD7771, and AD7779 data sheet EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/

EVAL-AD7779FMCZ user guide Required Software

AD777x evaluation software

EQUIPMENT NEEDED EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/

EVAL-AD7779FMCZ evaluation board System demonstration platform (SDP)—high speed (SDP-H1)

controller board (EVAL-SDP-CH1Z) DC/AC signal source (Audio Precision or similar) USB cable PC running Windows 7 with USB 2.0 port

An Internet connection may be required on a PC running Windows 8.1 or Windows 10

External 9 V supply (for standalone use)

GENERAL DESCRIPTION The EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ EVAL-AD7779FMCZ evaluation kit features the AD7770, AD7771, and AD7779 24-bit, analog-to-digital converters (ADCs). The board interfaces with the system demonstration platform SDP-H1 controller board (EVAL-SDP-CH1Z). The SDP-H1 controller board supplies power to the EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ evaluation board and also connects to a PC running a Windows® operating system via a USB cable. The AD777x evaluation software fully configures the AD7770, AD7771, and AD7779 device register functionality and provides dc and ac time domain analysis in the form of waveform graphs, histograms, and associated noise analysis for ADC performance evaluation.

The EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ evaluation board allows the user to evaluate the features of the ADC. The user PC software executable controls the AD7770, AD7771, and AD7779 over the USB cable through the SDP-H1 controller board.

Full specifications for the AD7770, AD7771, or AD7779 are available in the AD7770, AD7771, or AD7779 data sheets and should be consulted in conjunction with this user guide when working with the evaluation board.

http://www.analog.com/AD7770?doc=EVAL-AD7770FMCZ-7771FMCZ-7779FMCZ-UG-884.pdf







http://www.analog.com/EVAL-AD7770FMCZ?doc=EVAL-AD7770FMCZ-7771FMCZ-7779FMCZ-UG-884.pdf



ftp://ftp.analog.com/pub/evalcd/ad777x/











http://www.analog.com/eval-SDP-h1?doc=EVAL-AD7770FMCZ-7771FMCZ-7779FMCZ-UG-884.pdf
































http://www.analog.com

http://www.analog.com/SDP?doc=EVAL-AD7770FMCZ-7771FMCZ-7779FMCZ-UG-884.pdf


UG-884 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide

Rev. B | Page 2 of 32

TABLE OF CONTENTS Features .............................................................................................. 1

Online Resources .............................................................................. 1

Equipment Needed ........................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Evaluation Board Photograph ......................................................... 3

Evaluation Board Quick Start Guide ............................................. 4

Analog Inputs and Front-End Circuit ........................................... 5

Evaluation Board Hardware ............................................................ 6

Device Description ....................................................................... 6

Hardware Link Options ............................................................... 6

Serial Configuration Interface .................................................... 9

Evaluation Board Software ............................................................ 10

Software Installation .................................................................. 10

Launching the Software ............................................................. 11

Software Operation ........................................................................ 12

Overview of the Main Window ................................................ 12

Configuration Tab ...................................................................... 12

Waveform Tab ............................................................................. 14

Analysis Tab ................................................................................ 15

SAR Tab ....................................................................................... 17

Register Map Tab ........................................................................ 19

Exiting the Software ................................................................... 19

Evaluation Board Schematics and Layout ................................... 20

Ordering Information .................................................................... 30

Bill of Materials ........................................................................... 30

REVISION HISTORY 7/2017—Rev. A to Rev. B Added AD7771 ................................................................... Universal Added EVAL-AD7771FMCZ ............................................ Universal Change to Table 5 ........................................................................... 30 9/2016—Rev. 0 to Rev. A Added EVAL-AD7770FMCZ ............................................ Universal Changes to Figure 2 .......................................................................... 4 Changes to Device Description Section ........................................ 6 Changes to Software Installation Section .................................... 10 Added Figure 5; Renumbered Sequentially ................................ 10 Changes to Overview of the Main Window Section and SD Input Configuration Pop-Up Buttons Section ............................ 12 Changes to SAR Configuration Section ...................................... 17 2/2016—Revision 0: Initial Version

EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide UG-884


EVALUATION BOARD PHOTOGRAPH

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Figure 1. EVAL-AD7770FMCZ Evaluation Board with SDP-H1 Controller Board





EVALUATION BOARD QUICK START GUIDE To begin using the evaluation board, take the following steps:

1. Ensure that the evaluation board is disconnected from the USB port of the PC. Install the AD777x evaluation software from the CD included in the evaluation board kit. Restart the PC after the software installation is complete. (For complete software installation instructions, see the Software Installation section.)

2. Connect the SDP-H1 board to the evaluation board: CON J4 of the SDP-H1 board adapts to the receiving socket on the EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ EVAL-AD7779FMCZ printed circuit board (PCB).

3. Ensure that the boards are connected firmly together. 4. By default, the power for the evaluation board is supplied

from the SDP-H1 controller board. A number of power options available; see Table 3 for more information.

5. Connect the SDP-H1 board to the PC using the supplied USB cable.

6. Launch the AD777x evaluation software from the Analog Devices subfolder in the Programs menu.

The pin control mode is not directly supported in the Rev. H version of the software.

9V WALL WART, LDO BYPASS OPTIONS

ADR44512.5V REFERENCE

AD777x24-BIT, 8-CHANNEL

SAMPLING ADC

SAR AUX_IN±/–SMB

AINx CONNECTIONSSMB/AC INPUTS

TERMINAL BLOCK DC INPUTS 1355

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Figure 2. Hardware Configuration—Setting Up the EVAL-AD7770FMCZ













ANALOG INPUTS AND FRONT-END CIRCUIT As shown in Figure 2, the AIN0± to AIN7± analog Σ-Δ inputs are available on SMB or terminal block inputs. The AUXIN± inputs to the auxiliary successive approximation register (SAR) converter are available through the SMB inputs.

Figure 2 shows these connectors to the ADC input terminals. Each analog input differential pair has a second-order RC filter option and common-mode option to center the input signal at (AVDD1 + AVSSx)/2. An option is available to place an additional VCM buffer in U8 to add drive strength and also gain, attenuation, or filtering to this VCM signal. Channel 7 has the option to evaluate an external drive amplifier using an amplifier surfboard, to be plugged on J7/J10. The SL3, SL4, SL19, and SL20 solder link options select between applying the AIN±7 analog inputs directly to the RC filter and ADC, or to the surfboard inputs.

The evaluation board includes a buffer (AD8659) connected to AIN±0 and AIN±2, and a multiplexer that can be connected to

the AIN0± to AIN7± Σ-Δ inputs when the SAR is used for redundancy. If this function is required, solder a 0 Ω, 0402 size resistor to the unpopulated resistor footprints (see Figure 17 for more details), and move SL22 and SL23 to Position A.

The default configuration of the board is as follows:

• Connect the input signal from the input terminals through the second-order RC filter (do not populate) to the ADC channels.

• The board accepts ac signals from −1.25 V to +1.25 V. • The ADR441 2.5 V, low noise reference is used by default,

allowing a differential input range of 0 V to 2.5 V on each input.

• No external buffers are populated.


http://www.analog.com/ADR441?doc=EVAL-AD7770FMCZ-7771FMCZ-7779FMCZ-UG-884.pdf



EVALUATION BOARD HARDWARE DEVICE DESCRIPTION The AD7770, AD7771, and AD7779 is an 8-channel, simultaneously sampled, 24-bit, Σ-Δ ADC with an additional diagnostics 12-bit SAR. The AD7770, AD7771, and AD7779 offers one ADC per channel with synchronized sampling.

To cater to application specific ADC power scaling requirements, the user can select either the high resolution mode or low power mode. In high resolution mode, the AD7770 operates at 32 kSPS maximum, the AD7771 operates at 128 kSPS maximum, and the AD7779 operates at 16 kSPS maximum. In low power mode, the AD7770 operates at 8 kSPS maximum, the AD7771 operates at 32 kSPS, and the AD7779 operates at 8 kSPS maximum.

The AD7770, AD7771, and AD7779 also provides a low latency, sinc3 filter for digital filtering. The notches of the digital filter are automatically set to remove harmonics at the sampling frequency and the programmable gain amplifier (PGA) chopping frequency.

The sample rate converter allows the user to fine tune the decimation rate to maintain a number of samples per line cycle for varying input frequencies. Choosing a low output data rate increases the dynamic range, reducing the noise. Decimation rates can be programmed via the AD777x evaluation software.

Embedded analog functionality on each ADC channel eases system design. The AD7770, AD7771, and AD7779 has a fully buffered PGA on each channel to reduce analog input current. The AD7770, AD7771, and AD7779 also has a reference buffer on each channel, with different operation modes to minimize both the input current from the reference and the reference noise.

Full specifications for the AD7770, AD7771, or AD7779 are available in the AD7770, AD7771, or AD7779 data sheets and should be consulted in conjunction with this user guide when working with the evaluation board. Full details on the EVAL-SDP-CH1Z are available on the Analog Devices, Inc., website at http://www.analog.com/eval-SDP-H1.

HARDWARE LINK OPTIONS The default power link options are listed in Table 1, Table 2, and Table 3. The evaluation board can be powered by different sources, as described in Table 1. By default, the supply required for the evaluation board comes from the SDP-H1 controller board. The supply is regulated by the on-board ADP5070 switched mode power supply (SMPS), which generates the dual supply, and the ADP7118 and the ADP7182 low dropout (LDO) regulators reduce noise and generate the low noise, regulated, positive and negative rails.

Table 1. Default Link and Solder Link Options for Power Supply Link No. Default Option Description MAIN_SUPPLY A Unregulated input voltage source selection. Position A: the unregulated supply to the on-board LDOs is taken from the SDP-H1 12 V supply. Position B: the unregulated external supply to the on-board LDOs is taken from the J5 9 V wall wart input

or from the J6 connector. SL1 A IOVDD supply selection. Position A: IOVDD is supplied from the SDP-H1 board. Set to 3.3 V by default. Position B: IOVDD is supplied from ADP7118 3.3 V, precision LDO. Position C: EXT_IOVDD. IOVDD can be supplied from Pin 3 of the J17 terminal block (1.8 V to 3.3 V). The

SDP-H1 only supports 3.3 V logic. If IOVDD is operated below 3.3 V, populate the U6 buffer to avoid electrical problems.

SLP1 A AVDD1 supply selection. Position A: AVDD1 is taken from U14, the ADP7118 LDO. See SLP6 for more options. Position B: AVDD1 is taken from Pin 1 of J3, AVDD1 external supply. SLP2 A AVDD2 supply selection. Position A: AVDD2 is taken from U14, the ADP7118 LDO. See SLP6 for more options. Position B: AVDD2 is taken from Pin 1 of the J17 external source. SLP3 A AVDD4 supply selection. Position A: AVDD4 is taken from U14, the ADP7118 LDO. See SLP6 for more options. Position B: AVDD4 is taken from Pin 2 of the J17 external source. SLP6 A On-board regulated positive rail selection. Position A: 1.65 V. Use this option for dual-supply operation. Position B: 3.3 V. Use this option for single-supply operation. SL24 A Regulated negative rail selection. Position A: AVSSx is taken from U15, the ADP7182 1.65 V LDO. Use this option for dual-supply operation. Position B: AGND. Use this option for single-supply operation. Position C: AVSSx is supplied by Pin 2 of J3, the AVSSx external supply.































http://www.analog.com/ADP5070?doc=EVAL-AD7770FMCZ-7771FMCZ-7779FMCZ-UG-884.pdf















Table 2. AFE Options Link No. Default Option Description SL22 B SAR AUX+ input selection. Position A: AUXIN+ is connected to the on-board multiplexer, which is controlled by the AD7770, AD7771, and

AD7779 GPIO pins. If the multiplexer needs to be used, solder the unpopulated resistor that connects the multiplexer inputs to the Σ-Δ ADC inputs. The evaluation board includes an op amp connected to Channel 0 and Channel 2 of the Σ-Δ ADC.

Position B: direct connection from source to AUXIN+ SMB connector. SL23 B SAR AUX− input selection. Position A: AUXIN– is connected to the on-board multiplexer which is controlled by the

AD7770/AD7771/AD7779 GPIO pins. If the multiplexer needs to be used, solder the unpopulated resistor that connects the multiplexer inputs to the Σ-Δ ADC inputs. The evaluation board includes an op amp connected to Channel 0 and Channel 2 of the Σ-Δ ADC.

Position B: direct connection from source to AUXIN– SMB connector. SL3, SL19 A AIN7+ input driver selection. Position A: direct connection from source to AIN7+. Position B: the J7 and J10 surfboard connection drives the analog inputs. SL4, SL20 A AIN7− input driver selection. Position A: direct connection from source to AIN7−. Position B: the J7 and J10 surfboard connection drives the analog inputs. SLP5 A ADR441 external voltage reference supply selection. Position A: the reference is powered by the ADP5070. Use this option if the board is powered by the on-board

regulators. Position B: the reference is powered by the AVDD1 supply. Use this option if the board is powered by J3 and J17. SL2 A Voltage reference selection. Position A: the ADR441 is used as a voltage reference. Position B: the internal reference of the AD7770, AD7771, and AD7779 is used. Position C: the ADR441 is buffered and used as a reference. Open: an external voltage reference can be connected to the AD7779_REF SMB connector. SL25 A Common-mode voltage output (VCM) selection. Position A: VCM signal to analog front-end signal is AGND. Use this option for dual-supply operation. Position B: the VCM pin is buffered through the U8 output. Position C: the VCM signal to the analog front end is taken directly from the AD7770, AD7771, and AD7779

VCM pin. Open: an external VCM signal can be connected to the AD7779_VCM SMB connector.

Table 3. Digital Connections Link No. Default Option Description K0 to K15 Inserted Digital input/output solder links. These links are inserted by default for unbuffered digital input/output

connection between the controller board and the evaluation board. Remove and insert U6 for buffered digital inputs/outputs.

SL5, SL6 A Data interface format selection. The evaluation software only supports SPI control mode. The default condition is SPI configuration. See the AD7770, AD7771, and AD7779 data sheets for more information.

SL7 Inserted SL7 provides a path between the SYNC_OUT and SYNC_IN pins. The user can provide an asynchronous start signal to the device. On the next MCLK falling edge, the AD7770, AD7771, and AD7779 outputs a SYNC_OUT signal, which is synchronous to the MCLK. This signal synchronizes multiple AD7770, AD7771, and AD7779 devices or resets the SD modulators when phase compensation is used.

SL8 A Clock selection. Position A: the CLK_SEL pin is pulled low and selects the CMOS clock. Position B: the CLK_SEL pin is pulled high and selects the crystal oscillator placed in Y1. To select this

crystal oscillator, remove the SL9 connections and insert R69 and R70. SL9 A CMOS clock input selection: Position A: the on-board CMOS clock is selected (Y2). Position B: J2 can be used to provide an external CMOS clock through the SMB input terminal. Position C: MCLK is supplied from the J1 connector.




























Link No. Default Option Description SL10, SL11, SL13 A GPIO/mode pins. In SPI control mode, Pin 13 to Pin 16 act as GPIOs. See the AD7770, AD7771, and AD7779 data sheets

for more information about additional functionality of these pins for hardware sample rate update source.

Position A: Pin 13 to Pin 16 are connected to the GPIOx net that controls the on-board multiplexer, or can be used to update the SRC (R153 needs to be populated with a 0 Ω resistor).

In pin control mode, Pin 13 to Pin 16 (along with SL12) are used to set up the configuration of the device. For more information on GPIO configuration or pin control mode, see the AD7770, AD7771, and AD7779 data sheets.

Position B: Pin 13 to Pin 16 are connected to IOVDD. Position C: Pin 13 to Pin 16 are connected to DGND. SL12 A Alert/mode pin. In SPI control mode, this pin operates as an alert flag. Position A: error flag. This pin is connected to the J1 and J4 connectors. See SL21 for more details. In pin control mode, this pin becomes the Mode 3 input pin. Used in conjunction with the GPIO/mode

pins to set up the device configuration. See the AD7770, AD7771, and AD7779 data sheets for more details.

Position B: the pin is connected to IOVDD. Position C: the pin is connected to DGND. SL14 A CONVST_SAR selection. In SPI control mode, this link selects the conversion signal source. Position A: the SAR ADC is controlled through the J1 connector. In pin control mode, CONVST_SAR (Pin 17), along with SL5 and SL6, set up the serial interface used to

read back the conversions from the Σ-Δ ADC. Position A: CONVST_SAR (Pin 17) is connected to IOVDD. Position B: CONVST_SAR (Pin 17) is connected to DGND. SL15, SL16, SL17 A SPI data interface lines. In SPI mode configuration, SCLK, SDI, and SDO are used as digital interface pins. Position A: the SPI data interface lines are connected to the FMC-LPC connector. In pin control mode, these pins define the DCLK frequency used to read back the Σ-Δ data through the

DOUT interface. See the AD7770, AD7771, and AD7779 data sheets for more details. Position B: IOVDD. Position C: DGND. SL18 A SPI data interface line. In SPI mode configuration, CS (Pin 18) is used as a digital interface pin.

Position A: CS (Pin 18) is connected to the FMC-LPC connector.

In pin control mode, CS (Pin 18) acts as an alert pin.

Position B: error flag, CS (Pin 18) is connected to the J1 and J4 connectors. See SL21 for more details.

SL21 A Alert connection. Position A: SPI control mode. Position B: pin control mode.















On-Board Connectors

Table 4 provides information about the external connectors on the EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ EVAL-AD7779FMCZ.

Table 4. On-Board Connectors Connector Function J1 General connector for debugging purpose or to

connect an external controller J2 MCLK connector, supplies the external square

wave clock J3 External power supply connector J4 FMC connector J5 External power supply connector J6 External 9 V wall wart connection J7 Channel 7 surfboard evaluation header J8, J9 8-pin connector for input to Channel 0 through

Channel 3 J10 Channel 7 surfboard evaluation header J13, J14 8-pin connector for input to Channel 4 through

Channel 7 J15 External power supply, supplies all rails

independent of LDO supplies

SERIAL CONFIGURATION INTERFACE The AD7770, AD7771, and AD7779 can be configured by the field programmable gate array (FPGA) via a 4-wire SPI interface. Format 0 and Format 1 must be shorted to Position A for this mode to be active.

To operate the EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ EVAL-AD7779FMCZ evaluation board in standalone mode,

1. Connect a power supply (see Table 1 for options). 2. Connect the digital signal processor (DSP),

microcontroller, or FPGA to the J1 interface connector.












EVALUATION BOARD SOFTWARE SOFTWARE INSTALLATION The EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ EVAL-AD7779FMCZ evaluation kit includes software on a CD. Click the setup.exe file from the CD to run the installer. The default installation location for the software is C:\Program Files\Analog Devices\EVAL-AD777xFMCZ.

Install the evaluation software before connecting the evaluation board and SDP-H1 board to the USB port of the PC to ensure that the evaluation system is correctly recognized when it is connected to the PC.

There are two sections to the installation:

• AD777x evaluation software installation • SDP-H1 board drivers installation

Place the software and drivers in the appropriate locations by proceeding through all of the installation steps. Connect the SDP-H1 board to the PC only after the software and drivers are installed. The installer may prompt for permission to make changes to the computer. Click Yes to proceed (see Figure 3).

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Figure 3. User Account Control Permission Dialog Box

A security warning may appear as part of the SDP-H1 controller board driver installation. Click Install to proceed with the installation of the driver (see Figure 4). Without this confirmation, the software cannot operate correctly.

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Figure 4. EVAL-SDP-CB1Z Drivers Installation Confirmation Dialog Box

On a PC running Windows 8.1 or Windows 10, the following window may appear with a prompt to install .NET Framework 3.5. If so, an Internet connection may be required to complete the installation. Click Download and install this feature to complete the installation.

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Figure 5. .NET Framework 3.5 Installation Prompt

After installation is complete, connect the evaluation board to the SDP-H1 controller board. Connect the SDP-H1 controller board via the USB cable to the computer. Follow these steps to verify that the SDP-H1 controller board driver is installed and working correctly:

1. Allow the Found New Hardware Wizard to run. 2. After the drivers are installed, check that the board has

connected correctly by looking at the Device Manager of the PC. The Device Manager can be found by right clicking My Computer, selecting Manage, then Device Manager from the list of System Tools (see Figure 6).

3. The SDP-H1 board appears under ADI Development Tools as Analog Devices SDP-H1 or similar. The installation is complete.

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Figure 6. Device Manager


















LAUNCHING THE SOFTWARE The AD777x evaluation software can be launched when the evaluation board and the SDP-H1 controller board are correctly connected to the PC.

To launch the software, take the following steps:

1. From the Start menu, click Programs, Analog Devices, and then AD777x. The main window of the software then displays (see Figure 7).

2. If the AD7770, AD7771, and AD7779 evaluation system is not connected to the USB port via the SDP-H1 board when the software is launched, the Select Interface… dialog box appears. Connect the evaluation board to the USB port of the PC, wait a few seconds, and then click the green arrows to rescan the USB ports. When the connection is established, click Work Online to proceed.

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Figure 7. Select Interface Dialog Box









SOFTWARE OPERATION

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12

3 4

56

7 89

10 11

12

13

14 15

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Figure 8. Configuration Tab of the AD7779 Evaluation Software

OVERVIEW OF THE MAIN WINDOW The main window of the software displays the significant control buttons and analysis indicators of the evaluation board software (see Figure 8). Depending on which evaluation board is connected to the PC, the software title at the top of the window displays the corresponding device (AD7770, AD7771, or AD7779). The main window is divided into five tabs.

CONFIGURATION TAB General Configuration

The general configuration controls (Label 2 in Figure 8) define the voltage reference, external clock, the output data rate, number of samples, and if the sigma delta (ΣΔ) is read continuously or one time only.

When changing the ODR (SPS) value, click away from the field to process the update. The software programs the sample rate converter (SRC) registers accordingly.

Click SD Sample to acquire samples from the AD7770, AD7771, and AD7779.

ΣΔ ADC Diagnostic Pop-Up Button

The ΣΔ ADC diagnostic pop-up button (Label 3) selects the internal diagnostic inputs from the multiplexer. This input is common for all eight ADCs.

SD Input Configuration Pop-Up Buttons

The SD input configuration pop-up buttons (Label 4) select the ADC gain, enable the diagnostic mux to be the input for the channel (Rx), disable the SD channel, or configure the channel to monitor the voltage reference. Clicking this button selects the SD reference as AVDD3/AVSSx for all channels and the input diagnostic mux as the input for this channel.

Reference Voltage Pop-Up Buttons

The reference voltage pop-up buttons (Label 5) set the reference voltage used for calculating the results in the Waveform and Histogram tabs. The evaluation board has an external 2.5 V ADR441 reference; however, this reference can be bypassed using this pop-up button, and the user can change the external reference voltage value to ensure correct calculation of results in the Waveform and Histogram tabs. Internal reference and reference buffers can be selected using these pop-up buttons. If AVDD3/AVSSx is selected as the reference, the REF (V) value must be updated accordingly.

Regulators Pop-Up Button

The regulators pop-up button (Label 6) allows the user to overdrive the internal LDOs externally, and also provides information about the error detected on the regulators.











SD Errors Pop-up Buttons

The SD errors pop-up buttons (Label 7) show the errors detected on the SD channel.

Gain, Offset, and Phase Pop-up Buttons

The gain, offset, and phase pop-up buttons (Label 8) allow the user to calibrate the offset and gain of each specific SD channel. After the phase compensation updates, click START to apply the change.

START Button

Clicking START (Label 9) generates a pulse on the START pin to reset the internal sinc filter, which ensures that any update on the phase compensation register is correctly applied.

Control Configuration Pop-Up Button

The control configuration pop-up button (Label 10) allows the user to configure features such as the power mode (must be set to high power mode, unless a different clock is provided), the common-mode voltage (VCM), the internal oscillator, and the mode to update the ODR (SRC registers).

It is recommended not to change the SRC load source (Bit 7 in the SRC_UPDATE register, Address 0x064), because SRC_LOAD_ SOURCE can only be enabled via the GUI. Setting Bit 7 of Address 0x064 enables updating SRC via the hardware, which is not supported on the current evaluation board.

The SRC register can be updated manually; however, the update is not reflected in the ODR (SPS) field.

Errors related to the memory map appear in this pop-up.

Error Test Pop-Up Button

The error test pop-up button (Label 11) enables and disables the different error checkers implemented in the AD7770, AD7771, and AD7779.

Data Output Interface Pop-Up Button

The data output interface pop-up button (Label 12) adjusts the DOUT header and driver strength.

SPI Interface Pop-Up Button

The SPI interface pop-up button (Label 13) adjusts the various parameters for the SPI and shows any SPI errors.

SAR Input Pop-Up Button

The SAR input pop-up button (Label 14) allows the user to select the input signal for the SAR ADC.

SAR Power Pop-Up Button

The SAR power pop-up button (Label 15) enables and disables the SAR ADC. If the SAR is disabled, the SAR input mux is disabled as well.

Status Bar

The status bar (Label 16) displays the status of the board and indicates if the board is busy and cannot perform any other action.






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17

1923

18

20

21

22

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Figure 9. Waveform Tab of the AD7779 Evaluation Software

WAVEFORM TAB Waveform Graph and Controls

The data waveform (Label 18) shows each successive sample of the ADC output. The control tools (Label 20) in the graph allow the user to zoom in on the data. Change the scales on the graph by typing values into the x-axis and y-axis.

Analysis Channel

The noise/waveform analysis section (Label 24) and histogram graph show the analysis of the channel selected via the Analysis Ch drop-down box (Label 19).

Channel Selection

The channel selection control (Label 21) allows the user to choose which channels display on the data waveform. It also shows the analog inputs for that channel labeled next to the on and off controls. These controls only affect the display of the channels and do not have any effect on the channel settings in the ADC register map.

Display Units and Axis Controls

Use the Display Units drop-down box (Label 22) to select whether the data graph displays in units of voltages or codes. This affects both the waveform graph and the histogram graph. The axis controls can be switched between dynamic and fixed. When dynamic is selected, the axis automatically adjusts to show the entire range of the ADC results after each batch of samples. When fixed is selected, the user can program the axis ranges manually, and the ranges do not adjust automatically after each sample batch.

If the value is selected as hex, the x-axis of the graph shows the original data (twos complement). Due to the limitations of the software, the number shows as signed 32 bits rather than signed 24 bits.

Save Data

Click Save (Label 23) to save the samples to an external file.

Waveform Analysis

The Waveform Analysis section (Label 24) displays the results of the noise analysis for the selected analysis channel. The rms noise is only applicable with a constant dc value.




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25

26

28

30

29

27

Figure 10. Analysis Tab of the AD7779 Evaluation Software

ANALYSIS TAB FFT Graph and Histogram Selection

Use the FFT/histogram selection box (Label 26) to select between histogram and frequency analysis of the data.

FFT Graph and Controls

The FFT graph (Label 27) shows the fast Fourier transform of the sampled signal. Note that the windows applied is the 7-term Blackman Harris. The frequency is displayed on the x-axis and the amplitude is graphed on the y-axis. Use the control tools (Label 28) to zoom in on the data. Harmonic content can be selected by clicking Show Harmonic Content.

Analysis Channel

The noise/waveform analysis section (Label 29) and the FFT graph show the analysis of the channel selected via the Analysis Ch control (Label 30).

Channel Selection

The Analysis Ch control (Label 30) allows the user to choose which channels display on the data waveform. It also shows the analog inputs for that channel labeled next to the on and off controls. These controls only affect the display of the channels and do not have any effect on the channel settings in the ADC register map.

FFT Window Selection

The FFT window control allows the user to choose which external windowing method to apply to calculate the discrete Fourier transform.




1355

0-01

0

31

32

Figure 11. Histogram Tab of the AD7779 Evaluation Board Software

Histogram and Controls

The data histogram (Label 31) shows the number of times each sample of the ADC output occurs. The control tools in the graph allow the user to zoom in on the data. Change the scales on the graph by typing values into the x-axis and y-axis.

Histogram Analysis

The Histogram Analysis section (Label 32) shows the analysis of the channel selected via the Analysis Ch control.




1355

0-01

1

33

34 3837

39

36

35

Figure 12. SAR Waveform Tab of the AD7779 Evaluation Software

SAR TAB When the SAR ADC is enabled through the SAR power pop-up button (Label 15 in Figure 8), the SAR tab allows the user to sample and analyze data from the SAR ADC.

FFT Graph and Waveform Selection

Use the FFT/waveform selection box (Label 34) to select between waveform and frequency analysis of the data.

Waveform Graph and Controls

The data waveform (Label 35) shows each successive sample of the ADC output. The control tools (Label 36) in the graph allow the user to zoom in on the data. Change the scales on the graph by typing values into the x-axis and y-axis.

Analysis Channel

The noise/waveform analysis section (Label 39) and histogram graph show the analysis of the channel selected via the Analysis Ch control.

SAR Configuration

The SAR configuration controls (Label 37) allow the user to define the number of samples and the through output rate.

SAR Sample

Click SAR Sample (Label 38) to gather samples from the SAR. By clicking SAR Sample, the GUI configures the SPI interface to read back the data from the SAR. When the data is read back, the SPI is configured to read back data from the register map. Before clicking SAR Sample, enable the SAR using the SAR input pop-up button.




1355

0-01

2

42

40

41

Figure 13. SAR FFT Tab of the AD7779 Evaluation Software

FFT Graph and Controls

The FFT graph (Label 40) shows the fast Fourier transform of the sampled signal. The frequency is displayed on the x-axis and the amplitude is graphed on the y-axis. Use the control tools (Label 41) to zoom in on the data. Harmonic content can be selected by clicking Show Harmonic Content.

Analysis Channel

The noise/waveform analysis section (Label 42) and FFT graph show the analysis of the channel selected via the Analysis Ch control.




1355

0-01

3

44

48 49

45

46

47

Figure 14. Register Map and Configuration

REGISTER MAP TAB Register Tree

The register tree (Label 44) shows the full register map in a tree control. Each register is shown. Click the expand button next to each register to show all the bitfields contained within that register.

Register Control

The Register control (Label 45) allows the user to change the individual bits of the register selected in the register tree (Label 44). Click on each bit to toggle the value, or program the register value directly into the number control field on the right.

Bitfields List

The Bitfields list (Label 46) shows all the bitfields of the register selected in the register tree (Label 44). The values can be changed using the drop-down box or by entering a value directly into the number control on the right.

Documentation

The Documentation section (Label 47) contains the documentation for the register and bitfield selected in the register tree (Label 44).

Save and Load

The Save and Load buttons (Label 48 and Label 49) allow the user to save the current register map setting to a file and load the setting from the same file.

EXITING THE SOFTWARE To exit the software, click the close button at the top, right corner of the main window.



EVALUATION BOARD SCHEMATICS AND LAYOUT D

EFA

ULT

SET

TIN

G:

AD

C D

EFA

ULT

SPI

MO

DE

FOR

MA

T0 (S

L5),

FOR

MA

T1(S

L6) =

A, A

SL7

LIN

KS

SYN

C_I

N

DEF

AU

LT IN

TO S

YNC

_OU

T

DEFAULT AD

EFA

ULT

A

MC

LK

MIG

HT

NO

T PL

AC

E

PLA

CE

CLO

CK

AN

D X

TAL

AS

CLO

SE T

O T

HE

PAR

T A

S PO

SSIB

LE

1A

IN0–

2A

IN0+

3A

IN1–

4A

IN1+

5

AVS

S1A

6

AVD

D1A

7

REF

–

8

REF

+

9A

IN2–

10A

IN2+

11A

IN3–

12A

IN3+

13

MO

DE0

14

MO

DE1

15

MO

DE2

16

MO

DE3

17C

ON

VST_

SAR

18C

S

19SC

LK

20SD

I

21SD

O

22 DG

ND

23

DR

EGC

AP

24 IOVD

D

25D

OU

T3

26D

OU

T2

27D

OU

T1

28D

OU

T0

29D

CLK

30D

RD

Y

31

XTA

L1

32

MC

LK/X

TAL2

33ST

AR

T

34

SYN

C_O

UT

35 SYN

C_I

N

36R

ESET

37A

IN7+

38A

IN7–

39A

IN6+

40A

IN6–

41

REF

2+

42

REF

2–

43 AVD

D1B

44 AVS

S1B

45A

IN5+

46A

IN5–

47A

IN4+

48A

IN4–

49

REF

_OU

T

50 AVS

S2B

51

AR

EG2C

AP

52 AVD

DSB

53 AVS

S3

54

FOR

MA

T1

55

FOR

MA

T0

56

CLK

_SEL

57VC

M

58 AVD

D2A

59

AR

EG1C

AP

60 AVS

S2A

61

AVS

S4

62

AVD

D4

63

AU

XAIN

+

64 AU

XAIN

–

65

PAD

DLE

U1

AD

7770

C34

1uF

C36

0.1u

FC

370.

1uF

C38

0.1u

F

C40

DN

I

C41

0.1u

F

C42

DN

I

C43

0.1u

FC

450.

1uF

DR

EGC

AP

C46

DN

I

C47

0.1u

FC

480.

1uF

BA

SL5

BASL

6

SL7SY

NC

_OU

T

SYN

CIN

C50

0.1u

FC

520.

1uF

C56

0.1u

F

C57

DN

IB

A

SL8

R66

DN

I

R67 DN

I

R68 DN

I

J2

C59

DN

IR70

DN

I

C58

DN

I

R69

DN

I

1ST

2G

ND

3O

UT

4VC

C

Y2

8.19

2MH

zR

109

0Ω

C60

0.1u

F

MO

DE0

MO

DE1

MO

DE2

MO

DE3

XT1

XT2

DC

LK1/

SDI

DC

LK0/

SDO

ALE

RT/

CS DC

LK2/

SCLK

A B C

SL15 A B C

SL16 A B C

SL17

11D

IR

21B

13

1B24 GND

51B

36

1B4 7VCCB

81B

59

1B6

10 GND

111B

712

1B8

132B

114

2B2

15 GND

162B

317

2B4

18VCCB

192B

520

2B6

21 GND

222B

723

2B8

242D

IR25

2OE

262A

827

2A7

28 GND

292A

630

2A5 31VCCA

322A

433

2A3

34 GND

352A

236

2A1

371A

838

1A7

39 GND

401A

641

1A5

42VCCA

431A

444

1A345 GND

461A

247

1A1

481O

E

U6

SN74

LVC

H16

T245

-EP

DN

I

K5

K4

K3

K2

K1

K0

K7

K6

K8

K9

K10

K11

K12

K13

K14

K15

R71

0Ω

R72

0Ω

R73

0Ω

R74

0Ω

R76

0Ω

R77

0Ω

C61 0.1u

F

C62

0.1u

F

Y1

8.19

2MH

z

A

B

C

SL9

A B C

SL10 A B C

SL11 A B C

SL12A B C

SL13

C89 DN

I

R11

10Ω

C53

0.1u

F

R75 0Ω

R14

9D

NI

R15

00Ω

R15

210kΩ

R15

3D

NI

R15

40Ω

A

B

C

SL14

CO

NV_

SAR

BA

SL18

R15

5D

NI

BA

SL21

C35

1uF

C39

1uF

C44

1uF

C49

1uF

C51

1uF

C54

1uF

C55

1uF

AIN

0-

AIN

0+

AIN

1-

AIN

1+

AIN

2+

AIN

2-

AIN

3+

AIN

3-

AIN

4+

AIN

4-

AIN

5+

AIN

5-

AIN

6-

AIN

6+

AIN

7+

AIN

7-

AU

X-

AU

X+

IOVD

D

IOVD

DIO

VDD

AVD

D1

AVD

D2

AVD

D4

IOVD

D

IOVD

D

MO

DE0

MO

DE1

MO

DE2

MO

DE3

MO

DE0

MO

DE1

MO

DE2

MO

DE3

CS

SDO

SDI

SCLK

ALE

RT_

PIN

IOVD

D

IOVD

D

IOVD

D

CS

SCLKSD

I

SDO

SDO

_BU

FFER

ED

DC

LK_B

DR

DY_

BD

OU

T0_B

DO

UT1

_BD

OU

T2_B

DO

UT3

_B

SDI_

BU

FFER

EDSC

LK_B

UFF

ERED

CS_

BU

FFER

ED

RES

ET_B

STA

RT_

B

IOVD

D

VIO

CO

NVS

T

SYN

C_I

N_B

AD

7770

_REF

_OU

T

SDP_

MC

LK_B

UFF

ERED

CO

NVS

TSD

P_C

ON

VST

SDP_

MC

LKSD

P_M

CLK

_BU

FFER

ED

IOVD

D

GPI

O0

GPI

O1

GPI

O2

IOVD

D

IOVD

D

IOVD

D IOVD

D

ALE

RT_

SPI

AVS

SX

AVS

SX

AVS

SX

VREF

IOVD

D

AVSSX

AVS

SX

AVSSX

STA

RT

RES

ET

ALE

RT_

BA

LER

T_SP

I

ALE

RT_

PIN

DC

LKD

RD

Y

DO

UT0

DO

UT1

DO

UT2

DO

UT3

IOVD

DA

LER

T

SYN

C_I

N

13550-014

Figure 15. Evaluation Board Schematic—Page 1



AIN0+

AIN0–

AIN1+

AIN1–

AIN2+

AIN2–

AIN3+

AIN3–

12345678

J13

SREW

TER

M–8

_RA

12345678

J14

GND

AI0+

AI0–

AI1+

AI1–

AI2+

AI2–

AI3+

AI3–

GND9

C1DNI

C2DNI

C3DNI

R1

0Ω

R2

0Ω

C4DNI

R3

0Ω

R4

0Ω

R5 1kΩ

R6 1kΩ

R8

0Ω

R9

0Ω

AIN0–

AIN0+

C6DNI

C7DNI

C8DNI

R10

0Ω

R11

0Ω

C9DNI

R12

0Ω

R13

0Ω

R14 1kΩ

R15 1kΩ

R16

0Ω

R17

0Ω

C10DNI

C11DNI

C12DNI

R18

0Ω

R19

0Ω

C13DNI

R20

0Ω

R21

0Ω

R22 1kΩ

R23 1kΩ

R24

0Ω

R25

0Ω

C14DNI

C15DNI

C16DNI

R26

0Ω

R27

0Ω

C17DNI

R28

0Ω

R29

0Ω

R30 1kΩ

R31 1kΩ

R32

0Ω

R33

0Ω

AIN1+

AIN1–

AIN2+

AIN2–

AIN3+

AIN3–

AGND

VCM_OUT

AIN0+

AIN0–

VCM_OUT

AIN1+

AIN1–

VCM_OUT

AIN2+

AIN2–

VCM_OUT

AIN3+

AIN3–

1355

0-01

5




AIN4+

AIN4–

AIN5+

AIN5–

AIN6+

AIN6–

AIN7+

AIN7–

DEFAULT A

AUXIN+ AUXIN–

SAR INPUT MUX

12345678

J8

SREW

TER

M–8

_RA 1

2345678

J9

GND7

AI4+

AI4–

AI5+

AI5–

AI6+

AI6–

AI7+

AI7–

GND8

C18DNI

C19DNI

C20DNI

R34

0Ω

R35

0Ω

C21DNI

R36

0Ω

R37

0Ω

R38 1kΩ

R39 1kΩ

R40

0Ω

R41

0Ω

C22DNI

C23DNI

C24DNI

R42

0Ω

R43

0Ω

C25DNI

R44

0Ω

R45

0Ω

R46 1kΩ

R47 1kΩ

R48

0Ω

R49

0Ω

C26DNI

C27DNI

C28DNI

R50

0Ω

R51

0Ω

C29DNI

R52

0Ω

R53

0Ω

R54 1kΩ

R55 1kΩ

R56

0Ω

R57

0Ω

C30DNI

C31DNI

C32DNI

R58

0Ω

R59

0Ω

C33DNI

R60

0Ω

R61

0Ω

R62 1kΩ

R63 1kΩ

R64 0Ω

R65 0Ω

AUXIN+ AUXIN–

AUX–AUX+

BA

SL22

BA

SL23

BA

SL19

BA

SL3

BA

SL4

BA

SL20

1 VDD2 DB3 NC4 S8B5 S7B6 S6B7 S5B8 S4B9 S3B10 S2B11 S1B12 GND13 NC14 NC 15A2

16A1

17A0

18EN

19S1A

20S2A

21S3A

22S4A

23S5A

24S6A

25S7A

26S8A

27VSS

28DA

U11ADG707BRUZ

R127 DNI

R146 DNIR147 DNI

R148 DNIR156 DNIR157 DNIR158 DNIR159 DNIR160 DNI

–

+

1

215U12-A

AD8659ACPZ-R7

–

+

5

46 U12-B

AD8659ACPZ-R7

–

+

8

97U12-C

AD8659ACPZ-R7

–

+

12

1114 U12-D

AD8659ACPZ-R7

R89 DNIR110 DNIR116 DNIR117 DNIR125 DNIR126 DNIR128 DNI

AGNDAGND

VCM_OUT

AIN4+

AIN4–

VCM_OUT

AIN5+

AIN5–

VCM_OUT

AIN6+

AIN6–

VCM_OUT

AIN7+

AIN7–

SURF_7_OUT+

SURF_7_OUT–

SURF_7_IN+

SURF_7_IN–

AVDD1AVSSXAUX–_SWAUX+_SW

GPIO0GPIO1GPIO2

AIN7–AIN6–AIN5–AIN4–AIN3–AIN2–AIN1–AIN0–

AIN7+

AIN5+AIN6+

AIN4+AIN3+AIN2+AIN1+AIN0+

AVDD1

AUX+ AUX–AUX+_SW AUX–_SW

1355

0-01

6




POW

ER S

UPP

LY :

JAC

K/B

ENC

H O

R F

MZ

CO

NN

ECTI

ON

V+G

ND

J6 =

JA

CK

CO

NN

ECTO

R

STA

R P

OIN

T G

RO

UN

D

EXTE

RN

AL

SUPP

LY: S

TAN

D-A

LON

E O

PER

ATI

ON

AVD

D1

GN

D

IOVD

D

AVD

D2

AVS

Sx

AVD

D4

DG

ND

Pow

er S

eque

nce

Con

trol

J5-3

1 2 3

J6

J5-1

J5-2

J5-4

C70

10µF

D1

DN

I

N/A

B AM

AIN

_SU

PPLY

R78 0Ω

R13

2

0Ω

C69

0.1µ

F

C85

0.1µ

FC

8710

µF

C91

10µF

C93

0.1µ

FC

9410

µF

1 2 3J3

C5

0.1µ

FC

6310

µF

C10

7

0.1µ

FC

108

10µF

1 2 3 4J17

1GN

D

2VI

N1

3VI

N2

4VI

N3

5VI

N4

6PW

RG

D

7O

UT3

8O

UT2

9O

UT1

10VD

DU

7

AD

M11

85A

RM

Z

R79

1kΩ

D6

GR

EEN

R81

86k6

R82

10kΩ

R83

10kΩ

R84

10kΩ

C71 DN

I

C72 DN

I

C73 DN

I

C74 DN

IR

85 10.2kΩ

10.2kΩ

R86

R87

10.2kΩ

R88

10.2kΩ

Q1

SI23

04D

DS-

T1-G

E3

R91

10kΩ

R92

39kΩ

R93

4.53kΩ

R94

61.9kΩ

D2

E

B

C

Q2

R96 0Ω

R97 0ΩR98 0Ω R99 0Ω

R10

0

0ΩR

101

0ΩR

102

0ΩR

103

0Ω

R80

39kΩ

PGN

D

R90

10.2kΩ

VIN

_EXT

VIN

_EXT

+12V

VIN

EXT_

AVD

D1

EXT_

IOVD

D

EXT_

AVD

D2

EXT_

AVS

SX

EXT_

AVD

D4

VREG

AVD

D1

REG

_EN

_SM

PS

AN

ALO

G_L

DO

_EN

SMPS

_EN

V_5V

1_D

IOD

E

V-PO

S

VIN

V_5V

1_D

IOD

E

DIG

ITA

L_LD

O_E

N

13550-017




DEF

AU

LT À

IOVD

D S

UPP

LY S

ELEC

TIO

N

AVD

D1/

2/4

SUPP

LY S

ELEC

TIO

N

±3.3

V R

AIL

FO

R B

UFF

ERS

SMPS

+5/

+12V

INPU

T

C64

0.1µ

F

AB

SLP1

C65

0.1µ

F

AB

SLP2

IOVD

D

R14

15.1kΩ

R14

22kΩ

D4

RED

D5

RED

C76

1nF

C75

1nF

A B

SLP3

C77

0.1µ

F

C82

1nF

1IN

BK

2SY

NC

3SE

Q4

SLEW

5FB

1

6C

OM

P17

EN1

8SS

9EN

210

CO

MP2

11FB

2

12VR

EF

13A

GN

D

14VR

EG15

PVIN

116

PVIN

SYS

17PV

IN2

18SW

2

19PG

ND

20SW

1

21EP

U10

AD

P507

0AC

PZ

C66

33nF

C10

056

pF

C10

147

µF

C10

24.

7µF

C10

91µ

F

C11

01µ

FC

111

1µF

C11

239

pF

C11

327

nF

C11

510

µF

R14

3

8.66kΩ

R14

4

6.19kΩ

R14

517

.8kΩ

R16

2

107kΩ

R16

3

16.2kΩ

R16

464

.9kΩ

D7

L1 12µH

R16

5

14Ω

C11

622

µF

R16

616

.9kΩ

1 2

4 3

A2

LPD

5030

-682

MR

P

D3

L21µH

L31µ

H

C11

41µ

F

R16

7

17.8kΩ

C11

7

2.2µ

F

C11

8

2.2µ

F

C80

2.2µ

F

C81

2.2µ

F

1VO

UT

2SE

NSE

/AD

J

3G

ND

4EN

5SS

6VI

N

7EP

(GN

D)U3

AD

P711

8AC

PZN

-3.3

1VO

UT

2SE

NSE

/AD

J

3G

ND

4EN

5SS

6VI

N

7EP

(GN

D)

U13

AD

P711

8AC

PZN

-3.3

C67

2.2µ

FC

68

2.2µ

F

1VO

UT

2SE

NSE

/AD

J

3G

ND

4EN

5SS

6VI

N

7EP

(GN

D)

U14

AD

P711

8AC

PZN

1VO

UT

2VO

UT

3A

DJ

4EN

5N

C

6G

ND

7VI

N8

VIN

9PA

DD

LEU15

AD

P718

2AC

PZ

C95

2.2µ

F

C96

2.2µ

FA B

SLP6

R16

810kΩ

R169

17.4kΩ

R170

3.75kΩ

A B C

SL24

C11

92.

2µF

C12

02.

2µF

R17

110kΩ

R17

23.57kΩ

C12

30.

1µF

1VO

UT

2VO

UT

3A

DJ

4EN

5N

C

6G

ND

7VI

N8

VIN

9PA

DD

LEU5

AD

P718

2AC

PZ

R173

10kΩ

R174

17.4kΩ

R17

5D

NI

R17

6D

NI

R177DNI

R178DNI

R17

9

DN

I

R18

00Ω

R18

1

0Ω

R18

2

0Ω

R18

3

0Ω

ABC SL1

R18

40Ω

+3V3

-3V3

AVD

D1

AVD

D2

AVD

D4

AVS

SX

VPO

S

VNEG

IOVD

D

DIG

ITA

L_LD

O_E

N

AVD

D1

EXT_

AVS

SX

AVD

D2

V-PO

S

AN

ALO

G_L

DO

_EN

EXT_

IOVD

D

EXT_

AVD

D1

AVD

D4

EXT_

AVD

D4

AN

ALO

G_L

DO

_EN

+3.3

V

VIN

SMPS

_EN

VREG

VREG

VIN

PGN

D

PGN

D

PGN

D

PGN

D

V-PO

S

V-N

EG

REG

_EN

_SM

PS

V-PO

S

V-PO

SV-

NEG

+3.3

V

-3.3

V

DG

ND

EXT_

AVD

D2

V-N

EG

AVD

D1

AVS

SX

DG

ND

AG

ND

VIO

PGN

DPG

ND

DG

ND

DG

ND

DG

ND

13550-018




OPTIONAL HEADER CONNECTOR (SURF BOARD FOR CH7)

DEFAULT A

REFERENCE

2.5V REFERENCE

PRECISION VOLTAGE REFERENCE

ENSURE THIS IS ADR441 ON BOM

REFERENCE BUFFER

VCM BUFFER

AD7770 REFERENCE OUT

KEEP REFERENCE TRACKAS SHORT AS POSSIBLE

J7-1

J7-2

J7-3

J7-4

J7-5

J7-6

J7-7

J10-1

J10-2

J10-3

J10-4

J10-5

J10-6

J10-7

R7 0Ω

R107 0Ω

R1150Ω

R1180Ω

R1220Ω

2 +VIN

5 TRIM

6VOUT

4GND

U2ADR441BRZ

AB

SLP5

R104

15ΩC7822µF

C790.1µF

EXT_REF

C840.1µF

R95

0ΩR105 0Ω

C86 DNI

R108

0Ω

C88 DNI

R113 DNI

2IN–

3IN+

1OUT

U8-AADA4896-2

6IN–

5IN+

7OUT

U8-B

ADA4896-2

4 V–

8 V+U8-C

ADA4896-2

R114

DNI

R119 DNI

R120 DNI

R121

0Ω

C9210µF

R106 0Ω

R112 0Ω VCM_OUT

C83DNI

AD7770_REF

R123

0Ω C97DNI

C90DNI

R12

4

DN

I

C98

0.1µF

C99

10µF

A

B

C

SL2

A

B

C

SL25

AD7770_VCM

AGND

SURF_7_IN-

SURF_7_OUT+

SURF_7_OUT–

SURF_7_IN+

VCM_OUT

V-POS

AVDD1

EXT_REF

+3.3V

EXT_REF

VCM_OUT

VCM

VCM

AD7770_REF_OUT

AVSSX

–3.3V

AVSSX

AVSSX

VREF

AVSSX

AVSSX

–3.3V

+3.3V

1355

0-01

9




AF22AG23

AF20AF21

AH21AJ21

AG25AH25

AE25AF25

AC24AD24

AK26AJ26

AG27AG28

AG30AH30

AE30AF30

AB29AB30

Y30AA30

AD23AE24

AG20AH20

AJ22AJ23

AA20AB20

AC22AD22

AF26AF27

AJ27AK28

AC26AD26

AE28AF28

AD29AE29

AC29AC30

AE23AF23

AG22AH22

AK23AK24

AB24AC25

AB27AC27

AH26AH27

AK29AK30

AK20AK21

AJ24AK25

AD21AE21

AD27AD28

AJ28AJ29

EEPROM REQUIRED IN VITA STANDARD I2C LINE PULL-UP RESISTORS ON FPGA BOARD

SCLSDA

BOARD PRESENT PIN

LA06_PLA06_N

LA10_PLA10_N

LA14_PLA14_N

LA18_P_CCLA18_N_CC

LA27_PLA27_N

GA012P0V

12P0V

3P3V

GND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GND

GND

GND

GNDGND

GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

PG_C2M

LA01_P_CCLA01_N_CC

LA05_PLA05_N

LA09_PLA09_N

LA13_PLA13_N

LA17_P_CCLA17_N_CC

LA23_PLA23_N

LA26_PLA26_N

TCKTDITDO3P3VAUXTMSTRST_LGA13P3V

3P3V

3P3V

GND

GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GNDVADJ

CLK1_M2C_PCLK1_M2C_N

LA00_P_CCLA00_N_CC

LA03_PLA03_N

LA08_PLA08_N

LA12_PLA12_N

LA16_PLA16_N

LA20_PLA20_N

LA22_PLA22_N

LA25_PLA25_N

LA29_PLA29_N

LA31_PLA31_N

LA33_PLA33_N

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GNDVADJ

PRSNT_M2C_L

CLK0_M2C_PCLK0_M2C_N

LA02_PLA02_N

LA04_PLA04_N

LA07_PLA07_N

LA11_PLA11_N

LA15_PLA15_N

LA19_PLA19_N

LA21_PLA21_N

LA24_PLA24_N

LA28_PLA28_N

LA30_PLA30_N

LA32_PLA32_N

NO CONNECTNO CONNECT



NO CONNECT

IF EVAL BOARD DOES NOT USE JTAG TDI AND TDO THEN THEY MUSTBE SHORTED TOGETHER (AS SHOWN) SO AS NOT TO BREAK JTAG CHAIN

I2C ADDRESS SET BY CONTROLLER BOARD

C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32C33C34C35C36C37C38C39C40

J4-AASP-134604-01

D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31D32D33D34D35D36D37D38D39D40

J4-BASP-134604-01

G1G2G3G4G5G6G7G8G9G10G11G12G13G14G15G16G17G18G19G20G21G22G23G24G25G26G27G28G29G30G31G32G33G34G35G36G37G38G39G40

J4-CASP-134604-01

H1H2H3H4H5H6H7H8H9H10H11H12H13H14H15H16H17H18H19H20H21H22H23H24H25H26H27H28H29H30H31H32H33H34H35H36H37H38H39H40

J4-DASP-134604-01

1 E02 E13 E2

4VSS

5SDA

6 SCL7 WP

8

VCCU9

M24C02-WDW6TP

13579

246810

11 1213 1415 1617 1819 20

J1

HEADER-10X2

1234

J15

HEADER-4X1POL

R129

0Ω

3P3VAUX

3P3VAUX

GA1GA0

GA0

GA1

+12V

VIO

DCLK_B

SCLK_BUFFERED

DRDY_BDOUT0_B

DOUT2_BDOUT3_B

SDO_BUFFERED

SDI_BUFFEREDSYNC_IN_B

CS_BUFFEREDRESET_B START_BDOUT1_B

SDP_MCLK

SDP_CONVST

ALERT_B

STARTDCLK DRDY

RESET ALERTSDP_MCLK_BUFFERED CONVST

DOUT0 DOUT1DOUT2 DOUT3

CSSCLK SDISDO VIO

+12VGPIO2

VINVIO

SYNC_IN

VIO

GPIO2

1355

0-02

0




1355

0-02

1

Figure 22. Evaluation Board Layout, Component Side (Top)

1355

0-02

2

Figure 23. Evaluation Board Layout, Component Side (Bottom)



1355

0-02

3

Figure 24. Evaluation Board Layout, Layer 1, Component Side

1355

0-02

4

Figure 25. Evaluation Board Layout, Layer 2, GND Planes



1355

0-02

5

Figure 26. Evaluation Board Layout, Layer 3, Power Traces and GND Planes

1355

0-02

6

Figure 27. Evaluation Board Layout, Layer 4, Solder Side



ORDERING INFORMATION BILL OF MATERIALS

Table 5. Reference Designator Value Description Part Number +3V3, −3V3, AIN0+, AIN0−, AIN1+, AIN1−, AIN2+, AIN2−, AIN3+, AIN3−, AUX+, AUX−, AVDD1, AVDD2, AVDD4, AVSSX, CONV_SAR, DCLK0/SDO, DCLK1/SDI, EXT_REF, MODE0 to MODE3

Not applicable Red test points 20-313137

A2 Not applicable Coupled inductors, 6.8 µH, 1.2 A, 20% LPD5030-682MRB AD7779_REF, AD7779_VCM, AI0+, AI0−, AI1+, AI1−, AI2+, AI2−, AI3+, AI3−, AI4+, AI4−, AI5+, AI5−, AI6+, AI6−, AI7+, AI7−, AUXIN+, AUXIN−, J2

Not applicable Straight PCB mount SMB jacks 1-1337482-0

ALERT/CS, DCLK2/SCLK, DREGCAP, GND, GND7, GND8, GND9, PGND, XT1, XT2, SYNCIN, SYNC_OUT

Not applicable Black test points 20-3131

C1 to C4, C6 to C33, C86, C88, C89 Do not insert Ceramic capacitors, not inserted, 0603 Not applicable C5, C36 to C38, C41, C43, C45, C47, C48, C50, C52, C53, C56, C60 to C62, C64, C65, C69, C77, C79, C84, C85, C93, C98, C107, C123

0.1 µF Capacitors ceramic, 16 V, X7R, 0402 MC0402B104K160CT

C34, C35, C39, C44, C49, C51, C54, C55 1 µF Capacitors, 0402, 1 µF, 6.3 V, X5R 04026D105KAT2A C40, C42, C46 Do not insert 0402 capacitor location Not applicable C57 to C59, C71 to C74 Do not insert Ceramic capacitors, not inserted, 0402 Not applicable C63, C70, C87, C91, C92, C94, C99, C108 10 µF Capacitors, ceramic, 50 V, X5R, 1210 GRM32ER61H106K C66 33 nF SMD capacitor MC0603B333K500CT C67 C68, C80, C81, C95, C96, C117 to C120

2.2 µF Capacitors, 0603, 2.2 µF, 6.3 V MC0603X225K6R3CT

C75, C76, C82 1 nF 50 V, X7R, multilayer ceramic capacitors MC0402B102K500CT C78 22 µF 22 µF, SMD, tantalum, 0805, capacitor TACR226M010XTA C83, C90, C97 Do not insert Ceramic capacitors, 0603 Do not insert C100 56 pF SMD capacitor MC0603N560J500CT C101 47 µF SMD capacitor GRM31CR60J476ME19L C102 4.7 µF SMD capacitor C1608X5R0J475K/0.80 C109, C114 1 µF SMD capacitors C1005X5R1C105K050BC C110 1 µF SMD capacitor GRM188R61C105KA93D C111 1 µF SMD capacitor C1005X5R0J105M050BB C112 39 pF SMD capacitor MC0603N390J500CT C113 27 nF SMD capacitor C0402C273K3RACTU C115 10 µF SMD capacitor C3216X5R1C106M160AA C116 22 µF SMD capacitor GRM21BR60J226ME49L D1 Do not insert Do not insert Not applicable D2 Diode, Zener, 0.5 W, 4.7 V, SOD-123 MMSZ5230B-7-F D3, D7 20 V, 0.5 A Schottky, 0.5 A, 20 V, SOD-123FL MBR0520LT1G D4, D5 Red LED, SMD, red HSMC-C191 D6 Green LED, SMD, green LGQ971 IOVDD, S1, S3, S5, S5'2, S6'2, S7, S7'2, S8'2, VCM_OUT, VNEG, VPOS

Do not insert Test points, not inserted, keep hole clear of solder Not applicable

J1 Not applicable 20-pin (2 × 10), 0.1" pitch, header M20-9981046 J3 Not applicable Power socket block, 3-way, 3.81 mm MC1.5/3-G-3.81 J4 Not applicable 160-pin, 10 mm, male, VITA 57, connector ASP-134604-01 J5 Not applicable DC power connectors, 2 mm, SMT, power jack KLDX-SMT2-0202-A J6 Do not insert Socket terminal block, pitch 3.81 mm MC 1.5/3-G-3.81



Reference Designator Value Description Part Number J7 Not applicable 7-way, SSW, 2.54 mm, vertical socket (make sure

that socket lines up with connector on surfboard) SSW-107-01-T-S

J8, J13 Do not insert 8-pin screw terminal, pitch 3.81 mm, vertical 1727078 J9, J14 Not applicable 8-pin terminal header, pitch 3.81 mm, vertical MC 1,5/ 8-G-3,81 J10 Not applicable 7-way, SIP, 2.54 mm, TH header (make sure that

header lines up with connector on surfboard) TLW-107-05-G-S

J15 1 × 4-pin Header, vertical, not inserted Not applicable J17 Not applicable Power socket block, 4-way, pitch 3.81mm MC1.5/4-G-3.81 K0 to K15 Not applicable Resistors, 0402, 1%, 0 Ω 0 Ω L1 12 µH Inductor ME3220-123KLB L2, L3 1 µH Inductors ME3220-102MLB MAIN_SUPPLY Not applicable 2-way solder link (use 0 Ω 0603 resistor) Insert in Link Position A Q1 Not applicable MOSFET, N-channel, 30 V, 3.6 A, diode, SOT-23 SI2304DDS-T1-GE3 Q2 Not applicable Transistor, NPN, SOT-23 MMBT3904LT1G R1 to R4, R8 to R13, R16 to R21, R24 to R29, R32 to R37, R40 to R45, R48 to R53, R56 to R61, R64, R65, R111, R112, R121, R129

0 Ω Resistors, 0603, 1%, 0 Ω MC0063W06030R

R5, R6, R14, R15, R22, R23, R30, R31, R38, R39, R46, R47, R54, R55, R62, R63

1 kΩ Resistors, 1 kΩ, 0.063 W, 1%, 0603 MC0063W060311K

R7, R71 to R78, R95 to R103, R105 to R109, R115, R118, R122, R123, R132, R150

0 Ω Resistors, 0402, 1%, 0 Ω MC00625W040210R

R66 to R70, R89, R110, R116, R117, R125 to R128, R146 to R148, R153, R156 to R160, R175 to R179

Do not insert Resistors, not inserted, 0402 Not applicable

R79 1 kΩ Resistor, thick film, 1 kΩ, 0402, 63 mW, 1% CRCW04021K00FKED R80, R92 39 kΩ Resistors, 0402, 1%, 39 kΩ MC 0.0625W 0402 1% 39K R81 86.6 kΩ Resistor, 0402, 1%, 86.6 kΩ MC 0.0625W 0402 1% 86K6 R82 to R84, R91, R152 10 kΩ Resistors, 10 kΩ, 0.063 W, 1%, 0402 MC00625W0402110K R85 to R88, R90 10.2 kΩ SMD resistors MC 0.0625W 0402 1% 10K2 R93 4.53 kΩ Resistor, thick film, 4.53 kΩ, 63 mW, 1% CRCW04024K53FKED R94 61.9 Ω Resistor, 0402, 1%, 61.9 Ω MC 0.0625W 0402 1% 61R9 R104 15 Ω Resistor, 15 Ω, 0.063 W, 1%, 0603 MC0063W0603115R R113, R114, R119, R120, R124 Do not insert Resistors, not inserted, 0603 Not applicable R141 5.1 kΩ Resistor, 5.1 kΩ, 0.063 W, 1%, 0402 MC00625W040215K1 R142 2 kΩ Resistor, MC series, 2 kΩ, 62.5 mW, ±1%, 50 V,

0402 MC00625W040212K

R143 8.66 kΩ Resistor, 8.66 kΩ, 0.063 W, 1%, 0603 MC0063W060318K66 R144 6.19 kΩ Resistor, thick film, 6.19 kΩ, 0.2 W, 1% ERJP03F6191V R145, R167 17.8 kΩ Resistors, thick film, 17.8 kΩ, 1%, 0603 MCT 0603-50 1% P5 17K8 R149, R155 Do not insert SMD, resistors, 0402 Not applicable R154 0 Ω Resistor, 0402, 1%, 0 Ω MC00625W040210R R162 107 kΩ Resistor, 0603, 107 kΩ, 1% CRCW0603107KFKEA R163 16.2 kΩ Resistor, 0603, 16.2 kΩ 1%, 0.1 W ERJ3EKF1622V R164 64.9 kΩ Resistor, 0603, 64.9 kΩ, 1% CRCW060364K9FKEA R165 14 Ω Resistor, 14 Ω, 0.063 W, 1%, 0603 MC0063W0603114R R166 16.9 Ω Resistor, 16.9 Ω, 0.063 W, 1%, 0603 MC0063W0603116R9 R168 10 kΩ Resistor, thick film, 10 kΩ, 0.1 W, 1% RC0603FR-0710KL R169 17.4 kΩ Resistor, 0603, 17.4 kΩ, 1% CRCW060317K4FKEA R170 3.74 kΩ Thick film resistor, 3. 3.74 kΩ, 100 mW, 1% CRCW06033K74FKEA R171 10 kΩ Resistor, thick film, 10 kΩ, 0.1 W, 1% RC0603FR-0710KL R172 3.57 kΩ Resistor, 0603, 3.57 kΩ, 1% CRCW06033K57FKEA R173 10 kΩ Resistor, thick film, 10 kΩ, 0.1W, 1% RC0603FR-0710KL R174 17.4 kΩ Resistor, 0603, 17.4 kΩ, 1% CRCW060317K4FKEA



Reference Designator Value Description Part Number R180 to R184, SL7 0 Ω Resistors, 0402 1%, 0 Ω MC00625W040210R SL1, SL2, SL9 to SL17, SL24, SL25 Not applicable 3-way link option, insert 0 Ω in Position A MC 0.063W 0603 0R SL3 to SL6, SL19, SL20, SL22, SL23 Not applicable 2-way resistor link option (insert in Position A) MC 0.063W 0603 0R SL8, SL18, SL21 Not applicable 2-way resistor link option, default Position A MC 0.063W 0603 0R SLP1 to SLP6 Not applicable 2-way solder link (use 0 Ω, 0603 resistor) Insert in Link Position A U1 Not applicable 8-channel, 24-bit, simultaneous sampling ADC AD7 770ACPZ/AD7779ACPZ U2 Not applicable 2.5 V reference ADR441BRZ U3 Not applicable Linear regulator, 3.3 V, ultralow noise, CMOS ADP7118ACPZN-3.3 U5 Not applicable −28 V, −200 mA, low noise, linear regulator ADP7182ACPZ U6 Do not insert 16-channel level shifter SN74LVCH16T245 U7 Not applicable Quad voltage monitor and sequencer ADM1185ARMZ-1 U8 Not applicable IC, SM, dual low noise op amp, ADA4896, MSOP-8 ADA4896-2ARMZ U9 Not applicable IC, EEPROM, 2 kb, 400 kHz, TSSOP-8 M24C02-WDW6TP U10 Not applicable 1 A/0.6 A dc-to-dc switching regulator with

positive and negative outputs ADP5070ACPZ

U11 Not applicable 8-channel multiplexer ADG707BRUZ U12 Not applicable Operational amplifier AD8659ACPZ-R7 U13 Not applicable Linear regulator, 3.3 V, ultralow noise, CMOS ADP7118ACPZN-3.3 U14 Not applicable Linear regulator, adjustable voltage, ultralow

noise, CMOS ADP7118ACPZN

U15 Not applicable −28 V, −200 mA, low noise, linear regulator ADP7182ACPZ Y1 8.192 MHz 8.192 MHz crystal, 12 pF, SMD AA-8.192MAGE-T Y2 8.192 MHz Oscillator, SG-210 series, 8.192 MHz SG-210STF 8.1920ML

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG13550-0-7/17(B)








http://www.analog.com/ADM1185?doc=EVAL-AD7770FMCZ-7771FMCZ-7779FMCZ-UG-884.pdf

http://www.analog.com/ADA4896-2?doc=EVAL-AD7770FMCZ-7771FMCZ-7779FMCZ-UG-884.pdf


http://www.analog.com/ADG707?doc=EVAL-AD7770FMCZ-7771FMCZ-7779FMCZ-UG-884.pdf





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