EX3: Designing sequential systems using FSM EX 3ELECTRONICS I Designing sequential systems using FSM 1.1 Cooperative group TEAM NUMBER: ___________ DUE DATE: ________________ 1 st review due date: ________________ STUDY TIME: Study time (in hours) Group work Classroom and laboratory sessions Sessions out of classroom Individu al Student 1 Student 2 Student 3 STATEMENT: My signature below indicates that I have (1) made equitable contribution to EX 3 as a member of the group, (2) read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3) acknowledged by name anyone outside this group who assisted this learning team or any individual member in the completion of this document. Today’s date: __________________ Active members Roles: (reporter, simulator, etc.) (1) ________________________________________ _______________ 1
Transcript
EX3: Designing sequential systems using FSM
EX 3 ELECTRONICS I
Designing sequential systems using FSM
1.1 Cooperative groupTEAM NUMBER: ___________
DUE DATE: ________________ 1st review due date: ________________
STUDY TIME:
Study time
(in hours)
Group work Classroom and laboratory sessions
Sessions out of classroom
Individual Student 1
Student 2
Student 3
STATEMENT:
My signature below indicates that I have (1) made equitable contribution to EX 3 as a member of the group, (2) read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3) acknowledged by name anyone outside this group who assisted this learning team or any individual member in the completion of this document.
Acknowledgement of individual(s) who assisted this group in completing this document:
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EPSC – E1: Electronics I
(1) _______________________
(2) _______________________
1.2 Abstract Explain here the most significant developments, results or conclusions about the exercise. Use the remaining space in this sheet (200 words maximum).
(This section is mandatory. You must complete it in order to get a mark.)
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EX3: Designing sequential systems using FSM
CONTENT
Designing sequential systems using FSM....................................................................................................1
1.7.1 Visualise the problem of mechanical pushbuttons interfaced to digital systems..............................6
1.7.2 Solve the problem..............................................................................................................................6
1.8 Problem solution (títol 2)..........................................................................................................................7
1.8.1 Part 1 (títol 3)....................................................................................................................................7
1.13 Questions in solving EX2........................................................................................................................10
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EPSC – E1: Electronics I
1.3 DescriptionIn this third exercise, basic sequential systems will be implemented and tested. We learn how to describe any synchronous sequential system through the architecture of a FSM consisting of three blocks: (1) the state register, (2) the next state logic and (3) the output logic. The state register based on D-FF will be written in VHDL using a clock sensitive process, while the next state and output logic will be specified as combinational blocks. For example, the T-FF which will be used to obtain squared waveforms will be conceived as a simple FSM. Any other basic or standard sequential block, as a counter or a data register will be implemented in the same way. Part 1 will be devoted to the study of structured frequency dividers so that we will able to generate the required clock frequencies for our digital systems from an external crystal oscillator. In Part 2, the general architecture or a finite state machine (FSM) will be studied and used once more to implement any kind of sequential system like, in this case, a matrix keypad encoder or a traffic light controller. As in previous EX2, all the projects have to be simulated functionally in ModelSim or ActiveHDL so that their major bugs will be detected before attempting the final phase of prototyping. Furthermore, in this exercise, the gate-level or timed simulation of the final synthesised circuit will also be introduced and executed using TCL do macros and timing diagrams.
1.4 Topics The following topics have been listed from the course’s specific and cross-curricular learning objectives1: #9, #10 and #11. After studying Chapter 2 and successfully completing all the assignments in this task, you will be able to:
------------- Part 1 -------------
1. Explain the FSM architecture consisting of: (1) the state register, (2) the next state logic and (3) the output logic.
2. Design the block diagram of a structured synchronous crystal oscillator frequency divider using expandable counters and other basic components.
3. Design a toggle flip-flop (T-FF).
4. Generate a real-time square waveform of 1Hz from a high frequency crystal oscillator.
5. Assign pins and synthesise the project for a CPLD or FPGA chip in a training board.
------------- Part 2 -------------
6. Explain the way to write in VHDL a state diagram for a given FSM.
7. Use the Quartus II tool:state diagram netlist to produce automatically a state diagram from the VHDL listing
8. Explain how a matrix keypad encoder works.
9. Design a matrix keypad encoder using a simple synchronous canonical FSM.
10. Do gate-level simulations in ModelSim using VHO and DSO files.
11. Use the oscilloscope to measure pulsed wave parameters and signal delays.
1.5 Designing clock frequency dividers 1.5.1 Plan a quartz oscillator frequency divider chip
a) Draw the block diagram of a synchronous frequency divider for a crystal oscillator of 25.175 MHz. The system has to produce three clock signals: pulsed waveforms of 100 Hz and 5Hz, and a final square wave of 1Hz. Explore the many ways to do it, and choose an optimum architecture like the one represented in Fig. 1. Write down the main differences in the three VHDL writing styles, and explain why the last style, the one using cascaded blocks instantiating components into a top design is the best option.
1.5.2 Design a T-FF as a simple FSM
b) Explain using a circuit schematic or a block diagram the structure of a FSM.
c) Design a project and simulate using the FSM style a T-FF. Represent the timing diagram to show that the output of the system is he input frequency divided by 2.
Fig. 1 RTL netlist view for a given frequency divider (third design style) which produces pulsed waveforms of 1 Mhz, 1 kHz and 200 mHz
1.5.3 Design synchronous cascadable binary counters as FSM
d) Find or invent the VHDL code, using the FSM style, for a synchronous cascadable (CE and TC) modulo-N binary counter with asynchronous clear direct (CD). Do a ModelSim simulation to demonstrate the way it works. For large values of N, modify the code to speed up simulations (reduce the max_count constant to a lower value).
e) Finally design the synchronous clock divider system to obtain pulsed waveforms of 100 Hz and 5Hz, and a final square wave of 1Hz. Implement a Quartus-II project for the MAX128S chip in the UP2 and use the laboratory instruments (oscilloscope or logic analyser) to measure the output waveform parameters. Check the signals synchronicity with respect to the input clock and measure the circuit propagation delays.
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EPSC – E1: Electronics I
1.5.4 Do gate-level/timed simulations
f) Try to reach similar results in ModelSim performing gate-level simulations of the synthesised circuit. Circuit’s structure VHDL file vho and delay file sdo have to be used in the project instead of the source VHDL files by which functional simulations where conducted. Again, to speed up simulations, reduce the main counter’s Max_count constant.
1.6 Designing the 16-key keypad scanning decoder 1.6.1 Keypad characteristics and wiring
g) Find the characteristics of a commercial 16-key keypad like the one represented in Fig. 2. You may run the project downloading the Proteus design from the web page.
1 2 3
654
8 97
0
TS
HS
MS
SSENTER24H/AM-PM
A
B
C
D
1 2 43
Fig. 2 Example of a commercial matrix keypad and the value obtained when pressing key “E” while scanning (setting a “0”) at RowD. Indeed, the DEC2:4 will be an integrated part of the scanning chip, and so, only the 4 pull-up resistors are the necessary hardware for the interface. An adapted keyboard can be easily obtained sticking new plastic labels on the keys (in Proteus-VSM, you can decompose a component, make the required modifications and adding the new component to the library)
The keyboard will be available in the laboratory and ready to be connected to the FLEX_EXPAN_A connector of the UP2 board. The pin assignment is as follows:
1.6.2 Plan and code in VHDL the state diagram for the component
h) Invent what is usually called intellectual property (IP): a scanning chip for the 16-key keypad, which in some way has to be similar the commercial chip MM74C922. The chip has to be based essentially in a VHDL-written FSM running a state diagram for scanning rows and decoding the key pressed. See Fig. 3.
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EX3: Designing sequential systems using FSM
Fig. 3 RTL netlist view for the keyboard decoder identified as a component
i) Write the VHDL code for the chip’s state diagram and verify it using a ModelSim project. Compile the project and use the Quartus II tool: State diagram netlist to verify if the state diagram that implements the FSM coincides with the one specified.
j) In case of having used any of the projects in Unit 2.8, which really represent a complete solution of the previous section i), fix the problem that appears when clicking simultaneously 2 keys of the same column. For example, the solution can be to introduce a final tri-state buffer to deactivate/disconnect all the rows which are not driven at logic low. See Fig. 4.
Fig. 4 A short-circuit is produced when clicking several keys in the same column. Driving the row through tri-state buffers can be a possible solution to this problem
1.6.3 Complete the project adding clock and display modules
k) Complete the project adding: (1) a hex-7segment decoder so that the hexadecimal code captured when pressing key will be displayed into the 7 segment display of the UP2 board; (b) the previous frequency divider so that the keyboard scanner entity will be driven by the 100 Hz pulse waveform. Do the necessary ModelSim simulations to verify your entity.
1.6.4 Synthesise the matrix keyboard application into a CPLD or a FPGA chip
l) Synthesise the module into the CPLD 7128S of the UP2 board and test it.
Fig. 5 Main steps in the programmable chip design flow
1.7 Debouncing keys 1.7.1 Visualise the problem of mechanical pushbuttons interfaced to digital systems
m) Studying examples in Unit 2.8, and state the problem which arises when connecting a mechanical key, pushbutton or switch as an input to a digital system (synchronisation, glitches, bounces). See Fig. 6.
1.7.2 Solve the problem
n) Solve the problem designing a debouncing filter as a FSM to produce a clean and synchronised waveform considering any of these two options for the output: (1) Qa, a single pulse of one clock period wide; (2) Qb, a pulse that will last for all the push and release action.
RP10k
KEY
VccCLK
PB_L
Qa
Qb
DEBOUNCING CIRCUIT
KEY_FILTER
QaQbCLK
PB_L
Fig. 6 The problem of pressing and releasing mechanical keys and a circuit to solve it.
1.8 Problem solution (títol 2)1.8.1 Part 1 (títol 3)
Part 1.1 (títol 4)
És necessari que seguiu aquestes indicacions per qualsevol dels vostres documents en aquesta assignatura. Aprendre-les forma part de la competència de comunicació escrita. Adapteu els vostres documents al format subministrat per aquesta plantilla.
Si alguna indicació o format no l’acabeu d’entendre bé, pregunteu-nos-ho o aclariu els dubtes, però no lliureu mai res que no compleixi aquestes indicacions perquè no us ho corregirem i perdreu el temps.
Afegiu aquí el vostre text (estil normal) encapçalat amb títols (Títol 2 i 3 i 4), amb figures (estil “llegenda” o “epígrafe”) i referències creuades en el text com aquesta Fig. 7 (és una referència creuada a la llegenda, veureu que surt en color gris quan la cliqueu) a les figures que inseriu. Fixeu-vos que la primera vegada que obrireu aquest document en Word 2007, no us sortirà aquesta llegenda “Fig.”, així que haureu de crear-ne una, i després, encara que la esborreu,ja us quedarà la referència. Veureu també que la numeració de les figures és un paràmetre automàtic. Si seleccioneu tot el document, i premeu “F9” actualitzareu tota la numeració.
També l’índex de la pag. 2 és completament automàtic. Es genera sol ( a partir de referències, índex de continguts, Inseriu un índex de continguts) i s’actualitza sol a partir també de “F9” havent seleccionat tot el text de document. És possible que la primera vegada que l’actualitzeu desaparegui. No passa res, simplement cal tornar-lo a generar a partir del menú referències i taula de contingut.
Fixeu-vos en la Fig. 7. Les imatges han d’estar centrades i alineades amb el text. Si voleu posar un parell d’imatges a la mateixa línia, inseriu primer una taula d’un parell de columnes i tot seguit feu invisibles les vores. El millor que podeu fer és “cut & paste” de la pròpia taula que veieu, i, canviar les figures per les vostres.
Feu referència també en el text a les fonts bibliogràfiques o de web que consulteu d’aquesta manera [1] (és una referència creuada a l’element numerat [1]). Expliqueu perquè les heu consultat i quina informació útil heu trobat.
Per corregir la primera versió del vostre treball, no imprimiu ni lliureu des de les pàgines 3 a la 5. És l’enunciat del problema. Sols cal que imprimiu les 2 primeres pàgines que contenen els detalls personals, el resum i l’índex, i a partir d’aquesta mateixa pàgina 6. Però feu-ho amb la numeració correcta. És a dir, treballeu sempre sobre aquest document, i en tot cas, importeu altres textos que tingueu cap a aquest mateix document i formateu-los correctament.
Insistim sobre això mateix: treballeu sempre sobre aquest mateix fitxer per preparar la vostra solució. Així usareu tots els estils i formats que ja té predefinits aquest document.
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EX3: Designing sequential systems using FSM
Fig. 7 Exemple de peu de figura que segueix la numeració de l’enunciat (llegenda).
Heu d’instal·lar els correctors ortogràfics en català, espanyol i anglès en el vostre paquet d’eines office. I sobretot, corregir qualsevol error mentre escriviu. Si treballeu això estalviareu molta feina als vostres companys i instructors.
1.9 References Modify or add new references to this section. Follow the same format.
[1] http://epsc.upc.edu/projectes/ed/ . Comment: Course wed page where to find a lot of resources for the course. Specially, materials from previous editions. Read the section on theory about digital systems. [visited 12/2009]
[2] Brown,S., Vranesic, Z., “Fundamentals of digital logic with VHDL design”, McGraw-Hill, 2005. Comment: Figure 1. 7 contains an example of design flow for logic circuits and Figure 2.29 the structure of a typical CAD/EDA system.
[3] An image to define a concept map: http://redie.uabc.mx/contenido/vol2no1/art-11-eng/contenido-ruiz-figura1.png
Establish a study plan, a task distribution scheme and other requirements to succeed in producing a good solution when working cooperatively: flux diagrams, concept maps, schematics, tables, pictures, etc.
(This section is mandatory. It must be filled in order to get a mark.)
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EX3: Designing sequential systems using FSM
1.11 Topics and activities checklist
Topics Activities
Group member in
charge Comments
1 2 3
1. The architecture of a FSM b)
2. A block diagram for the frequency divider. a)
3. A toggle flip-flop (T-FF). c)
4. A square wave of 1 Hz from the 25.175 MHz crystal quartz oscillator. d)
5. Pin assignment tool e)
6. Use the digital oscilloscope to measure signal delays and waveforms parameters. e)
7. Do gate-level simulations in ModelSim f)
8. Explain how a matrix keyboard encoder works g)
9. Invent the block diagram for a scanning matrix keyboard or debouncing circuits h), m)
10. Translate a state diagram into VHDL code i), n)
11. Tristate buffers in VHDL j)
12. Use the Quartus II tool:state diagram netlist i)
13. Complete the whole project using most of the components in a structural design k), l)
1.12 Grading grid Here you are the way the exercise could be grades.
Part 1
Design and simulation
a), b), c), d), f)
Part 1
Implementation and laboratory
e)
Part 2
Design and simulation
g), h), i)
Part 2
Implementation and laboratory
k), l)
Total
Scores 2p 3p 3p 2p
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EPSC – E1: Electronics I
Self-assessment
Instructor’s grades
1.13 Questions in solving EX22
Write here your questions, comments, doubts, opinions, etc. ...
2 Add more sheets if necessary to report your progress or comments though the exercise.
Aquests fulls de dubtes i d’explicació de com heu anat fent l’exercici són obligatoris. Si no és present, no es corregeix l’exercici i s’ha de tornar a lliurar. Abans de corregir i posar-vos qualificacions volem saber quin ha estat procés en què heu dissenyat els circuits i comparar-lo amb les nostres pròpies observacions de classe.
