Examples of circuits manufactured in 2006 Title: ILC_ PHY4: Readout chip for Tungsten-Silicon calorimeter. Organization : Laboratoire de l’Accélérateur Linéaire - IN2P3/CNRS & Paris XI- Orsay –France Run : A35C5_5 This ASIC consists of 18 channels low noise charge preamplifiers, bi-gain CRRC2 180 ns shapers, 12bit track and hold and 5 MHz output multiplexer. It covers a dynamic range of 14 bits with a linearity at the per-mil level. The preamplifier gain can be adjusted from 0.3 V/pC to 5 V/pC to accommodate various detectors. A power pulsing feature has been added in order to exploit the 1% duty cycle of the accelerator. This feature is a key parameter to embed the front-end inside the detector, without cooling pipes. It also includes a commercial 12bit ADC (AMS IP) in order to send only digital data out. Contact : Gisèle Martin-Chassard Email : [email protected]Title: A Fast-Tracking Output-ripple-based PWM Buck Converte Organization: Integrated Power Electronics Laboratory, Dept of E & C E, The Hong Kong University of Science &Technology Run: A35C6_1, austiamicrosystems 0.35μm CMOS, chip “fullv2buck” Adaptive power supply is an effective power-management solution for optimization of power and performance in state-of-the-art VLSI systems. This design is an output-ripple- based PWM buck converter. Novel adaptive feedback algorithm is implemented in simple analog circuits to provide fast reference voltage tracking, as well as minimal energy dissipation during the course of tracking. Contact: Philip MOK Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong Tel: (852) 2358-8517, Fax: (852) 2358-1485, E-mail: [email protected]Title: 0.35um CMOS Band-pass Switched-Capacitor Filter Organization: Federal University of Rio de Janeiro – UFRJ, Brazil Run: A35C6_1, CAVIT This circuit is a 0.35um CMOS 6th order band-pass switched-capacitor filter to be applied in a monitoring system intended to detect the cavitation effect in hydraulic turbines used in electrical power generation plants. The objective of that monitoring system is to avoid the serious damages caused by cavitation effects to hydraulic turbines. The filter is intended to process the signal produced by an accelerometer that measures the mechanical vibrations caused by the cavitation bubbles inside the turbine. This switched-capacitor filter has its pass-band between 10 and 30 kHz and was derived from a passive ladder prototype filter using the bilinear transformation. The filter was implemented in fully differential architecture, using Euler’s switched-capacitor integrators with a switching frequency of 200 kHz. The chip die area is 0.913 mm2 and its power consumption is 1.635 mW from a +/- 2.5 V power supply. Contact: Antonio PETRAGLIA Federal University of Rio de Janeiro UFRJ-COPPE/Eletrica-Poli/DEL P.O. Box 68504, 21941-972 Rio de Janeiro, RJ, Brazil Tel: +55 21 2562 8198, Fax: +55 21 2562 8627, E-mail: [email protected]
Transcript
Examples of circuits manufactured in 2006
Title: ILC_ PHY4: Readout chip for Tungsten-Silicon calorimeter. Organization : Laboratoire de l’Accélérateur Linéaire - IN2P3/CNRS & Paris XI- Orsay –France Run : A35C5_5
This ASIC consists of 18 channels low noise charge preamplifiers, bi-gain CRRC2 180 ns shapers, 12bit track and hold and 5 MHz output multiplexer. It covers a dynamic range of 14 bits with a linearity at the per-mil level. The preamplifier gain can be adjusted from 0.3 V/pC to 5 V/pC to accommodate various detectors. A power pulsing feature has been added in order to exploit the 1% duty cycle of the accelerator. This feature is a key parameter to embed the front-end inside the detector, without cooling pipes. It also includes a commercial 12bit ADC (AMS IP) in order to send only digital data out. Contact : Gisèle Martin-Chassard Email : [email protected]
Title: A Fast-Tracking Output-ripple-based PWM Buck Converte Organization: Integrated Power Electronics Laboratory, Dept of E & C E, The Hong Kong University of Science &Technology Run: A35C6_1, austiamicrosystems 0.35µm CMOS, chip “fullv2buck”
Adaptive power supply is an effective power-management solution for optimization of power and performance in state-of-the-art VLSI systems. This design is an output-ripple-based PWM buck converter. Novel adaptive feedback algorithm is implemented in simple analog circuits to provide fast reference voltage tracking, as well as minimal energy dissipation during the course of tracking.
Contact: Philip MOK Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong Tel: (852) 2358-8517, Fax: (852) 2358-1485, E-mail: [email protected]
Title: 0.35um CMOS Band-pass Switched-Capacitor Filter Organization: Federal University of Rio de Janeiro – UFRJ, Brazil Run: A35C6_1, CAVIT
This circuit is a 0.35um CMOS 6th order band-pass switched-capacitor filter to be applied in a monitoring system intended to detect the cavitation effect in hydraulic turbines used in electrical power generation plants. The objective of that monitoring system is to avoid the serious damages caused by cavitation effects to hydraulic turbines. The filter is intended to process the signal produced by an accelerometer that measures the mechanical vibrations caused by the cavitation bubbles inside the turbine. This switched-capacitor filter has its pass-band between 10 and 30 kHz and was derived from a passive ladder prototype filter using the bilinear transformation. The filter was implemented in fully differential architecture, using Euler’s switched-capacitor integrators with a switching frequency of 200 kHz. The chip die area is 0.913 mm2 and its power consumption is 1.635 mW from a +/- 2.5 V power supply.
Contact: Antonio PETRAGLIA Federal University of Rio de Janeiro UFRJ-COPPE/Eletrica-Poli/DEL P.O. Box 68504, 21941-972 Rio de Janeiro, RJ, Brazil Tel: +55 21 2562 8198, Fax: +55 21 2562 8627, E-mail: [email protected]
Title: Lowpass Delta-Sigma Modulator with noise shaping DAC Organization: Dept of Electrical and Computer Engineering, National University of Singapore Run: A35C6_2, AMS 0.35 CMOS, Topcell 1
This chip is a 5th-order 4-bit quantization lowpass delta-sigma modulator employing a noise shaping dynamic element matching (NSDEM) technique to remove DAC non-linearity error. Unlike most existing dynamic element matching techniques that trade SNR for SFDR, the NSDEM improves both SFDR and SNR. The fabricated chip achieves 94dB SFDR and 84dB DR in 2.2MHz BW. Contact: Yong-Ping Xu Email: [email protected]
Title: AFTER: 72 analog channels chip with a 72 x 511 Switch Capacitor Array Organization: CEA / DAPNIA / SEDI, Saclay, France Run: A35C6-3, AMS 0.35µ CMOS, “AFTER_TOP”
AFTER is a circuit dedicated to the readout of the large Time Projection Chamber for the neutrino experiment in JAPAN (T2K ND280m). Each of the 72 channels includes a low noise Charge Sensitive Amplifier (4 Gains: 120fC to 600fC) following by a CR_RC2 shaper (16 peaking time values: 100ns to 2µs). The shaped signal is continuously sampling in a 511-cell analog circular buffer (1MHz to 50MHz rate). The sampling is stopped by an external request, and the analog memory (partially or totally) is read back at a rate up to 20MHz. The power consumption per channel is 6mW and the noise is < 850e- (120fC range, 200ns of peaking time and 30pF of input capacitor).
Contact: Pascal BARON ; Eric DELAGNES CEA/DAPNIA/SEDI/LDEF, 91191 Gif-sur-Yvette Cedex, France E-mail: [email protected]; [email protected]
Title: A 10-bits 5-MS/s 35-mW pipeline ADC dedicated to the Future Linear Collider Organization: Laboratoire de Physique Corpusculaire IN2P3/CNRS Run: A35C6_3, alice_06_04
A 10-bits pipeline architecture ADC prototype has been designed in the Austriamicrosystems 0.35um CMOS technology. This R&D is dedicated to the Very Front End electronics of the ECAL detector of the future International Linear Collider. The ADC is based on a 1.5bit/stage architecture and main measured performance is: - consumption @ 5MHz: 35mW / 5V - resolution: 10 bits - input dynamic: 2V differential - Integral Non-Linearity: +0.85/-0.70 LSB - Differential Non-Linearity: +0.56/-0.46 LSB
Contact: Samuel Manen, Laurent Royer Laboratoire de Physique Corpusculaire, IN2P3/CNRS 63177 AUBIERE Cedex, France E-mail: [email protected], [email protected]
Title: IMOTEP-A; a readout chip dedicated to small animal imaging Organization: Institut de Recherches Subatomiques - IN2P3/CNRS Run: A35C6_3
IMOTEP-A is dedicated to the readout of photomultipliers for small animal PET imaging. This prototype embodies 10 parallel channels for energy information detection with a dynamic range from 0.3 to 650 photoelectrons. Each channel consists of a low noise current mode preamplifier acted as an integrator, a gain corrector to compensate gain variation of photomultipliers, a CR-RC shaper to reduce out band noise and an analogue memory which allows a continuous readout. In order to gives the arrival time reference of large dynamic signals with a temporal resolution of one nanosecond, a current mode comparator with a very low threshold (~0.3 photoelectron) has been implemented. The bias settings and the different test modes are fully programmable respectively via DACs and control registers under the supervision of a JTAG controller.
Contact: Nicolas Ollivier-Henri, Claude Colledani IReS, 23 rue du Loess, 67037 Strasbourg Cedex, France E-mail [email protected], [email protected]
Title: Digitally Programmable Multi-phase Clock Generator for Time-interleaved Analog-to-digital Converters. Organization: Telecom Paris (ENST Paris) Run: A35C6_4, v1_plots
This circuit provides 4 clocks nominally suitable to be used as sampling clocks in a 2-channels or 4-channels time-interleaved analog-to-digital converter. The frequency of these clock signals ranges from 15 MHz to 50 MHz. In order to compensate any clock-skew as a result of fabrication mismatches, the phase of each clock can be independently advanced or delayed by means of digital control signals. The phase step size can be digitally selected in a range between 0.75 ps and 5.28 ps. This circuit is part of a demonstrator that performs a new mixed signal clock-skew calibration method: the analog correction subsystem is performed by this circuit while the measurement subsystem is performed by external digital circuitry that extracts the not yet corrected residual clock-skew from the digitalized samples.
Title: Delta-sigma modulator using a passive switched-capacitor low-pass filter Organization: SUPELEC Run: A35C6_4, monica
The goal of this prototype is to conceive an analogical to digital converter offering both mode versatile function: very low consumption or high resolution. Designed in a 0,35µ CMOS technology (AMS), the delta-sigma modulator is based on a switched-capacitors passive filter associated with an additional active low pass filter and digital signal processing to improve both linearity and global resolution. After measurement on circuit we obtain 13 bits in high resolution mode and a bandwidth of 15 kHz. This mode is compatible with standard audio application in mobile phone. In low consumption mode, less than 1 uA for 9 bits resolution, this circuit can be used to provide some steady measurement (battery level for example).
Contact: Philippe BENABES Department of Signal Processing and Electronic Systems Plateau de Moulon, 3 rue Joliot-Curie, 91192 Gif-sur-Yvette Cedex, France Tél : 01 69 85 14 19, E-mail: [email protected]
Title: Ultra Low Voltage Operationnal Amplifier, Chaotic Generator, PTAT sources, Substract Effect Measurement. Organization: L2MP ( Microelectronics and Materielas Laboratory of Provence ) Run: A35C6_4, L2MP_PROTO
This circuit is a multi project prototype. Our laboratory have differents teams and research interests. So, that is why we have proposed three different structures based on analog CMOS inverters to realize an ultra low voltage operational amplifier. There are some chaotics oscillators and in the same times some PTAT current sources with under voltage threshold technic design. A Gm-C filter is designed for 2.45 GHz applications. There is a substract measurement effect prototype based on two differents VCO. All these cicuits are on test in our laboratory.
Title: AFTER: 72 analog channels chip with a 72 x 511 Switch Capacitor Array Organization: Commissariat à l’Energie Atomique, Gif sur Yvette, France Run: A35C6_7, IdefX_ECLAIR
The IDeF-X ECLAIR ASIC is a 32 channels analogue front-end with self-triggering capability. Each channel includes a charge sensitive preamplifier with a continuous reset system, a pole zero cancellation system, a variable peaking time fourth order Sallen & Key type shaper with an input signal polarity selector, a stretcher (peak detector plus a storage capacitor) and a discriminator with an adjustable low level threshold. Each stretcher is connected to the output buffer thru an analogue multiplexer. Each discriminator output contributes to the trigger signal output thru a 32 inputs logical OR circuit. All the chip configurations (peaking time, thresholds, polarity…) are programmable via a serial link. The chip has been optimized for high resolution, X or gamma ray spectroscopy. Its low noise performances and its multiple tuning possibilities make it usable for high resolution imaging systems for industrial medical or space applications.
Title: A neuromimetic and modular ASIC : integration of biomimetic neurons Organization: Laboratoire IMS, Engineering of neuromorphic systems Run: A35S6_1, GALWAY
This chip emulates neurons electrical activity using a biophysical model ( Hodgkin-Huxley formalism). Five neurons have been integrated and are fully tunable. Their model cards are stored in an analog memory cell array. Such ASICs form the computation core of a complete simulation system dedicated to the inverstigation of the dynamics of biomimetic neural networks. For further information, please consult our web site on: http://neuromorphic.ims-bordeaux.fr Contact : Jean TOMAS Laboratoire IMS Université Bordeaux 1 351 cours de la Libération, 33405 Talence Cédex France E-mail :[email protected]
Title: DHCAL1_sept06 (new name: HARDROC1): 64 channel chip for the readout of RPCs Organization : Laboratoire de l’Accélérateur Linéaire - IN2P3/CNRS & Paris XI- Orsay -France
Run : A35S6-3, AMS 0.35µm SiGe , dhcal1_sept06
HARDROC1 (HAdronic Rpc Detector ReadOut Chip) is a 64 channels complete readout chip of the RPCs or GEMs foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider. Each channel includes a fast low impedance preamplifier with 6bits variable gain (Gain tunable between 0 and 4) to adapt the gain of each channel according to the detector choice. A slow variable shaper (50-150ns) and Track and Hold provides a multiplexed charge measurement up to 10pC. A fast channel made of a variable fast shaper followed by 2 low offset discriminators allows detecting 10 fC with 100% sensitivity. The thresholds are loaded by two 10 Bit- DACs. A digital memory is integrated to memorize the 2*64 outputs of the discriminators as well as the bunch crossing identification delivered by a 24 bits counter. Thus there is only one serial output to send data serially to the DAQ during the Inter Bunch of the ILC machine. This ASIC is fully power pulsed to reduce the power consumption to 10 µW per channel.
Title: 2 channel amplifier and constant fraction discriminator. Organization: European Synchrotron Radiation Facility (ESRF, Grenoble, France) Run: A35S6_3, asg203c
asg203c is a 2 channel amplifier and constant fraction discriminator. It meets the requirement for delay-line based readout of gaseous detectors for imaging X-ray photon scattering. It may also find other applications like photon counting using avalanche photo-diodes. The amplifier is of trans-impedance type, with a gain of 200 KOhms, a peaking time of 8 ns and a 50 Ohms input resistance. The time walk of the constant fraction discriminator is typically +/- 300 ps @ 17 dB amplitude.
Contact: Christian Hervé ESRF / CS BP 220, 38043 GRENOBLE Cedex, France Tel: 0476882047, Fax: 0476882020, E-mail: [email protected] http://www.esrf.fr
Title: UWB pulse detector based on super-regenerative architecture Organization: CEA-LETI Run: S12C6_1, PULSEDETECT
The circuit is a RF front end dedicated to Ultra Wide Band [3GHz-5GHz] pulse detection for low power applications. The circuit is based on an innovative super-regenerative architecture. It includes a Low Noise Amplifier, transconductor stage and pulse detector. The overall consumption of the chain remains below 10 mA for a RF gain above 50°dB. The sensitivity is above -99 dBm@10-3 for a 1°Mbit/s data rate. Contact: PELISSIER Michaël CEA-LETI – MINATEC, LETI/DCIS/SCME/LACR 17, av des Martyrs, 38054 Grenoble Cedex 9, France Tel : 04.38.78.35.28, Fax: 04.37.78.90.73 E-mail: [email protected]
This circuit is an Ultra-Wideband RF receiver optimised for low power applications. It was design for low data rate (≤1Mb/s) communications and for 30-meters range localisation (few 10cm precision) with a power consumption of less than 20mW. This receiver is based on energy detection of UWB pulses in the band 3GHz to 5GHz in compliance with the IEEE 802.15.4a standard. It consists in amplifying the RF signal, calculating the instantaneous signal’s power then 1-bit digitising and sampling at about 1GHz for delivering digital samples to the base-band circuit with different modes of operation. The architecture of the circuit was optimised for strong multi-path and non line of sight propagations of the RF signal. Excepting the very front-end amplifiers (LNA), the architecture of the receiver is completely digital allowing future implementations in nanometric technologies (65nm, 45nm).
Contact: David Lachartre CEA-Grenoble Minatec, DCIS-SCME 17, rue des Martyrs, 38054 Grenoble cedex 09, France Tel: 33 438783792, E-mail : [email protected]
Title: A 23GHz front end for ISM band Organization: IMS Lab, 341 crs de la libération, 33405 Talence Cedex Run: S12C6_1
The front-end implemented in Romarica is based on the combination of: - An inductive degeneration cascode LNA - A passive balun - A double balancy mixer
A previous chip, combining the same blocks in bipolar implementation, was realized in BiCMOS7RF technology from ST Micro. Such full CMOS realisation expects to show that the same specifications can be obtained under solely 1.2V at a cost of a twice larger current consumption (30mA). One can observe on the herein joined photograph that except RF and OL accesses routed with 50Ω microstrip lines, the entire core of the front end uses lumped passive components in order to hold on a good tuning accuracy and reasonable bulkiness (2161 µm x 1606µm).
Contact: Thierry TARIS IMS Lab., 341 crs de la libération, 33405 Talence Cedex, France Tel: 05 40 00 27 69, E-mail: [email protected]
In this circuit we present a new architecture for audio Analog-to-Digital Converters (ADCs) that includes a Built-in Self-Test (BIST) technique for the test of the Signal-to-Noise-plus-Distortion Ratio (SNDR). A periodical binary train is integrated in the chip in order to stimulate the converter. The reuse of the bandgap circuit already existing in the converter allows us to generate the test stimulus with a very small analogue overhead area. The output response analysis is performed by means of a sine-wave fitting algorithm. The reuse of the digital filter already existing in the converter allows us to generate a synchronized reference signal necessary for the fitting-algorithm. Therefore, the BIST overhead area is only 7.5% of the whole stereo converter area in a 0.13 µm HCMOS9 technology from STMicroelectronics. Contact: Salvador MIR E-mail: [email protected] Tel: +33 4 76 57 48 95
Title: SoC for microrobot control. Organization: University of Barcelona. Electronics Department. Run: S12C6_2, ISWARM_V2
SoC including a microprocessor (DW8051), 8K of program RAM, 2K or data RAM, several ADCs for sensor interfacing, specifically designed circuits for optical communications and a voltage regulator. The chip will enable movement, IR communications between robots, tactile sensing with a cantilever tip and optical programming of a robot of 3mmx3mm. Contact: Dr. A. Dieguez Departament d'Electronica Universitat de Barcelona C/Marti Franques, 1. E08028-Barcelona, Spain Tel: +34 93 4039149, Fax: +34 93 4021148, E-mail: [email protected]
Title: IBE06K1_CORR Organization: Imperial College London (Institute of Biomedical Engineering) Run: S12C6_4, CORRELATOR_CHIP
Ultra low power bitstream cross-correlator for adaptive ECG template classification. Contact: Dr Timothy G Constandinou, Amir Eftekhar, Professor Tor Sverre Lande and Professor Christofer Toumazou E-mail: [email protected], [email protected], [email protected], [email protected]
Title: Experimental Circuit Enabling the Comparison of the Security of 13 AES/SubBytes Versions against Side-Channel Attacks Organization: GET/ENST, department COMELEC, CNRS UMR 5141 Run: S12C6_4, STMicroelectronics, 0.13 um CMOS, technology HCMOS9GP, low-power CORE9GPLL standard cells, top cell name "SUBBYTES_TOP2"
Cryptographic circuits are vulnerable to attacks on their implementation. The attacks typically exploit some side-channel information, leaked via the power supply or the electromagnetical emanations. Several types of counter-measures have been proposed. The goal of the "SUBBYTES_TOP2" ASIC it to implement a couple of them, so as to compare their efficiency. The circuit thus features thirteen substitution boxes (a crucial combinatorial function employed in symmetric ciphers) from the algorithm AES, nicknamed SubBytes. The security features of the SubBytes blocks evaluated in this chip are: - the use of WDDL or SecLib logic gates, - the use of differential placement / routing / dummies, - the use of an electromagnetical shield. Testing results: The DIL-40 circuit is placed on a board that is controllable remotely via an "ACME fox" board. Power and electromagnetical signals are acquired by an Agilent 54855A oscilloscope.
Contact : PACALET Renaud GUILLEY Sylvain Institut Eurecom ENST 2229 route des Cretes, BP 193 46 rue Barrault 06904 Sophia-Antipolis Cedex 75634 PARIS Cedex 13 Tel: 0493008402, Fax: 0493002627 Tel: 0145818333, Fax: 0145804036 E-mail: [email protected] E-mail: [email protected] http://www.comelec.enst.fr/recherche/sen/demos.html
Title: Test structures for very low noise amplifier for radio astronomy Organization: University of Calgary Run: S09C6_1, CMPCYLG5
The circuit consists of two very large transistors. The gate, source, and drain terminals of these transistors have been modified in order to accommodate large DC currents flowing through them. The noise parameters of the transistors will be evaluated which will allow us to design two low noise amplifiers with these transistors.
Contact: Leonid Belostotski University of Calgary, E-mail: [email protected]
Title: Techniques for Low-Power Low-Voltage FM-to-Digital Delta Sigma Conversion. Organization: Institute of Biomedical Engineering - Imperial College London Run: S09C6_2, FC90_CHIP
The chip contains a 512-stage parallel FM-to-Digital Delta Sigma Modulator (FDSM). The FDSM adopts bit stream processing at its output providing substantial benefits in terms of simplicity, chip area and power consumption [1]. [1] F.Cannillo, C. Toumazou, T.S. Lande, "Bit stream processing for Delta-Sigma FM-to-Digital Converters", Proceedings of IEEE International Symposium on Circuits and Systems 2006, 21-24 May 2006. Contact: Francesco Cannillo E-mail: [email protected]
Title: An Ultra-Low-Voltage UWB Digital Baseband Processor Organization: Massachusetts Institute of Technology, Cambridge, MA, USA Run: S09C6_2, TOPPO_FILL_M17
A digital baseband processor for an Ultra-Wideband (UWB) receiver is implemented in a 90-nm CMOS process. It performs acquisition and demodulation of an UWB packet with a throughput of 500-MSPS for a data-rate of 100-Mbps. The chip has a core voltage operating range from 1-V down to 0.4-V. Contact: Vivienne Sze and Anantha P. Chandrakasan E-mail: [email protected], [email protected]
Title: A 2.5nJ/b 0.65V 3-to-5GHz Subbanded UWB Receiver in 90nm CMOS Organization: Massachusetts Institute of Technology, Cambridge, MA, USA Run: S09C6_2
A non-coherent 0-to-16Mb/s UWB receiver using 3-to-5GHz subbanded PPM signalling is implemented in a 90nm CMOS process. The RF and mixed-signal baseband circuits operate at 0.65V. Using duty-cycling, adjustable BPFs, and an energy-aware baseband, the receiver achieves 2.5nJ/b and 10^(-3) BER with -99dBm sensitivity at 100kb/s. Contact: Fred S. Lee and Anantha P. Chandrakasan E-mail: [email protected], [email protected]
Title: A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS Organization: Massachusetts Institute of Technology, Cambridge, MA, USA Run: S09C6_2
This circuit is an all-digital architecture for an ultra-wideband (UWB) transmitter that operates in three channels within the 3.1-5GHz UWB frequency range. The transmitter uses static logic and no analog bias currents, thus the energy is dissipated only in switching events and by subthreshold leakage currents. The transmitter supports pulse position modulation and a delay-based BPSK spectral scrambling technique, and consumes 43pJ/bit at a data rate of 16.7Mb/s. Contact: David Wentzloff and Anantha P. Chandrakasan E-mail: [email protected], [email protected]
Title: A low-power DSP for sensor networks Organization: Massachusetts Institute of Technology, Cambridge, MA, USA Run: S09C6_2
A custom micro-sensor processor chip intended for medium bandwidth applications, such as acoustic sensing, with sensor sampling rates of around 1--100kSPS. The node includes a programmable CPU, augmented by dedicated functional units for common signal processing tasks (Fourier transform and FIR filtering). Power consumption in the on-chip memory is reduced by dividing the memory into banks (resulting in reduced access energy) and by power-gating inactive banks (reducing leakage energy). The CPU, FIR, and FFT cores can also be power gated. Contact: Nathan Ickes, Daniel Finchelstein and Anantha P. Chandrakasan E-mail: [email protected], [email protected], [email protected]
Title: A 0.2V, 10 bit Open-Loop Delta Sigma Modulator for Audio Applications Organization: Nanoelectronics group (NANO), University of Oslo, Norway in cooperation with Center for Physical Electronics, Technical University of Denmark Run: S09C6_2, TOPLEVEL_V2
“The fabricated circuit is a differential low-power/low-voltage continuous-time open-loop Frequency Delta-Sigma Modulator (FDSM). By preintegrating the analog input signal using an analog modulo integrator, the quantized signal may be differentiated using a D Flip-Flop and a XOR-gate. Thus the signal propagates unchanged through the signal, while the quantization-noise is first order shaped. The very simple circuitry and the fact that quantization is performed in the time-domain allows for very low power supply voltage, and thus low power consumption. The bottleneck in the system is the analog integrator which is implemented using a frequency modulator (VCO). The main target of this implementation is to maximize VCO-linearity since non-linearity in the VCO transfer function introduces distortion in the system and thus lower SINAD due to the missing feedback. The circuit operates on a 0.2V supply voltage offering 10-bit SNR within an audio signal bandwidth. The power consumption is below 10 uW.”
Contact: Assoc. Prof. Dag T. WISLAND Department of Informatics, University of Oslo P.O.Box 1080 Blindern, N-0316 Oslo, Norway Tel: +4722852705, Fax: +4722852401, E-mail: [email protected]
Title: A 32 mW 14Gb/s AC coupled receiver in 90-nm CMOS Organization: Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada. Run: S09C6_2, ICLTRMH3
In this design a new receiver front-end architecture is implemented which can operate upto 14 Gb/s for a 80-fF capacitively coupled channel. This front-end recovers the NRZ signal from low swing pulses using non-linear circuit tachniques.The design also includesa 40GHz VCO and phase interpolator which can be used for clock recovery from the available NRZ signal. Contact: Masum Hossain E-mail: [email protected])
Title: A 32 mW 14Gb/s AC coupled receiver in 90-nm CMOS Organization: Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada. Run: S09C6_2, ICLBCS6D
In this design a new receiver front-end architecture is implemented which can operate upto 14 Gb/s for a 80-fF capacitively coupled channel. This front-end recovers the NRZ signal from low swing pulses using non-linear circuit tachniques.The design also includesa 40GHz VCO and phase interpolator which can be used for clock recovery from the available NRZ signal. Contact: Derek Ho E-mail: [email protected]
Title: Four 32 bit multipliers to investigate architectural and technology influence on total power Organization: Institute of Microtechnology, University of Neuchâtel, Switzerland Run: S09C6_4, TOP_WITH_IO
This circuit implement 4 different multipliers corresponding to all the possible combinations of two architectures (RCA basic multiplier and RCA parallel 4 multiplier) and two transistor types (SVT and LVT). In this way, it is possible to study the influence of technology as well as architectural modifications on the total power consumption. The choice of a nanometer technology was dictated by the desire to investigate the problem in processes were static power largely contributes to the total power consumption Contact:Schuster Christian Rue Breguet 2 2000 Neuchâtel Switzerland E-mail: [email protected]
Title: Nanokey for hardware identification Organization: University of Pisa, Italy Run: S09C6_4, NKEY_UNIPI
The nanokey is a circuit for the hardware identification of objects. Its core is an array of minimum size transistors. It exploits the intrinsic fluctuations of the transistor threshold voltage to provide an unclonable authentication in a challenge-response scheme. Challenge-response pairs are intrinsically unknown even to the manufactures and must be generated after fabrication by the authentication entity. The nanokey will represent the core of a passive microwave RFID transponder. Contact: Prof. Giuseppe Iannaccone Universita` di Pisa, Dipartimento di Ingegneria dell'Informazione Via Caruso 16, I-56122, Pisa, Italy Tel: +39 050 2217677/522, Fax: +39 050 2217677/522 E-mail: [email protected] http://www.iannaccone.org
Title: Bi-CMOS linear Power Amplifier for UMTS applications Organization: Microelectronics Lab., Electronics Dept, Faculty of Engineering, Università degli Studi di Pavia, Italy Run: S25S6_4, FF_MATRIX1A
This is a two-stage linear (class AB) power amplifier for WCDMA-UMTS applications. The preamplifier is a common emitter cascoded stage, which provides power amplification of the input signal and drives the subsequent stage linearly. The power stage employs a common base stage in order to provide the power amplification and enhanced isolation. The common-base solution doesn’t suffer of instability problems and can work above the collector-emitter breakdown voltage. As a result efficiency and linearity are increased compared to a cascode solution. In order to improve efficiency and linearity of the PA, series LC circuits with resonant frequency at 2fo are placed at the input and the output of the power stage, and they are integrated on the chip. The input and output matching networks (which are off chip) employ bonding wires in order to achieve the correct impedance transformation.
Title: XPAD3, A photon counting chip for X-Ray applications Organization: Centre de Physique des Particules de Marseille (CPPM, France) Run: Dedicated Run, IBM6RF 0,25µm
The X-ray pixel chip with adaptable dynamics (XPAD3) circuit is the next generation of 2D X-ray photon counting imaging chip to be connected to a pixel sensor using the bump and flip-chip technologies. This circuit, designed in IBM 0.25 mm technology, contains 9600 pixels (130 µm by 130µm) distributed into 80 columns of 120 elements each. Its features have been improved to provide high-counting rate over 10^9 ph/pixel/mm^2, high-dynamic range over 60 keV, very low-noise detection level of 100e-rms, energy window selection and fast image readout less than 2 ms/frame. An innovative architecture has been designed in order to prevent the digital circuits from bothering the very sensitive analogue parts placed in their neighbourhood. This allows to read the chip during acquisition while conserving the precise setting of the thresholds over the pixel array. Two design versions (XPAD3S and XPAD3C) differing mostly by the analogue part of the pixels will allow XPAD3 to satisfy various detectors and experimental configurations in applications like X-ray medical imagers, synchrotron radiation experiments such as diffraction, small angle X-ray scattering or macromolecular crystallography. Contact: Patrick Pangaud E-mail: [email protected] http://imxgam.in2p3.fr
Title: Force Feedback Organization: Department of Mechanical Engineering, Dalhousie University, Halifax, Canada. Run: M02P6_1, IMUDTFFB
Using past designs we have been able to grasp objects with micro-grippers. However, it is difficult to determine the force with which objects are being held. This gripping force is important when attempting to hold sensitive objects such as biological cells or spores. Our objective is to design an interface through which the user can actually 'feel' in his/her hand the grasping force exerted by micro-manipulators. This chip will facilitate this project and will be a major step toward our goal of haptic control of MEMS devices. Contact: Dr. Ted Hubbard E-mail: [email protected]
Title: A force measurement system for measuring stiction in MEMS Organization: Department of Mechanical and Industrial Engineering, University of Toronto, Toronto, Canada. Run: M02P6_4, IMUTRIL2
This chip is a force measurement system that can measure the stiction forces on both the in-plane surfaces and sidewalls of the suspended MEMS structures. The stiction forces that are due to surfaces forces such as van der waals and capillary forces are measured in both pull-off and pealing modes. These two modes are implemented through the use of the Cantilever Beam Array (CBA) and Sidewall adhesion measurement techniques. The motions of the contacting objects, whose stictions are under study, are measured using capacitive technique. The stction forces up to approximately 500 nN can be measured using this chip."
Title: RF MEMS Variable Capacitor Organization: Institute of RF& OE-ICs of Southeast University, Nanjin, China Run: M08M6_1, Memscap’s 8 µm MetalMUMPs technology, “IROIM08M60207top1”,
The chip is a variable MEMS capacitor with a high self-resonance frequency. The MEMS capacitor uses three sets of fingers; two sets are used to construct the RF capacitor and the third set is used for tuning. Contact: Jiwei Huang IROI, Southeast University, Nanjing, China, 210096 E-mail: [email protected]
Title: SPDT RF MEMS switch Organization: Institute of RF& OE-ICs of Southeast University, Nanjin, China Run: M08M6_1, Memscap’s 8 µm MetalMUMPs technology “IROIM08M60207top1”
The chip is a single-pole double-throw (SPDT) switching circuit using lateral metal-contact MEMS switches which operate from DC to 5GHz. A folded cantilever beam is proposed to reduce the driven voltage. The insertion loss of the SPDT switching circuit is below 0.8dB, whereas the return loss is higher than 20dB. The isolation at 5GHz is 40dB. Contact: Jiwei Huang IROI, Southeast University, Nanjing, China, 210096 E-mail: [email protected]
Title: SPST RF MEMS switch Organization: Institute of RF& OE-ICs of Southeast University, Nanjin, China Run: M08M6_1, Memscap’s 8 µm MetalMUMPs technology , “IROIM08M60207top1”
The chip is a single-pole double-throw (SPDT) switching circuit with an electrothermally actuated lateral-contact microrelay. The microrelay utilizing the parallel six-beam actuator requires a low voltage. The insertion loss of the switch is below 0.8dB at 8GHz, whereas the return loss is higher than 20dB. The isolation at 8GHz is 40dB. Contact: Jiwei Huang IROI, Southeast University, Nanjing, China, 210096 E-mail: [email protected]
Title: Magnetically actuated scanning microlens for NIR Raman spectroscopy Organization: Department of Mechanical Engineering, University of British Columbia, Vancouver, Canad Run: M08M6_3, IMMBCCHI
This design dedicates to a magnetically actuated scanning microlens for miniature confocal Near Infrared (NIR) Raman spectroscopy. One of the potential applications is non-invasive skin cancer diagnosis. The microlens is comprised of a 20??m thick ferromagnetic nickel platform via MetalMUMPs process integrated with a PDMS plano-convex lens of 1.25 mm and an effective focal length of 2.0 mm. The platform connected spring systems provide adjustable platform elevation and bidirectional scanning pivots. Full scanning range of 48??? driven by an external AC magnetic field is achieved when the nickel platform is evaluated at 470??m. A coplanar 152??m scanning range is demonstrated by a 22.2x10-3 Tesla external magnetic field at resonance. Contact: Chin Pang Billy SIU E-mail: [email protected]
Title: Chip for validation of the pseudorandom technique for MEMS test Organization: TIMA Laboratory, Reliable Mixed-Systems Group Run: CSMC 0.6µ CMOS, MEMS bulk micromachining, "mems_test"
This chip was designed in order to validate the technique proposed for functional test of MEMS. The test structure is composed of identical cantilevers equiped with heating resistances and piezoresistive sensors. Silicon etching has been done to free up cantilevers for an off-plane movement. A pseudorandom test sequence sent to the heating resistance excites the beam in the bending mode and the resulting stress is read out by means of the piezoresistive sensor placed close to the clamped edge of the cantilever. The processing applied to the sensor output sequence gives the system impulse response.
References: • Mir, S., Rufer, L., Dhayni, A., Built-In-Self-Test Techniques for MEMS, Microelectronics
