F MC-16L FAMILY 16-BIT MICROCONTROLLERS MB90660A SERIES · 2006-06-27 · 1.1Features 1 Chapter1:...

FUJITSU SEMICONDUCTORCONTROLLER MANUAL CM43-10107-1E

F2MC-16L FAMILY16-BIT MICROCONTROLLERS

MB90660A SERIESHARDWARE MANUAL

1996 FUJITSU LIMITED Printed in Japan

1. The products described in this manual and the specifications thereof may be changed without prior notice. To obtain up-to-date information and/or specifications, contact your Fujitsu sales representative or Fujitsu authorized dealer.

2. Fujitsu will not be liable for infringement of copyright, industrial property right, or other rights of a third party caused by the use of information or drawings described in this manual.

3. The contents of this manual may not be transferred or copied without the express permission of Fujitsu.

4. The products contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.

5. Some of the products described in this manual may be strategic materials (or special technology) as defined by the Foreign Exchange and Foreign Trade Control Law. In such cases, the products or portions thereof must not be exported without permission as defined under the Law.

PREFACE

Thank you for choosing FUJITSU semiconductor products.

The MB90660A series is a proprietary 16-bit single-chip microcontroller developed as a general-purpose version of the F2MC*-16L family of microcontrollers.

This manual is intended for engineers using this semiconductor product in actual applications, and presents descriptions of MB90660A series functions and operation. Be sure to read the entire manual carefully. For details about instructions used with this product, refer to the “F2MC-16L Programming Manual.”

*: F2MC stands for FUJITSU Flexible Microcontroller.

This manual is organized as follows.

Chapter 1. Overview

This chapter presents the features and model lineup of the MB90660A series, with block diagrams, pin assignments and guidelines for handling of devices.

Chapter 2. Hardware

This chapter presents the internal configuration of the F2MC-16L family CPU, as well as the specifications of hardware components in the MB90660A series.

Chapter 3. Operation

This chapter describes the MB90660A series clock generator units, reset and interrupt functions, memory access modes, and low-power consumption modes.

Chapter 4. Instructions

This chapter provides an overview of instructions used with the F2MC-16L family CPU.

Chapter 5. MB90P663A Specifications

This chapter describes specifications of the MB90P663A chip.

PREFACE

i

CONTENTS

CHAPTER 1 Overview .................................................................................................1.1 Features ....................................................................................................... 11.2 Product Lineup ............................................................................................ 31.3 Block Diagram ............................................................................................ 41.4 Pin Assignment ........................................................................................... 51.5 Dimensions.................................................................................................. 61.6 Pin Description............................................................................................ 71.7 Handling of Devices.................................................................................. 131.8 Mask Option List....................................................................................... 15

CHAPTER 2 Hardware ............................................................................................ 162.1 CPU ........................................................................................................... 162.2 Maps .......................................................................................................... 552.3 Parallel Ports ............................................................................................. 642.4 Multi-Function Timer................................................................................ 702.5 UART...................................................................................................... 1132.6 10-Bit 8-Input Channel A/D Converter (with 8-bit Resolution Mode)... 1292.7 PWM ....................................................................................................... 1472.8 16-Bit Reload Timer (with Event Count Function) ................................ 1532.9 External Interrupts................................................................................... 1682.10 Delayed Interrupt Generator Module ...................................................... 1732.11 Watchdog Timer, Timebase Timer Functions......................................... 1752.12 Low Power Consumption Control Circuits (CPU Intermittent Operation

Function, Oscillation Stabilization Wait Time, Clock Multiplier Function)...................................................................... 182

2.13 Interrupt Controller ................................................................................. 189

CHAPTER 3 Operation ......................................................................................... 1973.1 Clock Generation Block .......................................................................... 1973.2 Resets ...................................................................................................... 1983.3 Interrupts ................................................................................................. 2013.4 Memory Access Modes ........................................................................... 2193.5 Low Power Consumption Modes............................................................ 2233.6 Pin Status in Sleep, Stop, Hold and Reset Modes ................................... 230

CHAPTER 4 Instructions .................................................................................... 2314.1 Addressing............................................................................................... 2314.2 Instruction Set ......................................................................................... 2364.3 Instruction Map ....................................................................................... 256

CHAPTER 5 MB90P663A Specifications ................................................... 2795.1 Features ................................................................................................... 2795.2 PROM Writing Sequence........................................................................ 2795.3 PROM Option Settings............................................................................ 280

1.1 Features

1

Chapter 1:Overview

The MB90660A series of general-purpose, high-performance 16-bit microcontrollers is designed to provide the high speed real-time processing demanded by a wide variety of industrial and office equipment as well as process control applications.

The instruction system preserves the AT architecture used in the F2MC-8 series, with the addition of instructions for use with high-level languages, expanded addressing mode, enhanced multiplication and division instructions and improved bit processing instructions. Also, the addition of a 32-bit accumulator enables processing of long-word data.

Peripheral resources include on-chip multi-function timer, 4-channel 16-bit reload timer, 1-channel 8-bit PWM timer, 1-channel UART, 8-channel 10-bit A/D converter and 8-channel external interrupt functions.

1.1 Features

(1) Minimum execution time: ................ 62.5 ns at 4 MHz source oscillation

PLL clock multiplier method

(2) Instruction set optimized for controller applications

• Wide variety of data types (bit/byte/word/long-word)

• 23 addressing modes

• High coding efficiency

• 32-bit accumulator for higher precision computation

(3) Strengthened instructions for high-level language (C) and multitasking

• System stack pointer

• Strengthened pointer indirect instructions

• Barrel shift instructions

(4) Improved execution speed: .............. 4-byte queuing

(5) Powerful 8-level, 32-source interrupt function

(6) CPU-independent automatic transfer function (EI2OS)

(7) Multi-function timer

• PWM timer output function: ......... enables output while changing duty factor in real time

• Interval timer function

• Output of non-overlapping 3-phase waveform for interval control

(8) General-purpose ports: .................... up to 51 channels

(9) UART: ............................................. 1 channel

• Can be used for asynchronous transfer or as serial interface with clock (I/O extended serial interface)

(10) A/D converter: ................................. 10-bit, 8-channel

• 8-bit conversion mode available

Common to entire F2MC-16 family

1.1 Features

2 Chapter 1: Overview

(11) 16-bit reload timer: .......................... 4 channels

(12) 8-bit PWM timer: ............................ 1 channel

(13) External interrupts: .......................... 8 channels

(14) 18-bit timebase timer

• Watchdog timer function

(15) PLL clock multiplier function

(16) CPU intermittent operation function

(17) Selection of standby modes

(18) Package: QFP-64 (0.65-mm pitch)/SH-DIP-64

(19) CMOS process technology

1.2 Product Lineup

3

1.2 Product Lineup

Table 1.2.1 shows the models in the MB90660A series. All specifications other than ROM size and RAM size are common to all models.

Table 1.2.1 MB90660A Series Product Lineup

Package MB90662A MB90663A MB90P663A MB90V660A

Type Mass production products (mask ROM) One-time product Evaluation product

ROM size32K × 8 bit (internal ROM)

48K × 8 bit (internal ROM)

48K × 8 bit (internal PROM)

None

RAM size 1.64 K × 8 bits 2 K × 8 bits 2 K × 8 bits 4 K × 8 bits

CPU functions

Number of Instructions: 340Minimum execution time 62.5 nsAddressing types: 23Multiplication speed: 687.5 ns/16 bits, 437.5 ns/8 bitsDivision speed: 1312.5 ns/16 bits, 875.0 ns/8 bits

Ports

Input ports: 4 (All also serve as peripherals)I/O ports (N-ch open-drain): 8 (All also serve as peripherals)I/O ports (CMOS): 39 (24 ports also serve as peripherals)Total: 51

Multi-function timer

One 14-bit up/down counter timer, four compare registers with buffer, compare clear register with buffer, zero detection pin control, four output channels, non-overlapping 3-phase waveform output, independent 3-phase dead-time timer 4-bit carrier counter

UARTFull-duplex double bufferClock synchronous/asynchronous data transferOn-chip dedicated baud rate generator(asynchronous speeds: 62500, 31250, 19230, 9615, 4808, 2404, 1202 bps)

A/D converter

10-bit resolution × 8 channelsA/D conversion time 6.13 µs (98 machine cycles at 16 MHz machine clock, including sample & hold time)Start sources: selection from software, external, and multi-function timer output (RT0)Start modes: single, scan (multiple channel continuous), continuous (1-channel continuous), stop (syn-

chronous with start of scan mode conversion)

16-bit reload timer

16-bit reload timer operation (either toggled output or one-shot output selectable)(count clock selection from 0.125 µs, 0.5 µs, 2.0 µs at 16 MHz machine cycle)Event count function selectableInternal 4 channel

8-bit PWM8-bit resolution PWM operation (pulse output at any period and duty ratio)(count clock selection from 0.125 µs, 64.0 µs at 16 MHz machine cycle)

External interrupt8 independent channelsInterrupt source: Selectable between leading edge/training edge or high level/low level.

Low-power con-sumption modes

Sleep mode, stop mode, CPU intermittent operating functions

Process CMOS

Package QFP-64 (0.65-mm pitch) / SH-DIP-64

Operating voltage 4.5 to 5.5 V/16 MHz, 2.7 to 5.5 V/8 MHz

1.3 Block Diagram


1.3 Block Diagram

Note: In the above diagram, I/O ports are used both as internal function blocks and signal pins. A pin used as an internal module pin may not also be used as an I/O port.

Fig. 1.3.1 MB90660A Internal Configuration Block Diagram

Clock control

RAM

ROM

UART

10-bit A/D converter

CPU


External interrupts

8-bit PWM

F2MC-16L Series core

Interrupt controller

16-bit timer

FF

MC

-16B

US

8

P00to

P07

8

P10to

P17

8

P20to

P27

4

P30to

P33

8

P40to

P47

8

P50to

P57

7

P60to

P66

I/O ports

AVCCAVR

AVSSAN0 to 7

X0,X1

RSTX

MD0 to 2

INT0 to 7

SIN

SOT

SCK

(dead-time timer)

TRGDTTIRT0-3U,V,WX,Y,Z

circuit

TIM0TIM1TIM2TIM3

PWM

1.4 Pin Assignment

5

1.4 Pin Assignment

1.4.1 QFP-64 (0.65-mm pitch) Pin Assignments

1.4.2 SH-DIP-64 Pin Assignments

48 P27/TIM3/INT747 P26/TIM2/INT646 P25/TIM1/INT545 P24/TIM0/INT444 P2343 P2242 P2141 P2040 P1739 P1638 P1537 P1436 P1335 P1234 P1133 P10

64

P45

/IN

T1

63

P44

/IN

T0

62

P43

/PW

M61

P

42/S

CK

60

P41

/SO

T59

P

40/S

IN58

D

TT

I57

P

66/R

T0

56

Vcc

55

P65

/Z54

P

64/Y

53

P63

/X52

P

62/R

T3/

W51

P

61/R

T2/

V50

P

60/R

T1/

U49

V

ss

P46/INT2/TRG 1P47/INT3/ATGX 2

P50/AN0 3P51/AN1 4P52/AN2 5P53/AN3 6P54/AN4 7P55/AN5 8P56/AN6 9P57/AN7 10

AVcc 11AVR 12AVss 13P30 14P31 15P32 16

P33

17

MD

0 1

8R

ST

X

19M

D1

20

MD

2 2

1X

0 2

2X

1 2

3V

ss

24P

00

25P

01

26P

02

27P

03

28P

04

29P

05

30P

06

31P

07

32

<TOP VIEW>

MB90660A

64 Vcc63 P65/Z62 P64/Y61 P63/X60 P62/RT3/W59 P61/RT2/V58 P60/RT1/U57 Vss56 P27/TIM3/INT755 P26/TIM2/INT654 P25/TIM1/INT553 P24/TIM0/INT452 P2351 P2250 P2149 P2048 P1747 P1646 P1545 P1444 P1343 P1242 P1141 P1040 P0739 P0638 P0537 P0436 P0335 P0234 P0133 P00

P66/RT0 1DTTI 2

P40/SIN 3P41/SOT 4P42/SCK 5

P43/PWM 6P44/INT0 7P45/INT1 8

P46/INT2/TRG 9P47/INT3/ATGX 10

P50/AN0 11P51/AN1 12P52/AN2 13P53/AN3 14P54/AN4 15P55/AN5 16P56/AN6 17P57/AN7 18

AVcc 19AVR 20AVss 21P30 22P31 23P32 24P33 25

MD0 26RSTX 27MD1 28MD2 29

X0 30X1 31

Vss 32

<TOP VIEW>MB90660A

1.5 Dimensions


1.5 Dimensions

Note: Dimensions shown in these specifications are for reference purposes only. Users are advised to consult with Sumitomo for final product dimensions.

Fig. 1.5.1 Dimensions (SH-DIP-64, QFP-64 (0.65-mm pitch))

64-Pin Plastic SH-DIP

Units: mm (inches)

(DIP-64P-M01)

64-Pin Plastic QFP

Units: mm (inches)

(FPT-64P-M09)

(mounted height)

1.6 Pin Description

7

1.6 Pin DescriptionTable 1.6.1 MB90660A Pin Description (1)

Pin No.Pin Name Circuit Type Function

QFP SH-DIP

2223

3031

X0X1

A (oscillator) Crystal oscillator pins (32 MHz)

25 to 32 33 to 40 P00 to P07 B (CMOS) General-purpose I/O ports



45 to 48 53 to 56 P24 to P27

G (CMOS)

General-purpose I/O ports, enabled when reload timer output is disabled.

TIM0 to TIM3

I/O pins for reload timers 0 to 4. When used for reload timer input pin, these pins remain set for input functions at all times, therefore output from all other functions must be disabled unless intentionally executed. When used for reload timer output, these pins are active when output functions are enabled.

INT4 to INT7 External interrupt request pins. When external interrupt functions are enabled, these pins remain set for input functions at all times, therefore output from all other functions must be disabled unless intentionally exe-cuted.

14 to 17 22 to 25 P30 to P33 B (CMOS) General-purpose I/O port

59 3 P40

E (CMOS/H)

General-purpose I/O port. This function is enabled at all times.

SIN UART serial data input pin. When UART input opera-tion is in progress, this pin remains set for input func-tions at all times, therefore output from all other functions must be disabled unless intentionally exe-cuted.

60 4 P41

E (CMOS/H)

General-purpose I/O port. This function is enabled when UART serial data output is disabled.

SOT UART serial data output pin. This function is enabled when UART serial data output is enabled.

1.6 Pin Description


61 5 P42

E (CMOS/H)

General-purpose I/O port. This function is enabled when UART clock output is disabled.

SCK UART clock I/O pin. This function is enabled when UART clock output is enabled. When UART input oper-ation is in progress, this pin remains set for input func-tions at all times, therefore output from all other functions must be disabled unless intentionally exe-cuted.

62 6 P43

E (CMOS/H)

General-purpose I/O port. This function is enabled when the PWM output is disabled.

PWM PWM timer output pin. This function is enabled when the PWM timer waveform output is enabled.

6364

7 to 8 P44 to P45

D (CMOS/H)

General-purpose input ports. This function is enabled at all times.

INT0 to INT1 External interrupt request pins. When external interrupt functions are enabled, these pins remain set for input functions at all times.

1 9 P46

D (CMOS)

General-purpose input port. This function is enabled at all times.

INT2 External interrupt request pin. When external interrupt functions are enabled, these pins remain set for input functions at all times.

TRG Multi-function timer ‘timer clear’ trigger input pin. This input function is used at all times when multi-function timer input is enabled.

2 10 P47

D (CMOS/H)

General-purpose input port. This function is enabled at all times.

INT3 External interrupt request pin. When external interrupt functions are enabled, these pins remain set for input functions at all times.

ATGX A/D converter trigger input pin. This input function is used at all times when A/D converter input is operating.

3 to 10 11 to 18 P50 to P57

C (AD)

Open-drain type I/O ports. This function is enabled when the analog input enable register is set for port operation.

AN0 to AN7 A/D converter analog input pins. This function is enabled when the analog input enable register is set for A/D operation.

Table 1.6.1 MB90660A Pin Description (2)


QFP SH-DIP

1.6 Pin Description

9

50 58 P60

E (CMOS/H)

General-purpose I/O port. This function is enabled when multi-function timer waveform output is disabled and 3-phase waveform output is disabled.

RT1 Multi-function timer waveform output pin. This func-tion is enabled when multi-function timer output is enabled.

U 3-phase waveform output pin. This function is enabled when 3-phase waveform output is enabled.

51 59 P61

E (CMOS/H)



V 3-phase waveform output pin. This function is enabled when 3-phase waveform output is enabled.

52 60 P62

E (CMOS/H)



W 3-phase waveform output pin. This function is enabled when 3-phase waveform output is enabled.

53 61 P63

E (CMOS/H)

General-purpose I/O port. This function is enabled when 3-phase waveform output is disabled.

X 3-phase waveform output pin. This function is enabled when 3-phase waveform output is enabled.

54 62 P64

E (CMOS/H)


Y 3-phase waveform output pin. This function is enabled when 3-phase waveform output is enabled.

55 63 P65

E (CMOS/H)


Z 3-phase waveform output pin. This function is enabled when 3-phase waveform output is enabled.



QFP SH-DIP

1.6 Pin Description


57 1 P66

E (CMOS/H)

General-purpose I/O port. This function is enabled when multi-function timer waveform output is disabled.


58 2 DTTID (CMOS/H)

3-phase waveform output disable signal (DTTI) input pin.

11 19 AVCC

Power supplyAnalog circuit power supply pin. This supply must never be switched on or off unless potential equal to or greater than this AVCC circuit is applied to the VCC pin.

12 20 AVRPower supply

Analog circuit reference voltage input. This pin must never be switched on or off unless potential equal to or greater than this AVR circuit is applied to the AVCC pin.

13 21 AVSS Power supply Analog circuit ground level pin

182021

262829

MD0 to MD2F (CMOS/H)

Operating mode selection input pin. This pin should be connected directly to VCC or VSS when in use.

19 27 RSTX D (CMOS/H) External reset request input pin

56 64 VCC Power supply Digital circuit power supply pin

2449

3257

VSSPower supply Digital circuit ground level pin



QFP SH-DIP

1.6 Pin Description

11

Table 1.6.2 I/O Circuit Types (1)

Classification Circuit type Remarks

A • 3 MHz to 32 MHz

• Oscillator feedback resistor: approx. 1 MΩ

B • CMOS level I/O with standby control

• Pull-up option selectable with standby control

C • N-channel open-drain outputCMOS level hysteresis inputA/D control

D • CMOS level hysteresis input with no standby control

• Pull-up option selection available with no standby control

Clock input

STANDBY CONTROL

X1

X0

Digital input

Digital output

Digital output

STANDBYCONTROL

A/D input

Digital input

Digital output

A/DDISABLE

Digital input

1.6 Pin Description


E • CMOS level outputCMOS level hysteresis input with standby control

• Pull-up option selection available with standby control

F • CMOS level input (mask ROM products have CMOS hysteresis input) with no standby control

• MD2 have pull-down option selection available (*1), MD1/0 have pull-up option selection avail-able (*2), both are without standby control.

• MB90P663A has no noise filter. Also, it has no MD2 pin P-channel protective transistor (*3) and no pull-down resistor.

• MB90V660A has no pull-up or pull-down resistors and no noise filter.

G • CMOS level I/O with no standby control

• Pull-up option selection available with standby control

Table 1.6.2 I/O Circuit Types (2)

Classification Circuit type Remarks

Digital input

Digital output

Digital output

STANDBYCONTROL

Digital input

*1

*2

*3

Noise filter

Typ. 40 ns

Digital input

Digital output

Digital output

1.7 Handling of Devices

13


(1) Preventing Latch-Up

A phenomenon called latch-up may occur on CMOS IC devices if voltage higher than VCC or lower than VSS is applied to input and output pins, or if voltage greater than the rated voltage is applied between VCC and VSS. When latch-up occurs, supply current levels increase rapidly and can result in thermal damage to semiconductor elements. Sufficient care must be taken to avoid exceeding maximum rated values.

For the same reason, care must be taken to ensure that analog power supply levels do not exceed the level of the digital power supply. When turning power supply on or off, be sure that analog power supply (AVCC, AVR) and analog input levels do not exceed the digital power supply (VCC).

(2) Handling Unused Input Pins

Unused input pins can cause devices to malfunction if left open, and should therefore be pulled up or down as appropriate.

(3) Precautions for Use of External Clock

When an external clock is used, the signal should drive the X0 pin only. Figure 1.7.1 shows an example of an external clock connection.

Fig. 1.7.1 Example: Use of an External Clock

(4) Power Supply Pins

Whenever multiple VCC or VSS pins are used, semiconductor device design requires that all internal elements of identical potential be connected in order to prevent latch-up. Also, they must be connected to external power sources and grounds, in order to reduce unwanted radiation to prevent strobe signal erratic operation due to increases in ground level, and to maintain standards for total current output.

In addition it is recommended that the VCC and VSS of this device be connected with as little impedance as possible from the current supply source.

It is further recommended that an approx. 0.1-µF ceramic capacitor be placed near the device and connected between the VCC and VSS pins as a bypass capacitor.

X1

X0

MB90660AOPEN



(5) Crystal Oscillator Circuits

Noise in the vicinity of the X0 and X1 pins can be a cause of malfunction of this device. Designers should ensure that the X0 and X1 pins, and the crystal (or ceramic) oscillators as well as the bypass capacitor to ground be placed as close together as possible, and that the printed circuit board should be designed so as to provide as little interference as possible from other wiring.

Also, PC board artwork can contribute to stability of operation by surrounding the X0 and X1 pins with ground. This is strongly recommended.

(6) Pin Handling When A/D Converter Is Not In Use

When the A/D converter is not used, connect AVCC=VCC, and AVSS=AVR=VSS.

1.8 Mask Option List

15

1.8 Mask Option List

Various options are available with the MB90660A series, as shown on Table 1.8.1. The method for designating options differs according to the specific model.

Table 1.8.1 MB90660A Series Mask Option List

Note 1: Asynchronous receiving of reset input signal is a function that allows a reset signal to be received in cases when oscillator output to output ports (including peripheral resource outputs) is stopped, and forcibly places port output signals (including peripheral resource outputs) in Hi-Z state.

Note, however, that internal reset signals (for CPU or peripheral resources, etc.) are clock-synchronous, and therefore the CPU and peripheral resources are not initialized when the clock signal is stopped.

Note 2: For details about mask ordering and options, see the ROM Ordering Specifications.

Note 3: In relation to writing to the MB90P663A, see chapter 6 “MB90P663A Specifications.”

Note 4: Pin-by-pin pull-up/pull-down resistor selection is not available for the mode pins (MD2 to MD0). The ‘yes’ selection for mask ROM versions includes MD0/MD1 with pull-up resistor, and MD2 with pull-down resistor, and for OTP versions includes MD0/MD1 with pull-up resistor, but MD2 without pull-down resistor.

Note 5: The MB90P633A requires 8 machine cycles for option setting, so that no option settings may be entered between power-on and the start of clock signal supply. (This assumes all pins have no pull-up resistor, and asynchronous receiving of reset input is enabled.)

No.Description

MB90662AMB90663A

MB90P663A MB90V660A

Method of selection

Select when ordering mask Set using EPROM programmerNo setting available

1

P00 to P07P10 to P17P20 to P27P30 to P33P40 to P47P60 to P66RSTXDTTI

Pull-up resistor available for indi-vidual pins

Pull-up resistor available for indi-vidual pins

No selection. Pull-up resistor not available.

2

MD2Pull-down resistor

Blanket selec-tion available

No selection. Pull-down resistor not available No selection.

Pull-up or pull-down resistor not available

MD1 Pull-up resistor Pull-up resistor Blanket selec-tion availableMD0 Pull-up resistor Pull-up resistor

3

Asynchronous receiving of reset input sig-nalEnabledDisabled

Selection available Selection availableNo selection. Receiving enabled.

2.1 CPU

16 Chapter 2: Hardware

Chapter 2:Hardware

2.1 CPU

The F2MC-16L CPU core is a high-performance 16-bit CPU designed for applications requiring high-speed, real-time processing such as industrial applications, office automation (OA) products, and automotive devices. The F2MC-16L instruction set is designed to be optimized for controller applications, and handles a wide variety of control functions at high speed and high efficiency. In addition, while the F2MC-16L core is designed as a 16-bit data processing CPU, an on-chip 32-bit accumulator is included for handling of 32-bit data. This enables a number of instructions to include 32-bit data processing capability. Memory space can be expanded to a maximum of 16 Mbytes, and can be accessed by either the linear pointer or bank access method. The instruction set is based on F2MC-8 A-T architecture, enhanced by additional instructions for high level languages, expanded addressing modes, enhanced multiplication and division instructions, and improved bit processing.

The principal features of the F2MC-16L CPU core are:

• Minimum execution time: .................... 62.5 ns (at 4 MHz oscillation with 4x multiplier)

• Maximum memory space: .................... 16 Mbytes: linear and bank access

• Instruction set optimized for controller applications

Wide variety of data types: ................bit/byte/word/long-word

Expanded addressing modes: .............23

High coding efficiency

32-bit accumulator for higher computational accuracy (32-bit length)

• Powerful interrupt functions

Priority levels: ....................................8 (programmable)

• CPU-independent automatic transfer

Extended intelligent I/O service: ........Maximum 16 channels

• Instruction set adapted for high level language (C) and multitasking

System stack pointer

Wide variety of pointers

High-symmetry instruction set

Barrel shift instructions

• Improved execution speed: .................. 4-byte queuing

[CAUTION] The MB90660A series is designed to operate in single-chip mode only, and therefore can access only its own internal ROM, internal RAM and internal peripheral resources.

2.1 CPU

17

2.1.1 Memory Space Overview of CPU Memory Space

All data, programs and internal resources controlled by the F2MC-16L CPU are stored in the chip’s memory area of 16 Mbytes. The CPU is able to access each address in memory as well as each internal resource through the 24-bit address bus (Figure 2.1.1).

Fig. 2.1.1 Memory Map in Relation to F2MC-16L System

Peripheral circuits

Data

Interrupts

Programs

General-purpose

Program area

Data area


Peripheral circuits

portsGeneral-purpose ports

F2MC-16LCPU

FFFFFFH

FF8000H

810000H

800000H

0000C0H

0000B0H

000020H

000000H

[Device]

2.1 CPU


Types of Addressing

The F2MC-16L CPU uses two main methods to generate addresses. In linear addressing, one entire 24-bit address is designated by an instruction, and in bank addressing, the upper 8 bits of the address is designated by a bank register for a specific purpose, and the lower 16 bits are used as the addressing operand.

Linear addressing can be further broken down into two types: one using direct designation of a 24-bit address as operand, and another in which the lower 24 bits of a 32-bit general-purpose register or accumulator are referenced as the address (Figure 2.1.2).

Example 1. Linear Addressing: Addressing with 24-bit Operand

JMPP 123456H

Example 2. Linear Addressing: Indirect addressing through 32-Bit Register

MOV A, @RL1+7

Fig. 2.1.2 Examples of Linear Addressing

17 452D

12 3456

Program bank and program counter before execution

Program bank and program counter after execution

17452DH

123456H

JMPP 123456H

Next instruction

XXXX

003A

Previous AL

New AL

090700H

+7

3A

240906F9 (Upper 8 bits ignored)

RL1

2.1 CPU

19

Type of Bank Addressing

In bank addressing the 16-Mbyte memory space is divided into 256 banks of 64 Kbytes each, with bank addresses maintained in a system of bank registers. There are five types of bank registers available. Table 2.1.1 lists bank registers, the space accessed by each register, and principal uses.

Table 2.1.1 Spaces Accessed by Bank Registers

To enhance coding efficiency, each instruction has defined default spaces for each type of addressing as shown in Table 2.1.2. When an addressing operation uses a space other than its default space, a prefix code corresponding to the desired bank is attached to the beginning of the instruction to allow access to the bank space designated by that prefix code.

Table 2.1.2 Default Spaces

Bank register Space name Principal usesInitial

value at reset

Program bank register (PCB)

Program (PC) spaceStorage of instruction codes, vector tables, and immediate data

FFH

Data bank register (DTB) Data (DT) spaceStorage of readable/writable dataAccess to internal or external peripheral resource control registers and data registers

00H

User stack bank register (USB)

Stack (SP) space

Area used for stack access to registers for saving of PUSH/POP instructions and interrupt instruc-tions, etc.SSB is used when CCR S=1, USB used when S=0.

00H

System stack bank register (SSB)

00H

Additional bank register (ADB)

Additional (AD) space

Storage of data overflow from data (DT) space 00H

18/ After reset, DT, SP and AD spaces are located in bank 00 (000000H to 00FFFFH), and PC space is located in bank FF (FF0000H to FFFFFFH).

Default space Addressing method

Program space PC indirect, program access, branching

Data space Addressing using @RW0, @RW1, @RW4, @RW5; @A, addr16, dir

Stack space Addressing using PUSHW, POPW, @RW3, @RW7

Additional space Addressing using @RW2, @RW6

2.1 CPU


Figure 2.1.3 shows an example of memory space divided into banks, and the corresponding register bank settings.

Fig. 2.1.3 Example of Bank Space Settings and Physical Addresses

[CAUTION] The MB90660A series is designed to operate in single-chip mode only, and therefore can access only its own internal ROM, internal RAM and internal peripheral resources.

Program space

Additional space

Data space

User stack space

System stack space

:PCB (Program bank register)

:ADB (Additional bank register)

:USB (User stack bank register)

:DTB (Data bank register)

:SSB (System stack bank register)4BH

68H

92H

B3H

FFH

FFFFFFH

FF0000H

B3FFFFH

B30000H

92FFFFH

920000H

68FFFFH

680000H

4BFFFFH

4B0000H

000000H

Phy

sica

l add

ress

es

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21

Memory Space Allocation for Multi-Byte Length Data

Figure 2.1.4 shows the configuration of data in memory when multi-byte lengths data are used. Data is positioned with the lowest 8 bits at address n, and each subsequent 8 bits at address n+1, n+2, n+3, ...

Fig. 2.1.4 Memory Space Allocation with Multi-Byte Lengths

Data Writing to memory is executed starting with the lowest addresses first. Thus when writing 32-bit data, the lower 16 bits are transferred first, followed by the upper 16 bits.

Note that if a reset signal is applied immediately after the lower 16 bits are written, the upper 16 bits may not be written to memory.

Access to Multi-Byte Data

All accesses are based on bank units, so that for instructions accessing multi-byte data, address FFFFH will be followed by address 0000H within the same bank. Figure 2.1.5 shows an example of executing instruction access to multi-byte data.

Fig. 2.1.5 Execution of Instruction MOVW A, 080FFFFH

01010101

11001100

11111111

00010100

H

L

Address n

01010101 11001100 11111111 00010100

MSB LSB

AL before execution

AL after execution

01H

23H

H

L

800000H

?? ??

23H 01H

80FFFFH

2.1 CPU


2.1.2 RegistersF2MC-16L registers are broadly divided into dedicated registers located within the CPU, and general-purpose registers in internal RAM. The dedicated registers are dedicated hardware located inside the CPU, and their use is limited by the architecture of the CPU itself. In contrast, the general-purpose registers coexist with RAM in CPU address space, and are similar to the dedicated registers in that they may be accessed without designation of addresses, but differ in that they may be used for user-defined purposes in the same way as regular memory. Figure 2.1.6 shows the arrangement of dedicated registers and general-purpose registers within the MB90660A device.

Fig. 2.1.6 Dedicated Registers and General-purpose Registers

Dedicated registers

Accumulator

User stack pointer

System stack pointer

Processor status register

Program counter

Direct page register

Program bank register

Internal bus

General-purpose register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

CPU RAM

2.1 CPU

23

Special Registers

Table 2.1.3 lists the 11 dedicated registers in the F2MC-16L CPU.

Table 2.1.3 Dedicated Registers

Configuration Register name Function

Accumulator16-bit × 2 registers used to store results of calculation.May be linked for use as a 32-bit register.

User stack pointer 16-bit pointer for the user stack area

System stack pointer 16-bit pointer for the system stack area

Processor status 16-bit register indicating system status

Program counter 16-bit register having the address where the program is stored

Direct page register 8-bit register indicating direct page

Program bank register 8-bit register indicating program space

Data bank register 8-bit register indicating the data space

User stack bank register 8-bit register indicating the user stack space

System stack bank register 8-bit register indicating system stack space

Additional bank register 8-bit register indicating additional space

AH AL

USP

SSP

PS

PC

DPR

PCB

DTB

USB

SSB

ADB

2.1 CPU


Accumulator (A)

The accumulator (A) consists of two 16-bit registers, labeled AH and AL, used to hold the results of calculations, and also as temporary memory for data transfers. The AH and AL registers can be linked for 32-bit data processing, and only the AL register is used for processing of data in 16-bit word units or 8-bit byte units (see Figures 2.1.7 and 2.1.8).

Data stored in the accumulator may be used for calculations involving data in memory/registers (Ri, RWi, RLi). As with the F2MC-8 CPU, the F2MC-16L is designed so that when data of word length or less is transferred to the AL register, the previous contents of the AL register are automatically transferred to the AH register. This is called the data preservation function, and increases efficiency in various types of processing together by using calculations between the contents of the AL and AH registers.

MOVL A, @RW1+6 (Instruction: Read in long-word format the contents of RW1 + 8-bit offset as an address, and store the contents in A.)

Fig. 2.1.7 Example of 32-bit Data Transfer

MOVW A, @RW1+6 (Instruction: Read in word format the contents of RW1 + 8-bit offset as an address, and store the contents in A.)

Fig. 2.1.8 Example of AL - AH Transfer

A before execution

A after execution

XXXXH XXXXH

8F74H 2B52H

DTB A6H

8FH 74H

2BH 52H

15H 38H

MSB LSB

A61540H

A6153EH

RW1

+6

AH AL

Memory space

A before execution

A after execution

XXXXH 1234H

1234H 2B52H

DTB A6H

8FH 74H

2BH 52H

15H 38H

MSB LSB

A61540H

A6153EH

RW1

+6

AH AL

Memory space

2.1 CPU

25

When transferring byte-length or shorter data to register AL, the data is given a coded extension or zero extension and stored in AL in 16-bit length. Also, data in the AL register can be handled in either word length or byte length. When an arithmetic calculation instruction is executed on the contents of AL using byte processing, the upper 8 bits of the value of AL before processing are ignored and the upper 8 bits in the result will all be set to zero. (See Figures 2.1.9 and 2.1.10.)

MOV A, 3000H (Instruction: Extend the contents of address 3000H with zeros, and store the results in AL.)

Fig. 2.1.9 Example of Zero Extension

MOVX A, 3000H (Instruction: Extend the contents of address 3000H with coding, and store the results in AL.)

Fig. 2.1.10 Example of Coded Extension

A before execution

A after execution

XXXXH 2456H

2456H 0088H

DTB B5H

77H 88H

MSB LSB

B53000H

AH AL

Memory space

A before execution

A after execution

XXXXH 2456H

2456H FF88H

DTB B5H

77H 88H

MSB LSB

B53000H

AH AL

Memory space

2.1 CPU


User Stack Pointer (USP) and System Stack Pointer (SSP)

The USP and SSP are 16-bit registers, indicating addresses in memory where data is saved or restored during execution of PUSH/POP instructions and subroutines. The USP and SSP registers are treated in the same way by stack instructions, but the USP register is enabled when the S flag in the processor status register (PS) is set to ‘0’ and the SSP register is enabled when the S flag is set to ‘1’ (see Figure 2.1.11).

Because the S flag is set to '1' when an interrupt is received, register saving due to interrupts must be handled in memory areas indicated by the SSP register. Normally stack processing for interrupt routines uses the SSP, and stack processing other than for interrupt routines uses the USP register. When there is no need to divide stack space, the SSP register alone should be used.

If values set in the stack pointers designate odd-numbered addresses, word access will be broken into two parts, reducing efficiency. Therefore even-numbered addresses should be used.

The upper 8 bits of addresses used in stack pointers are stored in the SSB register for the SSP pointer, and in the USB register for the USP pointer.

Neither the SUP nor the SSP is initialized at reset, so that both have undefined values.

Example 1. PUSHW A, with S flag set to ‘0’

Example 2. PUSHW A, with S flag set to ‘1’

Fig. 2.1.11 Stack Operation Instructions and Stack Pointers

USP F328H XX XX

MSB LSB

C6F326HUSB C6H AL A624H

SSP 1234HSSB 56HS flag 0

Before execution ⇒

USP F326H

A6H 24HC6F326H

USB C6H AL A624H

SSP 1234HSSB 56H

After execution ⇒

S flag 0

⇐ User stack is used because S flag is ‘0’

USP F328H XX XX561232HUSB C6H AL A624H

SSP 1234HSSB 56HS flag 1

Before execution ⇒

USP F328H A6H 24H561232HUSB C6H AL A624H

SSP 1232HSSB 56H

After execution ⇒

S flag 1 ⇐ User stack is used because S flag is ‘1’

2.1 CPU

27

Processor Status Register (PS)

The PS register comprises bits that perform CPU operating controls and bits that indicate CPU status. As shown in Figure 2.1.12, the upper byte of the PS register is composed of the register bank pointer (RP) which indicates the top address of the register bank, and the interrupt level mask register (ILM), and the lower byte consists of the condition code register (CCR) which contains flags set to ‘1’ or ‘0’ to indicate results of instruction execution and interrupt generation.

Fig. 2.1.12 PS Register Structure

(1) Condition Code Register (CCR)

Figure 2.1.13 shows the configuration of the condition code register.

Fig. 2.1.13 Condition Code Register Configuration

I: Interrupt enable flag: Set to ‘1’ to enable all interrupt requests other than software interrupts. When the flag is ‘0’, interrupts are masked. This flag is cleared at reset.

S: Stack flag Set to ‘0’ to enable the USP register as the pointer used for stack operations. When the flag is ‘1,’ the SSP register is enabled. Following an interrupt or reset, the value is set to ‘1.’

T: Sticky bit flag Set to ‘1’ when one or more “1”s are contained in data shifted out from the carry field during execution of logical right-shift or arithmetic right-shift instructions. The value is ‘0’ at all other times. When the shift value is zero places, the bit is also set to ‘0.’

N: Negative flag Set to ‘1’ if the MSB of the results of arithmetic calculation is ‘1’ and cleared to ‘0’ if the result is zero.

Z: Zero flag Set to ‘1’ when the results of arithmetic calculation are all zeros, and cleared to ‘0’ at all other times.

V: Overflow flag Set to ‘1’ when execution of an arithmetic calculation results in a coded value indicating an overflow, and cleared to ‘0’ at all other times.

C: Carry flag Set to ‘1’ when an arithmetic calculation requires the MSB to be carried up or down one or more places, and cleared to ‘0’ at all other times.

PS ILM RP CCR

15 13 12 8 7 0

Initial value

x: Indeterminate

0 0 0 0 0 0 0 0 - 0 1 x x x x x

– I S T N Z V C

7 6 5 4 3 2 1 0

:CCR

Initial valuex: Indeterminate

- 0 1 x x x x x

2.1 CPU


(2) Register Bank Pointer (RP)

The RP register indicates the relationship between the general-purpose registers of the F2MC-16L core and the address of internal RAM where these registers are located. The top memory address of the register bank currently in use is indicated using the conversion formula [000180H + (RP) * 10H] (see Figure 2.1.14). The RP register has 5-bit configuration and can take values from 00H to 1FH corresponding to register banks having memory addresses 000180H to 00037FH. Note that addresses within this range must be in internal RAM to be used as general-purpose registers. The RP register is initialized to the value ‘00H’ by a reset.

The 8-bit immediate value can be transferred to the RP in the assumed form of instruction; only low-order 5-bit data are actually used.

Fig. 2.1.14 Register Bank Pointer

(3) Interrupt Level Mask Register (ILM)

The ILM register has 3-bit configuration, and indicates the level of CPU interrupt masking. To be received by the CPU, interrupt requests must have a stronger (higher) level than the setting of these three bits. The strongest (highest) level is 0 and the weakest (lowest) level is 7 (see Table 2.1.4). Thus for an interrupt to be received, it must be requested at a level with a smaller value than the current ILM register value. When an interrupt is received, the value of its level is stored in the ILM register, and no interrupts of equal or lower priority will then be received. Following a reset, all bits in the ILM register are initialized to ‘0.’ When instructions are executed, the full 8-bit immediate data value can be transferred to the ILM register, but only the upper three bits of the data are actually used.

Fig. 2.1.15 Interrupt Level Register

Table 2.1.4 Relative Strength of Levels in the Interrupt Level Mask Register (ILM)

ILM2 ILM1 ILM0Level value

Interrupt level enabled

0 0 0 0 Interrupt disabled

0 0 1 1 Level 0 only

0 1 0 2 Level 1 or stronger






B4 B3 B2 B1 B0 :RP

Initial value 0 0 0 0 0

ILM2 ILM1 ILM0 :ILM

Initial value 0 0 0

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29

Program Counter (PC)

The PC register is a 16-bit counter, indicating the lower 16 bits of the memory address containing the instruction code to be executed by the CPU. The upper 8 bits of the address are indicated by the PCB register. The value in the PC register is updated by branching instructions, subroutine call instructions, interrupts and resets.

This register can also be used as a base pointer for operand access.

Fig. 2.1.16 Program Counter

Direct Page Register (DPR) <Initial value: 01H>

The DPR register indicates the values addr8 through addr15 of the operand in direct addressing instructions, as shown in Figure 2.1.17. The DPR register has 8-bit length, and is initialized to ‘01H’ at a reset. Both read and write access are enabled using instructions.

Fig. 2.1.17 Generation of Physical Addresses by Direct Addressing

Program Counter Bank Register (PCB) <Initial value: value in reset vector>

Data Bank Register (DTB) <Initial value: 00H>

User Stack Bank Register (USB) <Initial value: 00H>

System Stack Bank Register (SSB) <Initial value: 00H>

Additional Data Bank Register (ADB) <Initial value: 00H>

This set of bank registers is used to indicate the memory banks where PC space, DT space, SP space (user), SP space (system) and AD space are allocated respectively. All have 8-bit length. Following a reset the PCB register is initialized to ‘FFH’ and all others to ‘00H.’ All except the PCB register are read/write enabled. The PCB register is enabled for read access only. The PCB register is overwritten by processing of instructions branching to full 16-Mbyte space including JMPP, CALLP, RETP and RETI, as well as by software interrupt instructions, hardware interrupts and exception processing. The operation of each of these registers is described in section 2.1.1 “Memory Space.”

Next instruction to be executed

PCB FEH PC ABCDH

FEABCDH

DTB register DDR register Direct address in instruction

24-bit

αααααααα ββββββββ γγγγγγγγ

ααααααααββββββββγγγγγγγγMSB LSB

physical address

2.1 CPU


General-purpose Registers

The F2MC-16L CPU core has general-purpose registers located at RAM addresses 000180H to 00037FH on the memory map. The register bank pointer (RP) is used to indicate which register bank is the currently active area of memory. Each bank contains the following three types of registers. These registers are not independent, and are related as shown in Figure 2.1.18.

Fig. 2.1.18 General-purpose Registers

Register Banks

Register banks have 16-bit x 8-channel configuration, and can be used as general-purpose registers for various calculation, including byte registers R0 to R7, word registers RW0 to RW7, or long-word registers RL0 to RL3 in. Register banks can also be used as pointers in various instructions, and the RS0 to RL3 registers can be used as linear pointers for direct access to full memory space. Table 2.1.5 lists the functions of each register.

The contents of registers in register banks, like ordinary RAM space, are not initialized at reset and retain their pre-reset status. Note however that values are undefined at power-on.

Table 2.1.5 Register Functions

R0 to R7Used as operands for various instructions.(note) R0 can also be used as a barrel-shift counter or a counter for normalize instructions.

RW0 to RW7

Used as pointers, and as operands for various instructions.(note) RW0 can also be used as a counter for string instructions.

RL0 to RL3

Used as long pointers, and as operands for various instructions.

• R0 to R7: 8-bit general-purpose register

• RW0 to RW7: 16-bit general-purpose register

• RL0 to RL3: 32-bit general-purpose register

R7 R6

R5 R4

R3 R2

R1 R0

RW3

RW2

RW1

RW0

16-bitMSB LSB

Higher

Lower

RW7

RW6

RW5

RW4

RL3

RL2

RL1

RL0

000180H+RP*10H

Top address of general-purpose register

2.1 CPU

31

2.1.3 Prefix CodesPrefix codes may be placed before instructions to partially alter the operation of the instruction. There are three types of prefixes: bank select prefixes, common register bank prefixes and flag change suppression prefixes.

Bank Select Prefixes

The area of memory space used in a data access operation is determined by individual addressing. By placing a bank select prefix before an instruction, any area of memory space accessed in that instruction can be specified without regard to the addressing mode. Table 2.1.6 lists bank select prefixes in relation to the areas of memory space selected.

Table 2.1.6 Bank Select Prefixes

Note that the instructions listed in Table 2.1.7 ignore bank select prefixes, and the bank select prefixes used with instructions listed in Table 2.1.8 take effect with the following instruction.

Table 2.1.7 Instructions Unaffected by Bank Select Prefixes

Bank select prefix Area selected

PCB PC space

DTB Data space

ADB AD space

SPBUser stack space when the S flag in the CCR register is ‘0,’ and system stack space when this flag is ‘1.’

Instruction type Instruction Effect of bank select prefix

String instructions MOVS MOVSWSCEQ SCWEQFILS FILSW

Instruction uses bank register desig-nated by operand, regardless of pre-fix.

Stack operation instructions

PUSHW POPW Instruction uses USB if S-flag is ‘0’ and SSB if S-flag is ‘1’, regardless of prefix.

I/O access instruc-tions

MOV A,io MOVX A,ioMOVW A,ioMOV io,A MOVW io,AMOV io,#imm8 MOVW io,#imm16MOVB A,io:bp MOVB io:bp,ASETB io:bp CLRB io:bpBBC io:bp,rel BBS io:bp,relWBTC io:bp WBTS io:bp

Space 000000H to 0000FFH is accessed, regardless of prefix.

Interrupt recovery instructions

RETI Uses SSB regardless of prefix.

2.1 CPU


Table 2.1.8 Instructions Retaining Bank Select Prefix Effect Until Next Instruction

Continuous Bank Select Prefix Codes

If bank select prefix codes are continuous, the last code is effective.

Fig. 2.1.19 Continuous Prefix Codes

Common Register Bank Prefix (CMR)

To facilitate exchange of data among multiple tasks, it is necessary to have some relatively simple means of accessing the same register regardless of the value of the RP at the particular moment. The CMR prefix can be placed before an instruction accessing a general-purpose register, to change all register accesses for that instruction to common banks in the range 000180H to 00018FH (the register bank selected when RP=0). Note that caution is required when using this prefix with the instructions listed in Table 2.1.9.

Table 2.1.9 Instructions Requiring Caution in Using the Common Register Bank Prefix

Instruction type Instruction

Flag change instructions AND CCR,#imm8 OR CCR,#imm8

PS recovery instructions POPW PS

ILM set instructions MOV ILM,#imm8

Instruction type Instruction Function


Do not use the CMR prefix with string instructions.

Flag change instruc-tions

AND CCR,#imm8 OR CCR,#imm8 The effect of the prefix is retained for the next instruction.

PS recovery instruc-tions

POPW PS The effect of the prefix is retained for the next instruction.

ILM setting instruc-tions

MOV ILM,#imm8 The effect of the prefix is retained for the next instruction.

Prefix codes

↑ The PCB prefix code will become effective.

…… ……ADB ADD A, 01HDTB PCB

2.1 CPU

33

Flag Change Suppression Prefix

The flag suppression code or no-change code (NCC) is used to suppress unwanted flag changes. The NCC is placed before the instruction in which flag changes are to be suppressed, and will suppress all flag changes resulting from that instruction. This prefix affects the T, N, Z, V and C flags.

Note that caution is required when using this prefix with the instructions shown in Table 2.1.10.

Table 2.1.10 Instructions Requiring Caution in Using Flag Change Suppression Prefix

About Interrupt Suppressing Instructions

Table 2.1.11 lists ten types of instructions with which hardware interrupt requests are not detected, and interrupt requests are ignored.

Table 2.1.11 Hardware Interrupt Suppressing Instructions

Thus as Figure 2.1.20 shows, when a hardware interrupt is generated during execution of one or more of these instructions, interrupt processing will be delayed until after the execution of the first an instruction that is not one of the above types and follows any of these instructions.

Instruction type Instruction Function


Do not use the NCC prefix with string instructions.

Flag change instruc-tions

AND CCR,#imm8 OR CCR,#imm8 The CCR will change according to instruction specifications whether the prefix is used or not. The effect of the prefix will be retained for the next instruction.

PS recovery instruc-tions

POPW PS The CCR will change according to instruction specifications whether the prefix is used or not. The effect of the prefix will be retained for the next instruction.

ILM setting instruc-tions

MOV ILM,#imm8 The effect of the prefix will be retained for the next instruction.

Interrupt instructionsInterrupt recovery instructions

INT #vct8 INT9INT addr16 INTP addr24RETI

The CCR will change according to instruction specifications whether the prefix is used or not.

Context switching instructions

JCTX @A The CCR will change according to instruction specifications whether the prefix is used or not.

MOV ILM,#imm8 PCB SPBAND CCR,#imm8 ADB CMROR CCR,#imm8 NCCPOPW PS DTB

2.1 CPU


Fig. 2.1.20 Interrupt Suppressing Instructions

Restrictions on Interrupt Suppressing Instructions Used with Prefix Codes

When a prefix code is placed before an interrupt suppressing instruction, the effect of the prefix code is extended to the first instruction that is not one of the interrupt suppressing instructions. Figure 2.1.21 shows an example.

Fig. 2.1.21 Interrupt Suppressing Instructions Used with Prefix Codes

Interrupt suppressing instructions

↑

………… (a)

……

↑ Interrupt request generated Interrupt accepted

(a) Normal interrupt

ADD A, 01H

Interrupt suppressing instructions

…MOV ILM, #imm8

MOV A, FFH

CCR not changed by NCC prefix.

NCC

CCR:XXX10XXCCR:XXX10XX

2.1 CPU

35

2.1.4 Interrupts, Extended Intelligent I/O Services, and ExceptionsThe F2MC-16L CPU has four types of functions capable of reacting to the occurrence of a particular event, interrupting the execution of the instruction that is currently being processed, and transferring control to a separately defined program.

• Hardware interrupts: ......................................... Interrupt processing triggered by events occurring in internal resources.

• Software interrupts: ........................................... Interrupt processing triggered by software instructions that generate specific events.

• Extended intelligent I/O services (EI2OS): ....... Transfer processing triggered by events occurring in internal resources.

• Exceptions: ........................................................ Processing interruptions triggered by the occurrence of abnormal circumstances.

Hardware Interrupts

(1) Overview

In a hardware interrupt, the CPU reacts to an interrupt request signal from one of its internal resource circuits, temporarily suspends the execution of the program that it has been executing, and transfers control to an interrupt processing program defined by the user.

Hardware interrupts are initiated when the level of the interrupt request is compared with the interrupt level mask (ILM) register in the CPU processor status (PS) register, and the contents of the I flag in the PS register are referenced by hardware to determine that interrupt conditions exist. When a hardware interrupt is generated, the CPU performs interrupt processing as follows.

• The contents of the A, DPR, ADB, DTB, PCB, PC and PS registers in the CPU are saved to the system stack.

• The level of the current interrupt request is stored in the ILM register field in the PS register.

• The CPU branches to the corresponding interrupt vector.

(2) Configuration

Three areas of the MB90660A chip are involved in hardware interrupt processing.

• Internal resources: ......... Interrupt enable bit and interrupt request bit (control of interrupt requests from internal resources.)

• Interrupt controller: ....... ICR register (assignment of interrupt levels and determination of priority of interrupts occurring at the same time.)

• CPU: .............................. I and ILM registers (comparison of the interrupt request level with the current level and assignment of interrupt enable status.)

Microcode (execution of the necessary steps in interrupt processing.)

Each of these functions is realized through register settings -- the internal resource control registers for the internal resources, the ICR register for the interrupt controller, and the CCR register for the CPU. Before a hardware interrupt can be used, therefore, settings must be made to three locations. For information about the ICR register, see ‘Interrupt Control Register (ICR)’ in the section “Extended Intelligent I/O Services.”

The interrupt vector tables referred to during interrupt processing are located in memory area FFFC00H to FFFFFFH, and the same tables are used for software interrupts. Table 2.1.12 lists interrupt numbers and interrupt vectors.

2.1 CPU


Table 2.1.12 Interrupt Numbers and Interrupt Vectors

(3) Operation

Each internal resource with a hardware interrupt function has both an ‘interrupt request flag’ that indicates whether an interrupt request has been made, and an ‘interrupt enable flag’ used to select whether that circuit will send its interrupt signal to the CPU or not. Each interrupt request flag is set by the occurrence of a particular event specific for internal resource, and if the interrupt enable flag has an ‘enable’ setting, the resulting interrupt request will then be set from the internal resource to the interrupt controller.

The interrupt controller simultaneously compares each interrupt received with the interrupt level bit (IL) in the interrupt control register (ICR), selects the highest-level interrupt (the one with the lowest IL value) and notifies the CPU. If more than one interrupt with the same level is received, the lowest interrupt number is given priority. For the relation between interrupt requests and ICR values, see section 2.2.3 “Interrupt Vector Assignments.”

The CPU compares the level of the received interrupt with the ILM field in the processor status (PS) register, and if the value of the interrupt level is less than the ILM setting and also the I flag in the PS register has the value ‘1,’ then microcoding for interrupt processing will begin as soon as the currently executing instruction is ended.

The top of the interrupt processing microcode references the ISE bit in the interrupt controller’s ICR register, verifies that the value of that bit is ‘0’ (0=interrupt), and then starts the body of the interrupt processing routine.

In interrupt processing, the 12 bytes in the A, DPR, ADB, DTB, PCB, PC and PS registers are saved to the area of memory designated by the SSB and SSP registers, the contents of the 3-byte interrupt vector is read and loaded into the PC and PCB register, the contents of the ILM field in the PS register are updated to the level of the current interrupt request, the S flag is set to ‘1’ and CPU processing branches to the interrupt routine.

The next instruction executed will be the interrupt processing program defined by the user.

Software interrupt

instruction

Vector address L

Vector address M

Vector address H

Mode register

Interrupt no.

Hardware interrupt

INT 0 FFFFFCH FFFFFDH FFFFFEH Unused #0 None

… … … … … … …

INT 7 FFFFE0H FFFFE1H FFFFE2H Unused #7 None

INT 8 FFFFDCH FFFFDDH FFFFDEH FFFFDF #8 (RESET vector)

INT 9 FFFFD8H FFFFD9H FFFFDAH Unused #9 None

INT 10 FFFFD4H FFFFD5H FFFFD6H Unused #10 <Exception>

INT 11 FFFFD0H FFFFD1H FFFFD2H Unused #11 Hardware interrupt #0

INT 12 FFFFCCH FFFFCDH FFFFCEH Unused #12 Hardware interrupt #1

INT 13 FFFFC8H FFFFC9H FFFFCAH Unused #13 Hardware interrupt #2

INT 14 FFFFC4H FFFFC5H FFFFC6H Unused #14 Hardware interrupt #3

… … … … … … …

INT 254 FFFC04H FFFC05H FFFC06H Unused #254 Unused

INT 255 FFFC00H FFFC01H FFFC02H Unused #255 <Stack fault>

2.1 CPU

37

Figure 2.1.22 shows the flow of interrupt processing from the generation of the hardware interrupt, until no more interrupt requests remain in the interrupt request program. Figure 2.1.23 shows the flow of hardware interrupt operations.

Fig. 2.1.22 A Hardware Interrupt from Generation to Removal

(1) Interrupt source occurs in internal resource.

(2) If the interrupt enable bit in that internal resource is set to ‘enable,’ an interrupt is request is generated from the internal resource to the interrupt controller.

(3) The interrupt controller receives the interrupt request, simultaneously determines its priority, and transfers it to the CPU at the corresponding interrupt level.

(4) The CPU receives the interrupt from the interrupt controller, and compares its interrupt level with the value of the IL bit in the processor status (PS) register.

(5) Only if the comparison shows a higher priority level than the interrupt level currently being processed, the CPU then checks the value of the I flag in the processor status (PS) register.

(6) If the check in step (5) shows that the I flag is set to ‘interrupt enabled’ status, the Processor waits for the end of execution of the instruction that is currently executing, and then sets the ILM register to the requested level.

(7) The indicated register settings are saved, the processor branches and transfers control to the interrupt processing routine.

(8) Software in the user-defined interrupt processing routine clears the interrupt source that occurred in step (1), and interrupt processing ends.

F2 M

C-1

6 b

us

Microcoding

Internal resource

Internal

Inte

rrup

t lev

el IL

Leve

l com

para

tor

Interrupt

PS: I: ILM: Interrupt level mask registerIR:

PS,PC… PS I ILM

F2MC-16L·CPU

peripheral circuit block

controller…

RAM

IR ComparatorCheck

ANDEnable FF

Source FF(8)

(1) (2)

(3)

(4)(5)(6)

(7)

Instruction register

Interrupt enable flagProcessor status register

2.1 CPU


Fig. 2.1.23 Flow of An Interrupt Operation

I: CCR register flagILM: CPU interrupt level mask registerIY: Internal resource interrupt requestIE: Internal resource interrupt enable flagISE: EI2OS enable flagIL: Interrupt resource interrupt request levelS: CCR register flag

Fetch and decode next instruction

Execute normal processing

Update PC register

Hardware interrupt

ISE = 1

Save contents of PS, PC, PCB, DTB, ADB, DPR, A registers to SSP stack, then set ILM=IL.

Expanded intelligent I/O service processing

I & IY & IE = 1AND

ILM > IL

INT instruction?

End of string instruction repetition?

Software interruptSave contents of PS, PC, PCB, DTB, ADB, DPR, A registers to SSP stack, then set I=0.

Set S ← 1, pick up interrupt vector, update PCB and PC

YES

NO NO YES

YES

YES

NO

NO

2.1 CPU

39

(4) Sample Sequence for Hardware Interrupt Usage

Fig. 2.1.24 Sample Sequence of Hardware Interrupt Usage

(1) Set system stack area.

(2) Initialize internal resources capable of generating interrupt requests.

(3) Set the ICR register in the interrupt controller.

(4) Place internal resources in ready status, set interrupt enable bits to ‘enable.’

(5) Set the ILM and I flags in the CPU to enable acceptance of interrupts.

(6) Interrupt source occurs in internal resource, generates a hardware interrupt request.

(7) Interrupt processing hardware saves contents of registers, branches to interrupt processing program.

(8) Interrupt processing program processes the internal resource that produces the interrupt.

(9) Remove the interrupt request from the internal resource circuit.

(10) Execute interrupt recovery instruction, return to execution of program before branching.

Start

Set system stack area

Set ICR register in interrupt controller

Initialize internal resources

Set ILM, I flags in PS register

Interrupt request generated

Stack processingBranch to interrupt vector

Hardware processing

Interrupt processing program

Process internal resource according to nature of interrupt

Clear interrupt source

Interrupt recovery instruction (RETI)

Set start of operation for internal resource. Set interrupt enable bit to

(10)

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

2.1 CPU


(5) Hardware Interrupt Requests during Writing to Internal Resource Areas

No hardware interrupt requests will be accepted during writing to internal resource areas. This is in order to avoid abnormal CPU operations that can occur in response to interrupts made during rewriting to resource interrupt control registers. Internal resource areas are not the I/O addressing area between 000000H to 0000FFH, but the areas allocated to the control registers and data registers of internal resources.

Fig. 2.1.25 Hardware Interrupt Request during Writing to Internal Resource Areas

(6) Interrupt Suppressing Instructions

The F2MC-16L uses certain interrupt suppressing instructions that do not detect the presence of hardware interrupt requests. See Table 2.1.11, “Hardware Interrupt Suppressing Instructions.”

(7) Multiple Interrupts

The F2MC-16L core supports multiple interrupts. Thus during processing of one interrupt, when another interrupt of a higher level is generated, control is transferred to the higher interrupt as soon as execution of the current instruction is ended. When processing of the stronger interrupt is completed, control reverts to the first interrupt routine.

When another interrupt of an equal or lower level is received, the new instruction is placed on hold and the current interrupt is processed to completion (unless indicated differently by the ILM register or I flag setting).

Note that multiple extended intelligent I/O services cannot be initiated, so that when one extended intelligent I/O service is being processed, all other interrupt requests and extended intelligent I/O services will be placed on hold.

Interrupt processing

↑ ↑ ↑

Write instruction to internal resource area

…

MOV A, #08

MOV io, A MOV A, 2000H

Interrupt request No branch togenerated here interrupt

Branch to interrupt here

2.1 CPU

41

(8) Saved Registers

Figure 2.1.26 shows the sequence in which registers are saved to the stack.

Fig. 2.1.26 Saving of Registers to Stack

(9) Cautionary Information

In some internal resources, interrupt requests are cleared when the control register or data registers are read. Once an interrupt request is generated, abnormal results may be produced if the interrupt source is cleared by a read operation before control is passed to the interrupt processing hardware.

For this reason, it is important not to execute register read instructions for such resources once an interrupt request has occurred.

Saving of registers for interrupt processing

SSP (SSP value before interrupt occurred)

SSP (SSP value after interrupt occurred)

A H

A L

DPR

DTB

ADB

PCB

P C

P S

MSB LSBWord (16 bits)

H

L

2.1 CPU


Software Interrupts

(1) Overview

In a software interrupt, the CPU reacts to the execution of a specific type of instruction, and transfers control from the execution of the program that it has been executing to an interrupt processing program defined by the user. Software interrupts are always initiated by execution of a software interrupt instruction. When a software interrupt is generated, the CPU performs the following interrupt processing.

• The contents of the A, DPR, ADB, DTB, PCB, PC and PS registers in the CPU are saved to the system stack.

• The I flag in the PS register is set to ‘0’ to disable hardware interrupts.

• The CPU branches to the corresponding interrupt vector.

Software interrupt requests are always initiated by the execution of the INT instruction, which is the software interrupt source, and do not involve the use of interrupt requests flags or enable flags.

The INT instruction itself has no interrupt level. Therefore the ILM bit is not updated by the INT instruction, and the I flag remains set to ‘0’ to retain interrupt request status.

(2) Configuration

All functions related to software interrupts are contained within the CPU. To use a software interrupt, it is necessary to execute the corresponding instructions.

As shown in Table 2.1.12, interrupt vectors for both hardware interrupts and software interrupts share the same space. For example, interrupt request number INT11 can be used for hardware interrupt #0, and can also be used for software interrupt INT #11. Thus the same interrupt processing subroutine will be called by both hardware interrupt #0 and software interrupt INT #11.

(3) Operation

When the CPU fetches a software interrupt instruction for execution, it activates the software interrupt processing microcoding routine. In software interrupt processing microcoding, the 12 bytes of data contained in memory in the A, DPR, ADB, DTB, PCB, PC and PS registers are saved in the area of memory designated by the SSB and SSP registers, then the contents of the 3-byte interrupt vector is read and loaded into the PC and PCB register, the I flag is set to ‘0’ and the S flag is set to ‘1’ and CPU processing branches to the interrupt routine. The next instruction executed will then be the interrupt processing program defined by the user.

Figure 2.1.27 shows the flow of interrupt processing from the generation of the software interrupt, until no more interrupt requests remain in the interrupt request program.

2.1 CPU

43

Fig. 2.1.27 A Software Interrupt from Generation to Removal

(1) Software interrupt instruction is executed.

(2) Contents of designated registers saved according to microcoding of software interrupt instruction.

(3) Interrupt processing ends with execution of RETI instruction in the user-defined interrupt processing routine.

(4) Precautionary Information

When the program bank register (PCB) has the value FFH, the CALLV instruction vector area overlaps the table for the INT #vct8 instruction. When creating software, care should be taken to avoid address duplication between the CALLV and INT #vct8 instructions.

F2 M

C-1

6 b

us Microcoding


PS,PC… PS I S

F2MC-16L • CPU

RAM

IRFetchQueue

Save

(1)

(2) Instruction register

Interrupt enable flagProcessor status register

2.1 CPU


Expanded Intelligent I/O Service (EI2OS)

EI2OS is a set of automatic data transfer functions between I/O ports and memory, which accomplish the same exchange of data as previous methods but in a direct memory access (DMA) style. This method has the following advantages in comparison with the previous interrupt processing methods.

• Elimination of need to write transfer programs, allowing reduction of overall program size.

• No internal registers used for transfer, speeding up transfer processing by eliminating the need to save register contents.

• Transfer can be stopped according to I/O status, eliminating unnecessary data transfers.

• Choice of increment or no update buffer addressing modes.

• Choice of increment or no update I/O register addressing modes.

When EI2OS processing ends, processing branches automatically to the interrupt processing program as soon as end conditions are set, allowing the user to determine the type of ending conditions to be used.

EI2OS functions are realized by a distributed hardware configuration located in two separate units. The related registers and descriptors are apportioned among the two blocks as follows.

• Interrupt control register: ............................................... located within the interrupt controller, used to indicate ISD addresses.

• Extended intelligent I/O service descriptor (ISD): ........ located in RAM, used to hold transfer mode, I/O address and transfer count, and buffer addresses.

Figure 2.1.28 shows an overview of extended intelligent I/O service operation.

Fig. 2.1.28 Overview of Extended Intelligent I/O Service

[CAUTION] The IOA pointer can designate the area 000000H to 00FFFFH. The BAP pointer can designate the area 000000H to FFFFFFH. The maximum data transfer designation by the data counter (DCT) is 65536 bytes.

Memory space

I/O register

Buffer

I/O registerPeripheral

Interrupt request

Interrupt control register


ISD

by IOA

by BAP

(4)

(1)

(3)

(3)

resource

by ICS(2)

(1) I/O register requests transfer

(2) The interrupt controller selects a descriptor

(3) Transfer source and destination are read from the descriptor

(4) Transfer is performed to/from I/O memory locations

(5) The interrupt source is automatically cleared

CPU

by DCT

(5)

2.1 CPU

45

Interrupt Control Register (ICR00 to ICR15)

The interrupt control register (ICR) is located inside the interrupt controller, and operates on all I/O resources that have interrupt functions. For the relation between interrupts and the ICR register, see section 2.2.3, “Interrupt Vector Allocation.” This register has the following three functions.

• Sets interrupt levels for each corresponding internal resource

• Determines whether interrupts from the corresponding internal resources are to be handled as normal interrupts or as extended intelligent I/O services

• Selects channels for extended intelligent I/O services

[CAUTION] Attempted access to this register by read-modify-write instructions may result in abnormal operation, and should be avoided.

Figure 2.1.29 shows the bit configuration of the interrupt control register.

[CAUTION] The ICS3-ICS0 bits are effective only when EI2OS has been started. The ISE bit is set to ‘1’ to start EI2OS, and otherwise is set to ‘0.’ If EI2OS has not been started, the ICS0 to ICS3 bits may have any value.

Fig. 2.1.29 Interrupt Control Register (ICR)

Interrupt control register (ICR) write configurationReset : 00000111B

Interrupt control register (ICR) read configurationReset : XX000111B

ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0

7 6 5 4 3 2 1 0

W W W W W W W W

–– –– S1 S0 ISE IL2 IL1 IL0

7 6 5 4 3 2 1 0

– – R R R R R R

2.1 CPU


[Bits 2 to 0] IL0, IL1, IL2: Interrupt level setting bits

These bits are used to set interrupt levels. Each bit is read/write enabled and sets the interrupt level of the corresponding internal resource. The initial value after reset is ‘7’ (no interrupt). For the relation between interrupt level setting bits and interrupt levels, see Table 2.1.13.

Table 2.1.13 Relation between Interrupt Level Setting Bits and Interrupt Levels

[Bit 3] ISE: Extended Intelligent I/O Service Enable Bit

This bit is used to enable EI2OS. It is read/write enabled, and is set to ‘1’ to enable EI2OS when an interrupt is generated. A setting of ‘0’ will start the interrupt sequence. Also, when EI2OS ends (either by count end or internal resource-controlled end) the ISE bit is set to ‘0.’ If the corresponding internal resource has no EI2OS function, a software instruction must be used to set the ISE bit to ‘0.’

The value is initialized to ‘0’ at a reset.

IL2 IL1 IL0 Level value

0 0 0 0 (highest priority interrupt)

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6 (lowest priority interrupt)

1 1 1 7 (no interrupt)

2.1 CPU

47

[Bits 7 to 4] ICS3 to ICS0: Extended Intelligent I/O Service Channel Select Bits

These bits are used to select EI2OS channels. Each is write-only, and designates an EI2OS channel. The values defined by these bits determine the address of the corresponding extended intelligent I/O service descriptor (ISD). The ICS bits are initialized to ‘0000’ at a reset.

Table 2.1.14 shows the relation between the ICS bits and corresponding channel numbers and descriptor (ISD) addresses.

Table 2.1.14 ICS Bit Values, Channel Numbers, and Descriptor Addresses

ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address

0 0 0 0 0 000100H

0 0 0 1 1 000108H

0 0 1 0 2 000110H

0 0 1 1 3 000118H

0 1 0 0 4 000120H

0 1 0 1 5 000128H

0 1 1 0 6 000130H

0 1 1 1 7 000138H

1 0 0 0 8 000140H

1 0 0 1 9 000148H

1 0 1 0 10 000150H

1 0 1 1 11 000158H

1 1 0 0 12 000160H

1 1 0 1 13 000168H

1 1 1 0 14 000170H

1 1 1 1 15 000178H

2.1 CPU


[Bits 5 to 4] S1, S0: Extended Intelligent I/O Service Status Bits

These are the EI2OS status bits. Each is read-only, and can be read to learn the EI2OS operating status and end status. Values are initialized to ‘00’ at a reset.

Table 2.1.15 indicates the relation between the S bits and EI2OS status.

Table 2.1.15 S Bits and EI2OS Status

Extended Intelligent I/O Service Descriptor (ISD)

The extended intelligent I/O service descriptor is located at internal RAM addresses 000100H to 00017FH, and is composed of the following.

• Control data for data transfer

• Status data

• Buffer address pointer

Figure 2.1.30 shows the configuration of the extended intelligent I/O service descriptor.

Fig. 2.1.30 Configuration of the Extended Intelligent I/O Service Descriptor

S1 S0 EI2OS Status

0 0 EI2OS operating or not started

0 1 Stop status caused by count end

1 0 Reserved

1 1 Stop status caused by request from internal resource

Data counter (highest 8 bits)

Data counter (lowest 8 bits)

I/O address pointer (highest 8 bits)

I/O address pointer (lowest 8 bits)

EI2OS status

Buffer address pointer (highest 8 bits)

Buffer address pointer (middle 8 bits)

Buffer address pointer (lowest 8 bits)Descriptor top address →

(DCTH)

(IOAH)

(BAPH)

(DCTL)

(IOAL)

(BAPL)

(BAPM)

(ISCS)

H

L

000100H + 8 × ICS

2.1 CPU

49

Data Counter (DCT)

This 16-bit register is used as a counter corresponding to the number of transfer data items. The counter is decremented by 1 after each data transfer. When this counter reaches zero, EI2OS is ended. Figure 2.1.31 shows the configuration of the data counter.

Fig. 2.1.31 Configuration of Data Counter

I/O Register Address Pointer (IOA)

This 16-bit register address pointer is used to indicate the lower address (A15 to A00) of the I/O register transferring data to and from the buffer. The upper address (A23 to A16) is all zeros and can designate any I/O address from 000000H to 00FFFFH. Figure 2.1.32 shows the configuration of the IOA register.

Fig. 2.1.32 Configuration of I/O Register Address Pointer

DCTH DCTL :DCT (indeterminate at reset)

15 14 13 12 11 10 9 8 7 6 5 4 3 12 0

IOAH IOAL :IOA (indeterminate at reset)

15 14 13 12 11 10 9 8 7 6 5 4 3 12 0

2.1 CPU


EI2OS Status Register (ISCS)

This 8-bit register is used to select update/fix handling, as well as transfer data length (byte/word) and transfer direction of the buffer address pointer and I/O register address pointer. Figure 2.1.33 shows the configuration of the ISCS register.

Fig. 2.1.33 Configuration of the ISCS Register

The significance of each bit is defined as follows.

[Bit 4] IF: This bit determines whether the I/O register address pointer is updated or held constant.

0: After data transfer, the I/O register address pointer is updated.

1: After data transfer, the I/O register address pointer is not updated.

[CAUTION] This setting applies to increment updating only.

[Bit 3] BW: This bit indicates the transfer data length.

0: Byte

1: Word

[Bit 2] BF: This bit determines whether the buffer address pointer is updated or held constant.

0: After data transfer, the buffer address pointer is updated.

1: After data transfer, the buffer address pointer is not updated.

[CAUTION] Updating changes only the lower 16 bits of the buffer address pointer. This setting applies to increment updating only.

[Bit 1] DIR: This bit indicates data transfer direction.

0: I/O address pointer → buffer address pointer

1: Buffer address pointer → I/O address pointer

[Bit 0] SE: This bit controls the end of extended intelligent I/O service by request from internal resources.

0: No end by request from internal resources

1: End by request from internal resources

:ISCS (undefined at reset)Reserved Reserved Reserved IF BW BF DIR SE

7 6 5 4 3 2 1 0

2.1 CPU

51

Buffer Address Pointer (BAP)

This 24-bit register stores addresses to be used for next transfer to be executed by the EI2OS. A separate BAP exists for each EI2OS channel, so that each EI2OS channel can execute transfer to any portion of the entire 16-Mbyte memory space. When the BF bit in the ISCS register is set to ‘update enable,’ only the lower 16 bits of the BAP register will be updated, and the BAPH field will not be changed.

Figure 2.1.34 shows the configuration of the BAP register.

Fig. 2.1.34 Configuration of Buffer Address Pointer

Figure 2.1.35 shows the operating flow of EI2OS, and Figure 2.1.36 shows the sequence of EI2OS operation by the user.

BAPM :BAP (undefined at reset)

(R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 12 023 22 21 20 19 18 17 16

BAPL

(R/W)

BAPH

(R/W)

2.1 CPU


Fig. 2.1.35 Flow of EI2OS Operation

Read ISD/ISCS

End request

Data indicated by IOA⇓ (data transfer)

To memory indicated by BAP

Memory indicated by BAP⇓ (data transfer)

To memory indicated by IOA

Update value

Update BAP

Interrupt sequence

BAP: Buffer address pointerI/OA: I/O address pointerISD: EI2OS descriptor

ISCS: EI2OS statusDCT: Data counterISE: EI2OS enable bit

S1, S0: EI2OSend status

Interrupt request generated from internal resource

ISE=1

Interrupt sequence

DIR=1

IF=0

Update IOA

BF=0

Decrement DCT

Set S1, S0 to ‘00’

Clear resourceinterrupt request

Resume CPU operation

Set S1, S0 to ‘01’ Set S1, S0 to ‘11’

Clear ISE to “0”

DCT=00

SE=1

NO

YES

YES

NO

NO

YES

YES

NO

YES

NO

YES

NO

determinedby BW

Update value determinedby BW

from resource?

(-1)

2.1 CPU

53

Fig. 2.1.36 Flow of User Operation for EI2OS

Processing by Software Processing by Hardware

Start

Initial settings

Set system stack area

Set EI2OS descriptor

Initialize internal resource

Set ICR in interrupt controller

Set internal resource

Set ILM, and I registers in PS

Execute user program(Interrupt request) and (ISE=1)

Transfer data

Determine branch to

(Branch to interrupt vector)

Reset extended intelligent

Process data in buffer

operating start Set interrupt enable bit

interrupt due to count-out or end request from resource

I/O service (switch channel, etc.)

RETI

NO

YES

S1,S0 = ‘01’ orS1,S0 = ‘11’

S1,S0 = ‘00’

2.1 CPU


Exception Processing

The F2MC-16L core provides exception processing for exceptions arising from the following causes.

(1) Execution of undefined instructions

Exception processing is fundamentally the same as interrupt processing, in that exception processing departs from normal processing at the point where the occurrence of an abnormal condition is detected at the boundary between instructions. In general, exception processing occurs as a result of an unexpected operation, and its use is recommended only in debugging or for startup of recovery software in emergency situations.

Exceptions Occurring from Execution of Undefined Commands

The F2MC-16L considers all codes not defined on the instruction map to be undefined instructions. Execution of undefined instructions is handled as the equivalent of the software interrupt instruction ‘INT 10.’ This means that after the contents of the AL, AH, DPR, DTB, ADB, PCB, PC and PS registers are saved to the system stack, the I flag is set to ‘0,’ the S flag is set to ‘1’ and the program branches to the vector indicated by interrupt number 10. The value of register PC that is saved to the stack will be the address containing the undefined instruction. For this reason, recovery using the RETI instruction is possible but meaningless since another exception will occur immediately.

2.1.5 Standby Control Register AccessThe MB90660A series microcontroller can be placed in any of its low-power consumption modes (stop mode and sleep mode) by writing to the power saving mode control register, provided that the instructions used are those shown in Table 2.1.16. Note however that operation of the MB90660A series microcontroller is not warranted if instructions other than those listed in Table 2.1.16 are used to place the chip in low-power consumption modes. When the low-power consumption mode control register is used to control functions other than change to low-power consumption modes, any instructions may be used.

When using word-length values to write to the low-power consumption mode control register, be sure to write to even numbered addresses. Attempting transition to low-power consumption modes by writing to odd numbered addresses may cause abnormal operation.

Table 2.1.16 Commands Used for Transition To Low-power Consumption Modes

MOV io,#imm8 MOV dir,#imm8 MOV eam,#imm8 MOV eam,Ri

MOV io,A MOV dir,A MOV addr16,A MOV eam,A

MOV @RLi+disp8,A MOVP addr24,A

MOVW io,#imm16 MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi

MOVW io,A MOVW dir,A MOVW addr16,A MOVW eam,A

MOVW @RLi+disp8,A MOVPWaddr24,A

SETB io:bp SETB dir:bp SETB addr16:bp

2.2 Maps

55

2.2 Maps

This section describes the allocation of MB90660A series memory space, I/O space, I/O space and the assignment of interrupt numbers.

2.2.1 Memory Space by ModeThe MB90660A memory space is shown in Fig. 2.2.1.

Fig. 2.2.1 MB90660A Memory Space Allocation

Model Address #1 Address #2 Address #3

MB90662A FF8000H 008000H 000780H

MB90663A FF4000H 004000H 000900H

MB90P663A FF4000H 004000H 000900H

MB90V660A (FE0000H) 004000H 001100H

ROM area

Peripherals

: Internal

: No access

RegistersRAM

FFFFFFH

Address #1

FF0000H

00FFFFH

Address #2

Address #3

000100H0000C0H

000000H

(image of bank FF)

ROM area

Single Chip Mode

Bank FF

Bank 00

2.2 Maps


The image of the bank FF ROM area appears in the upper portion of bank 00, in order to facilitate efficient use of the C compiler small model. The same is done with the lower 16 bits, so that it is possible to reference tables in ROM without designating a ‘far’ parameter in the pointer declaration.

For example, if address 00C000H is accessed what is actually accessed is the contents of ROM at FFC000H.

The MB90V660A allows the image of addresses FF4000H to FFFFFFH to be viewed in bank 00, and the image of addresses FE0000H to FF3FFFH can be viewed in bank FE and FF only.

[CAUTION] The MB90660A series has been designed to operate in single-chip mode only, and therefore can access only its own internal ROM, internal RAM and internal peripheral resources.

2.2 Maps

57

2.2.2 I/O MapThe following table provides an I/O map of the MB90660A series microcontroller.

Table 2.2.1 MB90660A I/O Map (1)

Address RegisterAbbrevia-

tionAccess Resource Name Initial Value

000000H Port 0 data register PDR0 R/W* Port 0 XXXXXXXX



000003H Port 3 data register PDR3 R/W* Port 3 ----XXXX

000004H Port 4 data register PDR4 R/W! Port 4 XXXXXXXX

000005H Port 5 data register PDR5 R/W* Port 5 11111111

000006H Port 6 data register PDR6 R/W* Port 6 -XXXXXXX

000007H to

00000FH

Open – *1 – –

000010H Port 0 direction register DDR0 R/W Port 0 00000000



000013H Port 3 direction register DDR3 R/W Port 3 ----0000

000014H Port 4 direction register DDR4 R/W Port 4 ----0000

000015H Analog input enable register ADER R/W Port 5 11111111

000016H Port 6 direction register DDR6 R/W Port 6 -0000000

000017H to

00001BH

Open – *1 – –

00001CH to

00001FH

System reserved area – *1 – –

000020HPWM operating mode control reg-ister

PWMC R/W

PWM

00000--1

000021H Open *1 –

000022H

PWM reload registerPRLL R/W XXXXXXXX

000023H PRLH R/W XXXXXXXX

2.2 Maps


000024H Serial mode register SMR R/W!

UART

00000-00

000025H Serial control register SCR R/W! 00000100

000026HInput data register/output data register

SIDR/SODR

R/W XXXXXXXX

000027H Serial status register SSR R/W! 00001-00

000028H Interrupt enable register ENIR R/W External interrupt 00000000

000029H Interrupt source register EIRR R/W

External interrupt

XXXXXXXX

00002AH

Interrupt level setting register ELVR R/W00000000

00002BH 00000000

00002CH

A/D controller status register ADCS R/W!

A/D converter

00000000

00002DH 00000000

00002EH

A/D data register ADCR R/W!XXXXXXXX

00002FH 000000XX

000030H

Control status register TMCSR0 R/W

16-bit reload timer 0

00000000

000031H ----0000

000032H 16-bit timer register / 16-bit reload timer register

TMR0/TMRLR0

R/WXXXXXXXX

000033H XXXXXXXX

000034H



00000000

000035H ----0000

000036H 16-bit timer register / 16-bit reload timer register

TMR1/TMRLR1

R/WXXXXXXXX

000037H XXXXXXXX

000038H



00000000

000039H ----0000

00003AH 16-bit timer register / 16-bit reload timer register

TMR2/TMRLR2

R/WXXXXXXXX

00003BH XXXXXXXX

00003CH



00000000

00003DH ----0000

00003EH 16-bit timer register / 16-bit reload timer register

TMR3/TMRLR3

R/WXXXXXXXX

00003FH XXXXXXXX




2.2 Maps

59

000040H Timer control status register TCSR R/W!


10000000

000041H Compare interrupt control register CICR R/W 00000000

000042H Timer mode control register TMCR R/W! 001-0000

000043H Compare/data switching register COER R/W ----0000

000044HCompare buffer mode control reg-ister

CMCR R/W ----10000

000045HZero-detection output control reg-ister

ZOCTR W ---X0000

000046H Output control buffer register OCTBR R/W 11111111

000047HZero-detection interrupt control register

ZICR R/W! 0---XXXX

000048H

Output compare buffer register 0 OCPBR0 WXXXXXXXX

000049H --XXXXXX

00004AH


00004BH --XXXXXX

00004CH


00004DH --XXXXXX

00004EH


00004FH --XXXXXX

000050H

Compare-clear buffer register CLRBR W00000000

000051H --000000

000052H Dead-time control register DTCR R/W! 00000000

000053H Dead-time setting register DTSR W XXX0XXXX

000054H Dead-time compare register DTCMR W XXXXXXXX

000055H Open – *1 – –

000056H

Timer pin control register TPCR R/W 16-bit reload timer-001-000

000057H -011-010

000058H to

00005EH

Open – *1 – –




2.2 Maps


00005FHMachine clock multiplier control register

CDCR W UART ----1111

000060H to

00008FH

Open – *1 – –

000090H to

00009EH


00009FHDelay interrupt source generation/release register

DIRR R/WDelay interrupt generation module

-------0

0000A0HLow-power consumption mode control register

LPMCR R/W!Low-power consumption

00011000

0000A1H Clock control register CKSCR R/W! 11111100

0000A2H to

0000A7H


0000A8H Watchdog timer control register WDTC R/W! Watchdog timer X-XXX111

0000A9H Timebase timer control register TBTC R/W! Timebase timer 1--00100

0000AAH to

0000AFH

Open – *1 – –

0000B0H Interrupt control register 00 ICR00 R/W!


00000111

0000B1H Interrupt control register 01 ICR01 R/W! 00000111










2.2 Maps

61

Note 1: Access prohibited

Note 2: The notation R/W! in the access column indicates registers having one or more read-only or write-only bits. For details, refer to the register listing under each individual resource.

Note 3: The notation R/W!, R/W* or W in the access column indicates registers in which access by read-modify-write instructions (bit set instructions, etc.) yields the designated value in the particular bit(s) accessed, but which also contain other bits having write-only access, which may cause abnormal operation if unintentionally accessed. Access by such instructions should therefore be avoided.

Description of initial values

[0]: ......... This bit is initialized to value 0.

[1]: ......... This bit is initialized to value 1.

[*]: ......... This bit is initialized to value 1 or 0, according to the level of the MD0 to MD2 bits.

[X]: ........ Initial value of this bit is undefined.

[-]: .......... This bit is not used. Initial value undefined.

[CAUTION] Write-only bits are initialized after reset to the value indicated in as the ‘initial value.’ Users should take care to note that this is not the read value.Also, the LPMCR, CKSCR and WDTC registers may be initialized or not depending on the type of reset applied. The initial value shown is applied only when these registers are initialized.

0000B8H Interrupt control register 08 ICR08 R/W!


00000111


0000BAH Interrupt control register 10 ICR10 R/W! 00000111

0000BBH Interrupt control register 11 ICR11 R/W! 00000111

0000BCH Interrupt control register 12 ICR12 R/W! 00000111

0000BDH Interrupt control register 13 ICR13 R/W! 00000111

0000BEH Interrupt control register 14 ICR14 R/W! 00000111

0000BFH Interrupt control register 15 ICR15 R/W! 00000111

0000C0H to

0000FFH





2.2 Maps


2.2.3 Interrupt Vector AllocationThe following table shows the allocation of MB90660A interrupt vectors.

Table 2.2.2 MB90660A Interrupt Vector Allocation

[CAUTION] indicates support for I2OS (no stop request), indicates I2OS support (with stop request), × indicates no I2OS support. Do not make the I2OS startup settings for ICRxx if I2OS is not supported.

Interrupt sourceRelation to I2OS

Interrupt vectorInterrupt control

register

Number Address ICR Address

Reset × #08 08H FFFFDCH – –

INT 9 instruction × #09 09H FFFFD8H – –

Exception × #10 0AH FFFFD4H – –

Multi-function timer DTTI input × #12 0CH FFFFCCH ICR00 0000B0H

External interrupt #0 #13 0DH FFFFC8HICR01 0000B1H

External interrupt #4 #14 0EH FFFFC4H

Multi-function timer trigger input/zero-detection

#15 0FH FFFFC0H ICR02 0000B2H

Multi-function timer zero-detection #17 11H FFFFB8H ICR03 0000B3H

Multi-function timer overflow/compare clear/zero-detection

#19 13H FFFFB0H ICR04 0000B4H

External interrupt #1 #21 15H FFFFA8HICR05 0000B5H

Multi-function timer compare match × #22 16H FFFFA4H

External interrupt #5 #23 17H FFFFA0HICR06 0000B6H

PWM underflow × #24 18H FFFF9CH

External interrupt #2 #25 19H FFFF98HICR07 0000B7H

External interrupt #6 #26 1AH FFFF94H

16-bit reload timer #0 #27 1BH FFFF90HICR08 0000B8H

16-bit reload timer #1 #28 1CH FFFF8CH

16-bit reload timer #2 #29 1DH FFFF88HICR09 0000B9H

16-bit reload timer #3 #30 1EH FFFF84H

A/D conversion end #31 1FH FFFF80H ICR10 0000BAH

Timebase timer interval interrupt × #34 22H FFFF74H ICR11 0000BBH

UART send completed #35 23H FFFF70H ICR12 0000BCH

UART receive completed #37 25H FFFF68H ICR13 0000BDH

External interrupt #3 #39 27H FFFF60HICR14 0000BEH

External interrupt #7 #40 28H FFFF5CH

Delay interrupt generator module × #42 2AH FFFF54H ICR15 0000BFH

2.2 Maps

63

2.2.4 Clock Signal Feed Map

Fig. 2.2.2 Clock Signal Feed Map

[CAUTION] The functions of the reload timer I/O pins (TIM0 to TIM3) can be determined by selecting up to 4 timer outputs and up to 4 timer inputs (8 possibilities) but only to a maximum of 4 pins.Thus it is not possible to use all four channels for input and output at the same time.

PWMPeripheral clock Output enable

Sel

ecto

r (

*ca

utio

n)

Clock inputClock input PWM output

Reload timer: ch0Peripheral clock Timer output

Timer input


Timer input


Timer input

UARTPeripheral clock Timer input

External clock PWM output

Multi-function timerPeripheral clock RT0 output

A/D converterPeripheral clock Trigger input

Timebase timer Timebase timer output (4x multiplier) Timebase timer output (512x multiplier)


Timer input

Peripheral clock outputPeripheral clock selection circuit

PLL circuit

Main oscillator circuit

fc/2

fc

fcX0

X1

SCK

PWM

TIM0

TIM1

TIM2

TIM3

2.3 Parallel Ports


2.3 Parallel Ports

The MB90660A series microcontroller provides 39 I/O ports, 4 input ports, and 8 open-drain output-only pins. Ports 0, 1, 2, 3, and 6 are I/O ports, functioning as input ports when the corresponding direction register has the value ‘0’ and as output ports when it has the value ‘1.’

Port 5 is an open-drain port, functioning as a port when the analog input enable register has the value ‘0.’

Ports 40 to 43 are I/O ports functioning as input ports when the corresponding direction register has the value ‘0’ and as output ports when it has the value ‘1.’ Ports 44 to 47 are input ports, used for read-only functions.

2.3.1 Register List

[CAUTION] Port 3 bits 15 to 12 have no register bit.Port 6 bit 7 has no register bit.Port 4 bits 7 to 4 are read-only.

PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0

Port data register

Address : PDR1 000001H

⇐Bit no.

Read/write⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value⇒ (X) (X) (X) (X) (X) (X) (X) (X)

PDR3 000003H

15 14 13 12 11 10 9 8

PDRx


⇐Bit no.


Port data register


PDR2 000002H

PDR4 000006H

7 6 5 4 3 2 1 0

PDRx

RD57 RD56 RD55 RD54 RD53 RD52 RD51 RD50

Port data register

Address : 000005H

⇐Bit no.

Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value ⇒ (1) (1) (1) (1) (1) (1) (1) (1)

15 14 13 12 11 10 9 8


⇐Bit no.

Read/write ⇒ (R) (R) (R) (R) (R/W) (R/W) (R/W) (R/W)Initial value ⇒ (X) (X) (X) (X) (X) (X) (X) (X)

Port data registerAddress : 000004H

7 6 5 4 3 2 1 0

PDR4

PDR5

2.3 Parallel Ports

65

[CAUTION] Port 3 bits 15 to 12 have no register bit.Port 4 bits 7 to 4 have no register bit.Port 5 has no DDRPort 6 bit 7 has no register bit.

DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0

Port direction register

Address : DDR1 000011H

⇐Bit no.


DDR3 000013H

15 14 13 12 11 10 9 8


⇐Bit no.




DDR2 000012H

7 6 5 4 3 2 1 0

DDRxDDR4 000014H

DDR6 000016H

DDRx

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

⇐Bit no.


Analog input enable register

Address : 000015H

15 14 13 12 11 10 9 8

ADER

2.3 Parallel Ports


2.3.2 Block Diagrams I/O Ports

Fig. 2.3.1 I/O Port Block Diagram

Open-drain Ports (Also Serve as Analog Input Ports)

Fig. 2.3.2 Open-drain Port Block Diagram

Input Port

Fig. 2.3.3 Input Port Block Diagram

Internal data bus

Data register read

Direction register write

Data register write

Direction register read

Data register

Direction register

Pin

Internal data bus

Data register read

ADER register write

Data register write

ADER register read

Data register

A D E R

Pin

RMW (read-modify-write instruction)

Internal data bus

Data register read

Pin

2.3 Parallel Ports

67

2.3.3 Detailed Register Descriptions(1) PDR 0, 1, 2, 3, 4, 5, 6 (Port data registers)

Register Allocation

[CAUTION] Port 3 bits 15 to 12 have no register bit.Port 6 bit 7 has no register bit.Port 4 bits 7 to 4 are read-only.

Register Description

All ports other than ports 0, 1 and 5 are provided with individual direction registers that can be used to set their individual signal pins to input or output when the corresponding peripheral resource is set not to use an output pin. When in input mode, reading the data registers allows the pin signal levels to be read, while in output mode, reading the data registers allows the latched data register values to be read. The same is true when using read-modify-write instructions.

When data registers are read for use as control output, the values read will be the values used for control output regardless of the setting of the direction registers.

[CAUTION] When the above registers are accessed using read-modify-write instructions (such as bit set instructions), the target bit will be set to the designated value, however for any other bits set for input the designated input value of the signal pin will be overwritten with the contents of the corresponding output register. For this reason, whenever pins used for input are switched to output, it is first necessary to write the desired values in the PDR register before setting the DDR register to switch to output.


Port data register


⇐Bit no.


PDR3 000003H

15 14 13 12 11 10 9 8

PDRx


⇐Bit no.


Port data register


PDR2 000002H

PDR6 000006H

7 6 5 4 3 2 1 0

PDRx


Port data register

Address : 000005H

⇐Bit no.


15 14 13 12 11 10 9 8


⇐Bit no.

Read/write ⇒ (R) (R) (R) (R) (R/W) (R/W) (R/W) (R/W)Initial value ⇒ (X) (X) (X) (X) (X) (X) (X) (X)

Port data registerAddress : 000004H

7 6 5 4 3 2 1 0

PDR4

PDR5

2.3 Parallel Ports


[CAUTION] The process of reading from and writing to I/O ports differs from reading from and writing to memory in the following ways.

Input Mode

Reading: The read value is the signal level of the corresponding pin.

Writing: The write data is stored in the output latch, and cannot be output to the pin.

Output Mode

Reading: The read value is the value stored in the PDR register.

Writing: The write data is stored in the output latch, and can also be output to the pin.

[CAUTION] Port 4 pins 7 to 4 are input-only pins, and can only be used to read the incoming signal level.

[CAUTION] Note also that read/write operations for ports 4 and 5 differ from those for other ports.

Port 5 (P57 to P50) is an open-drain type general-purpose I/O port which is designed to also function as an analog input signal pin. When used as a general-purpose port, the bit(s) corresponding to the ADER register must be set to ‘0.’

When port 5 is used as an input port, the entire contents of the output data register must be set to ‘1’ in order to turn off all open-drain output transistors, and external pull-up resistor must be mounted. Also, for read access, one of the following two operations should be followed depending on the instruction used.

When reading using read-modify-write instructions

⇒ Read the contents of the output data register. Even when each pin is externally driven to ‘0’ there should be no change, even to contents of bit(s) not designated by the instruction.

For reading using all other instructions

⇒ The level of each signal pin can be read.

When used as an output port, pin values can be changed by writing the desired value to the corresponding output data register.

Also, the pin corresponding to the bits set to ‘1’ in the analog input enable register allows the data ‘0’ to be read.

2.3 Parallel Ports

69

(2) DDR 0, 1, 2, 3, 4, 6 (Port direction registers)

Register Allocation

[CAUTION] Port 3 bits 15 to 12 have no register bit.Port 4 bit 7 has no register bit.Port 5 has no DDR.Port 6 bit 7 has no register bit.


When the corresponding signal pins are functioning as ports, the function of each pin is controlled as follows.

0: Input mode

1: Output mode

Values are initialized to ‘0’ at a reset.

[CAUTION] Port 6 should be placed in output mode when it is used as a multi-function timer output pin.

(3) ADER (Analog input enable register)


Port 5 signal pins are controlled as follows.

0: Port input mode

1: Analog input mode

The reset value is ‘1.’

[CAUTION] Be sure to select analog input mode whenever this port is used for analog input. This is because input of intermediate-level signals in port input mode will produce leak current.




⇐Bit no.


DDR3 000013H

15 14 13 12 11 10 9 8


⇐Bit no.




DDR2 000012H

7 6 5 4 3 2 1 0

DDRxDDR4 000014H

DDR6 000016H

DDRx

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0⇐Bit no.



Address : 000015H

15 14 13 12 11 10 9 8

ADER

2.4 Multi-Function Timer



2.4.1 OverviewThe multi-function timer controls up to 7 real-time output pins, and incorporates the following functions.

• Interval Timer Function

Produces pulse output or interrupt signal at fixed time intervals.

• PWM Output Function

Produces a fixed-period pulse with duty factor (ratio of ‘L’ output width to ‘H’ output width) varied in real-time.

• Three-Phase AC Sine Wave Approximation Output (Interval Control Output) Function

Produces an approximation of 3-phase AC sine wave output (with variable setting for non-overlapping intervals) as used in AC motor interval controls.

The multi-function timer also provides the following features:

• 14-bit Timer for Pulse Period Control

A prescaler provides a clock source signal selection of 1/2/8/16 machine cycles (minimum resolution: 62.5 ns at 16 MHz operation).

For AC motor control applications, carrier frequencies up to 30 kHz are available in 8-bit steps.

The selection of count modes includes up-count only or up/down count mode.

A buffer is provided, which can be used with the zero-detection feature to transfer from the buffer enabling period length adjustment in real-time.

• Compare Register for Duty Factor Control

The MB90660A has four compare registers enabling independent output pulse duty on individual four channels.

Each channel has a buffer, which can be used with the zero-detection feature to trigger buffer output enabling period length adjustment in real-time.

• Dead-time Timer for Non-Overlapping Control

The dead-time timer provides the ability to generate 3-channel PWM output in addition to non-overlapping inverted signals. This enables generation of AC motor control waveforms (U, V, W, X, Y, Z).

A prescaler provides, as dead-time timer clock source, signal selection of 1/2/8/16 machine cycles (minimum resolution: 62.5 ns at 16 MHz).

• DTTI Pin Input for Forced Stop Control

The DTTI pin input signal can be used together with software to forcibly fix pin output levels.

This input signal can be used for inactive period control in AC motor control applications.

The use of a clockless DTTI pin input signal enables pin control from external sources even when the MB90660A oscillator is stopped.

• Flag Set for Event Detection and Interrupt Generation

The 14-bit timer has a flag set used for zero detection and interrupt generation in case of overflow, compare clear register matching, TRG pin input signal clearing or matching with any of the 4-channel compare registers (interrupt output disable settings also available).


71

2.4.2 Register List

8 bit

R/W Timer control status register

R/W Compare interrupt control register

R/W Timer mode control register

R/W Compare/data switch register

R/W Compare buffer mode control register

W Zero detect output control register

Output control register

R/W Output control buffer register

R/W Zero detect interrupt control register

Output compare registers 0 to 3

W Output compare buffer registers 0 to 3

W Compare clear register

W Compare clear buffer register

R/W Dead-time timer control register

W Dead-time setting register

W Dead-time compare register

W Port data buffer register

Address : 000040H

Address : 000041H

Address : 000042H

Address : 000043H

Address : 000044H

Address : 000045H

Address : 000046H

Address : 000047H

Address : 000048H

Address : 00004FH

Address : 000050H : 000051H

Address : 000052H

Address : 000053H

Address : 000054H

Address : 000006H

TCSR

CICR

TMCR

COER

CMCR

ZOCTR

DTCR

DTSR

DTCMR

OCTR

OCTBR

ZICR

14 bit

OCPR0 to 3

⇑

⇑

CLRR

CLRBR

14 bit

PDBR

OCPBR0 to 3to



2.4.3 Block Diagram

2.4.3.1 Timer/Waveform Generator Unit Block Diagram

Fig. 2.4.1 Multi-Function Timer Block Diagram (1)

Invert or clear

TRG

14-bit timer Count clock

Timer clear interruptZero detect interruptTimer interruptCompare interrupt

Zero detect Set, reset

Set, reset, transfer RT0

Transfer request

CLRR, CLRBR

Comparator

(external input signal)

STCR, TMST, MODECES1, 0TCS1, 0

Prescaler (1, 2, 8, 16 machine cycles)

Zero detect

ZOSC, IME, CYC3 to 0Zero detect interrupt mask

Zero detect pin controlZSB0

Comparator, pin controlRO01, 0

OCPR0, OCPBR0

(external output)

PDR6PD66

Set, reset




OCPR1, OCPBR1

(to output selection

PDR0PD60

Set, reset




OCPR2, OCPBR2

(to outputselection

PDR1PD61

Set, reset




OCPR3, OCPBR3

(to outputselection

PDR2PD62

unit)

unit)

unit)Buffer transfer controlTREN, TMSK, BFS1, 0

14

Interrupt control

IIOSSTCIE, TCIRTZIE, TZIRTMIE, TMIRCIE3 to 0, CIR3 to 0


73

2.4.3.2 Output Select/Dead-time Generator Unit Block Diagram

Fig. 2.4.2 Multi-Function Timer Block Diagram (2)

DTTI interrupt DTTI interrupt

Flag set

DTTI

Inactive

RT2

ComparatorCompare

Count clock

Divide ratio

Active level

Mode selection

DTIE, DTIF

DTTI controlTOCE, TOC1, 0NRSL

(external signal)

(from waveform generator unit)

8-bit timer

Pre-scaler

Dead-timewaveform

Selector

generator

selection

P61/RT2/V

P64/Y

(external output)

Inactive

RT1

ComparatorCompare

Count clock

Divide ratio

Active level

Mode selection


8-bit timer

Pre-scaler

Dead-timewaveform

Selector

generator

selection

P60/RT1/U

P63/X

(external output)

Inactive

RT3

ComparatorCompare

Count clock

Divide ratio

Active level

Mode selection


8-bit timer

Pre-scaler

Dead-timewaveform

Selector

generator

selection

P62/RT3/W

P65/Z

(external output)

Waveform controlDMOD, DT1, 0DCS1, 0DTCMR

W

Z

V

X

U

X

8



2.4.4 Detailed Register Descriptions(1) Timer Control Status Register (TCSR)

This register controls software timer clear, clear interrupt from triggered input, zero detect interrupt, and overflow/compare-clear-match interrupt processing.

[Bit 7] STCR: Software timer clear bit

This bit initializes the timer.

Writing ‘0’ to this bit initializes the timer and the internal prescaler.

Writing ‘1’ to this bit is ignored and has no effect.

The read value is always ‘1.’

[Bit 6] IIOS: EI2OS interrupt function extension bit

This bit extends the interrupt functions for timer zero detection events.

Writing ‘1’ to this bit causes the TCIR bit and TMIR bit to have the same functions as the TZIR bit. Thus when a zero-detect event occurs, not only the TZIR but also the TCIR and TMIR bits will be simultaneously set to ‘1’ with the result that zero detection can start EI2OS on 3 channels of the OCPBR register.

This bit should only be overwritten when the timer is stopped. Also, if this bit is overwritten, the TCIR, TZIR and TMIR sources should be cleared before the respective interrupts are enabled.

[Bit 5] TCIE: Timer clear interrupt enable bit

This bit enables the timer clear interrupt request from an external trigger (TRG pin) input signal.

STCR Operation

0 Clear timer and prescaler

1 No operation

IIOS Description

0 Zero detection sets only the TZIR bit to ‘1’

1 Zero detection sets TZIR, TCIR and TMIR bits to ‘1’

TCIE Description

0 Disable timer clear interrupt request from external trigger input

1 Enable timer clear interrupt request from external trigger input

STCR IIOS TCIE TCIR TZIE TZIR TMIE TMIRInitial value

R/W R/W R/W R/W

TCSR7 6 5 4 3 2 1 0

10000000BAddress : 000040H

W R/W R/W R/W

bit


75

[bit 4] TCIR: Timer clear interrupt request flag

This flag indicates an interrupt request at the time the timer is cleared as a result of an external trigger (TRG pin) signal input.

The flag is set to ‘1’ when the timer is cleared as a result of an external trigger (TRG pin) signal input.

When the IIOS bit is ‘1’ this flag is set to ‘1’ when a zero-detect event occurs. Once this setting is made, the flag cannot be set to ‘1’ by clearing the timer.

To clear this bit, write '0' or clear by EI2OS.

Writing ‘1’ to this bit is ignored and will not change the bit value.

For read-modify-write instructions, the read value is always ‘1.’

[Bit 3] TZIE: Zero detect interrupt enable bit

This bit enables an interrupt request to be generated by a zero-detect event.

[Bit 2] TZIR: Zero detect interrupt request flag

This flag indicates a timer zero-detect interrupt request.

This bit is set to ‘1’ when a timer zero-detect event occurs.

To clear this bit, write ‘0’ or clear by EI2OS.

Writing ‘1’ to this bit has no effect, and will not change the bit value.


[Bit 1] TMIE: Timer interrupt request enable bit

This bit enables the timer overflow interrupt request, and the CLRR register match detect interrupt request.

TCIR Flag setting

0 No timer clear interrupt request from external trigger signal input

1 Timer clear interrupt request from external trigger signal input

TZIE Description

0 Zero detect interrupt request disabled

1 Zero detect interrupt request enabled

TZIR Flag setting

0 No zero detect interrupt request

1 Zero detect interrupt request

TMIE Description

0 Disable overflow/compare-clear-match detect interrupt request

1 Enable overflow/compare-clear-match detect interrupt request



[Bit 0] TMIR: Timer overflow/compare-clear-match interrupt request flag.

This flag indicates a timer overflow/compare-clear-match interrupt request.

This bit is set to ‘1’ by a timer overflow, or a match between the CLRR register and timer value.

When the IIOS bit is ‘1’ this bit is set to ‘1’ when a timer zero-detect event occurs. Once this setting is made, the flag cannot be set to ‘1’ by a timer overflow or match between the CLRR register and timer value.

To clear this bit, write ‘0’ or clear by EI2OS.



TMIR Flag setting

0 No interrupt request from overflow/compare-clear-match

1 Interrupt request from overflow/compare-clear-match


77

(2) Compare Interrupt Control Register (CICR)

This register controls interrupts due to matches between OCPR register and timer value, for each channel separately. Interrupt requests sent to the CPU are OR-linked results of interrupt requests on the four channels.

[Bits 15 to 12] CIE3 to CIE0: Compare-match interrupt request enable bits

CIE3: Interrupt request enable bit for CIR3




[Bits 11 to 8] CIR3 to CIR0: Compare-match interrupt request flag

These bits are set to ‘1’ when a match is detected between the corresponding OCPR register value and timer value.

To clear these bits, write ‘0’ or clear by EI2OS.

Writing ‘1’ to these bits has no effect, and will not change the bit value.


Each of the four bits corresponds to an OCPR register as follows.

CIR3: set to ‘1’ when a match is detected between the value of output compare register 3 (OCPR3) and the timer value.




CIEx Description

0 Disable compare-match interrupt request

1 Enable compare-match interrupt request

CIRx Flag setting

0 No compare-match interrupt request

1 Compare-match interrupt request

CIE3 CIE2 CIE1 CIE0 CIR3 CIR2 CIR1 CIR0Initial value

R/W R/W R/W R/W

CICR15 14 13 12 11 10 9 8

00000000BAddress : 000041H

R/W R/W R/W R/W

bit



(3) Timer Mode Control Register (TMCR)

This register determines the timer operating mode selection, timer start/stop setting, count clock selection and trigger input edge selection.

*1: The bit with the asterisk (∗) accepts only the first write value after reset.

*2: Access by read-modify type instructions may cause abnormal operation and should not be attempted with this register.

[Bit 7] TMST: Timer start/stop bit

This bit controls timer start/stop.

When the timer is started, the prescaler is initialized and count operations started.

[Bit 6] MODE: Timer count mode setting bit

This bit selects timer operation when a compare-clear-match occurs.

This bit is provided with a buffer, and can be overwritten at any time whether the timer is operating or stopped.

While the timer is operating, values are written to the buffer and the count mode is changed at the first zero-detection after writing.

Values are transferred from the buffer at every zero detection, whether or not the zero detection interrupt is masked.

[Bit 5]*: Reserved bit

Always write ‘1’ to this bit.

[Bit 4]: Empty

TMST Operation

0 Stop timer

1 Start timer

MODE Description

0Set timer in up-count mode.Timer is cleared by match, and count operation starts from 0000H.

1Set timer in up/down-count mode.At a match, the timer changes from up-count to down-count.At zero detection, timer changes from down-count to up-count.

TMST MODE ∗ – CES1 CES0 TCS1 TCS0Initial value

R/W R/W R/W R/W

TMCR7 6 5 4 3 2 1 0

001 – 0000BAddress : 000042H

R/W W W∗ ∗

bit


79

[Bits 3, 2] CES1, CES0: External trigger input edge selection bit

This bit selects the edge of the external trigger signal used to clear the timer.

When the selected edge is input, both the timer and prescaler are cleared.

[Bits 1, 0] TCS1, TCS0: Timer count clock selection bit

This bit selects the timer count clock source.

All bits in this register with the exception of the MODE bit should only be overwritten when the timer is stopped. Also, even when the timer is stopped, all bits other than the TMST bit and MODE bit should be set to the same value used at startup.

Note that the CES1, CES0 bits accept as valid data only the first write data after reset. Any second or subsequent data values will be ignored.

CES1 CES0 Edge detection setting for timer clearing

0 0 No operation (timer clear disabled)

0 1 Timer cleared at detection of rising edge

1 0 Timer cleared at detection of falling edge

1 1 Timer cleared at detection of both edges

TCS1 TCS0 Timer clock source

0 0 1 machine cycle

0 1 2 machine cycle

1 0 8 machine cycle

1 1 16 machine cycle



(4) Compare/Data Switching Register

This register is used to set switch between port register output and timer unit-only output.

[Bits 11 to 8] RT3 to RT0: Real-time output pin select bits

These bits are used to switch external pin functions.

(5) Compare Buffer Mode Control Register (CMCR)

This register controls transfer from the buffer register with respect to the OCPR register and CLRR register.

[Bit 3] TREN: Transfer enable bit

This bit enables data transfer to the OCPR register and CLRR register from the respective register buffers according to the conditions established by the buffer mode select bits BFS1, BFS0 (bits 1, 0).

[Bit 2] TMSK: Buffer transfer mask bit for zero detection

When the zero detect interrupt mask function is used, this bit determines whether or not data is transferred from the OCPR register and CLRR register buffers when the zero detect interrupt is masked.

RTOx Description

0 Operate pin as general-purpose port (PDBR output)

1 Operate pin as multi-function timer output

TREN Description

0 Disable transfer from buffer register to compare registers

1 Enable transfer from buffer register to compare registers

TMSK Description

0Execute data transfer from buffer register to compare registers at zero-detection, even when zero detect interrupt masking is used.

1Execute data transfer from buffer register to compare registers at zero detection only when zero detect interrupt is actually generated.

– – – – RTO3 RTO2 RTO1 RTO0Initial value

R/W R/W R/W R/W

COER15 14 13 12 11 10 9 8

----0000BAddress : 000043H

bit

– – – – TREN TMSK BFS1 BFS0Initial value

R/W R/W R/W R/W

CMCR7 6 5 4 3 2 1 0

----1000BAddress : 000044H

bit


81

[Bit 1] BFS1: Buffer mode select bit 1

This bit determines conditions for transferring data to the OCPR register for compare channels 1 to 3 from the buffer.

This bit may not be overwritten during operation.

[Bit 0] BFS0: Buffer mode select bit 0

This bit determines conditions for transferring data to the OCPR register for compare channel 0 from the buffer.

This bit may not be overwritten during operation.

[CAUTION] While the timer is stopped, data values from the buffer are transferred to the compare registers regardless of buffer mode (as long as transfer is enabled).

BFS1 Description

0Transfer from buffer to output compare register when compare-match exists.

1Transfer from buffer to output compare register when count value is 0000H.

BFS0 Description

0Transfer from buffer to output compare register when compare-match exists.

1Transfer from buffer to output compare register when count value is 0000H.



(6) Zero Detect Output Control Register (ZOCTR)

This register controls pin output when the timer value is 0000H.

Note: Access by read-modify type instructions may cause abnormal operation and should not be attempted with this register.

[Bit 12] ZOSC: Zero-detect output control function select bit

This bit determines the operation of real-time output pins under zero-detect conditions. The setting applies to for all pins for which ZSB0 to ZSB3 pin controls are enabled.

When this setting coincides with occurrence of an OCPR register match, the OCPR register match has priority.

[Bits 11 to 8] ZSB3 to ZSB0: Zero-detect control pin select bits

These bits select the real-time output pins that are subject to pin controls under zero-detect conditions. Pins ZSB3 to ZSB0 correspond respectively to pins RT3 to RT0.

ZOSC Description

0 Reset any pin set by ZSB3 to ZSB0 to ‘0’.

1 Set any pin set by ZSB3 to ZSB0 to ‘0’.

ZSBx Description

0 No pin control under zero-detect conditions

1 Pin control under zero-detect conditions

– – – ZOSC ZSB3 ZSB2 ZSB1 ZSB0Initial value

R/W R/W R/W R/W

ZOCTR15 14 13 12 11 10 9 8

----X0000BAddress : 000045H

R/W

bit


83

(7) Output Control Register and Output Control Buffer Register (OCTR, OCTBR)

These registers control the operation of real-time output pins under compare-match conditions.

[Bits 7 to 0] ROx1, ROx0: Real-time output pin function selection bits (X=3, 2, 1, 0)

These bits determine the operation of real-time output pins under OCPR register match conditions.

Up-count mode (MODE=0)

Up/down count mode (MODE=1)

Transfer from buffer registers to control registers when the timer is operating is governed by the buffer mode setting (BFS bit) in the CMCR register. When the timer is stopped, buffer values are transferred to control registers regardless of buffer mode. Note, however, that when transfer is disabled by the TREN bit, no transfer will take place regardless of buffer mode.

ROx1 ROx0 RTx pin operation at compare-match

0 0 Reset to ‘0’

0 1 Set to ‘1’

1 0 Transfer value of PDBR

1 1 No pin control

ROx1 ROx0 RTx pin operation at compare-match

0 0 During up-count: set to ‘0.’ During down-count: set to ‘1.’

0 1 During up-count: set to ‘1.’ During down-count: set to ‘0.’

1 0 Transfer value of PDBR

1 1 No pin control

(In the above table, x=0, 1, 2, 3)

RO31 RO30 RO21 RO20 RO11 RO10 RO01 RO00Initial value

R/W R/W R/W R/W

OCTR

7 6 5 4 3 2 1 0

11111111B

R/W R/W R/W R/W

bit

RO31 RO30 RO21 RO20 RO11 RO10 RO01 RO00

⇑ ⇑ ⇑ ⇑

11111111BOCTBRAddress : 000046H



(8) Zero-Detect Interrupt Control Register (ZICR)

This register controls the function to mask timer zero-detect interrupts for the specified number of times.


[Bit 15] IME: Interrupt mask enable bit

This bit enables a function that masks a specified number of occurrences of the timer zero-detect interrupt source.

When ‘1’ is written to this bit, the zero-detect interrupt source is masked for the number of times specified by the CYC3 to CYC0 bits. Thus the TZIR bit in the TCSR register is not set when an interrupt source occurs. This also has the effect of masking interrupt requests to the CPU.

The masking function can be disabled by setting this bit to ‘0.’

This bit should not be overwritten by read-modify-write instructions.

[Bits 11 to 8] CYC3 to CYC0: Mask count setting register

These bits determine the number of times that the interrupt source will be masked.

Together, these bits configure a 4-bit reload counter, which reloads when the count value reaches 0000B. Count values can also be loaded by writing directly to this register.

The mask count equals the value set in the register, and a register setting of 0000B means that no interrupt sources will be masked.

These bits have a buffer, so that while the timer is operating register values are written to the buffer only and are transferred to the counter only at reload opportunities. When the timer is stopped, values may be overwritten directly to the buffer and counter simultaneously.

IME Description

0 Disable interrupt source mask

1 Enable interrupt source mask

IME – – – CYC3 CYC2 CYC1 CYC0Initial value

W W W W

ZICR 15 14 13 12 11 10 9 8

0---XXXXB

R/W

bit

– – – – CYC3 CYC2 CYC1 CYC0

⇑

----XXXXBZICBRAddress : 000047H

Address : 000047H


85

(9) Output Compare Registers 0 to 3 and Output Compare Buffer Registers 0 to 3 (OCPR0 to OCPR3, OCPBR0 to OCPBR3)

These registers store compare values used to control real-time output pins.

Note: Access by read-modify type instructions may cause abnormal operation and should not be attempted with these registers.

These registers store the values that are compared with the 14-bit timer, and the associated buffer registers.

While the timer is operating, data transfer from the buffer register to the corresponding compare register is controlled by the buffer mode select bits (BFS1, BFS0) in the CMCR register. When the timer is stopped, buffer values may be transferred to compare registers regardless of buffer mode (as long as transfer is enabled).

Also, when using the zero-detect interrupt mask function, the TMSK bit in the CMCR register can be used to determine whether data will be transferred from buffer registers to compare registers while the zero-detect interrupt is masked.

– – CP13 CP12 CP11 CP10 CP09 CP08Initial value

W W W W

OCPR

15 14 13 12 11 10 9 8

--XXXXXXB

W W

bit

– – CP13 CP12 CP11 CP10 CP09 CP08

⇑

--XXXXXXBOCPBRAddress : 00004FH

CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00Initial value

W W W W

OCPR 7 6 5 4 3 2 1 0

XXXXXXXXB

W W W W

bit

CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00

⇑

XXXXXXXXBOCPBRAddress : 00004EH

00004DH

00004BH

000049H

00004CH

00004AH

000048H



(10) Compare Clear Buffer Register and Compare Clear Register (CLRBR, CLRR)

This register and buffer register store compare values used for the compare-clear function.

When the value in this register matches the timer value, the timer is cleared or switches to down-count operation.

While the timer is operating, data is transferred from the buffer register to the compare clear register when the timer value is 0000H. This transfer is controled by the TREN bit in the CMCR register.

Also, when using the zero-detect interrupt mask function, the TMSK bit in the CMCR register can be used to determine whether data will be transferred from buffer registers to compare registers while the zero-detect interrupt is masked.

Note: Access by read-modify type instructions may cause abnormal operation and should not be attempted with these registers.

When a match is detected between the value in this register and the timer value, the timer will be cleared if the MODE bit in the TMCR register is ‘0.’ If the MODE bit is ‘1,’ the timer will switch from up-count to down-count operation.

If the match occurs simultaneously with an OCPR register match, the MB90660A series chip will simultaneously execute both the pin control according to the OCPR register match, and the timer clear function according to the compare-clear match.

If the match occurs simultaneously with an OCPR register match in up/down mode, pin controls will operate during down-counting.

If the value in this register is 0000H, no CLRR register match detect operations will be executed.

– – CL13 CL12 CL11 CL10 CL09 CL08Initial value

W W W W

CLRR

15 14 13 12 11 10 9 8

--000000B

W W

bit

– – CL13 CL12 CL11 CL10 CL09 CL08

⇑

--000000BCLRBRAddress : 000051H

CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00Initial value

W W W W

CLRR 7 6 5 4 3 2 1 0

00000000B

W W W W

bit

CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00

⇑

00000000BCLRBRAddress : 000050H


87

(11) Dead-time Timer Control Register (DTCR)

This register controls the dead-time timer for output of non-overlappint 3-phase waveforms for AC inverter motor control.

To enable function controlled by this register, set the DT1 bit to ‘1.’

Note 1: The bit with the asterisk (∗) accepts only the first write value after reset.

Note 2: Access by read-modify type instructions should be attempted only after writing (setting) data to the bits indicated by the asterisk (∗).

[Bit 7] DMOD: Inactive level select bit

This bit controls the output polarity of the 3-phase waveform output.

This bit can be used to invert the output polarity of the resulting pin signal.

If 3-phase waveform output is not selected (DT1 bit = ‘0’), this bit has no significance.

[Bit 6] TOCE: 3-phase waveform output stop-input enable bit

This bit enables control of the 3-phase waveform output by the DTTI pin input signal.

If 3-phase waveform output is not selected (DT1 bit = ‘0’), this bit has no significance.

DMOD Description

0 Inactive level ‘0’ (positive polarity) signal output

1 Inactive level ‘1’ (negative polarity) signal output

TOCE Description

0 No control by DTTI pin

1 Control by DTTI pin

DMOD TOCE TOC1 TOC0 DTIE DTIF DT1 DT0Initial value

R/W R/W W R/W

DTCR 7 6 5 4 3 2 1 0

00000000BAddress : 000052H

W W W∗ ∗

bit

W∗ ∗ ∗



[Bits 5, 4] TOC1, TOC0: DTTI pin input condition setting bit

These bits determine input conditions by which DTTI pin signal input is used for control of 3-phase waveform output.

When the conditions determined by these bits are met by the input signal, the DTIF bit is set. If the TOCE bit is ‘1,’ then the six 3-phase output pins are held in inactive state.

[Bit 3] DTIE: DTTI pin input interrupt enable bit

This bit enables the DTTI pin input interrupt request.

[Bit 2] DTIF: DTTI signal input interrupt request flag

This flag is set to ‘1’ by the input at the DTTI pin of the signal enabled by the setting of the TOC0, TOC1 bits.

To clear this bit, write ‘0.’



[Bits 1, 0] DT1, DT0: Dead-time timer control bit

These bits switch the function of the dead-time timer output pins, and control the operation of non-overlapping signal generation.

All functions controlled by the DTCR, DTSR and CTCMR registers are enabled by setting the DT1 bit to ‘1.’

TOC1 TOC0 DTTI pin input signal conditions for 3-phase output control

0 0 During ‘0’ input

0 1 During ‘1’ input

1 0 From falling edge of DTTI signal, until DTIF bit is cleared

1 1 From rising edge of DTTI signal, until DTIF bit is cleared

DTIE Description

0 Disable DTTI pin input interrupt request

1 Enable DTTI pin input interrupt request

DTIF Flag setting

0 No interrupt from valid DTTI pin input

1 Interrupt from valid DTTI pin input

DT1 DT0 Pin signal Operation

0 0PWM output Dead-time timer function in stop status

0 1

1 0 3-phase waveform output Held at inactive level

1 1 3-phase waveform output Non-overlapping 3-phase signal output


89

(12) Dead Timer Setting Register (DTSR)

Note 1: The bits with the asterisk (∗) accept only the first write value after reset.

Note 2: Access by read-modify type instructions may cause abnormal operation and should not be attempted with this register.

[Bits 15, 14] DCS1, DCS0: Dead-time timer clock source select bits.

These bits select the dead-time timer clock source.

[Bit 13] NRSL: Noise cancellation select bit.

This bit selects/deselects the noise cancellation capability for DTTI pin input.

The noise cancellation circuit is able to cancel noise with a typical pulse width of 25 ns. Also, the use of the noise cancellation circuit generates delay with a typical pulse width of 25 ns in receiving the DTTI signal.

[Bit 12] *: Reserved bit


(13) Dead-Time Compare Register (DTCMR)


DCS1 DCS0 Dead-time timer clock source

0 0 1 machine cycle

0 1 4 machine cycles



NRSL Description

0 Input signal directly without passing through noise cancellation circuit

1 Input signal through noise cancellation circuit

DCS1 DCS0 NRSL ∗ – – – –Initial valueDTSR 15 14 13 12 11 10 9 8

XXX0XXXXBAddress : 000053H

W W W∗ ∗

bit

W∗ ∗

DTC7 DTC6 DTC5 DTC4 DTC3 DTC2 DTC1 DTC0Initial value

W W W W

DTCMR 7 6 5 4 3 2 1 0

XXXXXXXXBAddress : 000054H

W W W

bit

W



[Bits 15 to 8] DTC7 to DTC0: Dead-time compare register

This bits form a register that holds the compare value for the dead-time counter.

The compare value determines a common non-overlapping time for three dead-time timers.

Non-overlapping time is the product of the value in this register and the selected clock source. Note however that a setting value of 0000B is not permitted.

Only in the case that the clock source is set for ‘1 machine cycle’ (DCS1,0=00B), values of 0001B and higher in this register will alter the above calculation to (setting + 1) times the clock source. Therefore it is not possible to set a value of 1 × 1 machine cycle only.

(14) Port Data Register and Port Data Buffer Register (PDR6, PDBR)

Note: Access by read-modify type commands may cause abnormal operation and should not be attempted with this register.

The PDBR register functions as the buffer for the PDR6 register.

Bits corresponding to general-purpose port functions as selected by the COER register operate as normal I/O ports. In this case values written to the PDBR register are simultaneously transferred to the PDR6 register.

For bits selected as PWM output pins in the COER register, values written to address 000006B will be written to the PDBR register only, and transfer of these values to the PDR6 register is controlled by the OCTR register.

Fig. 2.4.3 Port Area Block Diagram

Initial value

R R R R

7 6 5 4 3 2 1 0

-XXXXXXXB

R R R

bit– RD66 RD65 RD64 RD63 RD62 RD61 RD60

⇑

PDR6

Initial value

W W W W

7 6 5 4 3 2 1 0

-XXXXXXXB

W W W

bit– RD66 RD65 RD64 RD63 RD62 RD61 RD60

PDBRAddress : 000006H

Inte

rnal

bus

Transfer controlSet/reset

To pinWRITE

READ

PDBR PDR6

COEROCTR


91

2.4.5 Operating Description(1) Timer/Waveform Generator

This block is capable of generating waveforms for four channels, and can be broadly classified in terms of the following circuit types.

• 14-Bit Timer

Compare-clear register: Sets upper limit for timer count

Prescaler: Generates timer count clock signal

Count control unit: Up/down selection, compare-clear function, etc.

Zero-detect circuit: Detects zero (0000H) condition in timer

• Pin Control Block (4 channels)

Zero-detect pin control unit: Sets/resets pins according to timer zero-detect signal

Output compare register and compare detect pin control block: Compares output with detect register for pin control, also

performs setting, resetting and buffer transfer.

Port data register and buffer: Register and buffer, also used as a port

• Interrupt Control Block: Outputs zero-detect, compare-detect and other interrupts

• Buffer Transfer Control Block: transfer control for all buffers

a) 14-Bit Timer

(1) Timer Start/Stop Control

When the TMST bit in the TMCR register is set to ‘1’ the timer is placed in operating state.

At this point the prescaler, used to generate the internal clock signal, is initialized and the timer begins counting from its stop-mode value.

When the TMST bit is set to ‘0’ the timer is placed in stop state.

Following a reset the timer is initialized to 0000H, and placed in stop state.

(2) Overflow

An overflow occurs when the timer in up-count mode changes from 3FFFH to 0000H. The timer count continues to increase from 0000H.

When the compare-clear register has any value other than 0000H (and match-detect operation is in effect for the compare-clear register), no overflow will occur because the count is cleared or the counting direction is reversed.

(3) Timer Count Clock (Prescaler)

The timer count clock signal is selected using the TCS1, TCS0 bits in the TMCR register.

The prescaler output for count clock signal may be selected from 1, 2, 8 or 16 machine cycles.

The prescaler is initialized when the timer is started, or cleared by a trigger signal.



(4) Timer Clearing

The following events are sources of timer clearing.

• Software clearing

• Clearing due to external trigger input

• Clearing due to matching between a compare register and timer value, in up-count mode.

Software clearing occurs when ‘0’ is written to the STCR bit in the TCSR register. Simultaneously with writing to the STCR bit, the timer and prescaler are cleared and the timer continues counting from 0000H.

Clearing due to external trigger input occurs by setting the CES1,0 bits of the TMCR register to determine the effective trigger edge. This bit will only accept the first value written after reset.

After input of the effective trigger signal edge, the timer and prescaler are cleared and the timer continues counting from 0000H. At this time the TCIR bit in the TCSR register is set.

An interval of 1 to 1.5 machine cycles is required between edge input and generation of the clear signal.

Clearing of the timer due to compare-clear matching causes the timer value to be cleared to 0000H on the next cycle of the count clock after the match is detected, however the prescaler is not cleared.

At this time the TMIR bit in the TCSR register is set, and the count operation continues.

Fig. 2.4.4 Timer Clearing Due to Trigger Signal Input

Timer clearing due to trigger signal input

Count clock

Timer value

Trigger input

Timer clear

1 to1.5 machine cycles

0000H


93

(5) Count Mode

When the MODE bit in the TMCR register is set to '0,' the timer operates in up-count mode. In up-count mode, each time the timer value matches the compare-clear register, the timer is cleared to 0000H and continues counting upward.

When the MODE bit is set to '1' the timer operates in up/down count mode. In up/down count mode, each time the timer value matches the compare-clear register, the timer switches direction from up-count to down-count. When the timer value reaches 0000H, the count switches direction again, from down-count to up-count.

Fig. 2.4.5 Operation in Two Count Modes

(6) Compare-Clear Operation

Whenever a match is detected between the compare-clear register and the timer value, the timer control block sends out a match signal to set the TMIR bit in the TCSR register, which controls the timer count.

If the timer is operating in up-count mode, the occurrence of a compare-clear match clears the timer to 0000H at the next count, and the count continues.

If the timer is operating in up/down count mode, the occurrence of a compare-clear match switches the direction at the next count, and the timer continues to count downwards.

Fig. 2.4.6 Compare-Clear Operation

Operation in Up-Count Mode

Timer value

Timer start Compare-clear Time

Operation in Up/Down Count Mode

Zero detected

CLRR

Timer value

Time

CLRR

⇑

match detected

⇑ ⇑Timer start

⇑Compare-clear match detected

⇑Compare-clear match detected

⇑

Count clock

Timer value

Compare-clear match

00

Up count mode

Up/down count mode

α : compare-clear register value

01 02αα-1

Count clock

Timer value

Compare-clear match

α-1 α-2αα-1



The compare-clear register has its own buffer register, into which data is written for transfer to the compare-clear register. When the timer is stopped, transfer occurs immediately when the data is written to the buffer. When the timer is operating, data transfer from the buffer occurs when the timer value is detected to be zero (as long as transfer is enabled).

When the comapre-clear register is set to 0000H in up-down count mode, no compare-clear match can occur, and the timer will count to overflow.

(7) Zero-Detect Block Operation

Whenever the timer value reaches 0000H, the zero-detect block sends a zero-detect signal to the count control block and zero detect pin control block, and at the same time sets the TZIR bit in the TCSR register.

The count control block receives the zero detect signal and switches the count direction from down-counting to up-counting.

(8) Zero-Detect Interrupt Mask Operation

The IME bit in the ZICR register can be set to ‘1’ to mask interrupt sources occurring from timer zero-detection.

The number of maskings can be counted with the 4-bit reload counter, and from one to 15 times.

Each time a timer value of zero is detected, the mask count down begins, and when the count value reaches 0000B, the next zero-detection will set the TZIR bit in the TCSR register. At this point the predetermined value will be reloaded and the count will continue.

While this mask function is operating, it is not possible to rewrite the reload counter directly, however the counter value can be overwritten through a buffer, to become effective at the next reload cycle.

Note that because a zero-detect condition will occur even if the timer value is 0000H at startup, the 4-bit counter will execute a count-down.

The count value is also reloaded when data is written to the ZICR register.

To disable this function, use a software instruction to write ‘0’ to the IME bit.

Also, if the mask cycle count is set to 0 times (0000B), no interrupt sources will be masked even if the IME bit is set to ‘1.’

Fig. 2.4.7 Zero-detect Interrupt Mask Operation

Timer value

Example: Up-count mode, mask cycle = 2

Zero-detect

4-bit counter value

TZIR set

2

⇑Start

1 0 2 1 0 2


95

When the zero-detect interrupt masking function is in use, the TMSK bit can be used to determine whether the data is to be transferred from buffer registers to the corresponding compare registers at the occurrence of a masked zero-detect event.

The following diagram shows the relation between zero-detect events and buffer transfers, depending the specified value of the TMSK bit.

Fig. 2.4.8 TMSK Bit Value Specification and Buffer Transfer Operation

Timer value

Start

Zero-detect

4-bit counter value

TZIR set

2 1 0 2 1 0 2

⇓⇓⇓ ⇓ ⇓ ⇓

⇓ ⇓

Buffer register

Compare register

Buffer register

Compare registerTMSK=0

TMSK=1

⇓



(9) Interrupts

The following five types of interrupt requests are sent to the CPU from the various timers in the MB90660A series chip.

Interrupt sources include timer clearing from trigger signal input, as well as zero-detect, overflow/compare-clear match, and output-compare match events.

a. Trigger Input Interrupts

The valid edge of a signal from an external trigger input pin, setting the CES1,0 bits in the TMCR register will set the TCIR bit in the TCSR register. At this point if the TCIE bit is set to ‘1,’ the timer will output an interrupt request to the CPU.

This interrupt can use extended intelligent I/O services.

b. Zero-detect Interrupts

When the timer value reaches 0000H, the TZIR bit in the TCSR register is set. At this point if the TZIE bit is set to ‘1,’ the timer will output an interrupt request to the CPU.

This interrupt can be masked for a given number of occurrences.


c. Timer Overflow/Compare-Clear Match Interrupts

When the timer overflows, or the compare-clear match occurs, the TMIR bit in the TCSR register is set. At this point if the TMIE bit is set to ‘1,’ the timer will output an interrupt request to the CPU.


d. Compare-Match Interrupts

When a compare-match event occurs, the CIR bit for the corresponding compare channel is set in the CICR register. At this point if the CIE bit corresponding to that compare channel is set to ‘1,’ the timer will output an interrupt request to the CPU.


97

b) Pin Control Block

The pin control block has 4 channels, and controls setting/resetting of the real-time output signal pins (RT0 to RT3) according to compare-detection events and zero-detection events involving the 14-bit timer.

(1) Compare/Port Switching Operation

The COER register determines whether the RT0 to RT3 signals function as PDBR output, or as real-time output pins.

This register controls the internal signals RT0 to RT3, and when the DTCR register is used to setup the dead-time timer for 3-phase waveform output, a non-overlapping waveform can be generated over any of the bits RT1 to RT3 selected here, and output over the six pins U to Z.

Table 2.4.1 External Pin Function Selection

The initial value of the PWM output (RT0 to RT3) is undefined. When setting initial values for these signal pins, the values in the PDR6 register should be set first, before output is enabled.

(2) Compare-Match Detect Operation (Output Compare Register)

Compare-match detection operates by continuous comparison of timer values with values in the OCPR register. When a match event occurs, a set/reset/transfer control signal is output to PDR accrding to the setting in the OCTR register, and at the same time the CIR bit in the CICR register for the corresponding compare register is set.

(3) Buffer Transfer Enable/Disable Control

Setting the TREN bit in the CMCR register to ‘0’ disables all four channels for transfer from the output compare buffer register to the output compare register. Thus any transfer sources generated while the TREN bit is set to ‘0’ will be ignored.

Once ‘1’ is written to the TREN bit, transfer operations from the buffer register will start with the generation of the next transfer source.

The TREN bit also controls transfer from the compare clear buffer register to the compare clear register.

In addition, this bit also controls transfers while the timer is stopped.

COER register RTOx

bit

DTCR register DT1 bit

DDR register P6x bit

External pin operations

X X 0 High-impedance state, functions as input pin

0 0 1 Functions as PDBR output

1 0 1 Functions as real-time output pin

0 1 1 Dead-time control output for PDBR output pins

1 1 1 Dead-time control output for real-time output pins



(4) Output Compare Buffer Transfer Control

While the timer is stopped, values are transferred to the output compare register simultaneously as they are written to the buffer register.

While the timer is operating, transfers from the compare buffer register to the output compare register are controlled by the buffer mode select bits (BFS0,1) in the CMCR register, which select either compare-match or zero-detect transfer mode.

The BFS1 bit selects the buffer mode for compare channels 1 to 3, and the BFS0 bit selects the buffer mode for compare channel 0.

When a compare-match event causes data to be transferred from the buffer to the output compare register, the value in the buffer register corresponding to the channel on which the match occurred is transferred to the output compare register on the next count following the count on which the match occurred.

Fig. 2.4.9 Compare Buffer Transfer Operation (1)

If zero-detect transfer mode is selected and the zero-detect buffer transfer mask select bit (TMSK) is set to 0B, then the buffer register value will be transferred to the output compare register whenever the timer count reaches 0000H.

Also, if the zero-detect buffer transfer mask select bit (TMSK) is set to ‘1’B, the value from the buffer register will be transferred to the output compare register only at zero-detect events when a zero-detect interrupt is generated (after the zero detect mask count has been terminated).

Note, however, that no transfer will occur when the count value is 0000H immediately after startup (including restarts).

Fig. 2.4.10 Compare Buffer Transfer Operation (2)

[CAUTION] The initial value of the output comapre register is indeterminate. If the timer is running without setting a value in the output fcompare register, the MB90660A chip will be comparing the count to an initially indeterminate value.

Timer value

Compare register value

Buffer register value

3

Compare Buffer Transfer: After a Compare-Match Event

4 521

Match signal

6 7

2 6 0

06

⇑Buffer register overwritten

Timer value

Compare register value

Buffer register value

1

Compare Buffer Transfer: After a Zero-Detect Event

00X 1

⇑Re-write ⇑Clear timer

2


99

(5) Compare Detect Pin Control Block Operation

The compare detect pin control block uses compare-match detection to control the real-time output pins.

Pin controls are provided for each real-time output pin, so that compare channels 0 to 3 correspond respectively to pins RT0 to RT3.

When the pin control block receives a match signal from the compare-match detection block, the controls defined in the output control register are applied to the corresponding pin(s).

Fig. 2.4.11 Output Pin Operation (1)

Pin Control Operation in Up-Count Mode

(1) Reset to ‘0’

(In this illustration, the value of x = 0, 1, 2, 3)

CLRR

OCPR

RTx

⇑ ⇑

(2) Set to ‘1’

CLRR

OCPR

RTx

⇑ ⇑

(3) Transfer PDBR register value

CLRR

OCPR

RTx

⇑ ⇑

(4) No pin control applied

CLRR

OCPR

RTx

⇑ ⇑

PDBR

⇑ ⇑



Fig. 2.4.12 Output Pin Operation (2)

For pin controls in up/down count mode, compare register values of 0000H are considered to apply during up-count operation, and compare register values equal to CLRR register values are considered to apply during down-count operation.

(6) Zero-Detect Pin Control Block

Whenever the zero-detect pin control block receives a zero-detect signal, the operation defined by the ZOSC pin in the ZOCTR register is applied to the pin(s) designated by the ZSB0 to ZSB3 bits.

The timing of zero-detect pin controls is the same as pin controls operating from output-compare register matching.

When both a zero-detect pin control and an output-compare match occur simultaneously, then regardless of the setting of the RTx pin, the zero-detect control operation is masked and pin controls are applied according to the output comapre match.

Pin Control Operation in Down-Count Mode

(1) During up-count ⇒ ‘0’, during down-count ⇒’1’

(In this illustration, the value of x = 0, 1, 2, 3)

CLRR

OCPR

RTx

⇑ ⇑

(2)During up-count ⇒ ‘1’, during down-count ⇒ ‘0’

CLRR

OCPR

RTx

⇑ ⇑

(3) Transfer PDBR register value

CLRR

OCPR

RTx

⇑ ⇑

(4) No pin control applied

CLRR

OCPR

RTx

⇑ ⇑

PDBR

⇑ ⇑


101

(2) Dead-time Generator Block Operation

The dead-time generator block receives input signals from real-time output pins RT1 to RT3, and when the DTCR register DT1 bit is ‘0’ outputs the RT1 to RT3 signals unchanged to the port block.

If the DT1 bit is ‘1’ the RT1 to 3 signals and their inverse signals are used to generate a non-overlapping signal which is output to the port block

.

Fig. 2.4.13 Dead-time Generator Block Operation

a) Non-Overlapping Signal Generator

When the DMOD bit in the DTCR register indicates an active level ‘1’ (positive polarity) signal, a non-overlapping signal is generated using the rising edges of the RT1 to RT3 signals and their inverse signals, by applying a delay equivalent to the non-overlapping interval setting in the DTCMR register.

If this interval is smaller than the non-overlapping interval determined by the RT1 to RT3 pulse width, the 8-bit counter counts the next edge delay. This therefore prevents the signal from fluctuating.

Pin Output signal

U Signal with delay applied at RT1 rising edge

V Signal with delay applied at RT2 rising edge

W Signal with delay applied at RT3 rising edge

X Inverted signal with delay applied at RT1 falling edge

Y Inverted signal with delay applied at RT2 falling edge

Z Inverted signal with delay applied at RT3 falling edge

Dead-time timer

Selector

Output

External pin RT0

(PDR6) RT0

(PDR0) RT1

(PDR1) RT2

(PDR2) RT3

PDR3

PDR4

PDR5

UVWXYZ

Selector

Selector

Selector

Selector

Selector

PORT66

buffer

PORT60

PORT61

PORT62

PORT63

PORT64

PORT65

DT1

External pin P60/RT1/U

External pin P61/RT2/V

External pin P62/RT3/W

External pin P63/X

External pin P64/Y

External pin P65/Z

Positive-Polarity Non-Overlapping Signal Generation

Count value

1 machine cycle

DTCMR

Time

1 machine cycle

setting value

RT1

U

X



Fig. 2.4.14 Positive-Polarity Non-Overlapping Signal Generation

When the DMOD bit in the DTCR register indicates an active level ‘0’ (negative polarity) signal, a non-overlapping signal is generated using the falling edges of the RT1 to RT3 signals and their inverse signals, by applying a delay equivalent to the non-overlapping interval setting in the DTCMR register.

If this interval is smaller than the non-overlapping interval determined by the RT1 to RT3 pulse width, the 8-bit counter counts the next edge delay. This therefore prevents the signal from fluctuating.

Fig. 2.4.15 Negative-Polarity Non-Overlapping Signal Generation

[CAUTION] The following table shows DTC7 to DTC0 bit values and the corresponding non-overlapping intervals. The setting 00H should not be used.

b) Operating Control

The dead-time timer operates when the DT1 bit is set to ‘1’ during the first write cycle after release of a reset to the DTCR register.At this time, if the DT1 bit is set to ‘0,’ the dead-time timer will be inoperable.

The second and subsequent write cycles can only overwrite the DTIE, DTIF and DT0 bits.

c) 3-Phase Waveform Output Disable Bit Operation

With the 3-phase waveform output enabled (DT1=‘1’), if the DT0 bit in the DTCR register is set to '0,' a non-overlapping 3-phase output signal is produced, and if the DT0 bit is set to ‘1’ the signal is fixed at inactive level.

Pin Output signal

U Inverted signal with delay applied at RT1 rising edge

V Inverted signal with delay applied at RT2 rising edge

W Inverted signal with delay applied at RT3 rising edge

X Signal with delay applied at RT1 falling edge

Y Signal with delay applied at RT2 falling edge

Z Signal with delay applied at RT3 falling edge

DTC7 to DTC0Non-overlapping interval (machine cycles)

Other than DCS1,0=00B When DCS1,0=00B

00000000 Setting prohibited Setting prohibited

00000001 1 × clock source 2 × clock source




* Clock source: Dead-time timer clock source selected by DCS1,0 bits in DTSR register.

Negative-Polarity Non-Overlapping Signal Generation

Count value

1 machine cycle

DTCMR

Time

1 machine cycle

setting value

RT1

U

X


103

d) Dead-time Timer Disable Input Pin Operation

The TOCE bit in the DTCR register can be set to ‘1’ to enable the DTTI pin input to control the 3-phase waveform output.

If a valid input as defined by the TOC1,0 bits is present at the DTTI pin, the 3-phase waveform output is fixed at inactive level.

Even when the pin is held inactive by the DTTI input signal, the timer continues to run and the waveform generating operation continues. However, no signal is output at the pin.

Fig. 2.4.16 DTTI Pin Operation (1)

Fig. 2.4.17 DTTI Pin Operation (2)

e) DTTI Pin Noise Cancellation Function

The DTTI pin input noise cancellation function can be used, by setting the NRSL bit in the DTSR register to ‘1.’ Selecting the noise cancellation function applies a delay equivalent to the pulse width of the noise cancellation signal width to the timing with which the output signal is fixed at inactive level.

The noise cancellation function acts to cancel noise with a typical pulse width of 25 ns.

3-phase output signal inactiveV/Y, W/Z operation similar

(1) DMOD=‘0’, TOCE=‘1’, TOC1, 0=‘01’

RT1

UX

DTTI

3-phase output signal inactiveV/Y, W/Z operation similar

(2) DMOD=‘1’, TOCE=‘1’, TOC1, 0=‘10’

RT1

U

X

DTTI

DTIF flag clear



(3) Use of Expanded Intelligent I/O Services

a) Transferring Data to the Compare Register

Any of trigger input interrupt, zero-detect interrupt and overflow/compare-match interrupt signals alone may use the expanded intelligent I/O service (EI2OS), but by setting the IIOS bit in the TCSR register to ‘1,’ it becomes possible for the zero-detect interrupt to output three interrupt requests. This makes it possible to use EI2OS to update a maximum of 65,536 data values on three channels after every zero-detect interrupt.

In the following example, data is updated on the three output data compare buffer registers OCPBR1 to OCPBR3.

(1) First, EI2OS descriptors are allocated to three channels for the OCPBR1 to OCPBR3 buffer registers.

• ICR2 (00B2H) ← 008H: select channel 0



(2) The EI2OS descriptors are set up.

Table 2.4.2 EI2OS Descriptor Settings

EI2OS is started by a zero-detect event, and data is transferred to the OCPBR1 to OCPBR3 buffer registers from the RAM area designated for each channel. In this example, EI2OS is started three times in the sequence ICR02, 03, 04 and data is transferred continuously to OCPBR1, 2, 3 in word-length units.

After the number of transfer cycles designated by the data counter (15 cycles in this example), the interrupt routine is executed over each channel. In this example, the sequence will be 15 transfer cycles to OCPBR1 followed by the interrupt routine corresponding to ICR02, then 15 transfer cycles to OCPBR2 and the interrupt routine corresponding to ICR03, then 15 transfer cycles to OCPBR3 and the interrupt routine corresponding to ICR04. If necessary, the user may disable EI2OS within the interrupt subroutine, and re-enter settings as needed.

Fig. 2.4.18 Use of EI2OS Data Transfer

ICR2 (from 0100H) ICR3 (from 0100H) ICR4 (from 0100H) Comment

BAP (buffer address pointer) RAM address (1) RAM address (2) RAM address (3) Transfer source address

ISCS (I2OS status) 01AH 01AH 01AH Transfer method setting *1

IOA (I/O address pointer) 04AH 04CH 04EHTransfer destination address (OCPBR1 to OCPBR3)

DTC (data counter) 00FH 00FH 00FH Data count (15 cycles)

*1: Setting designates: I/O address not updated, buffer (RAM) address updated, buffer → I/O transfer, word transfer.

Buffer address

Higher address

Data for OCPBR3 (RAM address 3)



pointer is incremented by +2

OCPBR3 00004A HOCPBR2 00004C HOCPBR1 00004E H

015

RAM


105

b) Use of the Dummy Transfer to Skip an Interrupt Routine

It is possible to mask interrupt sources arising from timer zero-detect events, by setting the IME bit in the ZICR register to ‘1.’ The same procedure can be applied when EI2OS is used.

EI2OS is used to perform a designated number of data transfer cycles before executing an interrupt routine.

This feature can be used as a control, by setting up cycles that transfer meaningless data (dummy transfers), to delay the execution of the interrupt routine until the interrupt source has occurred five times.

The following example illustrates the execution of the interrupt routine after 10 timer zero-detect events.

(1) EI2OS is enabled, and descriptor settings are made in the interrupt control register (ICR).

Example: ICR04 0 8 H ⇒ descriptor address 000100H

(2) EI2OS status register (ISCS) settings are entered, including byte transfer, no buffer address pointer increment, I/O ⇒ memory transfer.

Example: 0103H C 0 H

(3) A given address for dummy read cycles is set up for the I/O register address pointer (IOA).

Example: 0104H 0 0 0 0 H (PDR0)

(4) The desired number of transfer cycles is entered in the data counter (DCT).

Example: 0106H 0 A H

(5) An unused address is set up for the buffer address pointer for dummy write cycles.

Note that the external area should not be defined here. (Access cycle is made longer.)

With the above settings, the process operates as follows.

Fig. 2.4.19 Use of the Dummy Transfer to Skip an Interrupt Routine

This type of procedure somewhat reduces CPU processing capability, but enables the execution of an interrupt processing routine 1 out of 10 times with no burden on the user program.

User program

EI2OS (dummy transfer)

Interrupt routine

Zero-

RETI

detect 1⇓

Zero-detect 2⇓

Zero-detect 3⇓

Zero-detect 10⇓

• • • •



2.4.6 Operating Examples(1) 4-Channel PWM Output

The following example illustrates the use of the multi-function timer for 4-channel independent PWM output.

The multi-function timer register settings should be made as follows.

TCSR=00000000B

• STCR=0 : Initialize timer prior to startup

• TCIE=0 : Timer clear interrupt disabled

• TZIE=0 : Zero-detect interrupt disabled

• TMIE=0 : Timer interrupt disabled

CICR=11110000B

• CIE0 to CIE3=1 : Compare-match interrupt enabled

TMCR=001x0010B

• TMST=0 : Time count mode: up-count mode

• CES1,CES0=00 : External trigger not used

• TCS1,TCS0=10 : Timer count clock 8 machine cycles [0.5 µs at f=16 MHz]

COER=xxxx1111B

• RTO3 to RTO0=1 : General-purpose port/timer output switch: all pins function as timer output pins

CMCR=xxxx1111B

• BFS1,BFS0=11 : Buffer register transfer mode (compare 0 to 3): transfer at zero-detect event

ZOCTR=xxx01111B

• ZOSC=0 : Zero-detect pin control: reset to 0 at zero-detect event

• ZSB3-ZSB0=1 : Zero-=detect pin control: zero-detect control for RT0-RT3 pins

OCTBR=01010101B

• ROx1, x0=01 : Compare output operation: RT0-RT3 to ‘1’ at compare-match

ZICR=0xxxx000B

• IME=0 : Zero-interrupt mask control prohibited

OCPBR=0200H

• CPxx : Compare value: set according to desired output waveform

CLRBR=05FFH

• CLxx : Set compare-clear value

DTCR=00000000B

• TOC1,TOC0=00 : Dead-time timer: not started

After all settings are entered, set TMST=1 to start timer.

Then, re-write the OCPBR value at each compare-match interrupt to enable real-time pulse width control.


107

Figure 2.4.20 provides an overview of timer operation using the settings on the preceding page.

Compare Register Values and Output Waveforms Using the Given Settings

Note: For an ‘all-zero’ waveform, set the PDBR to ‘0’ with an OCTBR setting of 10B (transfer PDBR value).

Fig. 2.4.20 Operating Example (1)

Compare register settings

Output waveforms ‘1’ pulse width

0000H 768.0 µs

0001H 767.5 µs

to to to

05FEH 1.0 µs

05FFH 0.5 µs

*Note 0 µs

⇑ ⇑ ⇑ ⇑0200H 0300H 0400H

0200H 0300H 0400H 0500H

Timer value

Time

Compare register

Buffer register

Operation Initial ↑ ↑

05FH

RTI

bufferStart Rewrite setting

↑

bufferRewrite

↑

bufferTransfer

↑

bufferRewrite

↑

bufferTransfer

↑

bufferTransfer



(2) PWM Inverter Control for Sine Wave Approximation

The following example illustrates the use of the multi-function timer to approximate a sine wave output by controlling the PWM inverter.

The multi-function timer register settings should be made as follows.

TCSR=00000000B

• STCR=0 : Initialize timer prior to startup

• TCIE=0 : Timer clear interrupt disabled

• TZIE=0 : Zero-detect interrupt disabled

• TMIE=0 : Timer interrupt disabled

CICR=00000000B

• CIE3 to CIE0= : Compare-match interrupt disabled

TMCR=011x0000B

• MODE=1 : Up/down count mode

• TCS1,TCS0=00 : Timer count clock 1 machine cycle [62.5 ns at f=16 MHz]

COER=xxxx1110B

• RTO3 to 1=1 : General-purpose port/timer output switch: RTO3 to RTO1 pins function as timer output pins

CMCR=xxxxx110B

• BFS1=1 : Compare channels 1 to 3 buffer transfer ⇒ transfer when timer=0000H

ZOCTR=xxx11110B

• ZOSC=1 : Zero-detect pin control: set to 0 at zero-detect event

• ZSB=1110 : Zero-detect control for RT1 to RT3 pins

OCTBR=00000011B

• ROx1, x0=00 : Compare output operation: RT1 to RT3 ‘0’ for up-count, ‘1’ for down-count

ZICR=0xxxx000B

• IME=0 : Zero-interrupt mask control prohibited

OCPBR

• CPxx : Set according to desired output waveform

CLRBR=0190H (400D)

• CLxx : Set compare-clear value to half of carrier period (carrier frequency 20 kHz)

DTCR=00101010B

• DTCR=0 : 3-phase waveform output, positive polarity

• TOCE=1 : Output control according to DTTI

• TOC1,TOC0=01 : DTTI pin input condition: during input of ‘1’ signal

• DTIE=1 : DTTI interrupt enabled (DTIE=1)

• DT1,DT0=10 : Dead-time timer start/output fixed at inactive level


109

DTSR=0100XXXXB

• DCS1,DCS0=10 : Dead-time clock source 0.5 µs (8 machine cycles) [f=16 MHz]

DTCMR=00001010B

: Dead-time setting 0.5 × 10 = 5.0 µs [f=16 MHz]

• After all settings are entered, set TMST=1 to start timer and set DT0=1 to enable dead-time timer output. ← Start

Then, re-write the OCPBR value at each zero-detect interrupt to enable real-time pulse width control.



Figure 2.4.21 provides an overview of timer operation using the settings on the preceding page.

Fig. 2.4.21 Operating Example (2)

⇑ ⇑ ⇑0120H 0100H 00C0H

0120H 0100H 00C0H 00A0H

Timer value

Time

OCPR

OCPBR

Operation

0190H

U

rewrite bufferCompare-detect,

transfer bufferZero-detect,

X





0

Compare Register Values and Output Waveforms Using the Given Settings

* Dead-time timer start time will be the above pulse width less the non-overlapping interval.

Compare register settings

Output waveforms (RTOx) Pulse width

0000H 50.000 µs

0001H 49.875 µs

018FH 0.125 µs

0190H 0 µs

400 steps


111

(3) Interval Interrupt Using the Zero-Detect Interrupt Masking Function

The multi-function timer can be used as a 14-bit timer with count clock source selection set for 16 MHz, to generate interrupts at constant intervals up to a maximum of approximately 32.7 ms. And by using the zero-detect interrupt mask function, the interval time can be extended to approximately 458.7 ms when operating at 16 MHz. The interval time is determined by the formula:

• Interval time = CLRBR × TCS1 to TCS0 × MODE × (CYC + 1) [machine cycles]

CLRBR (14-bit timer value) : 0000H to 3FFFH(0 to 16383)

TCS1 to 0 (count clock sourse) : 1, 2, 8, or 16

MODE (count mode selection) : ‘1’ for up-count mode, ‘2’ for up/down count mode

CYC (zero-detect mask counter) : 00H to 0EH* (0 to 14) *See below

*: Note that when the above function is used with zero-interrupt masking, the first interrupt generation interval after the start of the count will be one count shorter than normal.

Fig. 2.4.22 Example: Constant Interval Setting Using Zero-Detect Interrupts

This is because zero-detect control immediately following timer startup require that both the zero-detect pin control and zero-detect mask counter be reduced by 1 at startup before the 14-bit timer count begins. In the above example, the first interrupt is generated after two counts, and the second and all subsequent interrupts at intervals of 3 counts.

For this reason, users needing to time the interval function immediately after the start of the timer count must reset the zero-detect mask counter immediately after the timer count begins. To to this, use the following procedure.

(1) Initialize all registers, setting the zero-detect mask counter for the desired interval.

(2) Start the timer.

(3) Rewrite the zero-detect mask counter, to a value that is one less than the value entered in step (1).

Because step (3) is performed while the timer count is in progress, the value must be written to the buffer, and the register will be updated at the next reload cycle. Because the new value will be used in the next zero-detect masking operation after startup, the effect will be that the interval is the same as the first interval after startup.

Example: Up-Count Mode, Zero-Detect Mask Counter Set for 2 Cycles

Timer value

Zero-detect

4-bit counter value

TZIR set⇑Start

Same length for all

2 21 10 0 2

1-count shortersubsequent intervals



When generating interrupts at identical intervals from timer startup, it is necessary that the value written be one less than the value of the zero-detect interrupt mask register immediately after startup. Therefore the maximum setting allowed is 0EH, corresponding to a maximum interval time of approximately 458.7 ms.

When it is acceptable for the first interval after timer startup to be shorter, the maximum setting value is 0FH (because the value is not reset immediately after timer startup), corresponding to a maximum interval time of approximately 491.4 ms.

Fig. 2.4.23 Example: Constant Interval Setting Using Zero-Detect Interrupts

Example: Up-Count Mode, Zero-Detect Mask Counter Set for 2 Cycles at All Times

Timer value

Zero-detect

4-bit counter value

TZIR set

⇑ Start

2 11 00 1 0

2 countsCount constantat all times

⇒ 2 counts 2 counts

⇑ Transfer from buffer

Immediately rewrite‘1’ to mask counter

• Zero-detect mask counter set to ‘2’ before timer count starts, then rewritten to ‘1’ immediately after timer startup.

2.5 UART

113

2.5 UART

The UART is a serial I/O port for asynchronous (start-stop synchronized) or CLK-synchronous communication with external circuits, and provides the following features.

• Full-duplex double buffer

• Asynchronous (start-stop synchronized) and CLK synchronous data communication capability

• Multi-processor mode support

• On-chip dedicated baud rate generator

Asynchronous: 19230 / 9615 / 31250 / 4808 / 2404 / 1202 bps

CLK synchronous: 2M / 1M / 500K / 250K bps

• Free baud rate setting from external clock input or internal timer

• Error detection (parity, framing, overrun)

• NRZ transfer format

• Intelligent I/O service support

2.5.1 Register List

15 8 7 0

SCR SMR

SSR SIDR(R)/SODR(W)

(R/W)

(R/W)

8 bit 8 bit

MD1 MD0 CS2 CS1 CS0 – SCKE SOEAddress : 000024H

7 6 5 4 3 2 1 0Serial mode register (SMR)

PEN P SBL CL A/D REC RXE TXEAddress : 000025H

15 14 13 12 11 10 9 8Serial control register(SCR)

D7 D6 D5 D4 D3 D2 D1 D0Address : 000026H

7 6 5 4 3 2 1 0 Serial input register,Serial output register

PE ORE FRE RDRF TDRE – RIE TIEAddress : 000027H

15 14 13 12 11 10 9 8Serial status register(SSR)

– – – – DIV3 DIV2 DIV1 DIV0Address : 00005FH

15 14 13 12 11 10 9 8 Machine clock dividercontrol register

(SIDR/SODR)

(CDCR)

CDCR (W)

2.5 UART


2.5.2 Block Diagram

Fig. 2.5.1 Overall Block Diagram

Receiving shifter

End receiving

SIDR

Dedicated baud

16-bit timer 0

External clock

Receiving clock

Receiving control circuits

Start bit detection circuit

Receiving bit counter

Receiving parity counter

Sending status decision circuit

EI2OS receiving error

Receiving interrupt

Sending clockSending

Start sending

Clock selection

Sending shifter

SODR

FFMC-16 BUS

SIN

generator signal (to CPU)

SOT

SCK

(to CPU)

interrupt (to CPU)

Control signals

SMRregister

MD1MD0CS2CS1CS0

SCKESOE

SCRregister

PENPSBLCLA/DRECRXETXE

SSRregister

PEOREFRERDRFTDRE

RIETIE

Control signals

rate clock

(internal connection)circuit

Sending control circuits

Sending start circuit

Sending bit counter

Sending parity counter

2.5 UART

115

2.5.3 Detailed Register Descriptions(1) SMR (Serial Mode Register)

Note 1: The SMR register determines the UART operating mode. Operating mode settings should be made while UART operations are stopped. No values should be written to this register while the UART is operating.

Note 2: Access to this register by read-modify-write instructions may result in abnormal operation, and should be avoided.

[Bits 7, 6] MD1, MD0 (Mode select):

These bits select the UART operating mode

Table 2.5.1 UART Operating Mode Selection

[CAUTION] Mode 1, asynchronous (multiprocessor) mode, allows one host CPU to operate with multiple slave CPU units. This UART resource is unable to recognize incoming data formats, and therefore in multi-processor mode only support operation as a master CPU unit.Also in this configuration the receiving parity check function cannot be used, and therefore the PEN bit in the SCR register should be set to ‘0.’

[Bits 5 to 3] CS2, CS1, CS0 (Clock Select):

These bits select the baud rate clock source. When the dedicated baud rate generator is selected, the baud rate can be determined at the same time.

Table 2.5.2 Clock Input Selection

[CAUTION] When the internal timer is selected, the MB90660A series selects 16-bit timer 0.The CS2, CS1 and CS0 bits are write-only, and have a read value of ‘1’ at all times.

[Bit 2] :Open

Mode no.

MD1 MD0 Operating mode

0 0 0 Asynchronous (start-stop synchronized) normal mode

1 0 1 Asynchronous (start-stop synchronized) multi-processor mode

2 1 0 CLK synchronous mode

– 1 1 Setting prohibited

CS2 to CS0 Clock input

000B to 100B Dedicated baud rate generator

101B Reserved

110B Internal timer

111B External clock

MD1 MD0 CS2 CS1 CS0 – SCKE SOEInitial value

W R/W R/W

SMR7 6 5 4 3 2 1 0

00000 – 00BAddress : 000024H

R/W R/W W W

2.5 UART


[Bit 1] SCKE (SCLK enable):

For communication in CLK synchronous mode (mode 2), this bit determines whether the SCK pin is used as a clock input pin or a clock output pin.

In CLK asynchronous modes or external clock mode, this bit should be set to ‘0.’

0: SCK pin functions as clock input pin

1: SCK pin functions as clock output pin

[CAUTION] When an external clcok source is selected, this pin must function as the clock input pin.

[Bit 0] SOE (Serial output enable):

This bit determines whether external pins (SOT) that also can be used as general-purpose I/O ports will function as serial output pins or as I/O port pins.

0: General-purpose I/O port pin function

1: Serial data output pin (SOT) function

(2) SCR (Serial Control Register)

The SCR register controls the transfer protocol used for serial transmission.

[Bit 15] PEN (Parity enable):

This bit determines whether parity bits are attached to data in serial transmission.

0: No parity

1: Parity

[CAUTION] Parity bit attachment is available only in asynchronous (start-stop synchronized) communications in normal mode (mode 0). In multi-processor mode (mode 1) and CLK-synchronous communication (mode 2), no parity bits may be attached.

[Bit 14] P (Parity):

This bit selects even or odd parity for data communications in which a parity bit is used.

0: Even parity

1: Odd parity

[Bit 13] SBL (Stop bit length):

This bit sets the length of the stop bit that marks the frame end in asynchronous (start-stop synchronized) communication.

0: 1 stop bit

1: 2 stop bits

PEN P SBL CL A/D REC RXE TXEInitial value

R/W W R/W R/W

SCR15 14 13 12 11 10 9 8

00000100BAddress : 000025H

R/W R/W R/W R/W

2.5 UART

117

[Bit 12] CL (Character length):

This bit sets the data length of one frame.

0: 7-bit data

1: 8-bit data

[CAUTION] 7-bit data handling is available only in asynchronous (start-stop synchronized) communications in normal mode (mode 0). In multi-processor mode (mode 1) and CLK-synchronous communication (mode 2), 8-bit data should be used.

[Bit 11] A/D (Address/data):

This bit determines the data format of sending and receiving frames in asynchronous (start-stop synchronized) communication in multi-processor mode (mode 1).

0: Data frame

1: Address frame

[Bit 10] REC (Receiver error clear):

This bit cleares the error flags (PE, ORE, FRE) in the SSR register.

A write value of ‘1’ is not valid, and the read value is ‘1’ at all times.

[CAUTION] When the UART is operating in receiving-interrupt enabled status, the value ‘0’ should only be written to the REC bit if one of the error flags PE, ORE or FRE is set to ‘1.’

[Bit 9] RXE (Receiver enable):

This bit controls UART receiver operations.

0: Receiver operation prohibited

1: Receiver operation enabled

[CAUTION] If receiver operation is prohibited while receiving is in progress (while data is present in the receiving shift register), the receiver will not stop operating until receiving of the current frame is completed, and the data has been stored in the receiving data buffer SIDR register.

[Bit 8] TXE (Transmitter enable):

This bit controls UART transmitter operations.

0: Transmitter operation prohibited

1: Transmitter operation enabled

[CAUTION] If transmitter operation is prohibited while receiving is in progress (while data is being output from the sending register), the transmitter will not stop operating until there is no more data remaining in the sending data buffer SODR register.

2.5 UART


(3) SIDR (Serial Input Data Register)SODR (Serial Output Data Register)

These registers function as receiving and sending data buffer registers.

When using 7-bit data length, the must significant (D7) contains invalid data. Be sure the TDRE bit in the SSR register is set to ‘1’ before writing to the SODR register.

Note 1: Writing to these addresses refers to writing to the SODR register, and reading refers to reading from the SIDR register.

Note 2: Access by read-modify type instructions may cause abnormal operation and should not be attempted with this register.

(4) SSR (Serial Status Register)

This register is composed of flags that indicate the operating status of the UART.

[Bit 15] PE (Parity error)

This interrupt request flag is set when a parity error occurs during receiving.

Once set, this flag is cleared by writing ‘0’ to the REC bit (bit 10) in the SCR register.

When this bit is set, data in the SIDR register is invalid.

0: No parity error

1: Parity error occurred

[Bit 14] ORE (Overrun error)

This interrupt request flag is set when an overrun error occurs during receiving.



0: No overrun error

1: Overrun error occurred

D7 D6 D5 D4 D3 D2 D1 D0Initial value

R R R R

SIDR7 6 5 4 3 2 1 0

IndeterminateAddress : 000026H

R R R R

Initial value

WW W W

SODR7 6 5 4 3 2 1 0

IndeterminateAddress : 000026H

W WW W

D7 D6 D5 D4 D3 D2 D1 D0

PE ORE FRE RDRF TDRE – RIE TIEInitial value

R R/W R/W

SSR15 14 13 12 11 10 9 8

00001 – 00BAddress : 000027H

R R R R

2.5 UART

119

[Bit 13] FRE (Framing error):

This interrupt request flag is set when a framing error occurs during receiving.



0: No framing error

1: Framing error occurred

[Bit 12] RDRF (Receiver data register full):

This interrupt request flag is set to indicate that data is present in the SIDR register.

This flag is set when receiving data is loaded into the SIDR register, and is automatically cleared when the data is read from the SIDR register.

0: No receive data

1: Receive data present

[Bit 11] TDRE (Transmitter data register empty):

This interrupt request flag is set to indicate that outgoing data has been written to the SODR register.

This flag is cleared when outgoing data is written to the SODR register. It is then reset when the written data starts loading into the sending shifter to indicate that the next data can be written to the SODR register.

0: Prohibits writing of transmit data

1: Enables writing of transmit data

[Bit 10] :Empty

[Bit 9] RIE (Receiver interrupt enable):

This bit controlls receiver interrupts.

0: Interrupt prohibited

1: Interrupt enabled

[CAUTION] Receiver interrupt sources include PE, ORE and FRE errors, as well as normal receiving as indicated by the RDRF flag.

[Bit 8] TIE (Transmitter interrupt enable):

This bit controls transmitter interrupts.

0: Interrupt prohibited


[CAUTION] Transmitter interrupt sources include tranmission requests as indicated by the TDRE flag.

2.5 UART


(5) CDCR (Machine Clock Divider Control Register)

The UART operating clock signal can be generated by dividing the machine clock signal pulse. The frequency divider is designed to enable constant baud rates from a variety of machine clock speeds. The CDCR register controls the machine clock frequency divider.


[Bits 11, 10, 9, 8] DIV3 to DIV0 (Divide 3 to 0)

These bits determine the machine clock division ratio.

Table 2.5.3 Machine Clock Division Ratios

According to the given machine clock speed φ, the following DIV3 to 0 bit values should be entered in the DCDR register to produce the baud rates shown in Table 2.5.4.

When using machine clock speeds or division ratios not listed here, be sure that the value (φ /div) does not exceed a maximum of 4 MHz.

DIV3 to DIV0 Division ratio

1110B Divide by 2

1101B Divide by 3

1100B Divide by 4

1011B Divide by 5

1010B Divide by 6

1001B Divide by 7

1000B Divide by 8

Machine clock φ div DIV3 DIV2 DIV1 DIV0 φ ÷ div

6 MHz 3 1 1 0 1

2 MHz

8 MHz 4 1 1 0 0

10 MHz 5 1 0 1 1

12 MHz 6 1 0 1 0

14 MHz 7 1 0 0 1

16 MHz 8 1 0 0 0

8 MHz 2 1 1 1 0

4 MHz12 MHz 3 1 1 0 1

16 MHz 4 1 1 0 0

– – – – DIV3 DIV2 DIV1 DIV0Initial value

W W

CDCR15 14 13 12 11 10 9 8

----1111BAddress : 00005FH

WW

2.5 UART

121

2.5.4 Operating Description(1) Operating Mode

The UART has the operating modes shown in Table 2.5.4. Mode settings can be switched by setting the values in the SMR and SCR registers.

Table 2.5.4 UART Operating Modes

Note that in asynchronous (start-stop synchronized) normal mode, stop bit length can be set for outgoing transmission only. For receiving, the setting is always 1 bit. The unit does not operate in modes other than those shown, and only these settings should be used.

Also note that switching modes is disabled while the UART is operating.

(2) UART Clock Selection

a) Dedicated Baud Rate Generator

When the dedicated baud rate generator is selected, the following baud rate settings are available.

Table 2.5.5 Baud Rate(i) When (φ/div)=2 MHz

(ii) When (φ/div)=4 MHz

Mode ParityData

lengthOperating mode Stop bit length

0Yes/No 7 Asynchronous (start-stop synchronized) nor-

mal mode1 bit or 2 bits

Yes/No 8

1 No 8+1Asynchronous (start-stop synchronized) multi-processor mode

2 No 8 CLK synchronous mode No

CS2 CS1 CS0Asynchronous (start-stop

synchronized) modeCLK synchronous mode

0 0 0 9615 (1)Prohibited

0 0 1 31250 (2)

0 1 0 4808 (3) 1 M

0 1 1 2404 500 k

1 0 0 1202 250 k

CS2 CS1 CS0Asynchronous (start-stop

synchronized) modeCLK synchronous mode

0 0 0 19230 (1)Prohibited

0 0 1 Prohibited

0 1 0 9615 (3) 2 M

0 1 1 4808 1 M

1 0 0 2404 500 k

2.5 UART


Baud rate values are determined as follows.

b) Internal Timer

When bits CS2 to CS0 are set to ‘110,’ the internal timer signal is selected, and 16-bit timer 0 operates in reload mode. In this case, baud rates are determined as follows.

Asynchronous (start-stop synchronized) (φ ÷ N)/(16 × 2 × (n+1))

CLK synchronous (φ ÷ N)/(2 × (n+1))

N: timer count clock source

n: timer reload value

Table 2.5.6 shows the relation between baud rates and reload values (hexadecimal values) at a machine cycle speed of 7.3728 MHz.

Table 2.5.6 Baud Rates and Reload Values

When selecting the internal timer (16-bit timer 0) as the baud rate clock source, note that the 16-bit timer 0 output signal TOT0 is already connected to this controller internally. Therefore, it is not necessary to make an external connection from the 16-bit timer 0 external output pins TIM0 to TIM3 to the UART esternal clock input pin SCK. Also, this means that unless used in some other fashion, the timer pins are available for use as I/O port pins.

c) External Clock

When bits CS2 to CS0 are set to ‘111’ the external clock source is selected and baud rates are determined by the following formula, in which f represents the external clock frequency.

Asynchronous (start-stop synchronized) mode: f/16

CLK synchronous: f

Note that f has a maximum value of 1 MHz.

(1) (φ ÷ div)/(16 × 13)

(2) (φ ÷ div)/26

(3) (φ ÷ div)/(16 × 13 × 2) (φ represents machine cycle speed)

Reload value N=21 (machine cycle division by 2)

N=23 (machine cycle division by 8)Baud rate

38400 2 –

19200 5 –

9600 11 2

4800 23 5

2400 47 11

1200 95 23

600 191 47

300 383 95

2.5 UART

123

(3) Asynchronous (Start-Stop Synchronized) Mode

a) Transfer Data Format

The UART handles only data in NRZ (non-return to zero) format. Figure 2.5.2 shows the data format.

Fig. 2.5.2 Transfer Data Format (Modes, 0, 1)

As shown in Figure 2.5.2, transfer data always begins with a start bit (‘L’ level data value), followed by the transfer data at the designated bit-length, and ends with a stop bit (‘H’ level data value). When an external clock signal is selected, the clock should be input at all times.

In normal mode (mode 0), data length may be set to 7 bits or 8 bits, however in multi-processor mode (mode 1) the data length must be 8 bits. Also, no parity bit may be attached in multi-processor mode. However, an A/D bit must be attached.

b) Receiving Operation

Whenever the RXE bit (bit 9) in the SCR register is set to ‘1’ the UART is receiving.

The appearance of a start bit on the receiving line allows one frame of data to be received according to the data format determined by the SCR register. When one frame of data has been received, error flags will be set if the corresonding errors have occurred, and then the RDRF flag (SSR register bit 12) will be set. At this time if the RIE bit (bit 9) in the SSR register is set to ‘1’ a receiving interrupt will be sent to the CPU. The CPU will check each of the flags in the SSR register and read the SIDR register if data has been received normally. If any errors have occured, the necessary processing should be followed.

The RDRF flag is cleared when the SIDR register is read.

c) Sending Operation

Whenever the TDRE flag (bit 11) in the SSR register is set to ‘1’ the UART is writing outgoing data to the SODR register. If the TXE bit (bit 8) is set to ‘1’ sending is in progress.

The TDRE flag is reset as soon as data placed in the SODR register starts to be transferred to the sending shift register for transmission. This enables the next unit of outging data to be placed in the SODR register. At this time if the TIE bit (bit 8) in the SSR register is set to ‘1’ a transmission interrupt is sent to the CPU, causing outgoing data to be placed into the SODR register.

The TDRE flag is momentarily cleared each time data is placed into the SODR register.

0 1 0 1 1 0 0 1 0 1 1

Start LSB MSB Stop........(mode 0)A/D Stop........(mode 1)

SIN,SOT

Transfer data value: 01001101B

2.5 UART


(4) CLK Synchronous Mode

a) Transfer Data Format

The UART handles only data in NRZ (non-return to zero) format. Figure 2.5.3 shows the relation between the sending and receiving clock and data in CLK synchronous mode.

Fig. 2.5.3 Transfer Data Format (Mode 2)

When an internal clock signal source (proprietary baud rate gemerator or internal timer) is selected, a data receiving synchronous clock signal is automatically generated each time data is transmitted.

When an external clock source is selected it is necessary to provide an accurate 1-byte clock signal whenever data is present in the sending data buffer register SODR (indicated by the TDRE flag = ‘0’). Note also that the sitnal must return to mark level before and after sending.

Data length is 8 bits only, and no parity bit may be attached. Also, there is no start/stop bit so that no error detection is enabled except for overrun errors.

b) Initialization

When using CLK synchronous mode, the initial values of each of the control registers are as follows.

(1) SMR Register

MD1, MD0 : 10

CS2, CS1, CS0 : Indicate clock input

SCKE : 1 for proprietary baud rage generator or internal timer, 0 for external clock

SOE : 1 to send, 0 to receive only

(2) SCR Register

PEN : 0

P, SBL, A/D : These bits have no significance

CL : 1

REC : 0 (to initialize)

RXE, TXE : At least one must be ‘1’

(3) SSR Register

RIE : 1 if interrupts are used, 0 if interrupts are not used

1 0 1 1 0 0 1 0

LSB MSB...................(mode 2)

Transfer data value: 01001101B

Mark

SODR write

SCLK

RXE,TXE

SIN,SOT

2.5 UART

125

TIE : 0

c) Start of Communication

Communication starts by writing to the SODR register. Note that even if no data is to be sent, it is first necessary to write dummy data to the SORD register.

d) End of Communication

The end of communication can be verified by the change of the RDRF flag in the SSR register to ‘1.’ To determine whether the communication was performed normally, read the ORE bit in the SSR register.

(5) Interrupt Generation and Flag Set Timing

The UART has five flags and two interrupt sources.

The five flags are the PE, ORE, FRE, RDRF and TDRE flags. The first three are set when receiving errors occur: the PE flag indicates a parity error, the ORE flag indicates an overrun error, and the FRE flag indicates a framing error. The RDRF flag is set when receiving data is loaded into the SORD register, and cleared when the data is read out of the SODR register. Note,however,that there is no parity detect function in mode 1, and no parity detect function or framing error detect function in mode 2. The TDRE flag is set when the SODR register is empty and ready for data write access, and is cleared when data is written to the SODR register.

The two interrupt sources are for receiving and sending respectively. During receiving, interrupt requests are initiated by the PE, ORE, FRE or RDRF flags. During sending, interrupt requests are initiated by the TDRE flag. The following sections describe interrupt flag set timing in each operating mode.

a) Mode 0 Receiving

The PE, ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPU after the end of a receiving transfer, when the final stop bit is detected. If any one of the PE, ORE or FRE flags is active, the data in the SIDR register will be invalid.

Fig. 2.5.4 ORE, FRE, RDRF Flag Set Timing (Mode 0)

b) Mode 1 Receiving

The ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPU after the end of a receiving transfer, when the final stop bit is detected. Also, if the receiving data length is 8 bits, the 9th bit indicating address/data will be invalid. If either the ORE or FRE flags is active, the data in the SIDR register will be invalid.

D6 D7 StopData

Receiving interrupt

PE,ORE,FRE

RDRF

2.5 UART


Fig. 2.5.5 ORE, FRE, RDRF Flag Set Timing (Mode 1)

c) Mode 2 Receiving

The ORE and RDRF flags are set and the interrupt request signal is sent to the CPU after the end of a receiving transfer, when the final stop bit is detected. If the ORE flag is active, the data in the SIDR register will be invalid.

Fig. 2.5.6 ORE, RDRF Flag Set Timing (Mode 2)

d) Mode 0 and Mode 1 Sending

The TDRE flag is cleared when data is written to the SODR register, and set (and an interrupt request sent to the CPU) as soon as the data is transferred to the internal shift register, to enable the next data write cycle. During sending operation, if ‘0’ is written to the TXE bit in the SCR register (including the RXE bit in mode 2), the TDRE bit inthe SSR register will be set to ‘1’ and UART sending operation will be disabled as soon as the sending shifter stops. Before sending stops, however, data written to the SODR register will be sent.

Fig. 2.5.7 TDRE Flag Set Timing (Mode 0, 1)

D7 Address data StopData

Receiving interrupt

ORE,FRE

RDRF

D5 D6 D7Data

Receiving interrupt

ORE

RDRF

SODR write

Sending interrupt

SOT output

Interrupt request to CPU

TDRE

ST: Start bit, D0 to D7: Data bits, SP: Stop bit, A/D: Address/data multiplexer

ST STSPSPD0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3A/D

2.5 UART

127

Fig. 2.5.8 TDRE Flag Set Timing (Mode 2)

(6) UART in Relation to EI2OS (Expanded Intelligent I/O Service)

See Section 3.3.2 “EI2OS.”

2.5.5 Cautionary InformationCommunication mode settings should be made while the UART is not operating. Accuracy of data sent or received during mode settings is not assured.

2.5.6 Sample ApplicationMode 2 is used when one host CPU is connected to multiple slave CPUs. (See Figure 2.5.9.) The UART only supports communications interfacing with host computer units.

Fig. 2.5.9 Sample System Configuration Using Mode 1

Transmission begins when the host CPU transfers address data. Address data is data handled while the A/D bit in the SCR register is set to ‘1’ and is used to select the slave CPU that is to receive the transmission. The selected slave CPU then communicates with the host CPU according to conditions established by the user. In normal data, the A/D bit is set to ‘0.’ Figure 2.5.10 illustrates the flow of this process.

No parity check function is available in mode 2, so that the PEN bit in the SCR register should be set to ‘0.’

SODR write

Sending interrupt

SOUT output

Interrupt request to CPU

TDRE

DO to D7: Data bits

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

Host CPU

Slave CPU #0

SOT

SIN

SOT SIN

Slave CPU #1

SOT SIN

2.5 UART


Fig. 2.5.10 Communications Flowchart Using Mode 1

(Host CPU)

START

Set transfer mode to 1

Set D0 to D7 to data selecting slave

Set A/D byte to ‘0’

Enable receiving operation

Communicate with slave CPU

Disable receiving operation

CPU, set A/D to ‘1’ and transfer1 byte

Communicationended?

Communicate withother slave CPU’s?

END

Yes

Yes

No

No

2.6 10-Bit 8-Input Channel A/D Converter (with 8-bit Resolution Mode)

129


The 10-bit 8-input Channel A/D Converter converts analog input voltage into digital values, and provides the following features.

• Conversion time : minimum 6.13 µs per channel (at 98 machine cycles/machine clock 16 MHz, including sample & hold time)

• Sample & hold time : minimum 3.75 µs per channel (at 60 machine cycles/machine clock 16 MHz)

• RC type successive approximation conversion with sample & hold circuit

• 10-bit/8-bit resolution

• Program selection analog input from 8 channels

• Single conversion mode : conversion of one selected channel

• Scan conversion mode : continuous conversion of multiple channels, programmable for up to 8 channels

• Continuous conversion mode: repeated conversion of a designated channel

• Stop conversion mode: conversion of one channel, followed by a temporary pause and standby for next instruction (may be synchronized with start of conversion)

• A/D conversion can be followed by an A/D conversion interrupt request to CPU. This interrupt, an option that is ideal for continuous processing can be used to start EI2OS to transfer the results of A/D conversion to memory.

• Startup may be by software, external trigger (falling edge) or multi-function timer (rising edge).

2.6.1 Register List

BUSY INT INTE PAUS STS1 STS0 STRT Reserved

⇐ Bit no.

Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (–)Initial value⇒ (0) (0) (0) (0) (0) (0) (0) (0)

Control status register - high

Address : 00002DH

15 14 13 12 11 10 9 8

ADCS1

MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

⇐ Bit no.

Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value⇒ (0) (0) (0) (0) (0) (0) (0) (0)

Control status register - low

Address : 00002CH

7 6 5 4 3 2 1 0

ADCS0

S10 – – – – – D9 D8

⇐ Bit no.

Read/write ⇒ (R/W) (R) (R) (R) (R) (R) (R) (R)Initial value⇒ (0) (0) (0) (0) (0) (0) (X) (X)

Data register - high

Address : 00002FH

15 14 13 12 11 10 9 8

ADCR1

D7 D6 D5 D4 D3 D2 D1 D0

⇐ Bit no.

Read/write ⇒ (R) (R) (R) (R) (R) (R) (R) (R)Initial value⇒ (X) (X) (X) (X) (X) (X) (X) (X)

Data register - low

Address : 00002EH

7 6 5 4 3 2 1 0

ADCR0

Chapter 2:



2.6.2 Block Diagram

Fig. 2.6.1 Block Diagram

Inpu

t circ

uit

Sample-and-hold circuit

Comparator

D/A converter

Sequential comparison

Da

ta b

usATGX

Operating clock

register

Data register

Dec

oder

A/D control register 1

A/D control register 2

Prescaler

AN0AN1AN2AN3

MPX

AVCC

AVR

AVSS

ADCR0,1

ADCS0,1

Peripheral clock circuit

Trigger start

AN4AN5AN6AN7

Timer startMulti-function timer (RT0 output)


131

2.6.3 Detailed Register Descriptions(1) ADCS1, ADCS0 (Control Status Registers)

Register Configuration


These registers provide control and status indicators for the A/D converter. The ADCS0 register data should not be overwritten while the A/D converter is operating.


Bit Descriptions

[Bit 15] BUSY (Busy flag and stop)

Read : This bit indicates that the A/D converter is operating. It is set when A/D conversion starts, and cleared when conversion ends.

Write : Writing ‘0’ to this bit will forcibly stop conversion. This is used to forcibly stop conversion in continuous and stop conversion modes.

Writing ‘1’ to this bit has no effect on operation. In single conversion mode, this bit is cleared when A/D conversion ends. In continuous and stop mode, this bit is not cleared until conversion is stopped by writing ‘0.’ This bit is initialized to ‘0’ at a reset.

[CAUTION] Do not execute a forced stop and software start (BUSY=0, STRT=1) simultaneously.

[Bit 14] INT (Interrupt)

This bit indicates data display bit. This bit is enabled when the conversion data is stored in ADCR. When this bit is set with the bit 5 (INTE) being 1, the interrupt request takes place. I2OS is activated if it is enabled. Writing 1 to this bit is meaningless. Clearing this bit is triggered by writing 0 to the CPU and the I2OS transfer. This bit is initialized to 0 at reset.

[CAUTION] Clearing this bit by writing 0 to the CPU should be done during halt of A/D conversion.

BUSY INT INTE PAUS STS1 STS0 STRT Reserved

⇐ Bit no.

Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (–)Initial value⇒ (0) (0) (0) (0) (0) (0) (0) (0)

Control status register - high

Address : 00002DH

15 14 13 12 11 10 9 8

ADCS1

MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

⇐ Bit no.


Control status register - low

Address : 00002CH

7 6 5 4 3 2 1 0

ADCS0



[Bit 13] INTE (Interrupt enable)

This bit enables/disables the interrupt when conversion ends.

0: Interrupt disabled


This bit should always be set when using I2OS functions. I2OS provided with the ability to be initiated with the interrupt requests.

This bit is initialized to ‘0’ at a reset.

[Bit 12] PAUS (A/D converter pause)

This bit is set when the A/D conversion operation is temporarily stopped.

Because the A/D converter has only one register in which to store the results of conversion, the last data will be lost in continuous conversion mode unless the results of the last conversion have already been read by the CPU. Therefore continuous conversion mode requires the system settings for the use of I2OS to automatically transfer the conversion results to memory as soon as each conversion is completed.

Note that it is possible for cases such as multiple interrupts to keep the existing conversion data from being transferred before new data is produced by the next conversion cycle. This bit provides a preventive function designed to handle such cases, by which this bit is set during the interval between the end of conversion and the transfer of the data register contents by I2OS. During that interval A/D conversion is stopped so that no new conversion data is stored. Once the transfer is completed by I2OS, the A/D converter automatically resumes conversion processing. This register is therefore valid only when using I2OS functions. This bit is initialized to ‘0’ at a reset.

[Bits 11, 10] STS1, STS0 (Start source select)

The value of these bits determines the A/D conversion start source. These bits are initialized to ‘00’ at a reset.

Table 2.6.1 STS Bit Settings

In modes with more than one start source, A/D conversion will be started by the first source to occur. Because the start sources are changed immediately when bit settings are changed, settings may be changed during A/D operation only when the intended conversion start source is not present.

When the external trigger input level is ‘L,’ STS bits can be set to start A/D conversion from external pin trigger sources.

[Bit 9] STRT (Start)

Write ‘1’ to this bit to start A/D conversion. To restart conversion, write ‘1’ to this bit again. No restart may be applied in stop mode. This bit is initialized to ‘0’ at a reset.

[CAUTION] Do not execute a forced stop and software start (BUSY=0, STRT=1) simultaneously.

STS1 STS0 Function

0 0 Software start

0 1 External pin trigger start and software start

1 0 Multi-function timer start and software start

1 1 External pin trigger start, multi-function timer start and software start


133

[Bit 8] Test bit

This is a test bit. Only the value ‘0’ should be written to this bit.

[Bits 7, 6] MD1, MD0 (A/D converter mode set)

These bits determine the operating mode setting. The following mode settings are available.

Table 2.6.2 MD Bit Settings

Single mode : Continuous A/D conversion from selected channel(s) ANS2 to ANS0 to selected channel(s) ANE2 to ANE0 with a pause after every conversion cycle.

Continuous mode : Repeated A/D conversion cycles from selected channels ANS2 to ANS0 to selected channels ANE2 to ANE0.

Stop mode : A/D conversion for each channel from selected channels ANS2 to ANS0 to selected channels ANE2 to ANE0, followed by a pause. Restart is determined by the occurrence of a start source.

.

MD1 MD0 Operating mode

0 0 Single mode; all restarts during operation enabled (initial value)

0 1 Single mode; restarts during operation disabled

1 0 Continuous mode; restarts during operation disabled

1 1 Stop mode; restarts during operation disabled

• When A/D conversion is started in continuous mode or stop mode, conversion operation continued until stopped by the BUSY bit.

• Conversion is stopped by writing ‘0’ to the BUSY bit.

• All restarts are disabled for any of the multi-function timer, external trigger and software start sources in single, continuous and stop modes.



[Bits 5, 4, 3] ANS2, ANS1, ANS0 (Analog start channel set)

These bits determine the starting channel for A/D conversion. When the A/D converter starts up, A/D conversion will begin from the channel selected by these bits.

Table 2.6.3 Conversion Start Channel Selected by ANS Bit Values

While A/D conversion is in progress, this bit group can be read to indicate the number of the channel on which A/D conversion is taking place. While A/D conversion is not executed in stop mode, this bit group indicates the channel on which the last conversion was performed immediately prior to stoppage. This bit group is initialized to ‘000’ at a reset.

[Bits 2, 1, 0] ANE2, ANE1, ANE0 (Analog end channel set)

These bits determine the ending channel for A/D conversion. When the A/D converter starts up, A/D conversion will end at the channel selected by these bits.

Table 2.6.4 Conversion End Channel Selected by ANE Bit Values

When the setting is the same as the channel setting in bits ANS2 to ANS0, conversion will be performed on the selected channel only. If continuous mode or stop mode is selected, the conversion channel will reach the channel designated by this bit group and then return to the channel selected by the ANS2 to ANS0 bits. Also if the ANS channel number is greater than the ANE channel number, channel conversion will proceed to AN7, after beginning with the channel selected by the ANS bits and then return to AN0 before ending at the channel designated by the ANE bit group, as in the following example.

Example:

Channel settings: ANS = Ch6, ANE = Ch3, single conversion modeOperation: Conversion channel Ch6 → Ch7 → Ch0 → Ch1 → Ch2 → Ch3

This bit group is initialized to ‘000’ at a reset.

ANS2 ANS1 ANS0 Start channel

0 0 0 AN0

0 0 1 AN1

0 1 0 AN2

0 1 1 AN3

1 0 0 AN4

1 0 1 AN5

1 1 0 AN6

1 1 1 AN7

ANE2 ANE1 ANE0 End channel

0 0 0 AN0

0 0 1 AN1

0 1 0 AN2

0 1 1 AN3

1 0 0 AN4

1 0 1 AN5

1 1 0 AN6

1 1 1 AN7


135

(2) ADCR1, ADCR0 (Data registers)



This register group is used to store the results of A/D conversion in digital values. The conversion results are in 10-bit format when the S10 bit has the value ‘0’, and in 8-bit format when the value is ‘1.’ The ADCR1 register contains the 2 most significant bits of the conversion value, and the ADCR0 register the lower 8 bits. The values of bits D9 to D0 are updated every time a conversion cycles is completed. Normally the value of these bits is the last converted value. All bit values except the S10 bit are undefined at reset. The S10 is initialized to ‘0’ at a reset.

The read values of bits 15 to 10 in the ADCR1 register are ‘0’ in 10-bit mode. In 8-bit mode the entire contents of the ADCR1 register are undefined, and all results are stored in the ADCR0 register.

The S10 bit must only be set or changed while A/D operation is stopped before conversion processing. If this bit is overwritten after conversion processing, the contents of the ADCR registers will be undefined.

S10 – – – – – D9 D8

⇐ Bit no.

Read/write ⇒ (R/W) (R) (R) (R) (R) (R) (R) (R)Initial value⇒ (0) (0) (0) (0) (0) (0) (X) (X)

Data register - high (in 10-bit mode)

Address : 00002FH

15 14 13 12 11 10 9 8

ADCR1

S10 – – – – – – –

⇐ Bit no.

Read/write ⇒ (R/W) (–) (–) (–) (–) (–) (–) (–)Initial value⇒ (0) (–) (–) (–) (–) (–) (–) (–)

Data register - high (in 8-bit mode)

Address : 00002FH

15 14 13 12 11 10 9 8

ADCR1

D7 D6 D5 D4 D3 D2 D1 D0

⇐ Bit no.

Read/write ⇒ (R) (R) (R) (R) (R) (R) (R) (R)Initial value⇒ (X) (X) (X) (X) (X) (X) (X) (X)

Data register - low

Address : 00002EH

7 6 5 4 3 2 1 0

ADCR0



2.6.4 Operating DescriptionThe A/D converter uses a successive approximation method of operation, and has 8-bit or 10-bit resolution. Only one channel of 16-bit registers is available to store the results of conversion, so that previous conversion data is lost each time a conversion cycle is completed. Therefore when operating in continuous conversion mode, it is necessary to use I2OS to sequentially transfer conversion data to memory.

The following pages describe the operating modes.


137

Single Mode

In single conversion mode, the analog input signals selected by the ANS bits and ANE bits are converted in order until the completion of conversion on the end channel determined by the ANE bits. A/D conversion then ends. If the start channel and end channel are the same (ANS=ANE), then conversion will operate on that channel only.

Example 3. ANS=000, ANE=011 ⇒ Start → AN0 → AN1 → AN2 → AN3 → End

Example 4. ANS=010, ANE=010 ⇒ Start → AN2 → End

Single Mode: Sample I2OS Startup

• Complete conversion of analog input AN1 to AN3

• Transfer conversion data in order to address 200H to 205H

• Software startup

• Highest priority interrupt level

I2OS Settings


MOV ICR10,#08H............................................................................................... (1)

Set I2OS descriptors

MOV BAPL,#00H ............................................................................................... (2)

MOV BAPM,#02H.............................................................................................. (3)

MOV BAPH,#00H............................................................................................... (4)

MOV ISCS,#18H................................................................................................. (5)

MOV IOAL,#2EH ............................................................................................... (6)

MOV IOAH,#00H ............................................................................................... (6)

MOV DCTL,#03H............................................................................................... (7)

MOV DCTH,#00H .............................................................................................. (7)

Set A/D converter

MOV ADCS0,#0BH............................................................................................ (8)

MOV ADCS1,#A2H............................................................................................ (9)

Other processing I2OS ends interrupt sequence

MOV ADCS1,#80HRETI..................................................................................................................... (10)

(1) Set highest priority interrupt level, start I2OS at interrupt, and set descriptor address

(2)(3)(4) Transfer destination addresses for conversion data

(5) Word-length transfer units, increment transfer destination address after transfer, and transfer from I/O to memory

(6) Set A/D converter results register

(7) Perform 3 I2OS transfer cycles, equal to number of conversion cycles.

(8) Single mode, start channel AN1, end channel AN3

......



(9) Software startup, start A/D conversion

(10) Recovery from interrupt

ICR10 : Interrupt control register

BAPL : Buffer address pointer - low

BAPM : Buffer address pointer - middle

BAPH : Buffer address pointer - high

ISCS : I2OS status register

I/OAL : I/O address register - low

I/OAH : I/O address register - high

DCTL : Data counter - low

DCTH : Data counter - high

Startup ⇒ AN1→ Interrupt → I2OS transfer

End Interrupt sequence

Parallel processing

AN2→ Interrupt → I2OS transfer


⇓

⇓

⇓


139

Continuous Mode

In continuous mode the analog input signals selected by the ANS bits and ANE bits are converted in order until the completion of conversion on the end channel determined by the ANE bits, then the converter returns to the ANS channel for analog input and repeats the process continuously. If the start channel and end channel are the same (ANS=ANE), then conversion will operate continuously on that channel only.

Example 1. ANS=000, ANE=011⇒ Start → AN0 → AN1 → AN2 → AN3 → AN0 ... → repeat

Example 2. ANS=010, ANE=010⇒ Start → AN2 → AN2 → AN2 ... → repeat

In continuous mode, conversion is repeated until ‘0’ is written to the BUSY bit. Writing ‘0’ to the BUSY bit forcibly stops the conversion operation.

Because forcibly stopping the operation requires the A/D converter to stop in the middle of a conversion cycle, no values are obtained from the incomplete conversion cycle. The value in the ADCR register will be the value of the last conversion cycle immediately before the stop.

Continuous Mode: Sample I2OS Startup

• Complete conversion of analog input on channels AN3 to AN5, obtain 2 cycles of conversion data from each channel.

• Transfer data in order to address 600H to 60BH

• Startup at external signal edge

• Highest priority interrupt level

I2OS Settings


MOV ICR10,#08H................................................................................................ (1)


MOV BAPL,#00H ............................................................................................... (2)

MOV BAPM,#06H.............................................................................................. (3)

MOV BAPH,#00H............................................................................................... (4)

MOV ISCS,#18H................................................................................................. (5)

MOV IOAL,#2EH ............................................................................................... (6)

MOV IOAH,#00H ............................................................................................... (6)

MOV DCTL,#06H............................................................................................... (7)

MOV DCTH,#00H .............................................................................................. (7)

Set A/D converter

MOV ADCS0,#9DH............................................................................................ (8)

MOV ADCS1,#A4H............................................................................................ (9)

Other processing I2OS end interrupt sequence

MOV ADCS1,#80H........................................................................................... (10)

RETI

......



(1) Set interrupt level at highest priority, start I2OS at interrupt, and set descriptor address


(5) Word-length transfer units, increment transfer destination address after transfer, and transfer from I/O to memory.

(6) Transfer source address

(7) Perform 6 I2OS transfer cycles, transfer 3 channels × 2 cycles of data

(8) Continuous mode, start channel AN3, end channel AN5

(9) External edge startup, start A/D conversion


Startup ⇒ AN3→ Interrupt → I2OS transfer

End



⇓

⇓

⇓Interrupt sequence

After total of 6 transfer cycles


141

Stop Mode

In stop mode the analog input signals selected by the ANS bits and ANE bits are converted in order, but conversion operation pauses for each channel. The pause is released by applying another start signal. At the completion of conversion on the end channel determined by the ANE bits, the converter returns to the ANS channel for analog input signal and repeats the conversion process continuously.

If the start channel and end channel are the same (ANS=ANE), then conversion will operate continuously on that channel only.

Example 1. ANS=000, ANE=011⇒ Start → AN0 → stop → start → AN1 → stop → start → AN2

→ stop → start → AN3 → stop → start → AN0 ... → repeat

Example 2. ANS=010, ANE=010⇒ Start → AN2 → stop → start → AN2 → stop → start → AN2 ... → repeat

In stop mode the startup source is only the source determined by the STS1, STS0 bits. This mode enables synchronization of the conversion start signal.

Stop Mode: Sample I2OS Startup

• Execute conversion of analog input channel AN3 12 times at fixed intervals.

• Transfer data in order to address 600H to 617H

• Startup at external signal edge

• Interrupt level at highest priority

I2OS Settings


MOV ICR10,#08H............................................................................................... (1)


MOV BAPL,#00H ............................................................................................... (2)

MOV BAPM,#06H.............................................................................................. (3)

MOV BAPH,#00H............................................................................................... (4)

MOV ISCS,#18H................................................................................................. (5)

MOV IOAL,#2EH ............................................................................................... (6)

MOV IOAH,#00H ............................................................................................... (6)

MOV DCTL,#0CH .............................................................................................. (7)

MOV DCTH,#00H .............................................................................................. (7)

Set A/D converter

MOV ADCS0,#DBH ............................................................................................ (8)

MOV ADCS1,#A4H............................................................................................. (9)

Other processing

I2OS end interrupt sequence

MOV ADCS1,#80H............................................................................................. (10)RETI

(1) Set interrupt level at highest priority, start I2OS at interrupt, and set descriptor address

......




(5) Word-length transfer units, increment transfer destination address after transfer, and transfer data from I/O to memory. End at request from peripheral resource.

(6) Transfer source address

(7) Perform 12 I2OS transfer cycles

(8) Stop mode, start channel AN3, end channel AN3 (1 channel conversion)

(9) External edge startup, start A/D conversion


Start ⇒ AN3→ Interrupt → I2OS transfer

End

Stop

External edge start

⇓

⇓

⇓Interrupt sequence

After 12 transfer cycles


143

Conversion Operations Using I2OS

The following chart illustrates the flow of operation from the start of A/D conversion through the transfer of conversion data, in continuous conversion mode.

Fig. 2.6.2 Example Use of I2OS

Start A/D conversion

Start I2OS

Indicates action determined by I2OS setting.

Sample & hold data

Convert data

End conversion

Transfer data

Generate interrupt

Process interrupt

Clear interrupt



Conversion Data Protection Function

A feature of the A/D converter is a conversion data protection function that allows the unit to protect the results of continuous conversion and multiple data sets.

Because there is only one conversion data register, continuous A/D conversion means that the last data in the register is lost each time conversion results are stored after a conversion cycle ends. To protect against loss of data, the A/D converter has a function that causes it to pause without storing the new data in the register even if the current conversion cycle ends until the previous data has been transferred to memory by I2OS.

The pause is cancelled when the I2OS transfer to memory is completed, and conversion resumes.

If the previous data is transferred to memory in time, A/D conversion continues without pause.

[CAUTION] This function is related to the INT and INTE bits in the ADCS1 register.

The data protection function has been designed to operate only in interrupt-enabled (INTE=1) state.

If the interrupt is disabled (INTE=0), this function will not operate and continuous A/D conversion processing will cause the previous set of conversion data to be lost when the next set is stored in the register.

Also, in interrupt-enabled mode (INTE=1), the INT bit cannot be cleared without using I2OS so that the data protection function may force A/D conversion to stay in a state of pause. In this case, an interrupt sequence is used to clear the INT bit and release the pause.

If interrupts are disabled while the A/D converter is in a state of pause during I2OS transfer, it is possible that the A/D converter will resume operation and the contents of the conversion data register may be lost before transfer can be completed.

Also, applying a restart during a state of pause destroys data waiting in the register.


145

.

Fig. 2.6.3 Flow of Data Protection Function Using I2OS

[CAUTION] The A/D start source bits STS1, STS0 in the ADSC1 register are set whenever an external trigger or timer unit is used to start the A/D converter, and the input value of the external trigger or timer unit signal should be at inactive level when this setting is made. If the signal is active, operation may start immediately.

The STS1, STS0 bit settings should be made when the ATGX pin is at ‘1’ (input) and the internal timer (multi-function timer) is set to ‘0’ (output).

Flow of the data preservation function (when using I2OS)

Set I2OS

Note

Continue

Interrupt routine

Flow during A/D converter pause omitted

Note: Applying a restart during a state of pause destroys data waiting in the register.Start A/D continuous conversion

End 1st conversion cycle

Store results in data register

End 2nd conversion cycle Start I2OS

End 3rd conversion cycle

Pause A/D conversion

I2OS ended?Store results in data register

I2OS ended?

Terminate all conversion cycles

Stop A/D conversionEnd

Start I2OS

Start I2OS

NOYESYES

NO



2.6.5 Other Precautionary InformationThe ADER bit(s) corresponding to pins used for analog input should be set to ‘1.’

The pins of port 5 are controlled as follows.

0: Port input mode

1: Analog input mode

These bits are initialized to ‘1’ after a reset.

[CAUTION] In port input mode, an intermediate-level signal input will cause an input leak current flow. Therefore whenever using analog input signals, be sure to select analog input mode.

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

⇐ Bit no.



ADER 000015H

15 14 13 12 11 10 9 8

ADER

2.7 PWM

147

2.7 PWM

The PWM block is an 8-bit reload timer module producing a PWM (pulse width modulation) output signal with pulse output controlled by the operation of the timer.

The hardware configuration includes an 8-bit timer/down-counter, two 8-bit reload registers for setting L-width and H-width values, control registers external pulse output pin, and interrupt output. The PWM block provides the following functions.

• PWM output operations : Pulse waveform output at any desired period and duty ratio.

Can also be used as a D/A converter with additional outside circuits.

Can output interrupt requests for counter underflow conditions.

2.7.1 A List of Registers

2.7.2 Block Diagram


PWMC R/W Operating mode control

PRLL R/W Holds L-level pulse width reload value

PRLH R/W Holds H-level pulse width reload value

Address: 000020H

000023H

000022H

8 bit (Function)

Output enabled (Port block)

TBT output, main clock divided by 4TBT output, main clock divided by 512

Count clock

PWM0

Invert Clear

Reload

IRQ

L/H select

(Operating mode control)

TBT: Timebase timer

PWM

selection

output latch

PEN

L/H selector

PRLL PRLBH

PRLHPWMC

FFMC-16BUS

PCNT (downcounter)

2.7 PWM


2.7.3 Detailed Register Descriptions(1) PWMC (PWM operating mode control register)

This register contains 5 bits that provide PWM block operating mode selection, pin output control, count clock selection and trigger control.

[Bit 7] PEN (PWM enable): PWM operation enable bit

This bit determines the start of PWM operation and the operating mode as follows.

Write ‘1’ to this bit to start the PWM count.

This bit is initialized to ‘0’ at a reset, and is read/write enabled.

[Bit 6] PCKS (PWM count clock select): Count clock select bit

This bit selects the down-counter operating clock.


[Bit 5] POE (PWM output enable): PWM pin output enable bit

This bit controls the external PWM pulse output pin as follows.


0 Stop operation (hold ‘L’ level output)

1 Start PWM operation

0 Main clock divided by 512

1 Main clock divided by 4

0 General-purpose I/O port pin function (Pulse output disabled)

1 PWM output pin function (Pulse output enabled)

PEN PCKS POE PIE PUF – – ∗

Initial value

R/W R/W

7 6 5 4 3 2 1 0

PWMCAddress : 000020H

R/W R/W R/W R/W

bit

0 X X 10 0 0 0

2.7 PWM

149

[Bit 4] PIE (PWM interrupt enable): PWM interrupt enable bit

This bit controls the PWM interrupt enable function.

When this bit is ‘1,’ an interrupt request will be generated whenever the PUF flag is set to ‘1.’

When this bit is set to ‘0,’ no interrupt request will be generated.

[Bit 3] PUF (PWM underflow flag): PWM counter underflow flag

This bit is set to ‘1’ when a PWM counter underflow occurs.

This bit is set to ‘1’ when the counter counts down from 00H to FFH, creating an underflow event. The bit value can be set to ‘0’ by writing ‘0’ or by a reset. For read-modify-write instructions, the read value is always ‘1.’


[Bit 0] Reserved.

When setting the PWMC register, always write ‘1’ to this bit.

(2) PRLL/PRLH (Reload registers)

These registers store the reload value for the down-counter PCNT register. Both are 8-bit registers, and have the following functions:

Both registers are read/write enabled.

0 Interrupt disabled

1 Interrupt enabled

0 No PWM counter underflow

1 PWM counter underflow occurred

Register Function

PRLL Stores L-level reload value

PRLH Stores H-level reload value

7 6 5 4 3 2 1 0

PRLL000022H

15 14 13 12 11 10 9 8

PRLH000023H

Address :

Access: R/W Initial value: undefined

2.7 PWM


2.7.4 Operating DescriptionThe PWM block has two 8-bit reload registers for L-level and H-level settings (PRLL, PRLH). Values written to these registers are reloaded at every alternation between L/H levels of the 8-bit down-counter (PCNT) so that the PWM pin output value is inverted at every reload cycle caused by a counter borrow event. This operation creates a pulse at the PWM output pin having L-level and H-level values corresponding to these reload register values.

Operation is started, or restarted, by writing bit values to these registers.

The following table shows the relation between reload operation and pulse output.

Table 2.7.1 Relation between Reload Operation and Pulse Output

When bit 4 (PIE) in the PWMC register is ‘1,’ an interrupt request is generated, indicating a borrow event as the counter value changes from 00H to FFH.

(1) Operating Mode

The PWM block starts operation when ‘1’ is written to bit 0 (PEN) in the PWMC (PWM mode control) register. This starts the counter operation.

Once operation is started, the count can be stopped by writing ‘0’ to bit 0 (PEN) in the PWMC (PWM mode control) register. After the count stops the pulse output is held at L level.

The PWM block has the following operating modes.

While the PWM is operating, a continuous pulse waveform is output with a designated frequency and designated duty ratio (the ratio between the H-level interval and L-level interval in the pulse wave). The PWM starts the pulse wave output, and does not stop until a ‘stop’ setting is entered.

Fig. 2.7.2 PWM Operating Mode: Output Waveform

Reload operation Change in pin signal output

PRLH ⇒ PCNT PWM [0 ⇒ 1] Rise

PRLL ⇒ PCNT PWM [1 ⇒ 0] Fall

Output pin PWM

⇓ Operation started by PEN bit (from L-level)

(Start)L: PRLL valueH: PRLH valueT: count clock (from PWMC clock select)

PEN

T × (L+1) µs T × (H+1) µs

2.7 PWM

151

(2) Reload Values and Pulse Widths

‘The value written to the reload register plus one (+1)’ is multiplied by the period of the count clock and the result is the width of the output pulse. Note that this means, if the reload register has a value of 00H, the pulse width will be equal to one period of the count clock. The following formulas determine the calculation of the pulse width.

L: PRLL value

Pl = T × (L+1) µs H: PRLH value

Ph = T × (H+1) µs T: count clock

Ph: high-level pulse width

Pl: low-level pulse width

(3) Count Clock Selection

The count clock used for PWM operations uses the output signal of a peripheral clock unit. There is a selection of two types of count clock input.

When bit 6 (PCKS) in the PWMC register is ‘0’ the count clock will be the main clock signal divided by 29.

When bit 6 (PCKS) in the PWMC register is ‘1’ the count clock will be the main clock signal divided by 22.

Note that irregularity may occur in the first count clock period after the PWM is started by a trigger signal, or the first period after the unit stops.

(4) Pulse Pin Output Control

Pulse output signals produced by the PWM module can be output from the external PWM pins.

The external pin output is enabled by bit 5 (POE) in the PWMC register. When this bit is ‘0’ (its initial value), no pulse signal is output from the external pins, and the pins function as a general-purpose port. When this bit is set to ‘1’ the PWM pulse signal is output from the external pins.

(5) Reload Register Write Timing

Writing to the reload registers PRLL and PRLH should be performed using word transfer instructions.

Unintended pulse widths may result from writing using two repeated byte transfer instructions in some timings.

On the above timing chart the PRLL value is rewritten from A to C before point (1), and the PRLH value is rewritten from B to D after point (1). Thus at timing (1) the PRL values are PRLL=C, PRLH=B so that for only one pulse cycle the L-level has a count value of C and the H-level has a count value of B.

PWMB C

A DA DB C CB

(1)

2.7 PWM


(6) Interrupts

Interrupts in the PWM module are normally activated when the L-level reload value is counted out and a borrow event occurs. The interrupt is also activated by the first counter borrow event after the PUF flag is cleared.

(7) Hardware Initialization

Hardware in the PWM block is initialized to the following values at a reset.

<Register> • PWMC=> 00000XX1B

<Pulse output> PWM=> ‘L’

<Interrupt request> IRQ=> ‘L’

Other than the above, no hardware is initialized.

2.8 16-Bit Reload Timer (with Event Count Function)

153


The 16-bit timer is configured from a 16-bit down-counter, a 16-bit reload register, a control register, and four output pins (with I/O functions selected by the timer pin select register). The choice of input clock signals includes 3 types of internal clock plus an external clock signal. The output pins (TOT) output a toggle-output waveform in reload mode, and in one-shot mode they output a square wave to indicate that the counting is in progress. The input pins are used for event input in event count mode, and can be used for trigger input or gate input in internal clock mode.

The MB90660A series includes four channels of this type of timer.

2.8.1 Register List

– – – – CSL1 CSL0 MOD2MOD1

Timer control status register - high

Address : ch0 000031H⇐Bit no.

Read/write⇒ – – – – (R/W) (R/W) (R/W) (R/W)Initial value⇒ – – – – (0) (0) (0) (0)

ch1 000035H

15 14 13 12 11 10 9 8

MOD0 ∗ OUTL RELD INTE UF CNTE TRG

⇐Bit no.

Read/write⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value⇒ (0) (0) (0) (0) (0) (0) (0) (0)

7 6 5 4 3 2 1 0

TMCSR

– OTE3 CSB3 CSA3 – OTE2 CSB2 CSA2

Timer pin control register - high

Address : 000057H

⇐Bit no.

Read/write ⇒ – (R/W) (R/W) (R/W) – (R/W) (R/W) (R/W)Initial value ⇒ – (0) (1) (1) – (0) (1) (0)

15 14 13 12 11 10 9 8


⇐Bit no.


Timer pin control register - lowAddress : 000056H

7 6 5 4 3 2 1 0

TPCR

ch2 000039H

ch3 00003DH

Timer control status register - low

Address : ch0 000030Hch1 000034H

ch2 000038H

ch3 00003CH

16-bit timer register - high / 16-bit reload register - high



ch1 000037H

15 14 13 12 11 10 9 8

⇐Bit no.


7 6 5 4 3 2 1 0

TMR/TMRLR

ch2 00003BH

ch3 00003FH

16-bit timer register - low / 16-bit reload register - low


ch2 00003AH

ch3 00003EH



2.8.2 Block Diagram

Fig. 2.8.1 Block Diagram (1)

Fig. 2.8.2 Block Diagram (2)

16-bit reload timer

OUT

Peripheral clock

Prescaler

Clear

GATE

Trigger

TIN

16-bit down counter

Clock selector

Reload

CTL.

IN CTL

φ

21

φ

23

φ

25

CSL1

CSL0

UF

IRQ

OUTL

INTE

UF

CNTE

TRG

F2 M

C-1

6BU

S

MOD2

MOD1

MOD0

16/

/16

/2

/3

2/

3

Clear

TOT

I2OSCLR

EXCK

Serial baud rate

RELD

(channel 0 only)

/8

16-bit reload timer TIM0

Selector

Timer I/O pins

*Provides selection of timer channel

channel 0TIN0

TOT0

16-bit reload timerchannel 1

TIN1

TOT1


TIN2

TOT2


TIN3

TOT3

TIM1

TIM2

TIM3

and direction (input/output) for each pin separately.


155

2.8.3 Detailed Register Descriptions(1) Timer Control Status Registers (TMCSR)



This register controls the 16-bit timer operating mode and interrupts. Rewriting of bits other than the UF, CNTE, and TRG bits should be done when CNTE=0.

Bit Description

[Bits 11, 10] CLS1, CSL0 (Clock select 1, 0)

Count clock select bits.

Table 2.8.1 shows the clock source selection options.

Table 2.8.1 Clock Source Setting Using CSL Bits

CSL1 CSL0Clock source

(machine cycle φ =16 MHz)

0 0 φ /21 (0.125 µs)

0 1 φ /23 (0.5 µs)

1 0 φ /25 (2.0 µs)

1 1 External event count mode

– – – – CSL1 CSL0 MOD2MOD1

Timer control status register - high


Read/write⇒ – – – – (R/W) (R/W) (R/W) (R/W)Initial value⇒ – – – – (0) (0) (0) (0)

ch1 000035H

15 14 13 12 11 10 9 8

MOD0 ∗ OUTL RELD INTE UF CNTE TRG

⇐Bit no.

Read/write⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value⇒ (0) (0) (0) (0) (0) (0) (0) (0)

7 6 5 4 3 2 1 0

TMCSR

ch2 000039H

ch3 00003DH

Timer control status register - low


ch2 000038H

ch3 00003CH



[Bits 9, 8, 7] MOD2, MOD1, MOD0

These bits determine operating mode as well as I/O pin functions.

The MOD2 bit is used to select input pin functions. When this bit is ‘0’ the input pin is used as a trigger input pin, so that whenever a valid edge is input the contents of the reload register are loaded into the counter and count operation continues. When this bit is ‘1’ gate count mode is selected, and the input pin becomes a gate, meaning that the counting will continue only as long as a valid level signal is input.

The MOD1, MOD0 bits are used to determine the pin functions in each mode. Tables 2.8.2 and 2.8.3 list the combinations of MOD2, MOD1, MOD0 bit settings.

Table 2.8.2 MOD2, MOD1, MOD0 bit settings (1)

Table 2.8.3 MOD2, MOD1, MOD0 bit settings (2)

[Bit 6] *: Reserved bit

This bit is reserved. The write value should always be ‘0.’

The read value is always ‘0.’

Internal clock mode (CSL0, CSL1=00, 01, 10)

MOD2 MOD1 MOD0 Input pin function Valid edge or level

0 0 0 Trigger disabled –

0 0 1 Trigger input Rising edge

0 1 0 ⇑ Falling edge

0 1 1 ⇑ Both edges

1 x 0 Gate input ‘L’ level

1 x 1 ⇑ ‘H’ level

Event count mode (CSL0, CSL1=11)

MOD2 MOD1 MOD0 Input pin function Valid edge or level

X

0 0 – –

0 1 Trigger input Rising edge

1 0 ⇑ Falling edge

1 1 ⇑ Both edges

X: May be any value


157

[Bit 5] OUTL

This bit sets the output level of the TOT pins. Pin levels are reversed by switching between settings of ‘0’ and ‘1.’

Table 2.8.4 RELD, OUTL Pin Settings

[Bit 4] RELD (Reload)

This is the reload enable bit. When the value is ‘1,’ the timer is in reload mode, and each time the counter value reaches an underflow condition from 0000H to FFFFH the contents of the reload register are loaded into the counter and the count operation continues. The value ‘0’ takes the single-shot operation mode and the count operation stops when the counter value reaches an underflow condition from 0000H to FFFFH.

[Bit 3] INTE (Interrupt enable)

This is the interrupt request enable bit. When the value is ‘1’ an interrupt request is generated each time the UF bit is set to ‘1.’ When the value is ‘0’ no interrupt request is generated even when the UF bit is set to ‘1.’

[Bit 2] UF (Underflow)

This is the timer interrupt request bit, and is set to ‘1’ each time the counter value reaches an underflow condition by going from 0000H to FFFFH. This bit can be cleared by writing ‘0’ or by the intelligent I/O service. Writing ‘1’ to this bit has no effect. With read-modify-write instructions, the read value is always ‘1.’

[Bit 1] CNTE (Count enable)

This is the timer count enable bit. Writing ‘1’ to this bit places the counter in trigger standby mode. Writing ‘0’ to this bit stops the counting operation.

[Bit 0] TRG (Trigger)

This is the software trigger bit. Writing ‘1’ to this bit applies a software trigger, causing the contents of the reload register to be loaded into the counter, thereby starting counter operation. Writing ‘0’ to this bit has no effect. The read value is always ‘0.’ Trigger input from this register is valid only when the CNTE bit is set to ‘1.’ When the CNTE bit is ‘0’ this bit has no effect.

RELD OUTL Output waveform

0 0 ‘H’ square wave during count

0 1 ‘L’ square wave during count

1 0 ‘L’ toggle output at start of count

1 1 ‘H’ toggle output at start of count



(2) TMR (16-Bit Timer Register) / TMRLR (16-Bit Reload Register)


TMR Register Contents

This register is able to read the count value from the 16-bit timer. Its initial value is undefined. This register should always be read using word transfer instructions.

TMRLR Register Contents

The 16-bit reload register saves the initial count value. Its initial value is undefined. This register should always be read using word transfer instructions.

16-bit timer register - high / 16-bit reload register - high



ch1 000037H

15 14 13 12 11 10 9 8

⇐Bit no.


7 6 5 4 3 2 1 0

TMR/TMRLR

ch2 00003BH

ch3 00003FH

16-bit timer register - low / 16-bit reload register - low


ch2 00003AH

ch3 00003EH


159

(3) TPCR (Timer Pin Control Registers)



This register is used to set functions (timer channel, I/O switching) for each of the timer pins (TIM0 to TIM3). This register should only be rewritten when the CNTE bit is set to ‘0.’

Bit Description

[Bits 14, 10, 6, 2] OTE3 to OTE0 (Output enable)

The register contains four output enable bits. When the bit value is ‘0’ the corresponding timer pin TIM functions as a timer input pin TIN (or general-purpose port), and when the value is ‘1’ the corresponding pin functions as a timer output pin TOT. The output waveform in reload mode is a toggle-output wave, and in one-shot mode the output is a square wave to indicate that the counting is in progress.

[Bits 13, 12/9, 8/5, 4/1, 0] CSB, CSA (Channel select)

These bits select the timer channel for each timer pin. Timer channel selections are listed in Table 2.8.5.

Table 2.8.5 OTE, CSB, CSA Bit Selections

Be careful that more than one timer input pin is not selected for the same timer channel.

Also note that any timer channel input (TIN) for which no timer input pins are selected will yield an ‘L’ level input signal.

OTEn CSBn CSAn TIMn pin function Remarks

0 0 0 TIN0 Channel 0 input TIM0 initial status




1 0 0 TOT0 Channel 0 output





Timer pin control register - high

Address : 000057H

⇐Bit no.


15 14 13 12 11 10 9 8


⇐Bit no.


Timer pin control register - lowAddress : 000004H

7 6 5 4 3 2 1 0

TPCR



2.8.4 Operating Description(1) Internal Clock Operation

A selection of clock sources is provided to enable timers to operate on clock signals that are multiples of the internal clock frequency, by dividing the machine clock period by 21, 23, or 25. A register setting allows the external input pins to be used for trigger input or gate input.

To start count operations simultaneously with the count-enable signal, both the CNTE bit and TRG bit should be set to ‘1.’ When the timer is in startup status (CNTE=1), trigger input from the TRG bit is valid at all times regardless of operating mode.

Counter startup and counter operation are shown in Figure 2.8.3. The time interval T (T= machine cycles) is required between the trigger input that starts the counter, and the loading of data from the reload register into the counter.

Fig. 2.8.3 Counter Startup and Operation

Count clock

Counter

Data load

CNTE (register)

TRG (register)

Reload data -1 -1 -1

T


161

(2) Underflow Operation

An underflow condition results when the counter value changes from 0000H to FFFFH. Thus an underflow will occur after an interval of [reload register setting value +1] counts.

When an underflow is generated, and the control register RELD bit is ‘1’ the contents of the reload register are loaded into the counter, and count operations continue. When the RELD bit is ‘0’ the counter stops at count FFFFH.

An underflow condition sets the UF bit in the control register, and if the INTE bit is set to ‘1’ an interrupt request is generated.

Figure 2.8.4 illustrates underflow operation.

Fig. 2.8.4 Underflow Operation

Count clock

Counter

Data load

Underflow set

Count clock

Counter

Underflow set

Reload data -1 -1 -10000H

[RELD=1]

0000H FFFFH

[RELD=0]



(3) Input Pin Functions (in Internal Clock Mode)

When an internal clock is selected as a clock source, the TIN pin can be used as either a trigger input or a gate input. When the TIN pin is used as a trigger input, the contents of the reload register are loaded into the counter whenever a valid edge is input, and count operation starts after the input prescaler is cleared.

The TIN input pulse should be at least 2 × T (T= machine cycles). Figure 2.8.5 illustrates trigger input operation.

Fig. 2.8.5 Trigger Input Operation

When the TIN pin is used as a gate input, the count functions only as long as the signal input from the TIN pin is at the valid level as determined by the MOD0 bit. During this time the count clock continues to operate without stopping. In gate mode, software triggers are enabled regardless of gate level. The pulse width at the TIN pin should be 2 × T (T = machine cycles) or more. Figure 2.8.6 illustrates gate input operation.

Fig. 2.8.6 Gate Input Operation

(4) External Event Count

When the external clock source is selected, the TIN pin becomes an external event input pin, and counts valid edges as defined by register setting. The pulse width at the TIN pin should be 4 × T (T = machine cycles) or more.

Count clock

Prescaler clear

Counter

Load

Rising edge detected

Reload data

TIN

-1 -1 -1 -1

2T to 2.5T

When MOD0 bit is ‘1’

Count clock

Counter

TIN

-1

(count functions during ‘H’ level input)

-1 -1


163

(5) Output Pin Function

In reload mode the TOT pin functions as a toggle output signal which is inverted by underflow conditions, and in one-shot mode the TOT pin functions as a pulse output signal indicating that the count is in progress. Output polarity can be set by the OUTL bit in the register, such that when OUTL=0, the toggle output has an initial value of 0, and the one-shot pulse is output as ‘1’ while the count is in progress. When OUTL=1, the output waveform is inverted.

Fig. 2.8.7 Output Pin Function (1)

Fig. 2.8.8 Output Pin Function (2)

Underflow

Start trigger

Count start

Inverted when OUTL=1TOT

CNTE

[RELD=1, OUTL=0]

Underflow

Start trigger

Inverted when OUTL=1TOT

CNTE

Waiting for start trigger

[RELD=0, OUTL=0]



(6) Intelligent I/O Service (I2OS) Function and Interrupts

This timer circuit has a circuit adapted for I2OS. This means that a timer overflow can be used to start the I2OS operation. The MB90660A has four timers, and all can be used with I2OS. Note however that each of the interrupt control registers (ICRx) in the interrupt controller is connected to two timers (Ch0 + Ch1, or Ch2 + Ch3), so that it is not possible to allocate different I2OS functions to Ch0 and Ch1, or to Ch2 and Ch3 at the same time. Also, each of the four timers has its own separate interrupt vector so that interrupts can be used for four functions simultaneously but because Ch0 and Ch1 (or Ch2 and Ch3) share a common interrupt control register as mentioned above, each pair of channels must have the same interrupt level.

(7) Counter Operating Status

Counter status is determined by the CNTE bit in the control register and the internal WAIT signal. Available settings include CNTE=0, WAIT=1 (STOP status), CNTE=1, WAIT=1 (trigger WAIT status) and CNTE=1, WAIT=0 (RUN status). Figure 2.8.9 shows the transitions among these three status.

Fig. 2.8.9 Counter Status Transition

Trigger from TIN

: Status transition by hardware

: Status transition by register access

End load operationLoad contents of reload register

LOAD CNTE=1,WAIT=0

into counter

TIN: Trigger input only enabled

TOT: Output initial value

Counter: Hold value at stop, undefined immediately after reset, until loaded

WAIT CNTE=1,WAIT=1

TIN: Functions as TIN

TOT: Functions as TOT

Counter: Run

RUN CNTE=1,WAIT=0

TIN: Input disabled

TOT: Output fixed

Counter: Hold value at stop, undefined immediately after reset

STOP CNTE=0,WAIT=1

Reset

CNTE=‘0’ CNTE=‘0’

CNTE=‘1’ CNTE=‘1’TRG=‘0’ TRG=‘1’

TRG=‘1’ TRG=‘1’

RELD·UF

RELD·UF


165

(8) Selection of Timer I/O Pins

The MB90660A series has a 4-channel internal timer, each channel with its own TOT (timer output) and TIN (timer input). The timer I/O pins (TIM0 to TIM3) can be connected to any one of the 8 available pins (TOT0 to TIT3) and (TIN0 to TIN3).

Fig. 2.8.10 Timer Pin Selection

Example Setting 1: All four pins used as output pins (TPCR=7654H)

Fig. 2.8.11 Timer Pin Setting: Example 1

16-bit reload timer

Channel 0TIM0 pin External pinTOT0

TIN0

Channel 1TOT1

TIN1

Channel 2TOT2

TIN2

Channel 3TOT3

TIN3

selector

TIM1 pinselector

TIM2 pinselector

TIM3 pinselector

TIM0

External pinTIM1

External pinTIM2

External pinTIM3

/8

/8

/8

/8

16-bit reload timer

Channel 0TOT0

TIN0

Channel 1TOT1

TIN1

Channel 2TOT2

TIN2

Channel 3TOT3

TIN3

TIM0

External pins

TIM1

TIM2

TIM3



Example Setting 2 (Initial status)

All four pins used as input pins (TPCR=3210H)


Example Setting 3

Two external pins used: channel 0 used for both input and output, and channel 2 used for output.


*Precautionary Information

a. Do not assign multiple external pins as input to the same channel.

Fig. 2.8.14 Example of Connection Prohibited

16-bit reload timer

Channel 0TOT0

TIN0

Channel 1TOT1

TIN1

Channel 2TOT2

TIN2

Channel 3TOT3

TIN3

TIM0

External pins

TIM1

TIM2

TIM3

16-bit reload timer

Channel 0TOT0

TIN0

Channel 1TOT1

TIN1

Channel 2TOT2

TIN2

Channel 3TOT3

TIN3

TIM0

External pins

TIM1

TIM2

TIM3

Channel 0TOT0

TIN0TIM0

TIM1Do not connect channels as shown in this illustration.


167

b. When using the same signal with multiple timers, the pins should be connected together outside the chip to be input.

Fig. 2.8.15 Input of Same Signal to Two Channels

(9) Use of Timer as PWC (Pulse width counter)

The MB90660A chip has one set of pins that functions both as timer I/O pins TIM0 to TIM3 and external interrupt request pins INT4 to INT7. This feature can be used to realize a PWC function, as illustrated below.

Example: Use of channel 0 to measure the high-level width of a pulse input at the TIM0/INT4 pin.

1. Set TIM0 to channel 0 input function

2. Set channel 0 to input clock mode, gate input (H level)

3. Set external interrupt request level to falling edge

4. Set counter to initial value

5. Enable timer count operation and external interrupt

6. After external interrupt request is generated, use EI2OS or interrupt routine to read counter value

7. High-level pulse width can be calculated using the difference between the read value and the counter initial value

Channel 0TOT0

TIN0

Channel 1TOT1

TIN1

TIM0

TIM1

Counter

Counting in progressInterrupt generated

n-1 n-2 n-3 n-4 n-5 n-6n

TIM0/INT4

2.9 External Interrupts



The MB90660A provides a selection of four types of external interrupt levels, both ‘H’ and ‘L’ levels as well as rising and falling edges.

2.9.1 Register Configuration

2.9.2 Block Diagram


EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

⇐ Bit no.


Interrupt enable register

Address : 000028H

7 6 5 4 3 2 1 0

ENIR

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

⇐ Bit no.


Interrupt source register

Address : 000029H

15 14 13 12 11 10 9 8

EIRR

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

⇐ Bit no.


7 6 5 4 3 2 1 0

ELVR


⇐ Bit no.


Interrupt request level setting register - high

Address : 00002BH

15 14 13 12 11 10 9 8

Interrupt request level setting register - low

Address : 00002AH

F2MC-16 bus


Edge detect circuit Request input


8

8

16

8Source F/F

Gate

Interrupt request level setting register

8IRQ


169

2.9.3 Detailed Register Descriptions(1) ENIR (Interrupt Enable Register)



The ENIR register is used to have the device pin serve as an external interrupt request input and to determine the operation of the external interrupt request input functions that generate interrupt requests to the interrupt controller. When ‘1’ is written to a bit in this register, the corresponding pin is used as an external interrupt request input and has the function of generating interrupt requests to the interrupt controller. When ‘0’ is written to a bit, the corresponding pins will store external interrupt request input source, but will not generate requests to the interrupt controller.

(2) EIRR (Interrupt Source Register)



The EIRR register can be read-accessed to show the presence of external interrupt requests, and can be write-accessed to clear the flip-flop settings that indicate these requests. A read value of ‘1’ indicates that an external interrupt request has been made at the pin corresponding to that bit. Writing ‘0’ to this register clears the request flip-flop setting at the corresponding bit. Writing ‘1’ has no effect in operation. For read-modify-write instructions, the read value is always ‘1.’

[CAUTION] In interrupt-enabled status, write-access to this register should write '0' only to bit(s) that have been set to ‘1.’ This is to avoid unconditional clearing of other flag bits that are not the flag bits for sources that have been set by interrupt requests.

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

⇐ Bit no.



Address : 000028H

7 6 5 4 3 2 1 0

ENIR

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

⇐ Bit no.

Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value⇒ (X) (X) (X) (X) (X) (X) (X) (X)


Address : 000029H

15 14 13 12 11 10 9 8

EIRR



(3) ELVR (Request Level Setting Register)



The ELVR register is used to select the mode of request detection. 2 bits are assigned to each pin, and are set in combination as shown below. For level interrupt signals, the signal can be set again even by clearing the register setting if the input is at active level.

Table 2.9.1 ELVR Bit Settings

2.9.4 Operating Description(1) External Interrupt Operations

When external interrupt requests are set, this resource will generate an interrupt request signal to the interrupt controller whenever an interrupt designated in the ELVR register is received at the corresponding input pin. Interrupts generated simultaneously are assigned priority values by the interrupt controller. If an interrupt from this resource has the currently highest priority, the interrupt controller will generate an interrupt request to the F2MC-16L CPU, which will compare the interrupt with the ILM bit in its own internal CCR register. If the interrupt has a higher level than the ILM bit, the CPU will then stop the currently executing instruction, and start the hardware interrupt processing microprogram.

LBx LAx Operation

0 0 Interrupt request at L level signal

0 1 Interrupt request at H level signal

1 0 Interrupt request at rising edge

1 1 Interrupt request at falling edge


⇐ Bit no.


Address : 00002AH

7 6 5 4 3 2 1 0

ELVR


⇐ Bit no.


Interrupt request level setting register - high

Address : 00002BH

7 6 5 4 3 2 1 0

Interrupt request level setting register - low

External interruptOther interrupt requests

Interrupt controller F2MC-16L CPU

ELVR

EIRR

ENIR

ICR yy

ICR xx

CMP

Source

IL

ILM

CMP

INTA


171

Fig. 2.9.2 External Interrupt Operation

In the hardware interrupt processing microprogram, the CPU reads the information in the ISE bit from the interrupt controller to verify that the particular interrupt is selected for interrupt processing, and then branches to the interrupt processing microprogram. The interrupt processing microprogram executes the user-defined interrupt processing program by reading interrupt vector areas, generating interrupt acknowledge signals to the interrupt controller, and transferring to the program counter the jump destination address of the macro instruction generated by the vectors.

2.9.5 Precautionary Information(1) Recovery from Standby

When using the external interrupt for the recovery from the standby in the clock stop mode, make the input request the high-level request. Low-level request may cause anomaly. Edge request will not allow the recovery from the standby in the clock stop mode.

(2) External Interrupt Operating Procedure

External interrupt register settings should be made using the following procedure.

1. Disable the target bits in the enable register.

2. Set the target bits in the request level setting register.

3. Clear the target bits in the source register.

4. Enable the target bits in the enable register.

(Note that steps 3 and 4 may be done in simultaneous write operations, using word access.)

When making settings to registers within this resource, it is first necessary to make a ‘disable’ setting in the enable register. Also, it is necessary to clear the source register before returning the enable register to ‘enable’ status. This is in order to avoid setting erroneous interrupt sources when making register settings or enabling interrupt status.



(3) External Interrupt Request Levels

(1) When the interrupt level uses edge interrupt detection, the pulse width must be at least three machine cycles to allow the edge detection function to operate.

(2) When the interrupt input level involves a level setting, incoming external interrupt signals are retained in an internal source storage circuit even after they have been cancelled, and the request to the interrupt controller remains active. Thus to cancel requests to the interrupt controller, it is necessary to clear the source storage circuit.

Fig. 2.9.3 Clearing Source Storage Circuit when Level Setting is Used

Fig. 2.9.4 Timing of Interrupt Source and Interrupt Request to Interrupt Controller

Interrupt Level detection

Source F/F Enable gate

To interrupt

Source remains stored unless cleared

(source storage circuit) controllerrequest

H level

Interrupt request to interrupt controller

Inactive due to clearing of source F/F

Interrupt request

2.10 Delayed Interrupt Generator Module

173


The Delayed interrupt generator module is used to generate interrupts for task switching. This module can be used to generate or delete software interrupt requests to the F2MC-16L CPU.

2.10.1 Register List

2.10.2 Block Diagram


2.10.3 Detailed Register Descriptions(1) DIRR (Delayed Interrupt Source Generate/Release Register)



The DIRR register controls the generation and release of delayed interrupt requests. Writing ‘1’ to this register causes a delayed interrupt request to be generated, and writing ‘0’ releases the delayed interrupt request. At a reset, this register is in source release mode. Either ‘0’ or ‘1’ may be written to the reserved bits, however in view of future expansion it is recommended that set-bit and clear-bit instructions be used when accessing this register.

– – – – – – – R0

⇐ Bit no.

Read/write ⇒ (–) (–) (–) (–) (–) (–) (–) (R/W)Initial value⇒ (–) (–) (–) (–) (–) (–) (–) (0)

Address :

00009FH

15 14 13 12 11 10 9 8

DIRR

F2MC-16L bus

Delayed interrupt source generate/release decoder

Source latch

– – – – – – – R0

⇐ Bit no.

Read/write ⇒ (–) (–) (–) (–) (–) (–) (–) (R/W)Initial value⇒ (–) (–) (–) (–) (–) (–) (–) (0)

Address :

00009FH

15 14 13 12 11 10 9 8

DIRR



2.10.4 Operating Description(1) Delayed Interrupts

When the CPU uses software instructions to write ‘1’ to the DIRR register, the request latch is set in the delayed interrupt generator module, and an interrupt request is sent to the interrupt controller. If other interrupt requests have a lower priority, or if there are no other requests, an interrupt is then generated to the F2MC-16L CPU, which compares the request with the ILM bit in its own internal CCR register. If the request level is higher than the ILM bit, then as soon as the current instruction finishes executing, the hardware interrupt processing microprogram is started. This causes the interrupt processing routine for this interrupt to be executed.

Fig. 2.10.2 Delayed Interrupt Generator

Generator Operation during the processing routine, the interrupt source is cleared by writing ‘0’ to the corresponding bit in the DIRR register, thereby switching tasks as well.

2.10.5 Precautionary Information(1) Delayed Interrupt Request Latch

This latch is set by writing ‘1’ to the corresponding bit in the DIRR register, and cleared by writing ‘0’ to the same bit. Thus the interrupt processing routine must contain software to clear the source, or else recovery from interrupt processing will only result in the start of another interrupt processing routine. Users should ensure that interrupt processing software is structured to avoid this problem.

Delayed interrupt generator module

Other requests

Interrupt controller F2MC-16L CPU

DIRR

ICR yy

ICR xx

CMP

IL

ILM

CMP

INTA

WRITE

2.11 Watchdog Timer, Timebase Timer Functions

175


The watchdog timer is composed of a 2-bit watchdog counter that uses as a clock source the carry signal of the 18-bit time base timer, plus a control register and a watchdog reset control unit. The timebase timer consists of an 18-bit timer plus circuits that control interrupt signals at intervals. Figure 2.11.1 shows the configuration of the watchdog timer and timebase timer.


Reserved – – TBIE TBOF TBR TBC1 TBC0

⇐ Bit no.

Read/write ⇒ (–) (–) (–) (R/W) (R/W) (W) (R/W) (R/W)Initial value⇒ (1) (–) (–) (0) (0) (1) (0) (0)

Timebase timer control register

Address : 0000A9H

15 14 13 12 11 10 9 8

TBTC

PONR – WRSTERST SRST WTE WT1 WT0

⇐ Bit no.

Read/write ⇒ (R) (–) (R) (R) (R) (W) (W) (W)Initial value⇒ (X) (–) (X) (X) (X) (1) (1) (1)

Watchdog timer control register

Address : 0000A8H

7 6 5 4 3 2 1 0

WDTC




Fig. 2.11.1 Watchdog Timer and Timebase Timer Block Diagram

F2 M

C-1

6 bu

s

Timebase

SelectorClock input

Timebase timer

Main clock (oscillator)

2-bit counter Watchdog reset

To WDGRST

From power-on

RSTX pin

From RST bit in

interrupt

TBC1

TBTC

TBC0

TBR

TBIE

TBOF

WDTC

WT1

WT0

WTE

PONR

WRST

ERST

SRST

ANDS

Q R

212

214

216

219

TBTRES

Selector

212 214 216 219

OFCLR

generator circuit

CLR internal reset generator circuit

generator

STBYC register

22

29to PWM timer


177

2.11.3 Detailed Register Descriptions(1) WDTC (Watchdog timer control register)


[CAUTION] Access by read-modify type instructions may cause abnormal operation and should not be attempted with this register.


This register contains bits used to control watchdog timer functions, plus bits that identify reset sources.

Bit Description

[Bits 7 to 3] PONR, WRST, ERST, SRST

These bits are flags that indicate reset sources. When a reset source occurs, the corresponding bit is set as shown in Table 2.11.1. These bits are cleared to ‘0’ after a WDTC read operation. Access to this register is read-only. Note that at power-on, the value of bits other than the power-on bit is not warranted. Therefore software should be structured to ignore the value of other bits when the PONR bit is ‘1.’

Table 2.11.1 Reset Source Bits and Reset Sources

[Bit 2] WTE

When the watchdog timer is in stop state, it can be returned to operating state by writing ‘0’ to this bit. The second and subsequent writing of ‘0’ will clear the watchdog timer counter. Writing ‘1’ to this bit has no effect.

The watchdog timer can be placed in stop state by power-on, hardware standby or watchdog timer reset. The read value is ‘1.’

Reset source PONR WRST ERST SRST

Power-on 1 – – –

Watchdog timer * 1 * *

External signal pin * * 1 *

RST bit * * * 1

(Asterisks (*) indicate previous value is retained.)

PONR – WRSTERST SRST WTE WT1 WT0

⇐ Bit no.

Read/write ⇒ (R) (–) (R) (R) (R) (W) (W) (W)Initial value⇒ (X) (–) (X) (X) (X) (1) (1) (1)

Watchdog timer control register

Address : 0000A8H

7 6 5 4 3 2 1 0

WDTC



[Bits 1, 0] WT1, WT0

These bits selects the interval time used by the watchdog timer. To be valid, data must be written when the watchdog timer starts. All write data written at other times is ignored. Table 2.11.2 shows interval time settings.

Access to this bit is write-only.

Table 2.11.2 Watchdog Timer Interval Select Bit

(2) TBTC (Timebase timer control register)



This register controls the operation of the timebase timer, as well as the interval interrupt time.

Bit Description

[Bit 15] Reserved bit.

This is a test bit. The write value should always be ‘1.’

[Bits 14 to 13] Not used.

[Bit 12] TBIE

This bit enables interval interrupts from the timebase timer. Write ‘1’ to enable this function, and ‘0’ to disable. The initial value is ‘0’ at a reset. This bit is read/write enabled.

WT1 WT0Interval time (source oscillation at 4 MHz) Main clock

cycle countMin Max

0 0 approx. 3.58 ms approx. 4.61 ms 214 ±211 cycles




Note: The maximum interval time assumes that the timebase counter is not reset while the watchdog timer is operating.

Reserved – – TBIE TBOF TBR TBC1 TBC0

⇐ Bit no.

Read/write ⇒ (–) (–) (–) (R/W) (R/W) (W) (R/W) (R/W)Initial value⇒ (1) (–) (–) (0) (0) (1) (0) (0)

Timebase timer control register

Address : 0000A9H

15 14 13 12 11 10 9 8

TBTC


179

[Bit 11] TBOF

This is the timebase timer interrupt request flag. If the TBIE bit has the value ‘1’ then setting this bit to ‘1’ will cause an interrupt request to be generated. This bit will be set to ‘1’ after every occurrence of the interval defined by the TBC1, TBC0 bits. This bit can be cleared by writing ‘0,’ transition into stop mode or hardware standby mode, by clearing the timebase timer using the TBR bit, or by a reset. Writing ‘1’ to this bit has no meaning.

With read-modify-write instructions, the read value is always ‘1.’

[CAUTION] When clearing the TBOF bit, be sure that the timebase timer interrupt is masked using either the TBIE bit or the CPU internal ILM bit.

[Bit 10] TBR

This bit clears all bits in the timebase timer counter to ‘0.’ Write ‘0’ to this bit to clear the timebase timer. Writing ‘1’ to this bit has no meaning. The read value is always ‘1.’

[CAUTION] When clearing the TBOF bit, be sure that the timebase timer interrupt is masked using either the TBIE bit or the CPU internal ILM bit.

[Bits 9, 8] TBC1, TBC0

These bits determine the time interval setting for the timebase timer. Interval settings are shown in Table 2.11.3. The value is initialized to ‘00’ by a reset. This bit is read/write enabled.

Table 2.11.3 Timebase Timer Interval Selection

TBC1 TBC0Interval time

at 4 MHzMain clock cycle count

0 0 1.024 ms 212 cycles

0 1 4.096 ms 214 cycles

1 0 16.384 ms 216 cycles

1 1 131.072 ms 219 cycles



2.11.4 Operating Description(1) Watchdog Timer

The watchdog timer function is used to detect program loops. If a program loop condition causes the designated time to elapse before ‘0’ is written to the WTE bit in the watchdog timer, the watchdog timer will generate a watchdog reset request.

Startup

When the watchdog timer is stopped, it can be started by writing ‘0’ to the WTE bit in the WDTC

register. At this moment, the value of the WT0, WT1 bits is used to determine the watchdog timer reset interval. The interval can only be defined by the data values effective at the time of startup.

Watchdog Timer Reset Prevention

Once the watchdog timer has been started, the program must clear the 2-bit watchdog counter at regular intervals. Specifically, this means that ‘0’ must be written to the WTE bit in the WDTC register at regular intervals. The watchdog counter is configured as a 2-bit counter and uses the carry signal of the timebase counter as its clock source. Thus when the timebase timer is cleared, the watchdog reset generation time may be longer than the setting.

Figure 2.11.2 shows the operation of the watchdog timer.

Fig. 2.11.2 Watchdog Timer Operation

Watchdog Function Stoppage

The watchdog timer is initialized and placed in stop state after startup by power-on reset, hardware standby or watchdog reset. The watchdog counter is also cleared by a reset from an external pin or software signal, but in these cases the watchdog function does not stop.

Other

The watchdog counter may be cleared by writing to the WTE bit, but is also cleared by a reset signal, transition to sleep mode or stop mode, or by a hold acknowledge signal.

Timebase

Watchdog

WTE write

Watchdog start Watchdog clear Watchdog reset generation

00 01 10 00 01 10 11 00

⇑


181

(2) Timebase Timer

The timebase timer functions as clock source for the watchdog counter, a timer for main clock and PLL clock oscillation stabilization time, and as an interval timer generating interrupts at regular designated intervals.

Timebase Timer

The timebase timer consists of an 18-bit counter that counts the oscillator input to produce the machine clock. The count operation is continuous as long as the oscillator signal is input. The timebase timer is cleared by a power-on reset, by transition to stop mode or hardware standby mode, by transition from main clock to PLL clock by setting the MCS bit in the CKSCR register, or by writing ‘0’ to the TBR bit in the TBTC register.

Clearing the timebase timer affects the watchdog counter and interval interrupt functions that operate using the output from the timebase timer.

Interval Interrupt Function

This function generates interrupts at regular intervals according to the timebase counter carry signal. The TBOF flag is set after each occurrence of an interval determined by the TBC1, TBC0 bits in the TBTC register. The setting of this flag is based on the last time that the timebase timer was cleared.

In a transition from main clock mode to PLL clock mode, the timebase timer is cleared because it is used as the timer for PLL clock oscillation stabilization wait time.

In transition to stop mode or hardware standby mode, the time base timer is used to time the oscillation stabilization period after recovery. Therefore the TBOF flag is cleared simultaneously with mode transition.

2.12 Low Power Consumption Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization WaitTime, Clock Multiplier Function)


2.12 Low Power Consumption Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization Wait Time, Clock Multiplier Function)

The MB90660A has the following operating modes: PLL clock mode, PLL sleep mode, watch mode, main clock mode, main sleep mode and stop mode. All modes other than PLL clock mode are classified as low power consumption modes.

In main clock mode and main sleep mode, the main clock (oscillator clock) signal operates alone, the operating clock signal is produced by dividing the main clock by two, and the PLL clock (VCO oscillator clock) signal is stopped.

In PLL sleep mode and main sleep mode, only the CPU operating clock is stopped, and all other clock signals operate.

In watch mode, only the timebase timer operates.

Stop mode, in which all oscillators are stopped, is the lowest power-consumption mode in which data values are retained.

The CPU intermittent operation function allows the clock signal feed to the CPU to operate intermittently for internal registers, internal memory, internal resources or external bus access. This enables reduced power consumption by lowering the CPU execution speed while maintaining the high speed clock feed to internal resources.

The PLL clock multiplier rate is set using the CS1, CS0 bits and may be either 1, 2, 3, or 4 times the clock signal feed.

The WS1, WS0 bits can be used to set the main clock oscillation stabilization wait period after wake-up from stop mode.


Reserved MCM WS1 WS0 Reserved MCS CS1 CS0

⇐ Bit no.

Read/write ⇒ (–) (R) (R/W) (R/W) (–) (R/W) (R/W) (R/W)Initial value⇒ (1) (1) (1) (1) (1) (1) (0) (0)

Clock selection register

Address : 0000A1H

15 14 13 12 11 10 9 8

CKSCR

STP SLP SPL RST Reserved CG1 CG0 Reserved

⇐ Bit no.

Read/write ⇒ (W) (W) (R/W) (W) (–) (R/W) (R/W) (–)Initial value⇒ (0) (0) (0) (1) (1) (0) (0) (0)

Address : 0000A0H

7 6 5 4 3 2 1 0

LPMCR

Low power consumption Register


183


Fig. 2.12.1 Power Consumption Control Circuits and Clock Generator Units

Clock input

Timebase timer

24

213

215

218

212 214 216 219

F2 M

C-1

6 B

us

Main clock

CPU clock

0/9/17/33 intermittent

Standby control circuit

RST Release

Peripheral clock

Interrupt request

Pin high-impedance Pin Hi-Z

RSTX pin

Internal RST

To watchdog timer

PLL multiplier circuit

1 2 3 4

CPU clock selector

CPU system

generator

CPU intermittentoperation functioncycle countselect circuit

Peripheral

generator

Oscillation

wait period

Internal reset

CKSCR

MCM

MCS

CKSCR

CS1

CS0

LPMCR

CG1

CG0

LPMCR

SLP

STP

CKSCR

WS1

WS0 stabilization

selector

control circuit

generation generator

SPL

RST

LPMCR

LPMCR

clock

system clock

or RST

(oscillator signal)

cycle selection

WDGRST

1/2

to PWM timer

22

29



2.12.3 Detailed Register Descriptions(1) LPMCR (Low Power Consumption Mode Control Register


Bit Description

[Bit 7] STP

Writing ‘1’ to this bit causes transition to clock mode (CKSCR.MCS=0) or stop mode (CKSCR.MCS=1). Writing ‘0’ to this bit has no effect. This bit can be cleared to ‘0’ by reset, and by wake-up from watch mode and stop mode. Access to this bit is write-only, and the read value is always ‘0.’

[Bit 6] SLP

Writing ‘1’ to this bit causes transition to sleep mode. Writing ‘0’ to this bit has no effect. This bit can be cleared to ‘0’ by reset, and by wake-up from sleep mode or stop mode.

When ‘1’ is written simultaneously to the STP bit and SLP bit, the result is transition to watch mode or stop mode. Access to this bit is write-only, and the read value is always ‘0.’

[Bit 5] SPL

When this bit is set to ‘0’ external pin levels are maintained while in watch mode or stop mode. A value of ‘1’ means that external pins are placed in high-impedance state when in watch mode or stop mode. This bit is cleared to ‘0’ at reset, and access is read-only.

[Bit 4] RST

Writing ‘0’ to this bit will generate an internal reset signal for 3 machine cycles. Writing ‘1’ to this bit has no effect. The read value is always ‘1.’

[Bit 3] Reserved bit


[Bits 2, 1] CG1, CG0

These bits determine the number of clock pause cycles in the CPU intermittent operation function.

These bits are initialized to ‘00’ by power-on reset or watchdog reset functions, but are not initialized by any other reset sources. Access is read-only.

The CPU intermittent operation function allows the clock signal to be fed to the CPU intermittently (with a given pause) for registers, internal memory, internal resources or external bus access. This enables reduced power consumption by lowering the CPU execution speed while maintaining the high speed clock feed to internal resources.


⇐ Bit no.


Address : 0000A0H

7 6 5 4 3 2 1 0

LPMCR


185



Table 2.12.1 CG Bit Settings

(2) CKSCR (Clock select register)


Bit Description



[Bit 14] MCM

This bit indicates whether the main clock or PLL clock has been selected as the machine clock source. The value ‘0’ indicates that the PLL clock is selected, and the value ‘1’ indicates that the main clock is selected. The MCS bit is ‘0’ and the MCM bit is ‘1’ during the PLL clock oscillation stabilization wait period. The length of the PLL clock oscillation stabilization wait period is fixed at 213 main clock cycles.

[Bits 13, 12] WS1, WS0

These bits determine the main clock oscillation stabilization wait period when wake-up from stop mode.

The value is initialized to ‘11’ by power-on reset, and is not initialized again by any other resets. Access is read-only.

Table 2.12.2 WS Bit Settings



CG1 CG0 CPU clock pause cycle count

0 0 0 cycles (CPU clock = resource clock)

0 1 9 cycles (CPU clock: resource clock = 1: approx. 3 to 4)



WS1 WS0Oscillation stabilization wait time

(at source oscillation of frequency 4 MHz)

0 0 No oscillation stabilization wait time

0 1 approx. 2.05 ms (213source oscillation counts)

1 0 approx. 8.19 ms (215 source oscillation counts)

1 1 approx. 65.54 ms (218 source oscillation counts)


⇐ Bit no.


Address : 0000A1H

15 14 13 12 11 10 9 8

CKSCR



[Bit 10] MCS

This bit selects either the main clock or PLL clock as the machine clock. Write ‘0’ to this bit to select the PLL clock, or write ‘1’ to select the main clock. If the value ‘1’ is overwritten by ‘0,’ the PLL clock oscillation stabilization wait period is generated, and therefore the timebase timer will be automatically cleared, and the TBOF bit in the timebase timer control register will also be cleared. Note that the length of the PLL clock oscillation stabilization wait period is fixed at 213 main clock cycles (approximately 2 ms at source oscillation of 4 MHz).

Note also that when the main clock is selected as the operating clock, the operating clock frequency will be the main clock divided by 2 (at source oscillation of 4 MHz, the operating clock speed will be 2 MHz).

This bit is initialized to ‘1’ by power-on or watchdog reset.

[CAUTION] When overwriting the MCS bit value ‘1’ with the value ‘0,’ always be sure that the TBIE bit or the CPU's ILM bit is used to mask the timebase timer interrupt.

[Bits 9, 8] CS1, CS0

These bits determine the PLL clock multiplier rate. These bits cannot be reset from external pins or by the RST bit, but are initialized to ‘00’ by a power-on reset.

When the MCS bit is ‘0,’ write access to these bits is prohibited. Be sure to set the MCS bit temporarily to ‘1’ (main clock mode) before rewriting the CS bits.

These bits are read/write-enabled.

Table 2.12.3 CS Bit Settings

[CAUTION] At 5 V operating voltage, the oscillator has a range of 3 MHz to 16 MHz. However, proper operation cannot be obtained when using any multiplier that yields a frequency exceeding the maximum operating frequency of the MB90660A CPU and peripheral resources, which is 16 MHz. Thus, for example, if the source oscillation is 16 MHz, 1x is the only permissible multiplier.

Also, the lowest operating frequency of the VCO oscillator is 4 MHz, so that no frequency lower than this level may be selected.

CS1 CS0 Machine clock (at source oscillation of 4 MHz)

0 0 4 MHz (operating frequency = oscillator frequency)

0 1 8 MHz (operating frequency = oscillator frequency × 2)




187

2.12.4 Operating DescriptionFor a description of low power consumption modes, see section 3.6 “Low Power Consumption Modes.”

(1) Clock Selection Mode Transition

Figure 2.12.2 illustrates the transition between each clock selection mode.

Note that the length of the PLL clock oscillation stabilization wait period is fixed at 213 main clock cycles (approximately 2 ms at source oscillation of 4 MHz).

[CAUTION] At 5 V operating voltage, the OSC oscillator has a range of 3 MHz to 16 MHz. However, proper operation cannot be obtained when using any multiplier that yields a frequency exceeding the maximum operating frequency of the MB90660A CPU and peripheral resources, which is 16 MHz. Thus, for example, if the source oscillation is 16 MHz, 1x is the only permissible multiplier.




(1) Clear MCS bit

(2) PLL clock oscillation stabilization wait ended and CS1, CS0 bits = ‘00’




(6) Set MCS bit (including hardware standby, watch dog reset)

(7) PLL clock and main clock timing synchronized

Fig. 2.12.2 Clock Selection Mode Transition Chart

Power-on

MainMCS=1MCM=1CS1/0=xx

Main⇒PLLxMCS=0MCM=1CS1/0=xx

PLL × 1MCS=0MCM=0CS1/0=00




PLL1⇒MainMCS=1MCM=0CS1/0=00



PPL4⇒MainMCS=1MCM=0CS1/0=11

(6)

(1)(2)

(3)

(4)

(5)

(6)

(6)

(7)

(7)

(7)

(7)

(6)(6)

(6)

2.13 Interrupt Controller

189


The interrupt control registers are located inside the interrupt controller and represent all I/O resources that have interrupt functions. The interrupt control registers have the following three functions.

• Setting interrupt levels for the corresponding peripheral resources

• Selection of normal interrupt or extended intelligent I/O service for each of the corresponding peripheral resources

• Selection of extended intelligent I/O service channels.



ICS3 ICS2 ISE IL2 IL1

⇐ Bit no.

Read/write ⇒ (w) (w) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value⇒ (0) (0) (0) (0) (0) (1) (1) (1)


Address : ICR01 0000B1H

15 14 13 12 11 10 9 8


⇐ Bit no.

Read/write ⇒ (W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value⇒ (0) (0) (0) (0) (0) (1) (1) (1)

7 6 5 4 3 2 1 0

orS1

orS0ICS3 ICS2

ICS1 ICS0ISE IL2 IL1 IL0or

S1orS0

ICR03 0000B3H

ICR05 0000B5H

ICR07 0000B7H

ICR09 0000B9H

ICR11 0000BBH

ICR13 0000BDH

ICR15 0000BFH

orS1

orS0ICS3 ICS2 ISE IL2 IL1 IL0

ICS1 ICS0orS1

orS0



ICR02 0000B2H

ICR04 0000B4H

ICR06 0000B6H

ICR08 0000B8H

ICR10 0000BAH

ICR12 0000BCH

ICR14 0000BEH

ICRxx

ICRxx




Fig. 2.13.1 Interrupt Controller Block Diagram

Selects I2OS vectorICS3 ICS2 ICS1 ICS0

Selects I2OS (CPU)Interrupt level

I2OS vector(CPU)

I2OS end

Determines interrupt/I2OS priority level

ISE IL2 IL1 IL0Interrupt request/I2OS request (peripheral resource)

32/

4/

4/

4/

Detects I2OS endcondition

S1 S0condition

2/

2/

2/

4/

4/

4

3/

F2 M

C-1

6BU

S


191

2.13.3 Detailed Register Description(1) ICR (Interrupt control register)


[CAUTION] Bits ICS3 to ICS0 are valid only when starting EI2OS. When starting EI2OS, set the ISE bit to ‘1.’ When not starting EI2OS, set the ISE bit to ‘0.’ If EI2OS is not started, the ICS3-ICS0 bits may have any value. *The read value is ‘1.’

[CAUTION] The ICS1 and ICS0 bits are valid for write access only, and the S1 and S0 bits are valid for read access only.



(1) Interrupt level setting bits: IL0, IL1, IL2

These bits are read/write enabled, and determine the interrupt level of the corresponding internal resource. The initial value by reset is level 7 (no interrupt). For the relation between interrupt level setting bits and interrupt levels, see Table 2.13.1.


⇐ Bit no.

Read/write ⇒ (w) (w) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value⇒ (0) (0) (0) (0) (0) (1) (1) (1)



15 14 13 12 11 10 9 8


⇐ Bit no.

Read/write ⇒ (W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value⇒ (0) (0) (0) (0) (0) (1) (1) (1)

7 6 5 4 3 2 1 0

orS1

orS0ICS3 ICS2

ICS1 ICS0ISE IL2 IL1 IL0or

S1orS0

ICR03 0000B3H

ICR05 0000B5H

ICR07 0000B7H

ICR09 0000B9H

ICR11 0000BBH

ICR13 0000BDH

ICR15 0000BFH

orS1

orS0ICS3 ICS2 ISE IL2 IL1 IL0

ICS1 ICS0orS1

orS0



ICR02 0000B2H

ICR04 0000B4H

ICR06 0000B6H

ICR08 0000B8H

ICR10 0000BAH

ICR12 0000BCH

ICR14 0000BEH

ICRxx

ICRxx



Table 2.13.1 Interrupt Level Set Bits and Interrupt Levels

(2) Extended Intelligent I/O Service Enable Bit: ISE

This bit is read/write enabled, and may be set to ‘1’ to start EI2OS when an interrupt request is generated. If the value is ‘0’ an interrupt sequence will be invoked. When EI2OS operation ends, the ISE bit is cleared to ‘0.’ If the corresponding peripheral resource does not have an EI2OS function, a software write instruction must be used to set the ISE bit to ‘0.’

This bit is initialized to ‘0’ at a reset.

(3) Extended intelligent I/O service channel select bit: ICS3 to ICS0

These bits are enabled for write access only, and are used to designate an EI2OS channel. The value set by these bits determines the address of the intelligent I/O service descriptor, described later in Table 2.13.2. The ICS bits are set to their initial values at a reset.

Table 2.13.2 shows the correspondence between ICS, channel numbers and descriptor address.


0 0 0 0 (strongest (highest priority) interrupt)

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6 (weakest (lowest priority) interrupt)

1 1 1 7 (no interrupt)


193

Table 2.13.2 ICS Bit Values, Channel Numbers, and Descriptor Addresses

(4) Extended Intelligent I/O Service End Status: S0, S1

These bits are read-only, and are read to determine the conditions for ending EI2OS processing. The initial value after reset is ‘00.’

Table 2.13.3 shows the relation between S-bit values and EI2OS ending conditions.

Table 2.13.3 S-Bit Values and EI2OS Ending Conditions

ICS3 ICS2 ICS1 ICS0 Channel selection Descriptor address

0 0 0 0 0 000100H

0 0 0 1 1 000108H

0 0 1 0 2 000110H

0 0 1 1 3 000118H

0 1 0 0 4 000120H

0 1 0 1 5 000128H

0 1 1 0 6 000130H

0 1 1 1 7 000138H

1 0 0 0 8 000140H

1 0 0 1 9 000148H

1 0 1 0 10 000150H

1 0 1 1 11 000158H

1 1 0 0 12 000160H

1 1 0 1 13 000168H

1 1 1 0 14 000170H

1 1 1 1 15 000178H

S1 S0 Ending condition

0 0 Reserved

0 1 Terminated at end of count

1 0 Reserved

1 1 End at request from resource



(5) Interrupt Vector Allocation

Table 2.13.4 shows MB90660A interrupt vector allocation.

Table 2.13.4 MB90660A Interrupt Vector Allocation

Interrupt sourceI2OS

relationInterrupt vector


Number Address ICR Address

Reset × #08 08H FFFFDCH – –

INT9 instruction × #09 09H FFFFD8H – –

Exception × #10 0AH FFFFD4H – –

Multi-function timer DTTI input × #12 0CH FFFFCCH ICR00 0000B0H

External interrupt #0 #13 0DH FFFFC8H

ICR01 0000B1H

External interrupt #4 #14 0EH FFFFC4H

Multi-function timer trigger input/zero-detection #15 0FH FFFFC0H ICR02 0000B2H

Multi-function timer zero-detection #17 11H FFFFB8H ICR03 0000B3H

Multi-function timer overflow/compare-clear/zero-detect

#19 13H FFFFB0H ICR04 0000B4H

External interrupt #1 #21 15H FFFFA8H

ICR05 0000B5H

Multi-function timer compare-clear × #22 16H FFFFA4H

External interrupt #5 #23 17H FFFFA0H

ICR06 0000B6H

PWM underflow × #24 18H FFFF9CH

External interrupt #2 #25 19H FFFF98H

ICR07 0000B7H

External interrupt #6 #26 1AH FFFF94H

16-bit reload timer #0 #27 1BH FFFF90H

ICR08 0000B8H

16-bit reload timer #1 #28 1CH FFFF8CH

16-bit reload timer #2 #29 1DH FFFF88H

ICR09 0000B9H

16-bit reload timer #3 #30 1EH FFFF84H

A/D converter conversion end #31 1FH FFFF80H ICR10 0000BAH

Timebase timer interval interrupt × #34 22H FFFF74H ICR11 0000BBH

UART sending end #35 23H FFFF70H ICR12 0000BCH

UART receiving end #37 25H FFFF68H ICR13 0000BDH

External interrupt #3 #39 27H FFFF60H

ICR14 0000BEH

External interrupt #7 #40 28H FFFF5CH

Delay interrupt generator module × #42 2AH FFFF54H ICR15 0000BFH


195

[CAUTION] In the above chart, indicates an I2OS relation (without stop request), indicates an I2OS relation (with stop request), × indicates no I2OS relation. No I2OS start setting should be entered for any bit ICRxx that has no relation to I2OS.

2.13.4 Operating DescriptionFor a description of interrupt and EI2OS operation, see section 3.3 “Interrupts.”

3.1 Clock Generation Block

196 Chapter 3:Operation

Chapter 3: Operation

3.1 Clock Generation Block

The clock generation block controls the operation of the internal clock, such as the sleep, watch, stop, and PLL clock multiplier function. This internal clock is called the “machine clock,” and one cycle of this clock is called the “machine cycle.” In addition, the clock produced by the source oscillator is the main clock, and the clock derived from the internal VCO oscillation is used as the PLL clock.

[CAUTION] At 5 V operating voltage, the oscillator has a range of 3 MHz to 16 MHz. However, proper operation cannot be obtained when using any multiplier that yields a frequency exceeding the maximum operating frequency of the MB90660A CPU and peripheral resources, which is 16 MHz. Thus, for example, if the source oscillation is 16 MHz, x1 is the only permissible multiplier.


Fig. 3.1.1 shows a block diagram of the clock generation circuit.

Fig. 3.1.1 Clock Generation Circuit Block Diagram

Reset

Interrupt

Watch mode/

Machine clock selection

Machine clock

Selection during

Watchdog interval selection

Monitor timer

Stop mode

S Q

R

S Q

R

S Q

R

1/41/2048 1/81/4

oscillation stabilization

X0 X1

transition

waiting period

sleep mode transition

PLL multiplier

1/2Timebase timer

Watchdog reset

1 2 3 4

3.2 Resets

197

3.2 Resets

3.2.1 Reset Source GenerationIf a reset source is generated, this device immediately interrupts the processing currently being executed, and begins waiting for reset release. Resets are generated by a number of different sources, as shown below:

• Generation of power-on reset

• Watchdog timer overflow

• Generation of external reset request through the RSTX pin

• Generation of reset request through software

Both wake-up from stop mode and a power-on reset require insertion of the oscillation stabilization period before operation can begin.

[CAUTION] In all modes other than stop mode, the external reset input signal is sampled using the internal clock, and therefore no reset input can be received while the external clock feed is stopped.

Note however that the optional setting "reset input asynchronous receiving 'on'" may be selected to forcibly set output ports (including peripheral resource outputs) in Hi-Z state.(This optional setting is available on models MB90P663A and MB90663A/2A/1A only.)

3.2.2 Operation after Reset ReleaseIf the reset source is withdrawn, this device immediately outputs the address where the reset vector is stored and fetches the reset vector and mode data. The reset vector and mode data are assigned to the four bytes FFFFDCH through FFFFDFH, and are transferred by the hardware to the registers shown in Fig. 3.2.1 after the reset is released.

Fig. 3.2.1 Reset Vector and Mode Data Storage Location and Storage Destination

Memory space

Mode data

Reset vector bits 23 to 16



F2MC-16L CPU

Mode

Register

Micro ROM

Reset sequence

FFFFDFH

FFFFDEH

FFFFDDH

FFFFDCH

PCB

PC

3.2 Resets


3.2.3 Reset SourcesThere are four reset sources, as shown in Table 3.2.1. Depending on the reset source, the initialized state of the machine clock and watchdog function vary.

The reset source register can be used to determine the reset source.

Table 3.2.1 Reset Sources

* Reset input during stop mode requires an oscillation stabilization wait interval, regardless of the reset source.

* Oscillation stabilization wait time at a power-on reset is fixed at 218 cycles at the source oscillation. All other oscillation stabilization wait times are determined by the CS1/CS0 bits in the clock selection register.

As shown in Fig. 3.2.2, there is a flip-flop corresponding to each reset source. Because the contents of these flip-flops can be obtained by reading the watchdog timer control register, whenever it is necessary to identify the reset generation source after the reset was released, process the value read from the watchdog timer control register and branch to an appropriate program. For reference purposes, the watchdog timer control register is shown again in Fig. 3.2.3.

Fig. 3.2.2 Reset Source Bit Block Diagram

Reset Generating source Machine clock Watchdog timerOscillation

stabilization wait?

Power on When power is applied Main clock Stopped Yes

Watchdog timer Watchdog timer overflow Main clock Stopped Yes

External pin Low level input to RSTX pinPrevious state retained

Previous state retained

No

SoftwareWriting “0” to RST bit in LPMCR



No

Power supply on

Power-on generation

RSTX pin

External reset request

No regular clearing

Watchdog timer reset

RST bit set

LPMCR.RST bit write

WTC register

WTC register read

F2MC-16 internal bus

detection circuit detection circuit generation detection circuit detection circuit

RSTX=L

S RF / F

S RF / F

S RF / F

S RF / F Delay circuit

Q Q Q Q

3.2 Resets

199

Fig. 3.2.3 WDTC (Watchdog Timer Control Register)

Even if multiple reset sources are generated, the corresponding reset source bits in the watchdog timer control register are set. Therefore, even if an external reset request and a watchdog reset are generated simultaneously, both the ERST bit and the WRST bit are set to “1”.

The only exception, however, is the power-on reset. When the PONR bit is “1”, the contents of the other bits do not indicate normal reset sources. Therefore, software should be written so that when the PONR bit is “1”, the contents of the other reset source bits are ignored.

Table 3.2.2 Correspondence between the Contents of the Reset Source Bits and Reset Sources

The reset source bits are cleared only by reading the watchdog timer control register. Once a reset source bit corresponding to a reset source that was generated is set, it remains “1” even if other reset sources are generated.

Reset source PONR WRST ERST SRST

Power on 1 Undefined Undefined Undefined

Watchdog timer * 1 * *

External pin * * 1 *

RST bit * * * 1

(Asterisks (“*”) in the table indicate that the previous value is retained.)

PONR – WRST ERST SRST WTE WT1 WT0

⇐ Bit no.

Read/write ⇒ (R) – (R) (R) (R) (W) (W) (W)Initial value⇒ (X) – (X) (X) (X) (1) (1) (1)

Address : 0000A8H

7 6 5 4 3 2 1 0

WDTC

3.3 Interrupts


3.3 Interrupts

The F2MC-16L has an interrupt function that interrupts the current processing when a predefined event, etc., occurs, and shifts control to a separately defined program. Interrupt functions can be divided into the following four types:

• Hardware interrupts: ....................................... Interrupt processing caused by the occurrence of an event in an on-chip resource

• Software interrupts: ........................................ Interrupt processing caused by an instruction generating a software event

• Extended Intelligent I/O Service (EI2OS): .....Transfer processing caused by the occurrence of an event in an on-chip resource

• Exceptions: .....................................................An interruption of processing caused by the occurrence of an operating exception

This section explains these four interrupt functions.

3.3.1 Hardware Interrupts(1) Overview

The hardware interrupt function temporarily interrupts program execution by the CPU in response to an interrupt request signal from an on-chip peripheral resource and shifts control to a user-defined interrupt processing program. The hardware interrupt is started up by comparing the interrupt level of the interrupt request with the interrupt level mask register in the CPU’s PS register and then referencing via the hardware the contents of the I flag in the PS; then, if the conditions for generating the interrupt are met, the interrupt is generated. The processing performed by the CPU when a hardware interrupt is generated includes the following:

Saving the contents of the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers within the CPU into the system stack

Setting the ILM bits in the PS register automatically to the same level as that of the interrupt currently being requested

Fetching the contents of the corresponding interrupt vector and then branching there

(2) Structure

The facilities related to hardware interrupts can be grouped into three parts:

On-chip resources: ..... Interrupt enable bit and interrupt request bit (Control of interrupt requests from resources)

Interrupt controller: .... ICR (Interrupt level assignment and determination of priority of simultaneously requested interrupts)

CPU: ........................... I, ILM (Comparison of level of requested interrupt with current level, identification of interrupt enable state)Microcode (Interrupt processing steps)

The on-chip resources are represented through the contents of the resource control register. The interrupt controller is represented through the contents of the ICR. The CPU is represented through the contents of the CCR, etc. When using hardware interrupts, these three settings must be made beforehand through software.

The interrupt vector table referenced during interrupt processing is assigned to the memory area from FFFC00H to FFFFFFH; this table is also used by software interrupts. The assignments in this device are shown in Table 3.3.1.

3.3 Interrupts

201

Table 3.3.1 MB90660A Interrupt Assignment Table (1)

Software interrupt

instruction

Vector address L

Vector address M

Vector address H

Mode register

Interrupt No. Hardware interrupt

INT 0 FFFFFCH FFFFFDH FFFFFEH Unused #0 None

INT 7 FFFFE0H FFFFE1H FFFFE2H Unused #7 None

INT 8 FFFFDCH FFFFDDH FFFFDEH FFFFDH #8 (RESET vector)

INT 9 FFFFD8H FFFFD9H FFFFDAH Unused #9 None

INT 10 FFFFD4H FFFFD5H FFFFD6H Unused #10 <Exception>

INT 11 FFFFD0H FFFFD1H FFFFD2H Unused #11 None

INT 12 FFFFCCH FFFFCDH FFFFCEH Unused #12 Multi-function timer DTTI input

INT 13 FFFFC8H FFFFC9H FFFFCAH Unused #13 External interrupt #0

INT 14 FFFFC4H FFFFC5H FFFFC6H Unused #14 External interrupt #4

INT 15 FFFFC0H FFFFC1H FFFFC2H Unused #15 Multi-function timer trigger input

INT 16 FFFFBCH FFFFBDH FFFFBEH Unused #16 None

INT 17 FFFFB8H FFFFB9H FFFFBAH Unused #17 Multi-function timer zero-detect

INT 18 FFFFB4H FFFFB5H FFFFB6H Unused #18 None

INT 19 FFFFB0H FFFFB1H FFFFB2H Unused #19 Multi-function timer overflow

INT 20 FFFFACH FFFFADH FFFFAEH Unused #20 None

INT 21 FFFFA8H FFFFA9H FFFFAAH Unused #21 External interrupt #1

INT 22 FFFFA4H FFFFA5H FFFFA6H Unused #22 Multi-function compare-match #1

INT 23 FFFFA0H FFFFA1H FFFFA2H Unused #23 External interrupt #5

INT 24 FFFF9CH FFFF9DH FFFF9EH Unused #24 PWM underflow

INT 25 FFFF98H FFFF99H FFFF9AH Unused #25 External interrupt #2

INT 26 FFFF94H FFFF95H FFFF96H Unused #26 External interrupt #6

INT 27 FFFF90H FFFF91H FFFF92H Unused #27 16-bit reload timer #0

INT 28 FFFF8CH FFFF8DH FFFF8EH Unused #28 16-bit reload timer #1

INT 29 FFFF88H FFFF89H FFFF8AH Unused #29 16-bit reload timer #2

INT 30 FFFF84H FFFF85H FFFF86H Unused #30 16-bit reload timer #3

INT 31 FFFF80H FFFF81H FFFF82H Unused #31 A/D conversion end

INT 32 FFFF7CH FFFF7DH FFFF7EH Unused #32 None

INT 33 FFFF78H FFFF79H FFFF7AH Unused #33 None

INT 34 FFFF74H FFFF75H FFFF76H Unused #34 Timebase timer

INT 35 FFFF70H FFFF71H FFFF72H Unused #35 UART sending end

INT 36 FFFF6CH FFFF6DH FFFF6EH Unused #36 None

INT 37 FFFF68H FFFF69H FFFF6AH Unused #37 UART receiving end

INT 38 FFFF64H FFFF65H FFFF66H Unused #38 None

INT 39 FFFF60H FFFF61H FFFF62H Unused #39 External interrupt #3

INT 40 FFFF5CH FFFF5DH FFFF5EH Unused #40 External interrupt #7

INT 41 FFFF58H FFFF59H FFFF5AH Unused #41 (Reserved)

... ... ... ... ... ... ...

3.3 Interrupts


(3) Operation

On-chip resources with a hardware interrupt request function have an ‘interrupt request flag,’ which indicates the existence of an interrupt request, and an ‘interrupt enable flag,’ which the resource uses to select whether or not to issue its own interrupt requests to the CPU. The interrupt request flag is set by the occurrence of an event unique to that resource; if the interrupt enable flag is set to “enabled,” the resource uses an interrupt request to the interrupt controller.

The interrupt controller compares the level of individual interrupt requests that are received simultaneously with the interrupt level (IL) in the ICR, selects the request with the highest level (the smallest IL value) and notifies the CPU. If there are multiple requests with the same interrupt level, the interrupt with the smaller interrupt level number is given priority. The relationship between each interrupt request and each ICR is determined by the hardware.

The CPU compares the interrupt level that it received with the ILM bits in the PS register, and if the interrupt level is less than the ILM and the I bit in the PS register is set to “1”, then once the instruction that is currently being executed is terminated, the CPU begins executing the interrupt processing microcode. At the top of the interrupt processing microcode, the ISE bit in the ICR in the interrupt controller is referenced; after confirming that it is “0” (i.e., an interrupt), the main body of interrupt processing is initiated.

In the main body of interrupt processing, after the 12 bytes of the PS and PC, PCB, DTB, ADB, DPR, and A are saved to the memory locations indicated by the SSB and SSP, a three-byte fetch is performed to get the interrupt vector, which is loaded into the PC and PCB. After updating the ILM bits in the PS to the level of the interrupt request that was accepted, the S flag is set and branch processing is performed. As a result, the next instruction that is executed is the user-defined interrupt processing program.

Fig. 3.3.1 shows the flow of processing from the occurrence of the hardware interrupt until the point when there are no more interrupt requests in the interrupt processing program. Fig. 3.3.2 shows the operational flow of hardware interrupts.

INT 42 FFFF54H FFFF55H FFFF56H Unused #42 Delay interrupt

INT 43 FFFF50H FFFF51H FFFF52H Unused #43 None

INT 254 FFFC04H FFFC05H FFFC06H Unused #254 None

INT 255 FFFC00H FFFC01H FFFC02H Unused #255 None

Table 3.3.1 MB90660A Interrupt Assignment Table (2)

Software interrupt

instruction

Vector address L

Vector address M

Vector address H

Mode register

Interrupt No. Hardware interrupt

... ... ... ... ... ... ...

3.3 Interrupts

203

Fig. 3.3.1 Hardware Interrupt Generation and Cancellation

(1) An interrupt source is generated within the peripheral.

(2) The interrupt enable bit within the peripheral is referenced, and if interrupts are enabled, an interrupt request is sent from the peripheral to the interrupt controller.

(3) After receiving the interrupt request, the interrupt controller determines the priority ranking of the interrupts that are requested simultaneously, and the interrupt level of the appropriate interrupt is transferred to the CPU.

(4) The CPU compares the interrupt level of the request from the controller with the IL bits in the processor status register.

(5) Only if the comparison in step (4) indicates that the requested interrupt has a higher priority level than that of the current interrupt processing, the I flag in the same processor status register is checked.

(6) Only if the check in step (5) indicates that the I flag is set to the interrupt enable state, the IL bits are set to the level of the new request. Once the execution of the current instruction is completed, interrupt processing immediately is performed and control is immediately passed to the interrupt processing routine.

(7) When the software in the user’s interrupt processing routine clears the interrupt source that was generated in step (1), the interrupt request is completed.

In steps (6) and (7), CPU interrupt processing time is determined as follows.

Interrupt start: 24 + 6 × (machine cycle count from Table 3.3.2)

Recovery from interrupt: 15 + 6 × (machine cycle count from Table 3.3.2)

Table 3.3.2 Compensated Cycle Count for Interrupt Processing Time

Address indicated by stack pointer Compensated cycle count

Internal area, even address 0

Internal area, odd address 2

F2 M

C-1

6 B

us

Microcode

Peripheral

Peripheral

Inte

rrup

t lev

el (

IL)

Leve

l com

para

tor

Interrupt


Register file PS I ILM

F2MC-16L · CPU

controller

…

IR ComparatorCheck

ANDEnable FF

Source FF

(1) (2)

(3)

(4)(5)(6)

(7)

Instruction register

Interrupt enable flagProcessor status

3.3 Interrupts


Fig. 3.3.2 Hardware Interrupt Operation Flow

I: Flag in CCRILM: CPU level registerIF: On-chip resource interrupt requestIE: On-chip resource interrupt enable flagISE: EI2OS enable flagIL: On-chip resource interrupt request levelS: Flag in CCR

Fetch and decode next instruction

Execute instruction normally

Update PC

ISE = 1

Save PS, PC, PCB, DTB, ADB, DPR, and A into SSP stack and then set ILM = IL

Extended Intelligent I/O Service Processing

I & IY & IE = 1AND

ILM > IL

INT instruction?

Repetition ofstring instructioncompleted?

Save PS, PC, PCB, DTB, ADB, DPR, and A into SSP stack and then set I = 0 and ILM = IL

S ←1Fetch interrupt vector

YES

NO NO YES

YES

YES

NO

NO

3.3 Interrupts

205

(4) Miscellaneous

As a special case, hardware interrupt requests are not accepted while writing to the I/O area. This is done in order to prevent the CPU from operating incorrectly as a result of an interrupt request occurring while a resource interrupt control register is being overwritten.

The F2MC-16L CPU supports multiple interrupts. Therefore, while interrupt processing is being executed, if an interrupt is generated that has a stronger interrupt level than the level of the interrupt that is being executed, then once the current instruction being executed is completed, control shifts to the interrupt with the higher interrupt level. Once that interrupt is completed, processing of the original interrupt is resumed. If, while an interrupt is being processed, an interrupt is generated with the same or a lower interrupt level, the new interrupt is put on hold and processing of the current interrupt continues, as long as the contents of the ILM bits or the I flag are not changed by an instruction. Note that the extended intelligent I/O service can not be started up more than once at one time; as long as one extended intelligent I/O service process is in progress, all other interrupt requests and extended intelligent I/O service requests are made pending.

The order of the registers saved into the stack is shown in Fig. 3.3.3.

Fig. 3.3.3 Registers Saved into the Stack

Saving of registers during an interrupt

Word (16 bits)

← SSP (value of SSP before generation of interrupt)

← SSP (value of SSP after generation of interrupt)

PCB

AH

AL

DPR

DPB

ADB

PC

PS

MSB LSB

H

L

↑

↓

3.3 Interrupts


3.3.2 Software Interrupts(1) Overview

The software interrupt function shifts control from the program that the CPU was in the process of executing to a user-defined interrupt processing program in response to the execution of a dedicated instruction. The processing performed by the CPU when a software interrupt is generated includes the following:

Saving the contents of the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers within the CPU into the system stack

Setting the I flag in the PS register, thus automatically disabling interrupts

Fetching the contents of the corresponding interrupt vector and then branching there

There is no interrupt request flag and enable flag for interrupt requests generated by executing the INT instruction (the software interrupt instruction); an interrupt request is always generated when the INT instruction is executed.

There is no interrupt level for the INT instruction. Therefore, when the INT instruction is executed, the ILM bits are not updated, the I flag is cleared, and continuing interrupt requests are put on hold.

(2) Structure

The facilities related to software interrupts all reside in the CPU:

CPU: ....................... Microcode: Interrupt processing steps

To use a software interrupt, it is necessary to execute the corresponding instruction.

As shown in Table 3.3.1, the same areas are used by the hardware interrupts and software interrupts for the interrupt vectors. For example, interrupt request number INT 11 is used by the hardware interrupt external interrupt #0 as well as by the software interrupt INT #11. Therefore, external interrupt #0 and INT #11 both call up the same interrupt processing routine.

(3) Operation

Once the CPU fetches and begins executing a software interrupt instruction, it begins executing the software interrupt processing microcode. In the software interrupt processing microcode, after the 12 bytes of the PS and PC, PCB, DTB, ADB, DPR, and A are saved to the memory locations indicated by the SSB and SSP, a three-byte fetch is performed to get the interrupt vector, which is loaded into the PC and PCB. After resetting the I flag and setting the S flag, branch processing is performed. As a result, the next instruction that is executed is the user-defined interrupt processing program.

Fig. 3.3.4 shows the flow of processing from the occurrence of the software interrupt until the point when there are no more interrupt requests in the interrupt processing program.

3.3 Interrupts

207

Fig. 3.3.4 Software Interrupt Generation and Release

(1) The software interrupt instruction is generated.

(2) The dedicated registers in the register file within the CPU are saved according to the microcode corresponding to the software interrupt instruction.

(3) Interrupt processing is terminated by the RETI instruction in the user interrupt processing routine.

(4) Miscellaneous

When the program bank register (PCB) is FFH, the CALLV instruction vector area overlaps the INT #vct8 instruction table. When creating software, be careful not to use a CALLV instruction and INT #vct8 instruction that use the same address.

F2 M

C-1

6 B

us

Microcode

PS: I: ILM: IR:

Register file PS I S

F2MC-16L · CPU

IR

FetchQueue

(1)

(2)

Save

B unit

Instruction bus

B unit: Bus interface unit

RAM

Interrupt enable flagProcessor status

Instruction registerInterrupt level mask registe

3.3 Interrupts


3.3.3 Extended Intelligent I/O Service (EI2OS)(1) Overview

The EI2OS is one type of hardware interrupt operation that transfers data automatically between I/O and memory. This function makes it possible to use DMA transfer to exchange data with I/O. This exchange has been done by the conventional interrupt processing program. Compared with methods used in conventional interrupt processing, the EI2OS offers the following benefits.

Because there is no need to describe a transfer program, the program size can be reduced.

Because the internal registers are not used during the transfer, there is no need to save data into the registers, resulting in a faster transfer speed.

Because I/O can stop the transfer when necessary, unneeded data is not transferred.

It is possible to select whether to increment/decrement or not to update the buffer address.

It is possible to select whether to increment/decrement or not to update the I/O register address (when there is a buffer address update).

When the EI2OS is terminated, program control automatically branches to the interrupt processing routine after the termination condition is set, making it possible for the user to determine the termination condition type.

An overview of the EI2OS is shown in Fig. 3.3.5.

Fig. 3.3.5 Overview of Extended Intelligent I/O Service

[CAUTION] The area accessible with the I/O address pointer (IOA) is 000000H to 00FFFFH. The area accessible with the buffer address pointer (BAP) is 000000H to FFFFFFH. The maximum number of transfer that can be designated by the data counter registers (DCTH/DCTL) is 65,536.

Memory space

I/O register

Buffer

I/O register

Interrupt request



ISD

by IOA

by BAP

(4)

(1)

(3)

(3)

Peripheral

by ICS

(2)

(1) I/O requests transfer.

(2) The interrupt controller selects the descriptor.

(3) The transfer source and destination are read from the descriptor.

(4) The transfer between I/O and memory is performed.

by DCT

CPU

3.3 Interrupts

209

(2) Structure

The facilities related to the EI2OS can be grouped into four parts:

On-chip resources: ........ Interrupt enable bit and interrupt request bit: Control of interrupt requests from resources

Interrupt controller: ....... ICR: Interrupt level assignment, determination of priority of simultaneously requested interrupts, and selection of EI2OS operation

CPU: .............................. I, ILM: Comparison of level of requested interrupt with current level, identification of interrupt enable state

Microcode: EI2OS processing steps

RAM: ............................ Descriptor: Description of EI2OS transfer information

Each of the registers are described below.

Interrupt control registers (ICR)

The interrupt control registers are located within the interrupt controller; one exists for each I/O that has an interrupt function. These registers have the following three functions:

Setting of the interrupt level for the corresponding peripheral

Selection of whether to handle interrupts from the corresponding peripheral as normal interrupts or as extended intelligent I/O service interrupt

Selection of the extended intelligent I/O service channel

Note that accessing this register through a read-modify-write instruction can cause misoperation. Fig. 3.3.6 shows the bit configuration for an interrupt control register.

Note: ICS3 to ICS0 are valid only when EI2OS is started up. When starting up EI2OS, set ISE to “1”; when not starting it up, set ISE to “0”. If EI2OS is not to be started up, it does not matter what ICS3 to ICS0 are set to.* When these bits are read, a “1” is returned.

ICS1 and 0 are write-only, S1 and S0 are read-only.

Fig. 3.3.6 Interrupt Control Register (ICR)

ICS3 ICS2ICS1 ICS0

ISE IL2 IL1 IL0Interrupt control register

W W * * R/W R/W R/W R/W

15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0

orS1

orS0 When reset: 00000111B

3.3 Interrupts


[Bits 10 to 8] or [Bits 2 to 0] IL0, IL1, IL2

These are the interrupt level setting bits. These bits specify the interrupt level of the corresponding on-chip resource. These bits can be read and written. The level is initialized to level 7 by a reset. The relationship between the interrupt level setting bits and each interrupt level is indicated in Table 3.3.3.

Table 3.3.3 Correspondence between the Interrupt Level Setting Bits and the Interrupt Level

[Bit 11] or [Bit 3] ISE

This bit is the EI2OS enable bit. This bit can be read and written. If this bit is “1” when an interrupt request is generated, the EI2OS is started up; if this bit is “0”, the interrupt sequence is started up. In addition, if the EI2OS is terminated abnormally (the S1 and S0 bits are other than “00”), the ISE bit is cleared to “0”. If the corresponding peripheral does not have the EI2OS function, the ISE bit must be set to “0” by software.

This bit is initialized to “0” by a reset.


0 0 0 0 (highest interrupt level)

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6 (lowest interrupt level)

1 1 1 7 (no interrupts)

3.3 Interrupts

211

[Bits 15 to 12] or [Bits 7 to 4] ICS3 to ICS0

These bits are the EI2OS channel selection bits. These bits are write-only bits that specify the EI2OS channel. The value set in these bits determines the address of the extended intelligent I/O service descriptor in memory (described later). The ICS bits are initialized by a reset.

Table 3.3.4 indicates the correspondence between the ICS bits, the channel number, and the descriptor address.

Table 3.3.4 Correspondence between the ICS Bits, the Channel Number, and the Descriptor Address

ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address

0 0 0 0 0 000100H

0 0 0 1 1 000108H

0 0 1 0 2 000110H

0 0 1 1 3 000118H

0 1 0 0 4 000120H

0 1 0 1 5 000128H

0 1 1 0 6 000130H

0 1 1 1 7 000138H

1 0 0 0 8 000140H

1 0 0 1 9 000148H

1 0 1 0 10 000150H

1 0 1 1 11 000158H

1 1 0 0 12 000160H

1 1 0 1 13 000168H

1 1 1 0 14 000170H

1 1 1 1 15 000178H

3.3 Interrupts


[Bits 13, 12] or [Bits 5, 4] S0, S1

These bits are the EI2OS termination status bits. These read-only bits can be used to determine the termination condition of the EI2OS by checking the value of these bits. These bits are initialized to “00” by a reset.

Table 3.3.5 shows the relationship between the S bits and the termination conditions.

Table 3.3.5 S Bits and Termination Conditions

S1 S0 Termination condition

0 0 Reserved

0 1 Termination due to count termination

1 0 Reserved

1 1 Termination due to request from resource

3.3 Interrupts

213

Extended Intelligent I/O Service Descriptor (ISD)

The extended intelligent I/O service Descriptor (ISD) resides in internal RAM between 000100H and 00017FH, and consists of the following information:

Control data for the data transfer

Status data

Buffer address pointer

Fig. 3.3.7 shows the Extended Intelligent I/O Service Descriptor configuration.

Fig. 3.3.7 Extended Intelligent I/O Service Descriptor Configuration

Data counter (DCT)

This 16-bit register is a counter that handles the transfer data count. Before a data transfer, the counter is decremented by 1. Once the counter reaches zero, EI2OS terminates. Fig. 3.3.8 shows the data counter configuration.

Fig. 3.3.8 Data Counter Configuration

I/O Register Address Pointer (IOA)

This 16-bit register indicates the low-order addresses (A15 to A0) of the I/O register used for buffering and data transfer. The high-order addresses are all zeroes; I/O can be specified for any address from 000000H to 00FFFFH. Fig. 3.3.9 shows the configuration of the IOA register.

Fig. 3.3.9 I/O Register Address Pointer Configuration

000100H + 8 × ICS

Data counter - highest 8 bits (DCTH)

Data counter - lowest 8 bits (DCTL)

I/O address pointer - highest 8 bits (IOAH)

I/O address pointer - lowest 8 bits (IOAL)

I2OS status (ISCS)

Buffer address pointer - highest 8 bits (BAPH)

Buffer address pointer - middle 8 bits (BAPM)

Buffer address pointer - lowest 8 bits (BAPL)

H

LISD top address

(Indeterminate at reset)15B15

14B14

13B13

12B12

11B11

10B10

9B09

8B08

7B07

6B06

5B05

4B04

3B03

2B02

1B01

0B00 : DCT

(Indeterminate at reset)15A15

14A14

13A13

12A12

11A11

10A10

9A09

8A08

7A07

6A06

5A05

4A04

3A03

2A02

1A01

0A00 : IOA

3.3 Interrupts


EI2OS status register (ISCS)

This 8-bit register indicates the update direction (increment/decrement) of the buffer address pointer and the I/O register address pointer, the transfer data format (byte/word), the transfer direction, and whether the buffer address pointer and the I/O register address pointer are updated or fixed. Fig. 3.3.10 shows the configuration of the ISCS register.

Fig. 3.3.10 ISCS Configuration

The contents of each bit are as follows:

[Bit 4] IF: This bit specifies whether the I/O register address pointer is updated or fixed.

0: The I/O register address pointer is updated after a data transfer.

1: The I/O register address pointer is not updated after a data transfer.

Note: Only incrementing is possible.

[Bit 3] BW: This bit specifies the transfer data length.

0: Byte

1: Word

[Bit 2] BF: This bit specifies whether the buffer address pointer is updated or fixed.

0: The buffer address pointer is updated after a data transfer.

1: The buffer address pointer is not updated after a data transfer.

Note: When updated, only the low-order 16 bits of the buffer address pointer are updated. Only incrementing is possible.

[Bit 1] DIR:This bit specifies the data transfer length.

0: I/O → buffer

1: Buffer → I/O

[bit 0] SE: This bit controls the termination of the extended intelligent I/O service upon a request from a resource.

0: The EI2OS does not terminate upon a request from a resource.

1: The EI2OS does terminate upon a request from a resource.

Buffer address pointer (BAP)

This 24-bit register holds the address to be used next by the EI2OS for transfers. Because there is an independent BAP for each EI2OS channel, each EI2OS channel can transfer data to an 16MB area. If updating is specified by the BF bit in the ISCS, only the low-order 16 bits of the buffer address pointer are updated. BAPH does not change.

Fig. 3.3.11 shows the operational flow of the EI2OS, while Fig. 3.3.12 shows the procedural flow for using the EI2OS.

[CAUTION] The MB90660A series operates only in single-chip mode, and therefore transfer is enabled only to internal peripheral resources and internal RAM.

:ISCS (Indeterminate at reset)Reserved ReservedReserved IF BW BF DIR SE

7 6 5 4 3 2 1 0

* The write value to bits 7 to 5 of the ISCS register must always be ‘0.’

3.3 Interrupts

215

(3) Operation

Figure 3.3.1 shows the operating flow of EI2OS, and Figure 3.3.2 shows the flow of operating procedures for EI2OS.

Fig. 3.3.11 Flow of EI2OS Operations

Read ISD/ISCS

Termination

Data indicated by IOA(data transfer) to memoryindicated by BAP

Data indicated by BAP(data transfer) to memoryindicated by IOA

Update value

Update BAP

Interrupt sequence

BAP: Buffer address pointerI/OA: I/O address pointerISD: EI2OS descriptor

ISCS: EI2OS statusDCT: Data counterISE: EI2OS enable bit

S1, S0: EI2OS termination status

Interrupt request generated by internal resource

ISE=1

Interrupt sequence

request

DIR=1

IF=0

Update IOA

BF=0

Decrement DCT

Set S1 and S0 to “00”

Clear resourceinterrupt request

Recover CPU operation

Set S1 and S0 to “01” Set S1 and S0 to “11”

Clear ISE to “0”

DCT=00

SE=1

NO

YES

YES

YES

NO

NO

NO

YES

YES

NO

YES

NO

YES

NO

determinedby BW

Update value determinedby BW

from resource?

(-1)

3.3 Interrupts


Fig. 3.3.12 Procedural Flow for Using EI2OS

Extended I2OS execution time in each operating flow is determined as follows.

• Data transfer continued (when stop conditions do not exist)= Sum of machine cycle times from Table 3.3.6 and Table 3.3.7.

Table 3.3.6 Execution time for Extended I2OS Continued

• Stop requested from resource= 36 + (6 × machine cycle time from Table 3.3.2).

• Count end= Sum of machine cycle times from Table 3.3.6 + Table 3.3.7 + [21 + (6 × Table 3.3.2)]

Table 3.3.7 Compensated Data Transfer Cycle Times for Extended I2OS Execution

B: Byte data transfer Even: even address, word transfer

Odd: odd address, word transfer

ISCS register SE bit Set to ‘0’ Set to ‘1’

I/O address pointer Fixed Updated Fixed Updated

Buffer address pointerFixed 32 34 33 35

Updated 34 36 35 37

I/O address pointerInternal access

B/even Odd

Buffer address pointer Internal accessB/even 0 +2

Odd +2 +4

Processing by CPU Processing by EI2OS

(Interrupt requests) AND (ISE = 1)Normal end status

Interrupt generated by “count out” or

I2OS Initial setting

Execute job

Transfer data

Reset extended

Process data in buffer

intelligent I/O service(channel switching)

by termination request from resource

3.3 Interrupts

217

3.3.4 ExceptionsIn the F2MC-16L series, exceptions are generated by the following sources, and then exception handling is performed.

• Execution of undefined instruction

Exception processing is basically the same as an interrupt; when the generation of an exception event at the boundary of an instruction is detected, normal processing is suspended and exception processing is performed. In general, exception processing is generated as the result of an unexpected operation; it is recommended that exception processing only be used for debugging purposes or for starting up recovery software in an emergency.

(1) Generation of an exception due to the execution of an undefined instruction

In the F2MC-16L, any code not defined in the instruction map is treated as an undefined instruction. If an undefined instruction is executed, processing equivalent to that of the software interrupt instruction “INT 10” is performed. In other words, after the contents of AL, AH, DPR, DTB, ADB, PCB, PC, and PS are saved into the system stack, the program branches to the routine indicated by the vector for interrupt #10. In addition, the I flag is cleared and the S flag is set. The value from the PC register saved into the stack is the address where the undefined instruction is stored. Therefore, while it is possible to resume processing by using the RETI or RETIQ instruction, doing so is meaningless since the exception will be generated again.

3.4 Memory Access Modes



3.4.1 The ModesThe F2MC-16L supports various modes according to the access method, the access area, and testing. In this module, these modes are grouped as follows:

Operation modes

Operation modes are the modes that control the operating status of the device. The operation mode is specified by the contents of the mode setting pin MDx and the Ex bit in the mode data. An operation mode can be selected for normal operations, starting an internal testing program, and starting a special testing function.

[CAUTION] The MB90660A series operates only in single-chip mode, and therefore bits MD2, MD1, MD0 should only be set to ‘011’ and bits M1, M0 should be set to ‘00.’

Bus modes

Bus modes are the modes that control the operation of internal ROM and the operation of external access functions. The bus mode is specified by the contents of the mode setting pin MDx and the Mx bit in the mode data.

The mode setting pins MDx specify the bus mode for reading reset vectors and mode data, and therefore the Mx bit in the mode data indicates the bus mode for normal operation.

[CAUTION] The MB90660A series operates only in single-chip mode, and therefore bits MD2, MD1, MD0 should only be set to ‘011’ and bits M1, M0 should be set to ‘00.’

Operation modes Bus mode

Single chip Programming EPROM Test functions

Single chip


219

3.4.2 Mode PinsThe mode pins MD2-MD0 can be used in combinations to determine MB90660A operation as shown in Table 3.4.1.

Table 3.4.1 Relationship between Mode Pins and Mode Setting

[CAUTION] The MB90660A series operates only in single-chip mode, and therefore bits MD2, MD1, MD0 should only be set to ‘011.’

Mode pin settings

Mode name

Reset vector access area

External data bus

widthRemarks

MD2 MD1 MD0

0 0 0

(Reserved: use prohibited)0 0 1

0 1 0

0 1 1 Internal vector mode Internal (Mode data)Controlled by mode data after reset sequence

1 0 0(Test mode: use prohibited)

1 0 1

1 1 1 Programming EPROM – –



3.4.3 Mode DataThe mode data is the CPU operation control data located in main memory at FFFFDFH. This data is fetched while the reset sequence is being executed and is stored in the device’s internal mode register. The contents of the mode register can only be changed during the reset sequence.

The mode set by this register is valid starting from the reset sequence and beyond.

The settings controlled by each bit are shown in Fig. 3.4.1.

Fig. 3.4.1 Mode Data Structure

Bus mode setting bits

These bits set the operation mode after the reset sequence. Table 3.4.2 shows the relation between bit values and functions.

Table 3.4.2 Bus Mode Select Bits and Functions

[CAUTION] The MB90660A series operates only in single-chip mode, and therefore M1, M0 should be set to ‘00.’

M1 M0 Function Remarks

0 0 Single-chip mode

0 1

(Prohibited)1 0

1 1

Bus mode setting bits

Mode Data

7 6 5 4 3 2 1 0

M1 M0 0 0 0 0 0 0

(Reserved)


221

Figure 3.4.2 illustrates the relation between access areas and physical addresses in single-chip mode.

Note: "Model" is an address that depends on the model in question.

Fig. 3.4.2 Relationship between Access Areas and the Physical Addresses According to the Bus Mode

Settings

Table 3.4.3 lists mode pin settings and mode data.

Table 3.4.3 Mode Pins and Mode Data Settings

[CAUTION] The MB90660A series operates only in single-chip mode.

Mode MD2 MD1 MD0 M1 M0

Single-chip mode 0 1 1 0 0

ROM

I/O

: Internal

: No access

FFFFFFH

Model #1

FF0000H

00FFFFH

Model #2

Model #3

000100H

0000C0H

000000H

ROM

RAM

Single-chip

3.5 Low Power Consumption Modes



The MB90660A supports the following operating modes: PLL clock mode, PLL sleep mode, watch mode, main clock mode, main sleep mode and stop mode. All modes other than PLL clock mode are classified as low-power consumption modes.

In main clock mode and main sleep mode, the main clock (OSC oscillator clock) signal operates alone, the operating clock signal is produced by dividing the main clock signal by two, and the PLL clock (VCO oscillator clock) signal is stopped. In PLL sleep mode and main sleep mode, only the CPU operating clock is stopped, and all other clock signals operate. In watch mode, only the timebase timer operates. Stop mode, in which all oscillators are stopped, is the lowest power-consumption mode in which data values are retained.

The CPU intermittent operation function allows the clock signal feed to the CPU to operate intermittently for registers, internal memory, internal resources or external bus access. This enables reduced power consumption by lowering the CPU execution speed while maintaining the high speed clock feed to internal resources.

The PLL clock multiplier rate is set using the CS1, CS0 bits and may be selected from either 1, 2, 3, or 4 times the clock signal feed.

Table 3.5.1 shows the MB90660A chip operating status in each of its operating modes.

Table 3.5.1 Low-power Consumption Modes and Operating State

Transition conditions

Oscillator Clock CPUPeripheral resources

PinsMode

exited by

Main sleep mode

MCS=1SLP=1

Operation Operation Stopped Operation OperationReset or interrupt

PLL sleep mode

MCS=0SLP=1

Operation Operation Stopped Operation OperationReset or interrupt

Watch mode (SPL=0)

MCS=0STP=1

Operation Stopped Stopped StoppedRetain pre-vious status

Reset or interrupt

Watch mode (SPL=1)

MCS=0STP=1

Operation Stopped Stopped Stopped HI-ZReset or interrupt

Stop mode (SPL=0)

MCS=1STP=1

Stopped Stopped Stopped StoppedRetain pre-vious status

Reset or interrupt

Stop mode (SPL=1)

MCS=1STP=1

Stopped Stopped Stopped Stopped HI-ZReset or interrupt


223

Figure 3.5.1 shows the configuration of the low-power consumption mode control register and clock select register.

LPMCR (Low-power consumption mode control register)

CKSCR (Clock select register)

Fig. 3.5.1 LPMCR/CKSCR Registers

[CAUTION] Access to the Low-power Consumption Mode Control Register

Only the instructions listed in Table 3.5.2 should be used for transition to low-power consumption modes (stop mode, sleep mode), which is accomplished by writing to the low power consumption mode control register (LPMCR). Use of any instructions other than those listed in Table 3.5.2 for transition to low-power consumption modes may cause abnormal operation. When the LPMCR register is used to control any functions other than transition to low power consumption modes, any instructions may be used.

When writing to the LPMCR register using word-length instructions, be sure to write to even-numbered addresses. Attempting transition to low-power consumption modes by writing to odd-numbered addresses may cause abnormal operation.

Table 3.5.2 Instructions Used for Transition to Low Power Consumption Modes

MOV io,#imm8 MOV dir,#imm8 MOV eam,#imm8 MOV eam,Ri

MOV io,A MOV dir,A MOV addr16,A MOV eam,A

MOV @RLi+disp8,A MOVP addr24,A

MOVW io,#imm16 MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi

MOVW io,A MOVW dir,A MOVW addr16,A MOVW eam,A

MOVW @RLi+disp8,A MOVPW addr24,A

SETB io:bp SETB dir:bp SETB addr16:bp


⇐ Bit no.


Address : 0000A0H

7 6 5 4 3 2 1 0

LPMCR


⇐ Bit no.


Address : 0000A1H

15 14 13 12 11 10 9 8

CKSCR



Each of the MB90660A low-power consumption modes and its operation are described as follows.

(1) Sleep Mode

Transition to Sleep Mode

Transition to sleep mode is initiated by writing ‘1’ to the SLP bit, and ‘0’ to the STP bit in the low-power consumption mode control register (LPMCR). Sleep mode stops only the clock signal feed to the CPU, stopping the CPU while the internal peripheral resource circuits continue to operate.

If an interrupt request is generated at the time that ‘1’ is written to the SLP bit, the standby control circuit will not execute transition to sleep mode. If the CPU status does not accept the interrupt, the next instruction will be executed. If the interrupt is accepted, processing will immediately branch to the interrupt processing routine.

In sleep mode, the contents of dedicated registers (such as accumulators) and internal RAM are retained.

Wake-up from Sleep Mode

The standby control circuit releases sleep mode at input of a reset signal or interrupt request. If wake-up from sleep mode is performed by a reset source, the MB90660A will be in reset state when it returns from sleep mode.

Wake-up from sleep mode will also be performed by the standby control circuit when any interrupt stronger (higher) than level 7 is generated by an internal resource circuit. After wake-up, the same processing is applied as for a normal interrupt. If the interrupt is accepted according to the values of the I flag, ILM bit and interrupt control register (ICR), the CPU will execute interrupt processing. If the interrupt is not accepted, execution will continue with the next instruction following the instruction that caused the transition to sleep mode.

[CAUTION] When interrupt processing is executed, the normal procedure is to first execute the instruction following the instruction that caused the transition to sleep mode before branching to interrupt processing.

(2) Watch Mode

Transition to Watch Mode

When the MCS bit in the clock select register is set to ‘0’ and ‘1’ is written to the STP bit in the low power consumption mode control register, the standby control circuit is set to place the MB90660A in watch mode. In watch mode all operations other than the main oscillator and timebase timer stop, and virtually all of the chip functions are shut down.

The SPL bit in the low power consumption mode control register can be used to control whether I/O pins retain their immediately prior values, or are placed in high-impedance state.

If an interrupt request is generated when ‘1’ is written to the STP bit, the standby control circuit will not make the transition to watch mode.


225

In clock mode, the contents of dedicated registers (such as accumulators) and internal RAM are retained.

Wake-up from Watch Mode

The standby control circuit is used for wake-up from watch mode at input of a reset signal or an interrupt request. If watch mode is released by a reset source, the MB90660A will be in reset state when it wakes up from clock mode.

For wake-up from watch mode, the standby control circuit will first release watch mode before moving into PLL clock oscillation stabilization wait state. Because the MCS bit is not cleared by an external reset signal, any instance in which the reset interval is shorter than the PLL clock oscillation stabilization wait period will result in the main clock being used for the reset sequence. Note also that in such instances the timebase timer is not cleared during the PLL clock oscillation stabilization wait period, and therefore the wait period may vary from 213 to 3*213 main clock cycles.

In watch mode, the occurrence of any interrupt request stronger (higher) than level 7 in a peripheral circuit will cause a wake-up from watch mode through the standby control circuit. After wake-up, the same processing is applied as for a normal interrupt. If the interrupt is accepted according to the values of the I flag, ILM bit and interrupt control register (ICR), the CPU will execute interrupt processing. If the interrupt is not accepted, execution will continue with the next instruction following the instruction that caused the transition to watch mode.

[CAUTION] When interrupt processing is executed, the normal procedure is to first execute the instruction following the instruction that caused the transition to sleep mode before branching to interrupt processing.

[CAUTION] Upon wake-up from watch mode, the MB90660A will transition into PLL clock oscillation stabilization wait state, so that when the PLL clock is not in use, the MCS bit should be overwritten with the value ‘1’ by the next instruction immediately after the reset or interrupt designation.

(3) Stop Mode

Transition to Stop Mode

The standby control circuit initiates transition to stop mode when the value ‘1’ is written to the STP bit in the low-power consumption mode control register while the MCS bit in the clock control register is set to ‘1.’ In stop mode, the source oscillation is stopped, stopping all MB90660A chip functions. This is therefore the mode with the lowest-power consumption in which data is retained.

Also, the SPL bit in the LPMCR register can be used to determine whether I/O pins are placed in high-impedance state or retain their values immediately preceding the transition to stop mode.

If an interrupt request is generated at the time that ‘1’ is written to the STP bit, the standby control circuit will not make the transition to stop mode.



In stop mode, the contents of dedicated registers (such as accumulators) and internal RAM are retained.

Wake-up from Stop Mode

The standby control circuit performs wake-up from stop mode at input of a reset signal or occurrence of an interrupt. If stop mode is exited by a reset source, the MB90660A will be in reset state when it wakes up from stop mode.

For wake-up from stop mode, the standby control circuit will move first to oscillation stabilization wait mode prior to wake-up from stop mode. Also, if a reset source is the cause for wake-up from stop mode, the reset sequence is initiated after an oscillation stabilization wait interval before the reset is applied.

During stop mode, any interrupt request stronger (higher) than level 7 generated from a peripheral circuit or any other source can wake up the MB90660A from stop mode. The wake-up sequence first passes into an oscillation stabilization interval defined by the WS1, WS0 bits in the CKSCR register, then follows the normal interrupt processing sequence. If the interrupt request is accepted according to the values of the I flag, ILM bit and interrupt control register (ICR), the CPU will branch to interrupt processing. If the interrupt is not accepted, execution will continue with the next instruction following the instruction that caused the transition to stop mode.

[CAUTION] When interrupt processing is executed, the normal procedure is to first execute the instruction following the instruction that caused the transition to stop mode before branching to interrupt processing.

(4) CPU Intermittent Operation Function

The CPU intermittent operation function allows the clock signal feed to the CPU to operate intermittently for registers, internal memory (ROM, RAM, I/O, or resource memory) or external bus access. This function delays the start of the internal bus cycle by introducing a fixed pause in the clock signal feed, thus reducing power consumption by lowering the CPU execution speed while maintaining the high speed clock feed to the internal resources. The CG1, CG0 bits select the number of fixed pause cycles in the clock feed to the CPU.

Note that external bus operations continue to use the same clock signal as the peripheral resources.

Instruction execution time using the CPU intermittent operation function can be calculated by adding the number of access cycles to register, internal memory and internal resources to the normal execution time increased by a fixed number of cycles in each pause.

Peripheral clock

CPU clock

Intermittent operation temporary ⇑Internal bus startup cyclepause cycle


227

(5) Oscillation Stabilization Wait Period Settings

The WS1, WS0 bits are used to select the length of the oscillation stabilization wait period applied after wake-up from stop mode. The user should select the appropriate wait period according to the characteristics of oscillator circuits connected to the X0 and X1 pins, as well as the types of oscillation elements used.

These bits are not initialized by any reset signals other than the power-on reset. At a power-on reset the value is initialized to ‘11.’ As a result the oscillation stabilization wait period at power-on is approximately 218 counts of the source oscillation.

(6) Machine Clock Switching

Main clock/PLL clock switching

The MB90660A can switch between the main clock and PLL clock, by writing to the MCS bit in the CKSCR register.

When the MCS bit is changed from ‘1’ to ‘0’ a PLL clock oscillation stabilization wait period (213machine clock cycles) is applied before switching from the main clock to the PLL clock.

When the MCS bit is changed from ‘0’ to ‘1’ operation switches from the PLL clock to the main clock at the next match between edges of the PLL clock and main clock signals (within 1 to 8 PLL clock cycles).

Because machine clock switching does not take place immediately upon overwriting the MCS bit, operation of resources that depend on the machine clock should be delayed until after the MCM bit is referenced to verify the switch in machine clock speeds.

Machine Clock Initialization

The MCS bit is not initialized by resets from external pins or the RST bit. The initial value following a reset is ‘1.’



(7) Status Transition

Figure 3.5.2 illustrates the transition possibilities among low power consumption modes.

(1) Oscillation stabilization wait time ends (7) MCS=0

(2) Reset release, MCS=1 (8) MCS=1

(3) Reset signal input (9) STP=1, MCS=0

(4) SLP=1, MCS=1 (10) SLP=1, MCS=0

(5) Interrupt input (11) Reset release, MCS=0

(6) STP=1, MCS=1

Fig. 3.5.2 Low Power Consumption Mode Transition Status

Oscillationstabilizationwait,Reset status

Power-on

Oscillation stabilizationwait mode

Reset status Watch mode

Stop modeMain clockrun mode

PLL clockrun mode

Main clocksleep mode

PLL clocksleep mode

(3)(3)

(1)

(2)

(3)

(3)(3)

(1)

(5)

(6)

(6)

(3)(11)

(7)

(9)(5)

(9)

(8)

(4) (5)(4) (10) (10)

(5)

(3)(3)

3.6 Pin Status in Sleep, Stop, Hold and Reset Modes

229

3.6 Pin Status in Sleep, Stop, Hold and Reset Modes

Tables 3.6.1 and 3.6 show pin status in sleep, stop, hold and reset modes, when the MB90660A is in single-chip mode.

In the MB90660A series, pull-up resistor is disconnected in stop mode at pins for which pull-up options are selected (pins of circuit types B and E in the “Pin Function Description”). Note, however, that pull-up resistor is not disconnected in stop mode for the P44-P47, RSTX and DTTI pins (pins of circuit type D in the “Pin Function Description”).

Table 3.6.1 Pin Status in Single Chip Mode

Note 1: Because the P47 to P44 pins are always in input status, either pull-up or pull-down pin processing should be applied to this port when not in use.

Note 2: In this mode output pins retain their immediately prior output level, and input pins are input-disabled. Immediately prior output level for internal peripheral resources means output according to settings made for that resource, and for ports means that the port output signal level is retained. Input disabled means that the first input gate nearest the pin is in enabled state but that the internal circuits are not activated, so that the level of the pin signal is not received by interior circuits.

Note 3: Input shut-off means that the first input gate nearest the pin is in operation-disabled state, and output Hi-Z means that the pin drive transistor is in drive-disabled state leaving the pin in high-impedance state.

Note 4: P27 to P24 do not have input shut off, therefore when this port is placed in output Hi-Z state, either pull-up or pull-down pin processing should be applied.

Pin Sleep modeStop mode

ResetSPL=0 SPL=1

P07 to P00P17 to P10P23 to P20P33 to P30P43 to P40P57 to P50P66 to P60

Retain immediatelyprior statusNote 2

Retain immediatelyprior status

Input cut off / Output Hi-ZNote3

Input disabled / Output Hi-Z

P27 to P24Retain immediatelyprior status

Retain immediatelyprior status

Input status / Output Hi-ZNote 4

Input disabled / Output Hi-Z

P47 to P44 Input status Note 1

4.1 Addressing

230 Chapter 4: Instructions

Chapter 4:Instructions

4.1 Addressing

In the F2MC-16L, the address format is determined by either the instruction’s effective address specification, or by the instruction code itself (implied addressing).

4.1.1 Effective address fieldThe address formats specified in the effective address field are shown in Table 4.1.1.

Table 4.1.1 Effective Address Field

Code Notation Address format Default bank

0001020304050607

R0R1R2R3R4R5R6R7

RW0RW1RW2RW3RW4RW5RW6RW7

RL0(RL0)RL1

(RL1)RL2

(RL2)RL3

(RL3)

Register directStarting from the left, “ea” corresponds to the byte, word and long-word types.

None

08090A0B

@RW0@RW1@RW2@RW3

Register indirect

DTBDTBADBSPB

0C0D0E0F

@RW0+@RW1+@RW2+@RW3+

Register indirect with post-incrementing

DTBDTBADBSPB

10111213

@RW0*disp8@RW1+disp8@RW2+disp8@RW3+disp8

Register indirect with 8-bit displacement

DTBDTBADBSPB

14151617

@RW4+disp8@RW5+disp8@RW6+disp8@RW7+disp8


DTBDTBADBSPB

18191A1B



DTBDTBADBSPB

1C1D1E1F

@RW0+RW7@RW1+RW7@PC+disp16

addr16

Register indirect with indexRegister indirect with indexPC indirect with 16-bit displacementDirect address

DTBDTBPCBDTB

4.1 Addressing

231

4.1.2 Addressing Details(1) Immediate value (#imm)

This format specifies the operand value directly.

• #imm4

• #imm8

• #imm6

• #imm32

(2) Compressed direct address (dir)

In this format, the operand specifies the low-order 8 bits of the memory address. Bits 8 to 15 of the address are specified by the DPR. Bits 16 to 23 of the address are indicated by the DTB.

(3) Direct address (addr16)

In this format, the operand specifies the low-order 16 bits of the memory address. Bits 16 to 23 of the address are indicated by the DTB.

(4) Register direct

This format specifies a direct register as the operand.

General-purpose registers

Byte: R0, R1, R2, R3, R4, R5, R6, R7

Word: RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

Long word: RL0, RL1, RL2, RL3

Dedicated registers

Accumulator: A, AL

Pointer: SP

Bank: PCB, DTB, USB, SSB, ADB

Page: DPR

Control: PS, CCR, RP, ILM

* Regarding the SP, either the USP or the SSP is selected and used, depending on the value of the S bit in the CCR. In addition, in a branching instruction, the PC is implicitly specified, and is not described in the instruction operand.

4.1 Addressing


(5) Register indirect (@RWj j = 0 to 3)

This format accesses the memory address indicated by the contents of the general-purpose register RWj. When RW0/RW1 is used, bits 16 to 23 of the address are indicated by DTB; if RW3 is used, bits 16 to 23 of the address are indicated by SPB, and if RW2 is used, bits 16 to 23 of the address are indicated by ADB.

(6) Register indirect with post-incrementing (@RWj + j = 0 to 3)

This format accesses the memory address indicated by the contents of the general-purpose register RWj. After the operand operation, RWj is incremented by the data length of the operand (by 1 for a byte, 2 for a word, and 4 for a long-word). When RW0/RW1 is used, bits 16 to 23 of the address are indicated by DTB; if RW3 is used, bits 16 to 23 of the address are indicated by SPB, and if RW2 is used, bits 16 to 23 of the address are indicated by ADB. Note that if the post-incremented result is the address of the register for which the increment specification was made, the value that is referenced subsequently is the incremented value. In addition, in such a case, if the instruction was a write instruction, the data written by the instruction is given priority, so the register that was to have been incremented contains the write data in the end.

(7) Register indirect with displacement

This format accesses the memory address indicated by the sum of the contents of the general-purpose register RWj and the displacement value. The displacement value can be one of two types, either a byte or a word, and is added as a signed value. When RW0, RW1, RW4, or RW5 is used, bits 16 to 23 of the address are indicated by DTB; if RW3 or RW7 is used, bits 16 to 23 of the address are indicated by SPB, and if RW2 or RW6 is used, bits 16 to 23 of the address are indicated by ADB.

(8) Register indirect with base index (@RW0 + RW7, @RW1 + RW7)

This format accesses the memory address indicated by the sum of the contents of the general-purpose register and either RW0 or RW1. Bits 16 to 23 of the address are indicated by DTB.

(9) Program counter indirect with displacement (@PC + disp16)

This format accesses the memory address indicated by the sum of the “instruction address + 4 + disp16”. The displacement value is a word length value. Bits 16 to 23 of the address are indicated by PCB.

The operand address is generally regarded as “the next instruction address + disp16”, but note that this does not hold true for the instructions indicated below:

• DBNZ eam, rel

• DWBNZ eam, rel

• MOV eam, #imm8

• MOVW eam, #imm16

• CBNE eam, #imm8, rel

• CWBNE eam, #imm16, rel

@RWi + disp8 i = 0 to 7@RWj + disp16 j = 0 to 3

4.1 Addressing

233

(10) Accumulator indirect (@A)

This format has two types: one in which the contents of AL specify bits 00 to 15 of the address and DTB indicates bits 16 to 23; and one in which the low-order 24 bits of A specify bits 00 to 23 of the address.

(11) I/O direct (io)

In this format, the memory address of the operand is specified directly by the 8-bit displacement value. Regardless of the value of DTB and DPR, the I/O space from 000000H to 0000FFH is accessed. The access space specification prefix has no effect on this addressing format.

(12) Long register indirect with displacement (@RLi + disp8 i = 0 to 3)

This format accesses the memory address indicated by the low-order 24 bits of the sum of the contents of the general-purpose register RLi plus the displacement value. The displacement value is 8 bits, and is added as a signed numeral.

(13) Compressed direct bit address (dir:bp)

This format specifies the low-order 8 bits of the memory address with the operand. In addition, bits 8 to 15 of the address are indicated by DPR. Finally, bits 16 to 23 of the address are indicated by DTB. The bit position is indicated by “:bp”, with larger numbers being closer to the MSB and smaller numbers being closer to the LSB.

(14) I/O direct bit address (io:bp)

This format directly specifies a bit within a physical address from 000000H to 0000FFH. The bit position is indicated by “:bp”, with larger numbers being closer to the MSB and smaller numbers being closer to the LSB.

(15) Direct bit address (addr16:bp)

This format directly specifies any bit within a 64-kilobyte region. Bits 16 to 23 of the address are indicated by DTB. The bit position is indicated by “:bp”, with larger numbers being closer to the MSB and smaller numbers being closer to the LSB.

(16) Register list (rlst)

This format specifies the register that is the target of a stack push/pop instruction.

Fig. 4.1.1 Register List Configuration

A register is selected when the corresponding bit is “1”, and is not selected when the corresponding bit is “0”.

RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0

MSB LSB

4.1 Addressing


(17) Program counter relative branching address (rel)

With this format, the address of the destination of a branching instruction is the sum of the value of the PC and the 8-bit displacement value. If the result exceeds 16 bits, the amount of the overflow is ignored and the bank register is not incremented or decremented; therefore, the address is kept within a 64-kilobyte bank. This format is used in unconditional and conditional branching instructions. Bits 16 to 23 of the address are indicated by PCB.

(18) Direct branching address (addr16)

With this format, the address of the destination of a branching instruction is specified directly by the displacement value. The displacement value is 16 bits, and indicates the branching destination within a logical memory space. This format is used in unconditional branching instructions and subroutine call instructions. Bits 16 to 23 of the address are indicated by PCB.

(19) Physical direct branching address (addr24)

With this format, the address of the destination of a branching instruction is specified directly by the displacement value. The displacement value is 24 bits, and specifies the physical address of the branching destination. This format is used in unconditional branching instructions, subroutine call instructions, and software interrupt instructions.

(20) Accumulator indirect branching address (@A)

In this format, the 16 bits of the accumulator AL specify the branching destination address. This address indicates a branching destination within a bank space; in this case, bits 16 to 23 of the address are indicated by the PCB. In the case of JCTX, however, bits 16 to 23 of the address are indicated by DTB. This format is used in unconditional branching instructions.

(21) Vector address (#vct)

The contents of the specified vector become the branching destination address. There are two data lengths for vector numbers: 4 bits and 8 bits. This format is used in subroutine call instructions and software interrupt instructions.

(22) Indirect specification branching address (@ear)

The word data in the address indicated by “ear” is the branching destination address.

(23) Indirect specification branching address (@eam)

The word data in the address indicated by “eam” is the branching destination address.

4.2 Instruction Set

235

4.2 Instruction Set

Table 4.2.1 Explanation of Items in Table of Instructions

Item Explanation

MnemonicUpper-case letters and symbols: ........ Described as they appear in assembler.Lower-case letters: ............................. Replaced when described in assembler.Numbers after lower-case letters: ...... Indicate the bit width within the instruction.

# Indicates the number of bytes.

~Indicates the number of cycles.See Table 4.2.4 for details about meanings of letters in items.

RGIndicates the register access count during execution of instruction. Used to calculate compensation values for CPU intermittent operation.

B

Indicates the compensation value for calculating the number of actual cycles during execution of instruction.The number of actual cycles during execution of instruction is the compensation value summed with the value in the “~” column.

Operation Indicates operation of instruction.

LH

Indicates special operations involving bits 15 through 08 of the accumulator.Z:........Transfers “0”.X: .......Sign-extended transfer through sign extension.-: .........Transfers nothing.

AH

Indicates special operations involving the high-order 16 bits in the accumulator.*: ........Transfers from AL to AH.-: .........No transfer.Z:........Transfers 00 to AH.X: .......Transfers 00H or FFH to AH using sign extension AL.

I

Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry).*: ........Changes due to execution of instruction.-: .........No change.S: ........Set by execution of instruction.R: .......Reset by execution of instruction.

S

T

N

Z

V

C

RMW

Indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.).*: ........Instruction is a read-modify-write instruction-: .........Instruction is not a read-modify-write instructionNote: A read-modify-write instruction cannot be used on addresses that have different mean-

ings depending on whether they are read or written.

4.2 Instruction Set


Number of execution cycles

The number of cycles required for the execution of an instruction is obtained by summing the value shown in the table for the “number of cycles” for the instruction in question, the compensation value (which depends on certain conditions), and the “number of cycles” needed for the program fetch.

When fetching a program in memory connected to the 16-bit bus, such as on-chip ROM, a program fetch is performed for each two-byte (word) boundary crossed by the instruction being executed; therefore, if there is any interference with data access, etc., the number of execution cycles increases.

When fetching a program in memory connected to the 8-bit external data bus, a program fetch is performed for each byte of the instruction being executed; therefore, if there is any interference with data access, etc., the number of execution cycles increases.

In CPU intermittent operation, each access to general-purpose registers, internal ROM, internal RAM, internal I/O functions or external bus causes the CPU clock to pause for a fixed number of cycles determined by the CG1/CG0 bits in the low power consumption mode control register. For this reason, the number of machine clock cycles required to execute an instruction under CPU intermittent operation is the normal number of cycles plus an offset number of cycles that is derived by multiplying the number of access operations by the length (in cycles) of the fixed pause.

4.2 Instruction Set

237

Table 4.2.2 Explanation of Symbols in Table of Instructions

Symbol Explanation

A

32-bit accumulatorThe bit length varies according to the instruction.

Byte:............ Low-order 8 bits of ALWord: .......... 16 bits of ALLong: ........... 32 bits of AL:AH

AHAL

High-order 16 bits of ALow-order 16 bits of A

SP Stack pointer (USP or SSP)

PC Program counter

PCB Program bank register

DTB Data bank register

ADB Additional data bank register

SSB System stack bank register

USB User stack bank register

SPB Current stack bank register (SSB or USB)

DPR Direct page register

brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB

brg2 DTB, ADB, SSB, USB, DPR, SPB

Ri R0, R1, R2, R3, R4, R5, R6, R7

RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RWj RW0, RW1, RW2, RW3

RLi RL0, RL1, RL2, RL3

diraddr16addr24ad24 0 to 15ad24 16 to 23

Compact direct addressingDirect addressingPhysical direct addressingBits 0 to 15 of addr24Bits 16 to 23 of addr24

io I/O area (000000H to 0000FFH)

#imm4#imm8#imm16#imm32ext(imm8)

4-bit immediate data8-bit immediate data16-bit immediate data32-bit immediate data16-bit data signed and extended from 8-bit immediate data

disp8disp16

8-bit displacement16-bit displacement

4.2 Instruction Set


bp Bit offset value

vct4vct8

Vector number (0 to 15)Vector number (0 to 255)

( )b Bit address

releaream

Branch specification relative to PCEffective addressing (codes 00 to 07)Effective addressing (codes 08 to 1F)

rlst Register list

Table 4.2.2 Explanation of Symbols in Table of Instructions (Continued)

Symbol Explanation

4.2 Instruction Set

239

Table 4.2.3 Effective Address Fields

*: The number of bytes for address extension is indicated by the “+” symbol in the “#” (number of bytes) column in the Table of Instructions and by the number of bytes in the detailed instruction rules.

Code Notation Address formatNumber of bytes in address extension

[Note]

0001020304050607

R0R1R2R3R4R5R6R7

RW0RW1RW2RW3RW4RW5RW6RW7

RL0(RL0)RL1

(RL10)RL2

(RL2)RL3

(RL3)

Register direct“ea” corresponds to byte, word, and long-word types, starting from the left

–

08090A0B

@RW0@RW1@RW2@RW3

Register indirect 0

0C0D0E0F

@RW0+@RW1+@RW2+@RW3+

Register indirect with post-incrementing 0

1011121314151617

@RW0+disp8@RW1+disp8@RW2+disp8@RW3+disp8@RW4+disp8@RW5+disp8@RW6+disp8@RW7+disp8

Register indirect with 8-bit displacement 1

18191A1B


Register indirect with 16-bit displacement 2

1C1D1E1F


addr16

Register indirect with indexRegister indirect with indexPC indirect with 16-bit displacementDirect address

0022

4.2 Instruction Set


Table 4.2.4 Number of Execution Cycles for Each Form of Addressing

Note: “(a)” is used in the “~” (number of cycles) column, column B (compensation value) and in the detailed instruction rules in the Table of Instructions.

Table 4.2.5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles

Note 1: “(b)”, “(c)”, and “(d)” are used in the “~” (number of cycles) column, column B (compensation value) and in the detailed instruction rules in the Table of Instructions.

Note 2: When the external data bus is used, it is necessary to add in the number of weighted cycles used for

Code Operand

(a)Number of accesses for

each form of addressing

Number of execution cycles for each form of

addressing

00to07

RiRWiRLi

Listed in Table of Instructions

Listed in Table of Instructions

08to0B

@RWj 2 1

0Cto0F

@RWj+ 4 2

10to17

@RWi+disp8 2 1

18to1B

@RWj+disp16 2 1

1C1D1E1F


addr16

4421

2200

Operand(b) byte (c) word (d) long

CyclesAccess cycles

CyclesAccess cycles

CyclesAccess cycles

Internal register +0 1 +0 1 +0 2

Internal RAM even addressInternal RAM odd address

+0+0

11

+0+2

12

+0+4

24

Even address on external data bus (16 bits)Odd address on external data bus (16 bits)

+1+1

11

+1+4

12

+2+8

24

External data bus (8 bits) +1 1 +4 2 +8 4

4.2 Instruction Set

241

ready input and automatic ready.

Table 4.2.6 Compensation Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles

Note 1: When the external data bus is used, it is necessary to add in the number of weighted cycles used for ready input and automatic ready.

Note 2: Because instruction execution is not slowed down by all program fetches in actuality, these compensation values should be used for “worst case” calculations.

Instruction Byte boundary Word boundary

Internal memory – +2

External data bus (16 bits) – +3

External data bus (8 bits) +3 –

4.2 Instruction Set


4.2.1 F2MC-16L Instruction Set (340 Instructions)

Table 4.2.7 Transfer Instructions (Byte) (41 Instructions)

Note: For an explanation of “(a)” to “(d)”, see Table 4.2.3 and Table 4.2.4.

Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW

MOV A,dirMOV A,addr16MOV A,RiMOV A,earMOV A,eamMOV A,ioMOV A,#imm8MOV A,@AMOV A,@RLi+disp8MOVN A,#imm4

MOVX A,dirMOVX A,addr16MOVX A,RiMOVX A,earMOVX A,eamMOVX A,ioMOVX A,#imm8MOVX A,@AMOVX A,@RWi+disp8MOVX A,@RLi+disp8

MOV dir,AMOV addr16,AMOV Ri,AMOV ear,AMOV eam,AMOV io,AMOV @RLi+disp8,AMOV Ri,earMOV Ri,eamMOV ear,RiMOV eam,RiMOV Ri,#imm8MOV io,#imm8MOV dir,#imm8MOV ear,#imm8MOV eam,#imm8MOV @AL,AH / MOV @A,T

XCH A,earXCH A,eamXCH Ri,earXCH Ri,eam

2312

2+22231

2322

2+22223

2312

2+232

2+2

2+2333

3+2

22+2

2+

3422

3+(a)323101

3422

3+(a)323510

3422

3+(a)3103

4+(a)4

5+(a)2552

4+(a)3

45+(a)

79+(a)

0011000020

0011000012

00110022121100100

2042

(b)(b)00

(b)(b)0

(b)(b)0

(b)(b)00

(b)(b)0

(b)(b)(b)

(b)(b)00

(b)(b)(b)0

(b)0

(b)0

(b)(b)0

(b)(b)

02x(b)

02x(b)

byte (A) ← (dir)byte (A) ← (addr16)byte (A) ← (Ri)byte (A) ← (ear)byte (A) ← (eam)byte (A) ← (io)byte (A) ← (imm8)byte (A) ← ((A))byte (A) ← ((RLi)+disp8)byte (A) ← imm4

byte (A) ← (dir)byte (A) ← (addr16)byte (A) ← (Ri)byte (A) ← (ear)byte (A) ← (eam)byte (A) ← (io)byte (A) ← (imm8)byte (A) ← ((A))byte (A) ← ((RWi)+disp8)byte (A) ← ((RLi)+disp8)

byte (dir) ← (A)byte (addr16) ← (A)byte (Ri) ← (A)byte (ear) ← (A)byte (eam) ← (A)byte (io) ← (A)byte ((RLi)+disp8) ← (A)byte (Ri) ← (ear)byte (Ri) ← (eam)byte (ear) ← (Ri)byte (eam) ← (Ri)byte (Ri) ← imm8byte (io) ← imm8byte (dir) ← imm8byte (ear) ← imm8byte (eam) ← imm8byte ((A)) ← (AH)

byte (A) ←→ (ear)byte (A) ←→ (eam)byte (Ri) ←→ (ear)byte (Ri) ←→ (eam)

ZZZZZZZZZZ

XXXXXXXXXX

-----------------

ZZ--

*******-**

*******-**

-----------------

----

----------

----------

-----------------

----

----------

----------

-----------------

----

----------

----------

-----------------

----

*********R

**********

************--*-*

----

**********

**********

************--*-*

----

----------

----------

-----------------

----

----------

----------

-----------------

----

----------

----------

-----------------

----

4.2 Instruction Set

243

Table 4.2.8 Transfer Instructions (Word/Long-Word) (38 Instructions)


Mnemonic # ~ RG B Operation LH AH I S T N Z V C RM

MOVW A,dirMOVW A,addr16MOVW A,SPMOVW A,RWiMOVW A,earMOVW A,eamMOVW A,ioMOVW A,@AMOVW A,#imm16MOVW A,@RWi+disp8MOVW A,@RLi+disp8

MOVW dir,AMOVW addr16,AMOVW SP,AMOVW RWi,AMOVW ear,AMOVW eam,AMOVW io,AMOVW @RWi+disp8,AMOVW @RLi+disp8,AMOVW RWi,earMOVW RWi,eamMOVW ear,RWiMOVW eam,RWiMOVW RWi,#imm16MOVW io,#imm16MOVW ear,#imm16MOVW eam,#imm16MOVW @AL,AH / MOVW @A,T

XCHW A,earXCHW A,eamXCHW RWi,earXCHW RWi,eam

231122+22323

231122+22322+22+3444+2

22+22+

341223+(a)332510

341223+(a)351034+(a)45+(a)2524+(a)3

45+(a)79+(a)

00011000012

000110012212110100

2042

(c)(c)000(c)(c)(c)0(c)(c)

(c)(c)000(c)(c)(c)(c)0(c)0(c)0(c)0(c)(c)

02x(c)02x(c)

word (A) ← (dir)word (A) ← (addr16)word (A) ← (SP)word (A) ← (RWi)word (A) ← (ear)word (A) ← (eam)word (A) ← (io)word (A) ← ((A))word (A) ← imm16word (A) ← ((RWi)+disp8)word (A) ← ((RLi)+disp8)

word (dir) ← (A)word (addr16) ← (A)word (SP) ← (A)word (RWi) ← (A)word (ear) ← (A)word (eam) ← (A)word (io) ← (A)word ((RWi)+disp8) ← (A)word ((RLi)+disp8) ← (A)word (RWi) ← (ear)word (RWi) ← (eam)word (ear) ← (RWi)word (eam) ← (RWi)word (RWi) ← imm16word (io) ← imm16word (ear) ← imm16word (eam) ← imm16word (A) ← (AH)

word (A) ←→ (ear)word (A) ←→ (eam)word (RWi) ←→ (ear)word (RWi) ←→ (eam)

-----------

------------------

----

*******-***

------------------

----

-----------

------------------

----

-----------

------------------

----

-----------

------------------

----

***********

**************-*-*

----

***********

**************-*-*

----

-----------

------------------

----

-----------

------------------

----

-----------

------------------

----

MOVL A,earMOVL A,eamMOVL A,#imm32

MOVL ear,AMOVL eam,A

22+5

22+

45+(a)3

45+(a)

200

20

0(d)0

0(d)

long (A) ← (ear)long (A) ← (eam)long (A) ← imm32

byte (ear1) ← (A)long (eam1) ← (A)

---

--

---

--

---

--

---

--

---

--

***

**

***

**

---

--

---

--

---

--

4.2 Instruction Set


Table 4.2.9 Addition and Subtraction Instructions (Byte/Word/Long-Word) (42 Instructions)



ADD A,#imm8ADD A,dirADD A,earADD A,eamADD ear,AADD eam,AADDC AADDC A,earADDC A,eamADDDC A

SUB A,#imm8SUB A,dirSUB A,earSUB A,eamSUB ear,ASUB eam,ASUBC ASUBC A,earSUBC A,eamSUBDC A

2222+22+122+1

2222+22+122+1

2534+(a)35+(a)234+(a)3

2534+(a)35+(a)234+(a)3

0010200100

0010200100

0(b)0(b)02x(b)00(b)0

0(b)0(b)02x(b)00(b)0

byte (A) ← (A) + imm8byte (A) ← (A) + (dir)byte (A) ← (A) + (ear)byte (A) ← (A) + (eam)byte (ear) ← (ear) + (A)byte (eam) ← (eam) + (A)byte (A) ← (AH) + (AL) + (C)byte (A) ← (A) + (ear) + (C)byte (A) ← (A) + (eam) + (C)byte (A) ← (AH) + (AL) + (C) (hexadecimal)byte (A) ← (A) - imm8byte (A) ← (A) - (dir)byte (A) ← (A) - (ear)byte (A) ← (A) - (eam)byte (ear) ← (ear) - (A)byte (eam) ← (eam) - (A)byte (A) ← (AH) - (AL) - (C)byte (A) ← (A) - (ear) - (C)byte (A) ← (A) - (eam) - (C)byte (A) ← (AH) - (AL) - (C) (hexadecimal)

ZZZZ-ZZZZZ

ZZZZ--ZZZZ

----------

----------

----------

----------

----------

----------

----------

----------

**********

**********

**********

**********

**********

**********

**********

**********

-----*----

-----*----

ADDW AADDW A,earADDW A,eamADDW A,#imm16ADDW ear,AADDW eam,AADDCW A,earADDCW A,eamSUBW ASUBW A,earSUBW A,eamSUBW A,#imm16SUBW ear,ASUBW eam,ASUBCW A,earSUBCW A,eam

122+322+22+122+322+22+

234+(a)235+(a)34+(a)234+(a)235+(a)34+(a)

0100201001002010

00(c)002x(c)0(c)00(c)002x(c)0(c)

word (A) ← (AH) + (AL)word (A) ← (A) + (ear)word (A) ← (A) + (eam)word (A) ← (A) + imm16word (ear) ← (ear) + (A)word (eam) ← (eam) + (A)word (A) ← (A) + (ear) + (C)word (A) ← (A) + (eam) + (C)word (A) ← (AH) - (AL)word (A) ← (A) - (ear)word (A) ← (A) - (eam)word (A) ← (A) - imm16word (ear) ← (ear) - (A)word (eam) ← (eam) - (A)word (A) ← (A) - (ear) - (C)word (A) ← (A) - (eam) - (C)

----------------

----------------

----------------

----------------

----------------

****************

****************

****************

****************

-----*-------*--

ADDL A,earADDL A,eamADDL A,#imm32SUBL A,earSUBL A,eamSUBL A,#imm32

22+522+5

67+(a)467+(a)4

200200

0(d)00(d)0

long (A) ← (A) + (ear)long (A) ← (A) + (eam)long (A) ← (A) + imm32long (A) ← (A) - (ear)long (A) ← (A) - (eam)long (A) ← (A) - imm32

------

------

------

------

------

******

******

******

******

------

4.2 Instruction Set

245

Table 4.2.10 Increment and Decrement Instructions (Byte/Word/Long-Word) (12 Instructions)

Table 4.2.11 Compare Instructions (Byte/Word/Long-Word) (11 Instructions)



INC earINC eam

DEC earDEC eam

22+

22+

35+(a)

35+(a)

20

20

02x(b)

02x(b)

byte (ear) ← (ear) + 1byte (eam) ← (eam) + 1

byte (ear) ← (ear) - 1byte (eam) ← (eam) - 1

--

--

--

--

--

--

--

--

--

--

**

**

**

**

**

**

--

--

-*

-*

INCW earINCW eam

DECW earDECW eam

22+

22+

35+(a)

35+(a)

20

20

02x(b)

02x(b)

word (ear) ← (ear) + 1word (eam) ← (eam) + 1

word (ear) ← (ear) - 1word (eam) ← (eam) - 1

--

--

--

--

--

--

--

--

--

--

**

**

**

**

**

**

--

--

-*

-*

INCL earINCL eam

DECL earDECL eam

22+

22+

79+(a)

79+(a)

40

40

02x(d)

02x(d)

long (ear) ← (ear) + 1long (eam) ← (eam) + 1

long (ear) ← (ear) - 1long (eam) ← (eam) - 1

--

--

--

--

--

--

--

--

--

--

**

**

**

**

**

**

--

--

-*

-*


CMP ACMP A,earCMP A,eamCMP A,#imm8

122+2

123+(a)2

0100

00(b)0

byte (AH) - (AL)byte (A) - (ear)byte (A) - (eam)byte (A) - imm8

----

----

----

----

----

****

****

****

****

----

CMPW ACMPW A,earCMPW A,eamCMPW A,#imm16

122+3

123+(a)2

0100

00(c)0

word (AH) - (AL)word (A) - (ear)word (A) - (eam)word (A) - imm16

----

----

----

----

----

****

****

****

****

----

CMPL A,earCMPL A,eamCMPL A,#imm32

22+5

67+(a)3

200

0(d)0

long (A) - (ear)long (A) - (eam)long (A) - imm32

---

---

---

---

---

***

***

***

***

---

4.2 Instruction Set


Table 4.2.12 Unsigned Multiplication and Division Instructions (Word/Long-Word) (11 Instructions)

*1: 3 when dividing into zero, 7 when an overflow occurs, and 15 normally.


*3: 6 + (a) when dividing into zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.


*5: 6 + (a) when dividing into zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.

*6: (b) when dividing into zero or when an overflow occurs, and 2 x (b) normally.

*7: (c) when dividing into zero or when an overflow occurs, and 2 x (c) normally.

*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not 0.

*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not 0.

*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.

*11: 3 when word (AH) is zero, and 11 when word (AH) is not 0.

*12: 4 when word (ear) is zero, and 12 when word (ear) is not 0.

*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not 0.



DIVU A

DIVU A,ear

DIVU A,eam

DIVUW A,ear

DIVUW A,eam

MULU AMULU A,earMULU A,eamMULUW AMULUW A,earMULUW A,eam

1

2

2+

2

2+

122+122+

*1

*2

*3

*4

*5

*8*9*10*11*12*13

0

1

0

1

0

010010

0

0

*6

0

*7

00(b)00(c)

word (AH) / byte (AL)Quotient → byte (AL) Remainder → byte (AH)

word (A) / byte (ear)Quotient → byte (A) Remainder → byte (ear)

word (A) / byte (eam)Quotient → byte (A) Remainder → byte (ear)

long (A) / word (eam)Quotient → word (A) Remainder → word (ear)

long (A) / word (eam)Quotient → word (A) Remainder → word (eam)

byte (AH) * byte (AL) → word (A)byte (A) * byte (ear) → word (A)byte (A) * byte (eam) → word (A)word (AH) * word (AL) → Long (A)word (A) * word (ear) → Long (A)word (A) * word (eam) → Long (A)

-

-

-

-

-

------

-

-

-

-

-

------

-

-

-

-

-

------

-

-

-

-

-

------

-

-

-

-

-

------

-

-

-

-

-

------

-

-

-

-

-

------

*

*

*

*

*

------

*

*

*

*

*

------

-

-

-

-

-

------

4.2 Instruction Set

247

Table 4.2.13 Logical 1 Instructions (Byte/Word) (39 Instructions)



AND A,#imm8AND A,earAND A,eamAND ear,AAND eam,A

OR A,#imm8OR A,earOR A,eamOR ear,AOR eam,A

XOR A,#imm8XOR A,earXOR A,eamXOR ear,AXOR eam,ANOT ANOT earNOT eam

222+22+

222+22+

222+22+122+

234+(a)35+(a)

234+(a)35+(a)

234+(a)35+(a)235+(a)

01020

01020

01020020

00(b)02x(b)

00(b)02x(b)

00(b)02x(b)002x(b)

byte (A) ← (A) and imm8byte (A) ← (A) and (ear)byte (A) ← (A) and (eam)byte (ear) ← (ear) and (A)byte (eam) ← (eam) and (A)

byte (A) ← (A) or imm8byte (A) ← (A) or (ear)byte (A) ← (A) or (eam)byte (ear) ← (ear) or (A)byte (eam) ← (eam) or (A)

byte (A) ← (A) xor imm8byte (A) ← (A) xor (ear)byte (A) ← (A) xor (eam)byte (ear) ← (ear) xor (A)byte (eam) ← (eam) xor (A)byte (A) ← not (A)byte (ear) ← not (ear)byte (eam) ← not (eam)

-----

-----

--------

-----

-----

--------

-----

-----

--------

-----

-----

--------

-----

-----

--------

*****

*****

********

*****

*****

********

RRRRR

RRRRR

RRRRRRRR

-----

-----

--------

----*

----*

----*--*

ANDW AANDW A,#imm16ANDW A,earANDW A,eamANDW ear,AANDW eam,A

ORW AORW A,#imm16ORW A,earORW A,eamORW ear,AORW eam,A

XORW AXORW A,#imm16XORW A,earXORW A,eamXORW ear,AXORW eam,ANOTW ANOTW earNOTW eam

1322+22+

1322+22+

1322+22+122+

2234+(a)35+(a)

2234+(a)35+(a)

2234+(a)35+(a)235+(a)

001020

001020

001020020

000(c)02x(c)

000(c)02x(c)

000(c)02x(c)002x(c)

word (A) ← (AH) and (A)word (A) ← (A) and imm16word (A) ← (A) and (ear)word (A) ← (A) and (eam)word (ear) ← (ear) and (A)word (eam) ← (eam) and (A)

word (A) ← (AH) or (A)word (A) ← (A) or imm16word (A) ← (A) or (ear)word (A) ← (A) or (eam)word (ear) ← (ear) or (A)word (eam) ← (eam) or (A)

word (A) ← (AH) xor (A)word (A) ← (A) xor imm16word (A) ← (A) xor (ear)word (A) ← (A) xor (eam)word (ear) ← (ear) xor (A)word (eam) ← (eam) xor (A)word (A) ← not (A)word (ear) ← not (ear)word (eam) ← not (eam)

------

------

---------

------

------

---------

------

------

---------

------

------

---------

------

------

---------

******

******

*********

******

******

*********

RRRRRR

RRRRRR

RRRRRRRRR

------

------

---------

-----*

-----*

-----*--*

4.2 Instruction Set


Table 4.2.14 Logical 2 Instructions (Long-Word) (6 Instructions)

Table 4.2.15 Sign Inversion Instructions (Byte/Word) (6 Instructions)

Table 4.2.16 Normalize Instruction (Long-Word) (1 Instruction)

*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases.



ANDL A,earANDL A,eam

ORL A,earORL A,eam

XORL ¨A,earXORL A,eam

22+

22+

22+

67+(a)

67+(a)

67+(a)

20

20

20

0(d)

0(d)

0(d)

long (A) ← (A) and (ear)long (A) ← (A) and (eam)

long (A) ← (A) or (ear)long (A) ← (A) or (eam)

long (A) ← (A) xor (ear)long (A) ← (A) xor (eam)

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

**

**

**

**

**

**

RR

RR

RR

**

**

**

--

--

--


NEG A

NEG earNEG eam

1

22+

2

35+(a)

0

20

0

02x(b)

byte (A) ← 0 - (A)

byte (ear) ← 0 - (ear)byte (eam) ← 0 - (eam)

X

--

-

--

-

--

-

--

-

--

*

**

*

**

*

**

*

**

-

-*

NEGW A

NEGW earNEGW eam

1

22+

2

25+(a)

0

20

0

02x(c)

word (A) ← 0 - (A)

word (ear) ← 0 - (ear)word (eam) ← 0 - (eam)

-

--

-

--

-

--

-

--

-

--

*

**

*

**

*

**

*

**

-

-*


NRML A,R0 2 *1 1 0 long (A) ← Shift to the position where 1 was formerly placedbyte (R0) ← Number of shifts at that time

- - - - - - * - - -

4.2 Instruction Set

249

Table 4.2.17 Shift Instructions (Byte/Word/Long-Word) (18 Instructions)

*1: 6 when R0 is 0, 5 + (R0) in all other cases.

*2: 6 when R0 is 0, 6 + (R0) in all other cases.



RORC AROLC A

RORC earRORC eamROLC earROLC eam

ASR A,ROLSR A,ROLSL A,RO

22

22+22+

222

22

35+(a)35+(a)

*1*1*1

00

2020

111

00

02x(b)02x(b)

000

byte (A) ← Right rotate with carrybyte (A) ← Left rotate with carry

byte (ear) ← Right rotate with carrybyte (eam) ← Right rotate with carrybyte (ear) ← Left rotate with carrybyte (eam) ← Left rotate with carry

byte (A) ← Arithmetic right barrel shift (A,RO)byte (A) ← Logical right barrel shift (A,RO)byte (A) ← Logical left barrel shift (A,RO)

--

----

---

--

----

---

--

----

---

--

----

---

--

----

**-

**

****

***

**

****

***

--

----

---

**

****

***

--

-*-*

---

ASRW ALSRW A / SHRW ALSLW A / SHLW A

ASRW A,R0LSRW A,R0LSLW A,R0

111

222

222

*1*1*1

000

111

000

000

word (A) ← Arithmetic right shift (A,1 bit)word (A) ← Logical right shift (A,1 bit)word (A) ← Logical left shift (A,1 bit)

word (A) ← Arithmetic right barrel shift (A,RO)word (A) ← Logical right barrel shift (A,RO)word (A) ← Logical left barrel shift (A,RO)

---

---

---

---

---

---

---

---

**-

**-

*R*

***

***

***

---

---

***

***

---

---

ASRL A,ROLSRL A,ROLSLL A,RO

222

*2*2*2

111

000

long (A) ← Arithmetic right barrel shift (A,RO)long (A) ← Logical right barrel shift (A,RO)long (A) ← Logical left barrel shift (A,RO)

---

---

---

---

**-

***

***

---

***

---

4.2 Instruction Set


Table 4.2.18 Branch 1 Instructions (31 Instructions)

*1: 4 when branching, 3 when not branching.

*2: 3 × (c) + (b)

Note 1: Read (word) branch address.

Note 2: W: Save (word) into stack; R: read (word) branch address.

Note 3: Save (word) into stack.

Note 4: W: Save (long-word) into W stack; R: read (long-word) R branch address.

Note 5: Save (long-word) into stack.



BZ / BEQ relBNZ / BNE relBC / BLO relBNC / BHS relBN relBP relBV relBNV relBT relBNT relBLT relBGE relBLE relBGT relBLS relBHI relBRA rel

JMP @AJMP @addr16JMP @earJMP @eamJMPP @ear *3JMPP @eam *3JMPP addr24

CALL @ear *4CALL @eam *4CALL addr16 *5CALLV #vct4 *5CALLP @ear *6CALLP @eam *6CALLP addr24 *7

22222222222222222

1322+22+4

22+3122+4

*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1

2334+(a)56+(a)4

67+(a)671011+(a)10

00000000000000000

0010200

1000200

00000000000000000

000(c)0(d)0

(c)2x(c)(c)2x(c)2x(c)*22x(c)

Branch when (Z) = 1Branch when (Z) = 0Branch when (C) = 1Branch when (C) = 0Branch when (N) = 1Branch when (N) = 0Branch when (V) = 1Branch when (V) = 0Branch when (T) = 1Branch when (T) = 0Branch when (V) xor (N) = 1Branch when (V) xor (N) = 0Branch when ((V) xor (N)) or (Z) = 1Branch when ((V) xor (N)) or (Z) = 0Branch when (C) or (Z) = 1Branch when (C) or (Z) = 0Unconditional branching

word (PC) ← (A)word (PC) ← addr16word (PC) ← (ear)word (PC) ← (eam)word (PC) ← (ear). (PCB) ← (ear+2)word (PC) ← (eam). (PCB) ← (eam+2)word (PC) ← ad24 0-15. (PCB) ← ad24 16-23

word (PC) ← (ear)word (PC) ← (eam)word (PC) ← addr16Vector call instructionword (PC) ← (ear) 0-15. (PCB) ← (ear)16-23word (PC) ← (eam) 0-15. (PCB) ← (eam)16-23word (PC) ← addr0-15. (PCB) ← addr16-23

---------------------------------

---------------------------------

---------------------------------

---------------------------------

---------------------------------

---------------------------------

---------------------------------

---------------------------------

---------------------------------

---------------------------------

4.2 Instruction Set

251

Table 4.2.19 Branch 2 Instructions (19 Instructions)

*1: 5 when branching, 4 when not branching


*3: 7 + (a) when branching, 6 + (a) when not branching



*6: 8 + (a) when branching, 7 + (a) when not branching

Note 1: Return from stack (word)

Note 2: Return from stack (long)

Note 3: RWj+ addressing mode should not be used with the CBNE/CWBNE instructions.



CBNE A,#imm8,relCWBNE A,#imm16,rel

CBNE ear,#imm8,relCBNE eam,#imm8,relCWBNE ear,#imm16,relCWBNE eam,#imm16,rel

DBNZ ear,relDBNZ eam,rel

DWBNZ ear,relDWBNZ eam,rel

INT #vct8INT addr16INTP addr24INT9RETI

LINK #imm8

UNLINK

RET *7RETP *8

34

44+55+

33+

33+

23411

2

1

11

*1*1

*2*3*4*3

*5*6

*5*6

2016172015

6

5

46

00

1010

22

22

00000

0

0

00

00

0(b)0(c)

02x(b)

02x(c)

8x(c)6x(c)6x(c)8x(c)6x(c)

(c)

(c)

(c)(d)

Branch when byte (A) ≠ imm8Branch when word (A)≠ imm16

Branch when byte (ear)≠ imm8Branch when byte (eam)≠ imm8Branch when word (ear)≠ imm16Branch when word (eam)≠ imm16

Branch when byte (ear)=(ear)-1. (ear)≠ 0Branch when byte (eam)=(eam)-1. (eam)≠ 0

Branch when word (ear)=(ear)-1. (ear)≠ 0Branch when word (eam)=(eam)-1. (eam)≠ 0

Software interruptSoftware interruptSoftware interruptSoftware interruptRecovery from interrupt

At the entrance of function, save old frame pointers into a stack, set up new frame point-ers, reserve area for local pointers.At the exit of function, recover the old frame pointers from the stack.

Recover from the subroutine.Recover from the subroutine.

--

----

--

--

-----

-

-

--

--

----

--

--

-----

-

-

--

--

----

--

--

RRRR*

-

-

--

--

----

--

--

SSSS*

-

-

--

--

----

--

--

----*

-

-

--

**

****

**

**

----*

-

-

--

**

****

**

**

----*

-

-

--

**

****

**

**

----*

-

-

--

**

****

--

--

----*

-

-

--

--

----

-*

-*

-----

-

-

--

4.2 Instruction Set


Table 4.2.20 Other Control Instructions (Byte/Word/Long-Word) (36 Instructions)

*1: PCB, ADB, SSB, USB, and SPB: .. 1 cycleDTB, DPR: ..................................... 2 cycles

*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when RLST = 0

*3: 29 + 3 × (pop count) - 3 × (last register number to be popped), 8 when RLST = 0

*4: Pop count x (c), or push count x (c)

*5: Pop count, or push count



PUSHW APUSHW AHPUSHW PSPUSHW rlst

POPW APOPW AHPOPW PSPOPW rlst

JCTX @a

AND CCR,#imm8OR CCR,#imm8

MOV RP,#imm8MOV ILM,#imm8

MOVEA RWi,earMOVEA RWi,eamMOVEA A,earMOVEA A,eam

ADDSP #imm8ADDSP #imm16

MOV A,brglMOV brg2,A

NOPADBDTBPCBSPBNCCCMR

1112

1112

1

22

22

22+22+

23

22

1111111

444*3

334*2

14

33

22

32+(a)11+(a)

33

*11

1111111

000+&

000+&

0

00

00

1100

00

00

0000000

(c)(c)(c)*4

(c)(c)(c)*4

6x(c)

00

00

0000

00

00

0000000

word (SP) ← (SP) -2, ((SP)) ← (A)word (SP) ← (SP) -2, ((SP)) ← (AH)word (SP) ← (SP) -2, ((SP)) ← (PS)(SP) ← (SP) - 2n, ((SP)) ← (rlst)

word (A) ← ((SP)), (SP) ← (SP) + 2word (AH) ← ((SP)), (SP) ← (SP) + 2word (PS) ← ((SP)), (SP) ← (SP) + 2(rlst) ← ((SP)), (SP) ← (SP)

Context switching instruction

byte (CCR) ← (CCR) and imm8byte (CCR) ← (CCR) or imm8

byte (RP) ← imm8byte (ILM) ← imm8

word (RWi) ← earword (RWi) ← eamword (A) ← earword (A) ← eam

word (SP) ← ext(imm8)word (SP) ← imm16

byte (A) ← (brg1)byte (brg2) ← (A)

No operationPrefix code for AD space accessPrefix code for DT space accessPrefix code for PC space accessPrefix code for SP space accessPrefix code for flag unchange settingPrefix for common register banks

----

----

-

--

--

----

--

Z-

-------

----

*---

-

--

--

--**

--

*-

-------

----

--*-

*

**

--

----

--

--

-------

----

--*-

*

**

--

----

--

--

-------

----

--*-

*

**

--

----

--

--

-------

----

--*-

*

**

--

----

--

**

-------

----

--*-

*

**

--

----

--

**

-------

----

--*-

*

**

--

----

--

--

-------

----

--*-

*

**

--

----

--

--

-------

----

----

-

--

--

----

--

--

-------

4.2 Instruction Set

253

Table 4.2.21 Bit Manipulation Instructions (21 Instructions)



*3: 10 when condition is satisfied, 9 when not satisfied

*4: Undefined count

*5: Until condition is satisfied

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.


MOVB A,dir:bpMOVB A,addr16:bpMOVB A,io:bp

MOVB dir:bp,AMOVB addr16:bp,AMOVB io:bp,A

SETB dir:bpSETB addr16:bpSETB io:bp

CLRB dir:bpCLRB addr16:bpCLRB io:bp

BBC dir:bp,relBBC addr16:bp,relBBC io:bp,rel

BBS dir:bp,relBBS addr16:bp,relBBS io:bp,rel

SBBS addr16:bp,rel

WBTS io:bp

WBTC io:bp

343

343

343

343

454

454

5

3

3

554

776

777

777

*1*1*2

*1*1*2

*3

*4

*4

000

000

000

000

000

000

0

0

0

(b)(b)(b)

2x(b)2x(b)2x(b)

2x(b)2x(b)2x(b)

2x(b)2x(b)2x(b)

(b)(b)(b)

(b)(b)(b)

2x(b)

*5

*5

byte (A) ← ( dir:bp )bbyte (A) ← ( addr16:bp )bbyte (A) ← ( io:bp )b

bit ( dir:bp )b ← (A)bit ( addr16:bp )b ← (A)bit ( io:bp )b ← (A)

bit ( dir:bp )b ← 1bit ( addr16:bp )b ← 1bit ( io:bp )b ← 1

bit ( dir:bp )b ← 0bit ( addr16:bp )b ← 0bit ( io:bp )b ← 0

Branch when ( dir:bp )b = 0Branch when ( addr16:bp )b = 0Branch when ( io:bp)b = 0

Branch when ( dir:bp )b = 1Branch when ( addr16:bp )b = 1Branch when ( io:bp)b = 1

Branch when (addr16:bp) b = 1, bit = 1

Wait until (io:bp) b = 1

Wait until (io:bp) b = 0

ZZZ

---

---

---

---

---

-

-

-

***

---

---

---

---

---

-

-

-

---

---

---

---

---

---

-

-

-

---

---

---

---

---

---

-

-

-

---

---

---

---

---

---

-

-

-

***

***

---

---

---

---

-

-

-

***

***

---

---

***

***

*

-

-

---

---

---

---

---

---

-

-

-

---

---

---

---

---

---

-

-

-

---

***

***

***

---

---

*

-

-

4.2 Instruction Set


Table 4.2.22 Accumulator Manipulation Instructions (Byte/Word) (6 Instructions)

Table 4.2.23 String Instructions (10 Instructions)

*1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7n + 5 when match occurs

*2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case

*3: (b) x (RW0) + (b) × (RW0): when accessing a source and a destination in different areas, the value of item (b) should be computed separately for each.

*4: (b) × n

*5: 2 × (RW0)

*6: (c) × (RW0) + (c) × (RW0): when accessing a source and a destination in different areas, the value of item (c) should be computed separately for each.

*7: (c) × n

*8: 2 × (RW0)

m: RW0 value (counter value)

n: Loop count



SWAPSWAPW / XCHW A,TEXTEXTWZEXTZEXTW

111111

321211

000000

000000

byte (A)0-7 ←→ (A)8-15word (AH) ←→ (AL)byte signed extensionword signed extensionbyte zero extensionword zero extension

--X-Z-

-*-X-Z

------

------

------

--**RR

--****

------

------

------


MOVS / MOVSIMOVSD

SCEQ / SCEQISCEQD

FILS / FILSI

22

22

2

*2*2

*1*1

6m+6

+&+&

+&+&

+&

*3*3

*4*4

*3

byte transfer @AH+ ← @AL+, counter = RW0byte transfer @AH- ← @AL-, counter = RW0

byte search @AH+ ← AL, counter = RW0byte search @AH- ← AL, counter = RW0

byte fill @AH+ ← AL, counter = RW0

--

--

-

--

--

-

--

--

-

--

--

-

--

--

-

--

**

*

--

**

*

--

**

-

--

**

-

--

--

-

MOVSW / MOVSWIMOVSWD

SCWEQ / SCWEQISCWEQD

FILSW / FILSWI

22

22

2

*2*2

*1*1

6m+6

+)+)

+)+)

+)

*6*6

*7*7

*6

word transfer @AH+ ← @AL+, counter = RW0word transfer @AH- ← @AL-, counter = RW0

word search @AH+ ← AL, counter = RW0word search @AH- ← AL, counter = RW0

word fill @AH+ ← AL, counter = RW0

--

--

-

--

--

-

--

--

-

--

--

-

--

--

-

--

**

*

--

**

*

--

**

-

--

**

-

--

--

-

4.3 Instruction Map

255

4.3 Instruction Map

Because the F2MC-16L operation codes each consist of one or two bytes, the instruction map consists of numerous pages. The structure of the instruction map is shown below.

Fig. 4.3.1 Structure of F2MC-16L Instruction Map

Instructions that consist of only one byte (such as NOP) are concluded on the basic page. Regarding instructions that require two bytes (such as MOVS), the existence of the map for the second byte is indicated when the first byte is referenced, so it is clear that it is necessary to use the following byte to reference the map for the second byte.

Basic Page Map First byte

2-byte instructionsBit manipulation

“ea” instructions x 9 Second byteInstructionsCharacter stringmanipulation instructions

4.3 Instruction Map


The correspondence between the actual instruction code and the instruction map is shown below.

Note 1: Extended page maps are provided for bit manipulation instructions, character string manipulation instructions, two-byte instructions, and “ea” instructions; multiple-extended-page maps exist for each type of instruction.

Fig. 4.3.2 Correspondence between Actual Instructions and the Instruction Maps

Instruction code First byte Second byte operand operand

May not exist for some instructions

Length differs according to the

[Basic page map]

[Extension page map] Note 1

• • •

XY

UV

+W

+Z

instruction

4.3 Instruction Map

257

4.3

Bas

ic P

age

Map

Tab

le 4

.3.1

Bas

ic P

age

Map

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

+ 0

+ 1

+ 2

+ 3

+ 4

+ 5

+ 6

+ 7

+ 8

+ 9

+ A

+ B

+ C

+ D

+ E

+ F

NO

P

INT

9

AD

DD

C

NE

G

PC

B

DT

B

AD

B

SP

B

LIN

K

UN

LIN

K

MO

V

NE

GW

LSLW

AS

RW

LSR

W

imm

#8

CM

R

NC

C

SU

BD

C

JCT

X

EX

T

ZE

XT

SW

AP

AD

DS

P

AD

DL

SU

BL

MO

V

CM

PL

EX

TW

ZE

XT

W

SW

AP

W

AD

DS

PA

ILM

, #8

#16

AD

D

SU

B

AD

DC

CM

P

AN

D

OR

DIV

U

MU

LU

AD

DW

SU

BW

CB

NE

A,

CM

PW

AN

DW

OR

W

XO

RW

MU

LUW

A, d

ir

A, d

ir

A A

CC

R, #

8

CC

R, #

8

A A A A

#

8, r

el

A A A A A

AD

D

SU

B

SU

BC

CM

P

AN

D

OR

XO

R

NO

T

AD

DW

SU

BW

CW

BN

E

CM

PW

AN

DW

OR

W

XO

RW

NO

TW

A, #

8

A, #

8

A

A, #

8

A

, #8

A

, #8

A

, #8

A

A, #

16

A, #

16

A

, #16

, rel

A

, #16

A

, #16

A

, #16

A, #

16

A

MO

V A

, dir

MO

V

d

ir, A

MO

V

A, #

8M

OV

X

A, #

8M

OV

d

ir, #

8M

OV

X

A, d

irM

OV

W

A, S

PM

OV

W

SP

, AM

OV

W

A, d

irM

OV

W

dir,

AM

OV

W

A, #

16M

OV

L

A, #

32P

US

HW A

PU

SH

W

AH

PU

SH

W

PS

PU

SH

W r

lst

MO

V A

, io

MO

V

io, A

MO

V

A, a

ddr1

6M

OV

a

ddr

16, A

MO

V

io

, #8

MO

VX

A

, io

MO

VW

io, #

16M

OV

X

A

, add

r16

MO

VW

A

, io

MO

VW

io, A

MO

VW

A, a

ddr1

6M

OV

W

ad

dr16

, AP

OP

W A

PO

PW

AH

PO

PW

PS

PO

PW

rls

t

BR

A

re

lJM

P @

AJM

P a

ddr1

6JM

PP

a

ddr2

4C

ALL a

ddr1

6C

ALL

P

add

r24

RE

TP

RE

T

INT

#v

ct8

INT

add

r16

INT

P

add

r24

RE

TI

Bit

Str

ing

Tw

o-by

te

ope

ratio

n i

nstr

uctio

ns

inst

ruct

ions

ope

ratio

n i

nstr

uctio

ns

ea inst

ruct

ion

s (1

)

ea ea ea ea ea ea

ea ea MO

VE

A

RW

i, ea

MO

V Ri,

eaM

OV

W

R

Wi,

eaM

OV e

a, R

iM

OV

W

ea

, RW

iX

CH

Ri,

eaX

CR

W

RW

i, ea

inst

ruct

ion

s (2

)

inst

ruct

ion

s (3

)

inst

ruct

ion

s (4

)

inst

ruct

ion

s (5

)

inst

ruct

ion

s (6

)

inst

ruct

ion

s (7

)

inst

ruct

ion

s (8

)

inst

ruct

ion

s (9

)

MO

V A

, Ri

MO

V R

i, A

MO

V

R

i, #8

MO

VX

A, R

iM

OV

X A

,@R

Wi+

d8M

OV

N A

, #4

CA

LLV

#4B

Z /B

EQ re

lB

NZ

/BN

Ere

lB

C /B

LO rel

BN

C/B

HS

rel

BN

rel

BP

rel

BV

rel

BN

Vre

lB

Tre

lB

NT

rel

BLT

rel

BG

Ere

lB

LEre

lB

GT

rel

BLS

rel

BH

Ire

l

MO

VW

A, R

Wi

MO

VW

RW

i, A

MO

VW

R

Wi,

#16

MO

VW

@R

Wi+

dBM

OV

W W

i+dB

, A

A

A

R

P, #

8

A

@

A

#

8

A

, #32

A

, #32

A

A

A

A

, #32

: Ins

truc

tion

s w

ith 2

-byt

e in

stru

ctio

n co

des

(con

tinue

d o

n ex

tend

ed m

aps

)

4.3 Instruction Map


Tab

le 4

.3.2

Bit

Man

ipu

lati

on

Inst

ruct

ion

Map

(F

irst

byt

e =

6 C

H)

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

+ 0

+ 1

+ 2

+ 3

+ 4

+ 5

+ 6

+ 7

+ 8

+ 9

+ A

+ B

+C

+D

+ E

+ F

MO

VB

A

, io:

bpM

OV

B

io

:bp,

AC

LRB

io:b

pS

ET

B

io

:bp

BB

S

io:

bp, r

elB

BC

i

o:bp

, rel

WB

TS

io:b

pW

BT

C

io:

bp

MO

VB

A

, dir:

bp M

OV

B

A, a

ddr1

6:bp

MO

VB

d

ir: b

p,A

MO

VB

ad

dr16

: bp,

AC

LRB

dir:

bpC

LRB

addr

16:b

pS

ET

B

di

r:bp

SE

TB

a

ddr1

6:bp

BB

C

dir:

bp,r

elB

BC

ad1

6:bp

, rel

BB

Sad

16:

bp, r

elB

BS

d

ir:bp

, rel

SB

BS ad

16:b

p

4.3 Instruction Map

259

Tab

le 4

.3.3

Ch

arac

ter

Str

ing

Man

ipu

lati

on

Inst

ruct

ion

Map

(F

irst

byt

e =

6EH)

+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

MO

VS

IM

OV

SD

MO

VS

WI

MO

VS

WD

PC

B, P

CB

PC

B, D

TB

PC

B, A

DB

PC

B, S

PB

DT

B, P

CB

DT

B, D

TB

DT

B, A

DB

DT

B, S

PB

AD

B, P

CB

AD

B, D

TB

AD

B, A

DB

AD

B, S

PB

SP

B, P

CB

SP

B, D

TB

SP

B, A

DB

SP

B, S

PB

SC

EQ

IS

CE

QD

SC

WE

QI

SC

WE

QD

FIL

SI

FIL

SW

IP

CB

DT

B

AD

B

SP

B

PC

B

DT

B

AD

B

SP

B

PC

B

DT

B

AD

B

SP

B

PC

B

DT

B

AD

B

SP

B

PC

B

DT

B

AD

B

SP

B

PC

B

DT

B

AD

B

SP

B

4.3 Instruction Map


Tab

le 4

.3.4

Tw

o-b

yte

Inst

ruct

ion

Map

(F

irst

byt

e =

6FH)

+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

MO

V

A, D

TB

MO

V

A, A

DB

MO

V

A, S

SB

MO

V

A, U

SB

MO

V

A. D

PR

MO

V

A. @

A

MO

V

A, P

CB

RO

LC

A

LSLW

A

, R0

MO

VW

A

, @A

AS

RW

A

, R0

LSR

W

A, R

0

MO

V

DT

B, A

MO

V

AD

B, A

MO

V

SS

B, A

MO

V

US

B, A

MO

V

DP

R. A

MO

V

@

AL.

AH

MO

VX

A, @

A

RO

RC

A

LSLL

A

, R0

MO

VW

@

AL,

AH

AS

RL

A

, R0

LSR

L

A, R

0

MO

VX

A, @

RL0

+d8

MO

VX

A, @

RL1

+d8

MO

VX

A, @

RL2

+d8

MO

VX

A, @

RL3

+d8

LSL

A

, R0

NR

ML

A

, R0

AS

R

A, R

0

LSR

A

, R0

MO

V

@R

L0+

d8, A

MO

V

@R

L1+

d8, A

MO

V

@R

L2+

d8, A

MO

V

@R

L3+

d8, A

MO

V

A, @

RL0

+d8

MO

V

A, @

RL1

+d8

MO

V

A, @

RL2

+d8

MO

V A

, @R

L3+

d8

MO

VW

@R

L0+

d8, A

MO

VW

@R

L1+

d8, A

MO

VW

@R

L2+

d8, A

MO

VW

@R

L3+

d8, A

MO

VW

A, @

RL0

+d8

MO

VW

A, @

RL1

+d8

MO

VW

A, @

RL2

+d8

MO

VW

A, @

RL3

+d8

4.3 Instruction Map

261

Tab

le 4

.3.5

“ea”

Inst

ruct

ion

s 1

(Fir

st b

yte

= 7

0H)

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D

+E

+F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

AD

DL

A

, RL0

AD

DL

A

, RL0

AD

DL

A

, RL1

AD

DL

A

, RL1

AD

DL

A

, RL2

AD

DL

A

, RL2

AD

DL

A

, RL3

AD

DL

A

, RL3

AD

DL

A

, @R

W0

AD

DL

A

, @R

W1

AD

DL

A

, @R

W2

AD

DL

A

, @R

W3

AD

DL

A

, @R

W0+

AD

DL

A

, @R

W1+

AD

DL

A

, @R

W2+

AD

DL

A

, @R

W3+

AD

DL

A,

@

RW

0+d8

AD

DL

A,

@

RW

1+d8

AD

DL

A,

@

RW

2+d8

AD

DL

A,

@

RW

3+d8

AD

DL

A,

@

RW

4+d8

AD

DL

A,

@

RW

5+d8

AD

DL

A,

@

RW

6+d8

AD

DL

A,

@

RW

7+d8

AD

DL

A,

@R

W0+

d16

AD

DL

A,

@R

W1+

d16

AD

DL

A,

@R

W2+

d16

AD

DL

A,

@R

W3+

d16

AD

DL

A,

@R

W0+

RW

7A

DD

L A

,

@R

W1+

RW

7A

DD

L A

,

@

PC

+d16

AD

DL

A,

a

ddr1

6

AN

DL

A

, RL0

AN

DL

A

, RL0

AN

DL

A

, RL1

AN

DL

A

, RL1

AN

DL

A

, RL2

AN

DL

A

, RL2

AN

DL

A

, RL3

AN

DL

A

, RL3

AN

DL

A

, @R

W0

AN

DL

A

, @R

W1

AN

DL

A

, @R

W2

AN

DL

A

, @R

W3

AN

DL

A, @

RW

0+A

ND

L

A

, @R

W1+

AN

DL

A, @

RW

2+A

ND

L

A, @

RW

3+

SU

BL

A

, RL0

SU

BL

A

, RL0

SU

BL

A

, RL1

SU

BL

A

, RL1

SU

BL

A

, RL2

SU

BL

A

, RL2

SU

BL

A,R

L3S

UB

L

A

, RL3

A

, @R

W0

SU

BL

A

, @R

W1

SU

BL

A

, @R

W2

SU

BL

A

, @R

W3

SU

BL

A

, @R

W0+

SU

BL

A

, @R

W1+

SU

BL

A

, @R

W2+

SU

BL

A

, @R

W3+

SU

BL

A,

@

RW

0+d8

SU

BL

A,

@

RW

1+d8

SU

BL

A,

@

RW

2+d8

SU

BL

A,

@

RW

3+d8

SU

BL

A,

@

RW

4+d8

SU

BL

A,

@

RW

5+d8

SU

BL

A,

@

RW

6+d8

SU

BL

A,

SU

BL

A,

@R

W0+

d16

SU

BL

A,

@R

W1+

d16

SU

BL

A,

@R

W2+

d16

SU

BL

A,

@R

W3+

d16

SU

BL

A,

@R

W0+

RW

7S

UB

L A

,

@R

W1+

RW

7S

UB

L A

,

@

PC

+d1

6S

UB

L A

,

a

ddr1

6

CW

BN

E

R

W0,

#16,

rel

CW

BN

E

R

W1,

#16,

rel

CW

BN

E

R

W2,

#16,

rel

CW

BN

E

R

W3,

#16,

rel

CW

BN

E

R

W4,

#16,

rel

CW

BN

E

R

W5,

#16,

rel

CW

BN

E

R

W6,

#16,

rel

CW

BN

E

R

W7,

#16,

rel

CW

BN

E

@

RW

0,

#1

6, r

elC

WB

NE

@

RW

1,

#1

6, r

elC

WB

NE

@

RW

2,

#1

6, r

elC

WB

NE

@

RW

3,

#1

6, r

el

C

WB

NE

@R

W1+

RW

7,

#1

6, r

elC

WB

NE

@

PC

+d1

6,

#1

6, r

elC

WB

NE

add

r16,

#16,

rel

CW

BN

E

@

RW

0+d8

,

#1

6, r

elC

WB

NE

@

RW

1+d8

,

#1

6, r

elC

WB

NE

@R

W2+

d8,

#16,

rel

CW

BN

E

@R

W3+

d8,

#16,

rel

CW

BN

E

@

RW

4+d8

,

#1

6, r

elC

WB

NE

@

RW

5+d8

,

#1

6, r

elC

WB

NE

@

RW

6+d8

,

#1

6, r

elC

WB

NE

@

RW

7+d8

,

#1

6, r

elC

WB

NE

@R

W0+

d16,

#16,

rel

CW

BN

E

@R

W1,

d16

,

#1

6, r

elC

WB

NE

@R

W2+

d16,

#16,

rel

CW

BN

E

@R

W3+

d16,

#16,

rel

CW

BN

E

@R

W0+

RW

7,

#1

6, r

el

CM

PL

A,

@R

W0+

d8C

MP

L A

,

@

RW

1+d8

CM

PL

A,

@

RW

2+d8

CM

PL

A,

@

RW

3+d8

CM

PL

A,

@R

W4+

d8C

MP

L A

,

@

RW

5+d8

CM

PL

A,

@

RW

6+d8

CM

PL

A,

@

RW

7+d8

CM

PL

A,

@R

W0+

d16

CM

PL

A,

@R

W1+

d16

CM

PL

A,

@R

W2+

d16

CM

PL

A,

@R

W3+

d16

CM

PL

A,

@R

W0+

RW

7C

MP

L A

,

@R

W1+

RW

7C

MP

L A

,

@

PC

+d16

CM

PL

A,

a

ddr1

6

CM

PL

A

, RL0

CM

PL

A

, RL0

CM

PL

A

, RL1

CM

PL

A

, RL1

CM

PL

A

, RL2

CM

PL

A

, RL2

CM

PL

A

, RL3

CM

PL

A

, RL3

CM

PL

A

, @R

W0

CM

PL

A

, @R

W1

CM

PL

A

, @R

W2

CM

PL

A

, @R

W3

CM

PL

A

, @R

W0+

CM

PL

A, @

RW

1+C

MP

L

A, @

RW

2+C

MP

L

A, @

RW

3+

AN

DL

A,

@

RW

0+d8

AN

DL

A,

@

RW

1+d8

AN

DL

A,

@R

W2+

d8A

ND

L A

,

@

RW

3+d8

AN

DL

A,

@R

W4+

d8A

ND

L A

,

@

RW

5+d8

AN

DL

A,

@

RW

6+d8

AN

DL

A,

@

RW

7+d8

AN

DL

A,

@R

W0+

d16

AN

DL

A,

@R

W1+

d16

AN

DL

A,

@R

W2+

d16

AN

DL

A,

@R

W3+

d16

AN

DL

A,

@R

W0+

RW

7A

ND

L A

,

@R

W1+

RW

7A

ND

L A

,

@

PC

+d16

AN

DL

A,

add

r16

OR

L A

,

@R

W0+

d8O

RL

A,

@

RW

1+d8

OR

L A

,

@R

W2+

d8O

RL

A,

@

RW

3+d8

OR

L A

,

@R

W4+

d8O

RL

A,

@

RW

5+d8

OR

L A

,

@

RW

6+d8

OR

L A

,

@

RW

7+d8

OR

L A

,

@R

W0+

d16

OR

L A

,

@R

W1+

d16

OR

L A

,

@R

W2+

d16

OR

L A

,

@

RW

3+d1

6O

RL

A,

@R

W0+

RW

7O

RL

A,

@R

W1+

RW

7O

RL

A,

@

PC

+d1

6O

RL

A,

add

r16

XO

RL

A,

@

RW

0+d8

XO

RL

A,

@

RW

1+d8

XO

RL

A,

@R

W2+

d8X

OR

L A

,

@

RW

3+d8

XO

RL

A,

@R

W4+

d8X

OR

L A

,

@

RW

5+d8

XO

RL

A,

@

RW

6+d8

XO

RL

A,

@

RW

7+d8

XO

RL

A,

@R

W0+

d16

XO

RL

A,

@R

W1+

d16

XO

RL

A,

@R

W2+

d16

XO

RL

A,

@R

W3+

d16

XO

RL

A,

@R

W0+

RW

7X

OR

L A

,

@R

W1+

RW

7X

OR

L A

,

@

PC

+d1

6X

OR

L A

,

add

r16

OR

L

A

, RL0

OR

L

A

, RL0

OR

L

A

, RL1

OR

L

A

, RL1

OR

L

A

, RL2

OR

L

A

, RL2

OR

L

A

, RL3

OR

L

A

, RL3

OR

L

A

, @R

W0

OR

L

A

, @R

W1

OR

L

A

, @R

W2

OR

L

A

, @R

W3

OR

L

A, @

RW

0+O

RL

A, @

RW

1+O

RL

A, @

RW

2+O

RL

A, @

RW

3+

XO

RL

A

, RL0

XO

RL

A

, RL0

XO

RL

A

, RL1

XO

RL

A

, RL1

XO

RL

A

, RL2

XO

RL

A

, RL2

XO

RL

A

, RL3

XO

RL

A

, RL3

XO

RL

A

, @R

W0

XO

RL

A

, @R

W1

XO

RL

A

, @R

W2

XO

RL

A

, @R

W3

XO

RL

A, @

RW

0+X

OR

L

A, @

RW

1+X

OR

L

A, @

RW

2+X

OR

L

A, @

RW

3+

CB

NE

R

0,

#8

, rel

CB

NE

R

1,

#8

, rel

CB

NE

R

2,

#8

, rel

CB

NE

R

3,

#8

, rel

CB

NE

R

4,

#8

, rel

CB

NE

R

5,

#8

, rel

CB

NE

R

6,

#8

, rel

CB

NE

R

7,

#8

, rel

CB

NE

@R

W0,

#8, r

elC

BN

E

@R

W1,

#8, r

elC

BN

E

@R

W2,

#8, r

elC

BN

E

@R

W3,

#8, r

el

CB

NE

@R

W1+

RW

7

#8

, rel

CB

NE

@P

C+

d16,

#8, r

elC

BN

E

add

r16,

#8, r

el

CB

NE

@R

W0+

d8,

#8, r

elC

BN

E

@

RW

1+d8

,

#8

, rel

CB

NE

@

RW

2+d8

,

#8

, rel

CB

NE

@

RW

4+d8

,

#8

, rel

CB

NE

@

RW

6+d8

,

#8

, rel

CB

NE

@

RW

7+d8

,

#8

, rel

CB

NE

@R

W0+

d16,

#8, r

elC

BN

E

@R

W1+

d16,

#8, r

elC

BN

E

@R

W2+

d16,

#8, r

elC

BN

E

@R

W3+

d16,

#8, r

elC

BN

E

@R

W0+

RW

7

, #8

, rel

CB

NE

@

RW

3+d8

,

#8

, rel

CB

NE

@

RW

5+d8

,

#8

, rel

SU

BL

@R

W7+

d8

Pro

hibi

t

Pro

hibi

t

Pro

hibi

t

Pro

hibi

t

Pro

hibi

t

Pro

hibi

t

Pro

hibi

t

Pro

hibi

t

4.3 Instruction Map


Tab

le 4

.3.6

“ea”

Inst

ruct

ion

s 2

(Fir

st b

yte

= 7

1H)

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D

+E

+F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

JMP

P

@

RL0

JMP

P

@

RL0

JMP

P

@

RL1

JMP

P

@

RL1

JMP

P

@

RL2

JMP

P

@

RL2

JMP

P

@

RL3

JMP

P

@

RL3

JMP

P

@@

RW

0

JMP

P

@@

RW

1

JMP

P

@@

RW

2

JMP

P

@@

RW

3

JMP

P @

@R

W0+

JMP

P @

@R

W1+

JMP

P @

@R

W2+

JMP

P @

@R

W3+

JMP

P @

@R

W0+

d8

JMP

P @

@R

W1+

d8

JMP

P @

@R

W2+

d8

JMP

P @

@R

W3+

d8

JMP

P @

@R

W4+

d8

JMP

P @

@R

W5+

d8

JMP

P @

@R

W6+

d8

JMP

P @

@R

W7+

d8

JMP

P

@ @

RW

0+d1

6

JMP

P

@ @

RW

1+d1

6

JMP

P

@ @

RW

2+d1

6

JMP

P

@ @

RW

3+d1

6

JMP

P

@ @

RW

0+R

W7

JMP

P

@ @

RW

1+R

W7

JMP

P @

@P

C+

d16

JMP

P @

addr

16

CA

LLP

@R

L0

CA

LLP

@R

L0

CA

LLP

@R

L1

CA

LLP

@R

L1

CA

LLP

@R

L2

CA

LLP

@R

L2

CA

LLP

@R

L3

CA

LLP

@R

L3

CA

LLP

@

RW

0

CA

LLP

@

@R

W1

CA

LLP

@

@R

W2

CA

LLP

@

@R

W3

CA

LLP

@@

RW

0+

CA

LLP

@@

RW

1+

CA

LLP

@@

RW

2+

CA

LLP

@@

RW

3+

INC

L

R

L0

INC

L

R

L0

INC

L

R

L1

INC

L

R

L1

INC

L

R

L2

INC

L

R

L2

INC

L

R

L3

INC

L

R

L3

INC

L

@R

W0

INC

L

@R

W1

INC

L

@R

W2

INC

L

@R

W3

INC

L @

RW

0+

INC

L @

RW

1+

INC

L @

RW

2+

INC

L @

RW

3+

DE

CL

RL0

DE

CL

RL0

DE

CL

RL1

DE

CL

RL1

DE

CL

RL2

DE

CL

RL2

DE

CL

RL3

DE

CL

RL3

DE

CL

@

RW

0

DE

CL

@

RW

1

DE

CL

@

RW

2

DE

CL

@

RW

3

DE

CL

@R

W0+

DE

CL

@R

W1+

DE

CL

@R

W2+

DE

CL

@R

W3+

MO

VL

A, R

L0

MO

VL

A, R

L0

MO

VL

A, R

L1

MO

VL

A, R

L1

MO

VL

A, R

L2

MO

VL

A, R

L2

MO

VL

A, R

L3

MO

VL

A, R

L3

MO

VL

A

, @R

W0

MO

VL

A

, @R

W1

MO

VL

A

, @R

W2

MO

VL

A

,@ R

W3

MO

VL

A, @

RW

0+

MO

VL

A, @

RW

1+

MO

VL

A, @

RW

2+

MO

VL

A, @

RW

3+

MO

VL

RL0

, A

MO

VL

RL0

, A

MO

VL

RL1

, A

MO

VL

RL1

, A

MO

VL

RL2

, A

MO

VL

RL2

, A

MO

VL

RL3

, A

MO

VL

RL3

, A

MO

VL

@

RW

0, A

MO

VL

@

RW

1, A

MO

VL

@

RW

2, A

MO

VL

@

RW

3, A

MO

VL

@R

W0+

, A

MO

VL

@R

W1+

, A

MO

VL

@R

W2+

, A

MO

VL

@R

W3+

, A

MO

V

R

0, #

8

MO

V

R

1, #

8

MO

V

R

2, #

8

MO

V

R

3, #

8

MO

V

R

4, #

8

MO

V

R

5, #

8

MO

V

R

6, #

8

MO

V

R

7, #

8

MO

V

@R

W0,

#8

MO

V

@R

W1,

#8

MO

V

@R

W2,

#8

MO

V

@R

W3,

#8

MO

V @

RW

0+, #

8

MO

V @

RW

1+, #

8

MO

V @

RW

2+, #

8

MO

V @

RW

3+, #

8

MO

VE

A

A

, RW

0

MO

VE

A

A

, RW

1

MO

VE

A

A

, RW

2

MO

VE

A

A

, RW

3

MO

VE

A

A

, RW

4

MO

VE

A

A

, RW

5

MO

VE

A

A

, RW

6

MO

VE

A

A

, RW

7

MO

VE

A

A, @

RW

0

MO

VE

A

A, @

RW

1

MO

VE

A

A, @

RW

2

MO

VE

A

A, @

RW

3

MO

VE

A A

, @R

W0+

MO

VE

A A

, @R

W1+

MO

VE

A A

, @R

W2+

MO

VE

A A

, @R

W3+

CA

LLP

@@

RW

0+d8

CA

LLP

@@

RW

1+d8

CA

LLP

@@

RW

2+d8

CA

LLP

@@

RW

3+d8

CA

LLP

@@

RW

4+d8

CA

LLP

@@

RW

5+d8

CA

LLP

@@

RW

6+d8

CA

LLP

@@

RW

7+d8

CA

LLP

@

@R

W0+

d16

CA

LLP

@

@R

W1+

d16

CA

LLP

@

@R

W2+

d16

CA

LLP

@

@R

W3+

d16

CA

LLP

@

@R

W0+

RW

7

CA

LLP

@

@R

W1+

RW

7

CA

LLP

@@

PC

+d1

6

CA

LLP

@ad

dr16

INC

L

@R

W0+

d8

INC

L

@R

W1+

d8

INC

L

@R

W2+

d8

INC

L

@R

W3+

d8

INC

L

@R

W4+

d8

INC

L

@R

W5+

d8

INC

L

@R

W6+

d8

INC

L

@R

W7+

d8

INC

L @

RW

0+d1

6

INC

L @

RW

1+d1

6

INC

L @

RW

2+d1

6

INC

L @

RW

3+d1

6

INC

L @

RW

0+R

W7

INC

L @

RW

1+R

W7

INC

L @

PC

+d1

6

INC

L a

ddr1

6

DE

CL

@

RW

0+d8

DE

CL

@

RW

1+d8

DE

CL

@

RW

2+d8

DE

CL

@

RW

3+d8

DE

CL

@

RW

4+d8

DE

CL

@

RW

5+d8

DE

CL

@

RW

6+d8

DE

CL

@

RW

7+d8

DE

CL

@R

W0+

d16

DE

CL

@R

W1+

d16

DE

CL

@R

W2+

d16

DE

CL

@R

W3+

d16

DE

CL

@R

W0+

RW

7

DE

CL

@R

W1+

RW

7

DE

CL

@P

C+

d16

DE

CL

add

r16

MO

VL

A,

@

RW

0+d8

MO

VL

A,

@

RW

1+d8

MO

VL

A,

@

RW

2+d8

MO

VL

A,

@

RW

3+d8

MO

VL

A,

@

RW

4+d8

MO

VL

A,

@

RW

5+d8

MO

VL

A,

@

RW

6+d8

MO

VL

A,

@

RW

7+d8

MO

VL

A,

@R

W0+

d16

MO

VL

A,

@R

W1+

d16

MO

VL

A,

@R

W2+

d16

MO

VL

A,

@R

W3+

d16

MO

VL

A,

@R

W0+

RW

7

MO

VL

A,

@R

W1+

RW

7

MO

VL

A,

@

PC

+d1

6

MO

VL

A,

a

ddr1

6

MO

VL

@R

W

0+d8

, A

MO

VL

@R

W

1+d8

, A

MO

VL

@R

W

2+d8

, A

MO

VL

@R

W

3+d8

, A

MO

VL

@R

W

4+d8

, A

MO

VL

@R

W

5+d8

, A

MO

VL

@R

W

6+d8

, A

MO

VL

@R

W

7+d8

, A

MO

VL

@R

W0+

d16,

A

MO

VL

@R

W1+

d16,

A

MO

VL

@R

W2+

d16,

A

MO

VL

@R

W3+

d16,

A

MO

VL

@R

W0+

RW

7, A

MO

VL

@R

W1+

RW

7, A

MO

VL

@P

C+

d16,

A

MO

VL

add

r16,

A

MO

V @

R

W0+

d8, #

8

MO

V @

R

W1+

d8, #

8

MO

V @

R

W2+

d8, #

8

MO

V @

R

W3+

d8, #

8

MO

V @

R

W4+

d8, #

8

MO

V @

R

W5+

d8, #

8

MO

V @

R

W6+

d8, #

8

MO

V @

R

W7+

d8, #

8

MO

V @

R W

0+d1

6, #

8

MO

V @

RW

1+d1

6, #

8

MO

V @

RW

2+d1

6, #

8

MO

V @

RW

3+d1

6, #

8

MO

V @

RW

0+R

W7,

#8

MO

V @

RW

1+R

W7,

#8

MO

V @

P C

+d1

6, #

8

MO

V

add

r16,

#8

MO

VE

A A

,

@R

W0+

d8

MO

VE

A A

,

@R

W1+

d8

MO

VE

A A

,

@R

W2+

d8

MO

VE

A A

,

@R

W3+

d8

MO

VE

A A

,

@R

W4+

d8

MO

VE

A A

,

@R

W5+

d8

MO

VE

A A

,

@R

W6+

d8

MO

VE

A A

,

@R

W7+

d8

MO

VE

A A

, @

RW

0+d1

6

MO

VE

A A

, @

RW

1+d1

6

MO

VE

A A

, @

RW

2+d1

6

MO

VE

A A

, @

RW

3+d1

6

MO

VE

A A

,@

RW

0+R

W7

MO

VE

A A

,@

RW

1+R

W7

MO

VE

A A

, @

PC

+d16

MO

VE

A A

,

add

r16

4.3 Instruction Map

263

Tab

le 4

.3.7

“ea”

Inst

ruct

ion

s 3

(Fir

st b

yte

= 7

2H)

+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

RO

LC

R

0

RO

LC

R

1

RO

LC

R

2

RO

LC

R

3

RO

LC

R

4

RO

LC

R

5

RO

LC

R

6

RO

LC

R

7

RO

LC

@R

W0

RO

LC

@R

W1

RO

LC

@R

W2

RO

LC

@R

W3

RO

LC @

RW

0+

RO

LC @

RW

1+

RO

LC @

RW

2+

RO

LC @

RW

3+

RO

LC

@R

W0+

d8

RO

LC

@R

W1+

d8

RO

LC

@R

W2+

d8

RO

LC

@R

W3+

d8

RO

LC

@R

W4+

d8

RO

LC

@R

W5+

d8

RO

LC

@R

W6+

d8

RO

LC

@R

W7+

d8

RO

LC @

RW

0+d1

6

RO

LC @

RW

1+d1

6

RO

LC @

RW

2+d1

6

RO

LC @

RW

3+d1

6

RO

LC @

RW

0+R

W7

RO

LC @

RW

1+R

W7

RO

LC @

PC

+d1

6

RO

LC

add

r16

RO

RC

R0

RO

RC

R1

RO

RC

R2

RO

RC

R3

RO

RC

R4

RO

RC

R5

RO

RC

R6

RO

RC

R7

RO

RC

@

RW

0

RO

RC

@

RW

1

RO

RC

@

RW

2

RO

RC

@

RW

3

RO

RC

@R

W0+

RO

RC

@R

W1+

RO

RC

@R

W2+

RO

RC

@R

W3+

INC

R0

INC

R1

INC

R2

INC

R3

INC

R4

INC

R5

INC

R6

INC

R7

INC

@

RW

0

INC

@

RW

1

INC

@

RW

2

INC

@

RW

3

INC

@R

W0+

INC

@R

W1+

INC

@R

W2+

INC

@R

W3+

DE

C

R

0

DE

C

R

1

DE

C

R

2

DE

C

R

3

DE

C

R

4

DE

C

R

5

DE

C

R

6

DE

C

R

7

DE

C

@R

W0

DE

C

@R

W1

DE

C

@R

W2

DE

C

@R

W3

DE

C @

RW

0+

DE

C @

RW

1+

DE

C @

RW

2+

DE

C @

RW

3+

MO

V

A

, R0

MO

V

A

, R1

MO

V

A

, R2

MO

V

A

, R3

MO

V

A

, R4

MO

V

A

, R5

MO

V

A

, R6

MO

V

A

, R7

MO

V

A, @

RW

0

MO

V

A, @

RW

1

MO

V

A, @

RW

2

MO

V

A, @

RW

3

MO

V A

, @R

W0+

MO

V A

, @R

W1+

MO

V A

, @R

W2+

MO

V A

, @R

W3+

MO

V

R

0, A

MO

V

R

1, A

MO

V

R

2, A

MO

V

R

3, A

MO

V

R

4, A

MO

V

R

5, A

MO

V

R

6, A

MO

V

R

7, A

MO

V

@R

W0,

A

MO

V

@R

W1,

A

MO

V

@R

W2,

A

MO

V

@R

W3,

A

MO

V @

RW

0+, A

MO

V @

RW

1+, A

MO

V @

RW

2+, A

MO

V @

RW

3+, A

MO

VX

A, R

0

MO

VX

A, R

1

MO

VX

A, R

2

MO

VX

A, R

3

MO

VX

A, R

4

MO

VX

A, R

5

MO

VX

A, R

6

MO

VX

A, R

7

MO

VX

A

, @R

W0

MO

VX

A

, @R

W1

MO

VX

A

, @R

W2

MO

VX

A

, @R

W3

MO

VX

A, @

RW

0+

MO

VX

A, @

RW

1+

MO

VX

A, @

RW

2+

MO

VX

A, @

RW

3+

XC

H

A

, R0

XC

H

A

, R1

XC

H

A

, R2

XC

H

A

, R3

XC

H

A

, R4

XC

H

A

, R5

XC

H

A

, R6

XC

H

A

, R7

XC

H

A, @

RW

0

XC

H

A, @

RW

1

XC

H

A, @

RW

2

XC

H

A, @

RW

3

XC

H A

, @R

W0+

XC

H A

, @R

W1+

XC

H A

, @R

W2+

XC

H A

, @R

W3+

RO

RC

@

RW

0+d8

RO

RC

@

RW

1+d8

RO

RC

@

RW

2+d8

RO

RC

@

RW

3+d8

RO

RC

@

RW

4+d8

RO

RC

@

RW

5+d8

RO

RC

@

RW

6+d8

RO

RC

@

RW

7+d8

RO

RC

@R

W0+

d16

RO

RC

@R

W1+

d16

RO

RC

@R

W2+

d16

RO

RC

@R

W3+

d16

RO

RC

@R

W0+

RW

7

RO

RC

@R

W1+

RW

7

RO

RC

@P

C+d

16

RO

RC

a

ddr1

6

INC

@

RW

0+d8

INC

@

RW

1+d8

INC

@

RW

2+d8

INC

@

RW

3+d8

INC

@

RW

4+d8

INC

@

RW

5+d8

INC

@

RW

6+d8

INC

@

RW

7+d8

INC

@R

W0+

d16

INC

@R

W1+

d16

INC

@R

W2+

d16

INC

@R

W3+

d16

INC

@R

W0+

RW

7

INC

@R

W1+

RW

7

INC

@P

C+d

16

INC

add

r16

DE

C

@R

W0+

d8

DE

C

@R

W1+

d8

DE

C

@R

W2+

d8

DE

C

@R

W3+

d8

DE

C

@R

W4+

d8

DE

C

@R

W5+

d8

DE

C

@R

W6+

d8

DE

C

@R

W7+

d8

DE

C @

RW

0+d1

6

DE

C @

RW

1+d1

6

DE

C @

RW

2+d1

6

DE

C @

RW

3+d1

6

DE

C @

RW

0+R

W7

DE

C @

RW

1+R

W7

DE

C @

PC

+d1

6

DE

C a

ddr1

6

MO

V

A,

@

RW

0+d8

MO

V

A,

@

RW

1+d8

MO

V

A,

@

RW

2+d8

MO

V

A,

@

RW

3+d8

MO

V

A,

@

RW

4+d8

MO

V

A,

@

RW

5+d8

MO

V

A,

@

RW

6+d8

MO

V

A,

@

RW

7+d8

MO

V

A,

@R

W0+

d16

MO

V

A,

@R

W1+

d16

MO

V

A,

@R

W2+

d16

MO

V

A,

@R

W3+

d16

MO

V

A,

@R

W0+

RW

7

MO

V

A,

@R

W1+

RW

7

MO

V

A,

@

PC

+d1

6

MO

V

A,

a

ddr1

6

MO

V @

R

W0+

d8, A

MO

V @

R

W1+

d8, A

MO

V @

R

W2+

d8, A

MO

V @

R

W3+

d8, A

MO

V @

R

W4+

d8, A

MO

V @

R

W5+

d8, A

MO

V @

R

W6+

d8, A

MO

V @

R

W7+

d8, A

MO

V @

R W

0+d1

6, A

MO

V @

R W

1+d1

6, A

MO

V @

R W

2+d1

6, A

MO

V @

R W

3+d1

6, A

MO

V @

R W

0+R

W7,

A

MO

V @

R W

1+R

W7,

A

MO

V @

P C

+d16

, A

MO

V a

ddr1

6, A

MO

VX

A,

@

RW

0+d8

MO

VX

A,

@

RW

1+d8

MO

VX

A,

@

RW

2+d8

MO

VX

A,

@

RW

3+d8

MO

VX

A,

@

RW

4+d8

MO

VX

A,

@

RW

5+d8

MO

VX

A,

@

RW

6+d8

MO

VX

A,

@

RW

7+d8

MO

VX

A,

@R

W0+

d16

MO

VX

A,

@R

W1+

d16

MO

VX

A,

@R

W2+

d16

MO

VX

A,

@R

W3+

d16

MO

VX

A,

@R

W0+

RW

7

MO

VX

A,

@R

W1+

RW

7

MO

VX

A,

@P

C+

d16

MO

VX

A

, a

ddr1

6

XC

H A

,

@R

W0+

d8

XC

H A

,

@R

W1+

d8

XC

H A

,

@R

W2+

d8

XC

H A

,

@R

W3+

d8

XC

H A

,

@R

W4+

d8

XC

H A

,

@R

W5+

d8

XC

H A

,

@R

W6+

d8

XC

H A

,

@R

W7+

d8

XC

H A

, @

RW

0+d1

6

XC

H A

, @

RW

1+d1

6

XC

H A

, @

RW

2+d1

6

XC

H A

, @

RW

3+d1

6

XC

H A

, @

RW

0+R

W7

XC

H A

, @

RW

1+R

W7

XC

H A

, @

PC

+d1

6

XC

H A

,

add

r16

4.3 Instruction Map


Tab

le 4

.3.8

“ea”

Inst

ruct

ion

s 4

(Fir

st b

yte

= 7

3H)

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D

+E

+F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

JMP

@R

W0

JMP

@R

W1

JMP

@R

W2

JMP

@R

W3

JMP

@R

W4

JMP

@R

W5

JMP

@R

W6

JMP

@R

W7

JMP

@

@R

W0

JMP

@

@R

W1

JMP

@

@R

W2

JMP

@

@R

W3

JMP

@@

RW

0+

JMP

@@

RW

1+

JMP

@@

RW

2+

JMP

@@

RW

3+

JMP

@@

RW

0+d8

JMP

@@

RW

1+d8

JMP

@@

RW

2+d8

JMP

@@

RW

3+d8

JMP

@@

RW

4+d8

JMP

@@

RW

5+d8

JMP

@@

RW

6+d8

JMP

@@

RW

7+d8

JMP

@@

RW

0+d1

6

JMP

@@

RW

1+d1

6

JMP

@@

RW

2+d1

6

JMP

@@

RW

3+d1

6

JMP

@@

RW

0+R

W7

JMP

@@

RW

1+R

W7

JMP

@@

PC

+d16

JMP

@

addr

16

CA

LL

@

RW

0

CA

LL

@

RW

1

CA

LL

@

RW

2

CA

LL

@

RW

3

CA

LL

@

RW

4

CA

LL

@

RW

5

CA

LL

@

RW

6

CA

LL

@

RW

7

CA

LL

@@

RW

0

CA

LL

@@

RW

1

CA

LL

@@

RW

2

CA

LL

@@

RW

3

CA

LL @

@R

W0+

CA

LL @

@R

W1+

CA

LL @

@R

W2+

CA

LL @

@R

W3+

INC

W

R

W0

INC

W

R

W1

INC

W

R

W2

INC

W

R

W3

INC

W

R

W4

INC

W

R

W5

INC

W

R

W6

INC

W

R

W7

INC

W

@

RW

0

INC

W

@

RW

1

INC

W

@

RW

2

INC

W

@

RW

3

INC

W

@R

W0+

INC

W

@R

W1+

INC

W

@R

W2+

INC

W

@R

W3+

DE

CW

R

W0

DE

CW

R

W1

DE

CW

R

W2

DE

CW

R

W3

DE

CW

R

W4

DE

CW

R

W5

DE

CW

R

W6

DE

CW

R

W7

DE

CW

@R

W0

DE

CW

@R

W1

DE

CW

@R

W2

DE

CW

@R

W3

DE

CW

@

RW

0+

DE

CW

@

RW

1+

DE

CW

@

RW

2+

DE

CW

@

RW

3+

MO

VW

A, R

W0

MO

VW

A, R

W1

MO

VW

A, R

W2

MO

VW

A, R

W3

MO

VW

A, R

W4

MO

VW

A, R

W5

MO

VW

A, R

W6

MO

VW

A, R

W7

MO

VW

A

, @R

W0

MO

VW

A

, @R

W1

MO

VW

A

, @R

W2

MO

VW

A

, @R

W3

MO

VW

A, @

RW

0+

MO

VW

A, @

RW

1+

MO

VW

A

, @R

W2+

MO

VW

A, @

RW

3+

MO

VW

RW

0, A

MO

VW

RW

1, A

MO

VW

RW

2, A

MO

VW

RW

3, A

MO

VW

RW

4, A

MO

VW

RW

5, A

MO

VW

RW

6, A

MO

VW

RW

7, A

MO

VW

@

RW

0, A

MO

VW

@

RW

1. A

MO

VW

@

RW

2, A

MO

VW

@

RW

3, A

MO

VW

@R

W0+

, A

MO

VW

@R

W1+

, A

MO

VW

@R

W2+

, A

MO

VW

@R

W3+

, A

MO

VW

R

W0,

#16

MO

VW

R

W1,

#16

MO

VW

R

W2,

#16

MO

VW

R

W3,

#16

MO

VW

R

W4,

#16

MO

VW

R

W5,

#16

MO

VW

R

W6,

#16

MO

VW

R

W7,

#16

MO

VW

@R

W0,

#16

MO

VW

@R

W1,

#16

MO

VW

@R

W2,

#16

MO

VW

@R

W3,

#16

MO

VW

@

R

W0+

, #16

MO

VW

@

R

W1+

, #16

MO

VW

@

R

W2+

, #16

MO

VW

@

R

W3+

, #16

XC

HW

A, R

W0

XC

HW

A, R

W1

XC

HW

A, R

W2

XC

HW

A, R

W3

XC

HW

A, R

W4

XC

HW

A, R

W5

XC

HW

A, R

W6

XC

HW

A, R

W7

XC

HW

A

, @R

W0

XC

HW

A

, @R

W1

XC

HW

A

, @R

W2

XC

HW

A

, @R

W3

XC

HW

A, @

RW

0+

XC

HW

A, @

RW

1+

XC

HW

A, @

RW

2+

XC

HW

A, @

RW

3+

CA

LL@

@R

W0+

d8

CA

LL@

@R

W1+

d8

CA

LL@

@R

W2+

d8

CA

LL@

@R

W3+

d8

CA

LL@

@R

W4+

d8

CA

LL@

@R

W5+

d8

CA

LL@

@R

W6+

d8

CA

LL@

@R

W7+

d8

CA

LL@

@R

W0+

d16

CA

LL@

@R

W1+

d16

CA

LL@

@R

W2+

d16

CA

LL@

@R

W3+

d16

CA

LL

@@

RW

0+R

W7

CA

LL

@ @

RW

1+R

W7

CA

LL C

ALL

@

addr

16

INC

W

@

RW

0+d8

INC

W

@

RW

1+d8

INC

W

@

RW

2+d8

INC

W

@

RW

3+d8

INC

W

@

RW

4+d8

INC

W

@

RW

5+d8

INC

W

@

RW

6+d8

INC

W

@

RW

7+d8

INC

W

@R

W0+

d16

INC

W

@R

W1+

d16

INC

W

@R

W2+

d16

INC

W

@R

W3+

d16

INC

W

@R

W0+

RW

7

INC

W

@R

W1+

RW

7

INC

W

@P

C+

d16

INC

W

add

r16

DE

CW

@R

W0+

d8

DE

CW

@R

W1+

d8

DE

CW

@R

W2+

d8

DE

CW

@R

W3+

d8

DE

CW

@R

W4+

d8

DE

CW

@R

W5+

d8

DE

CW

@R

W6+

d8

DE

CW

@R

W7+

d8

DE

CW

@

RW

0+d1

6

DE

CW

@

RW

1+d1

6

DE

CW

@

RW

2+d1

6

DE

CW

@

RW

3+d1

6

DE

CW

@

RW

0+R

W7

DE

CW

@

RW

1+R

W7

DE

CW

@

PC

+d16

DE

CW

add

r16

MO

VW

A

,

@R

W0+

d8

MO

VW

A

,

@R

W1+

d8

MO

VW

A

,

@R

W2+

d8

MO

VW

A

,

@R

W3+

d8

MO

VW

A

,

@R

W4+

d8

MO

VW

A

,

@R

W5+

d8

MO

VW

A

,

@R

W6+

d8

MO

VW

A

,

@R

W7+

d8

MO

VW

A

, @

RW

0+d1

6

MO

VW

A

, @

RW

1+d1

6

MO

VW

A

, @

RW

2+d1

6

MO

VW

A

, @

RW

3+d1

6

MO

VW

A

, @

RW

0+R

W7

MO

VW

A

, @

RW

1+R

W7

MO

VW

A

,

@P

C+d

16

MO

VW

A

,

add

r16

MO

VW

@

RW

0+d8

, A

MO

VW

@

R W

1+d8

, A

MO

VW

@

R W

2+d8

, A

MO

VW

@

R W

3+d8

, A

MO

VW

@

RW

4+d8

, A

MO

VW

@

RW

5+d8

, A

MO

VW

@

RW

6+d8

, A

MO

VW

@

RW

7+d8

, A

MO

VW

@

RW

0+d1

6, A

MO

VW

@

RW

1+d1

6, A

MO

VW

@

RW

2+d1

6, A

MO

VW

@

RW

3+d1

6, A

MO

VW

@

RW

0+R

W7,

A

MO

VW

@

RW

1+R

W7,

A

MO

VW

@

PC

+d1

6, A

MO

VW

a

ddr1

6, A

MO

VW

@R

W0+

d8, #

16

MO

VW

@R

W1+

d8, #

16

MO

VW

@R

W2+

d8, #

16

MO

VW

@R

W3+

d8, #

16

MO

VW

@R

W4+

d8, #

16

MO

VW

@R

W5+

d8, #

16

MO

VW

@R

W6+

d8, #

16

MO

VW

@R

W7+

d8, #

16

MO

VW

@R

W0

+d1

6, #

16

MO

VW

@R

W1

+d1

6, #

16

MO

VW

@ R

W2

+d1

6, #

16

MO

VW

@R

W3

+d1

6, #

16

MO

VW

@R

W0

+R

W7,

#16

MO

VW

@R

W1

+R

W7,

#16

MO

VW

@P

C

+d1

6, #

16

MO

VW

a

d

dr16

, #16

XC

HW

A,

@R

W0+

d8

XC

HW

A,

@R

W1+

d8

XC

HW

A,

@R

W2+

d8

XC

HW

A,

@R

W3+

d8

XC

HW

A,

@R

W4+

d8

XC

HW

A,

@R

W5+

d8

XC

HW

A,

@R

W6+

d8

XC

HW

A,

@R

W7+

d8

XC

HW

A,

@R

W0+

d16

XC

HW

A,

@R

W1+

d16

XC

HW

A,

@R

W2+

d16

XC

HW

A,

@R

W3+

d16

XC

HW

A,

@R

W0+

RW

7

XC

HW

A,

@R

W1+

RW

7

XC

HW

A,

@P

C+

d16

XC

HW

A,

a

ddr1

6

@@

PC

+d16

4.3 Instruction Map

265

Tab

le 4

.3.9

“ea”

Inst

ruct

ion

s 5

(Fir

st b

yte

= 7

4H)

+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

AD

D

A

, R0

AD

D

A

, R1

AD

D

A

, R2

AD

D

A

, R3

AD

D

A

, R4

AD

D

A

, R5

AD

D

A

, R6

AD

D

A

, R7

AD

D

A, @

RW

0

AD

D

A, @

RW

1

AD

D

A, @

RW

2

AD

D

A, @

RW

3

AD

D A

, @R

W0+

AD

D A

, @R

W1+

AD

D A

, @R

W2+

AD

D A

, @R

W3+

AD

D

A,

@

RW

0+d8

AD

D

A,

@

RW

1+d8

AD

D

A,

@

RW

2+d8

AD

D

A,

@

RW

3+d8

AD

D

A,

@

RW

4+d8

AD

D

A,

@

RW

5+d8

AD

D

A,

@

RW

6+d8

AD

D

A,

@

RW

7+d8

AD

D

A,

@R

W0+

d16

AD

D

A,

@R

W1+

d16

AD

D

A,

@R

W2+

d16

AD

D

A,

@R

W3+

d16

AD

D

A,

@R

W0+

RW

7

AD

D

A,

@R

W1+

RW

7

AD

D

A,

@P

C+

d16

AD

D

A,

addr

16

SU

B

A

, R0

SU

B

A

, R1

SU

B

A

, R2

SU

B

A

, R3

SU

B

A

, R4

SU

B

A

, R5

SU

B

A

, R6

SU

B

A

, R7

SU

B

A, @

RW

0

SU

B

A, @

RW

1

SU

B

A, @

RW

2

SU

B

A, @

RW

3

SU

B A

, @R

W0+

SU

B A

, @R

W1+

SU

B A

, @R

W2+

SU

B A

, @R

W3+

AD

DC

A, R

0

AD

DC

A, R

1

AD

DC

A, R

2

AD

DC

A, R

3

AD

DC

A, R

4

AD

DC

A, R

5

AD

DC

A, R

6

AD

DC

A

. R7

AD

DC

A, @

RW

0

AD

DC

A, @

RW

1

AD

DC

A, @

RW

2

AD

DC

A, @

RW

3

AD

DC

A, @

RW

0+

AD

DC

A, @

RW

1+

AD

DC

A, @

RW

2+

AD

DC

A, @

RW

3+

CM

P

A, R

0

CM

P

A

, R1

CM

P

A

, R2

CM

P

A

, R3

CM

P

A

, R4

CM

P

A

, R5

CM

P

A

, R6

CM

P

A

, R7

CM

P

A, @

RW

0

CM

P

A, @

RW

1

CM

P A

, @R

W2

CM

P A

, @R

W3

CM

P A

, @R

W0+

CM

P A

, @R

W1+

CM

P A

, @R

W2+

CM

P A

, @R

W3+

AN

D

A

, R0

AN

D

A

, R1

AN

D

A

, R2

AN

D

A

, R3

AN

D

A

, R4

AN

D

A

, R5

AN

D

A

, R6

AN

D

A

, R7

AN

D

A, @

RW

0

AN

D

A, @

RW

1

AN

D

A, @

RW

2

AN

D

A, @

RW

3

AN

D A

, @R

W0+

AN

D A

, @R

W1+

AN

D A

, @R

W2+

AN

D A

, @R

W3+

OR

A, R

0

OR

A, R

1

OR

A, R

2

OR

A, R

3

OR

A, R

4

OR

A, R

5

OR

A, R

6

OR

A, R

7

OR

A

, @R

W0

OR

A

, @R

W1

OR

A

, @R

W2

OR

A

, @R

W3

OR

A, @

RW

0+

OR

A, @

RW

1+

OR

A, @

RW

2+

OR

A, @

RW

3+

XO

R

A

, R0

XO

R

A

, R1

XO

R

A

, R2

XO

R

A

, R3

XO

R

A

, R4

XO

R

A

, R5

XO

R

A

, R6

XO

R

A

, R7

XO

R

A, @

RW

0

XO

R

A, @

RW

1

XO

R

A, @

RW

2

XO

R

A, @

RW

3

XO

R A

, @R

W0+

XO

R A

, @R

W1+

XO

R A

, @R

W2+

XO

R A

, @R

W3+

DB

NZ

R

0, r

DB

NZ

R

1, r

DB

NZ

R

2, r

DB

NZ

R

3, r

DB

NZ

R

4, r

DB

NZ

R

5, r

DB

NZ

R

6, r

DB

NZ

R

7, r

DB

NZ

@

RW

0, r

DB

NZ

@

RW

1, r

DB

NZ

@

RW

2, r

DB

NZ

@

RW

3, r

DB

NZ

@R

W0+

, r

DB

NZ

@R

W1+

, r

DB

NZ

@R

W2+

, r

DB

NZ

@R

W3+

, r

SU

B

A,

@

RW

0+d8

SU

B

A,

@

RW

1+d8

SU

B

A,

@

RW

2+d8

SU

B

A,

@

RW

3+d8

SU

B

A,

@

RW

4+d8

SU

B

A,

@

RW

5+d8

SU

B

A,

@

RW

6+d8

SU

B

A,

@

RW

7+d8

SU

B

A,

@R

W0+

d16

SU

B

A,

@R

W1+

d16

SU

B

A,

@R

W2+

d16

SU

B

A,

@R

W3+

d16

SU

B

A,

@R

W0+

RW

7

SU

B

A,

@R

W1+

RW

7

SU

B

A,

SU

B

A,

add

r16

AD

DC

A,

@

RW

0+d8

AD

DC

A,

@

RW

1+d8

AD

DC

A,

@

RW

2+d8

AD

DC

A,

@

RW

3+d8

AD

DC

A,

@

RW

4+d8

AD

DC

A,

@

RW

5+d8

AD

DC

A,

@

RW

6+d8

AD

DC

A,

@

RW

7+d8

AD

DC

A,

@R

W0+

d16

AD

DC

A,

@R

W1+

d16

AD

DC

A,

@R

W2+

d16

AD

DC

A,

@R

W3+

d16

AD

DC

A,

@R

W0+

RW

7

AD

DC

A,

@R

W1+

RW

7

AD

DC

A,

@P

C+d

16

AD

DC

A,

add

r16

CM

P

A

,

@R

W0+

d8

CM

P

A

,

@R

W1+

d8

CM

P

A

,

@R

W2+

d8

CM

P

A

,

@R

W3+

d8

CM

P

A

,

@R

W4+

d8

CM

P

A

,

@R

W5+

d8

CM

P

A

,

@R

W6+

d8

CM

P

A

,

@R

W7+

d8

CM

P

A

, @

RW

0+d1

6

CM

P

A

, @

RW

1+d1

6

CM

P

A

, @

RW

2+d1

6

CM

P

A

, @

RW

3+d1

6

CM

P

A

, @

RW

0+R

W7

CM

P

A

, @

RW

1+R

W7

CM

P

A

, @

PC

+d1

6

CM

P

A

, a

ddr1

6

AN

D

A,

@

RW

0+d8

AN

D

A,

@

RW

1+d8

AN

D

A,

@

RW

2+d8

AN

D

A,

@

RW

3+d8

AN

D

A,

@

RW

4+d8

AN

D

A,

@

RW

5+d8

AN

D

A,

@

RW

6+d8

AN

D

A,

@

RW

7+d8

AN

D

A,

@R

W0+

d16

AN

D

A,

@R

W1+

d16

AN

D

A,

@R

W2+

d16

AN

D

A,

@R

W3+

d16

AN

D

A,

@R

W0+

RW

7

AN

D

A,

@R

W1+

RW

7

AN

D

A,

@

PC

+d1

6

AN

D

A,

a

ddr1

6

OR

A

,

@R

W0+

d8

OR

A

,

@R

W1+

d8

OR

A

,

@R

W2+

d8

OR

A

,

@R

W3+

d8

OR

A

,

@R

W4+

d8

OR

A

,

@R

W5+

d8

OR

A

,

@R

W6+

d8

OR

A

,

@R

W7+

d8

OR

A

, @

RW

0+d1

6

OR

A

, @

RW

1+d1

6

OR

A

, @

RW

2+d1

6

OR

A

, @

RW

3+d1

6

OR

A

, @

RW

0+R

W7

OR

A

, @

RW

1+R

W7

OR

A

, @

PC

+d1

6

OR

A

, a

ddr1

6

XO

R

A

,

@R

W0+

d8

XO

R

A

,

@R

W1+

d8

XO

R

A

,

@R

W2+

d8

XO

R

A

,

@R

W3+

d8

XO

R

A

,

@R

W4+

d8

XO

R

A

,

@R

W5+

d8

XO

R

A

,

@R

W6+

d8

XO

R

A

,

@R

W7+

d8

XO

R

A

, @

RW

0+d1

6

XO

R

A

, @

RW

1+d1

6

XO

R

A

, @

RW

2+d1

6

XO

R

A

, @

RW

3+d1

6

XO

R

A

,@

RW

0+R

W7

XO

R

A

,@

RW

1+R

W7

XO

R

A

, @

PC

+d1

6

XO

R

A,

add

r16

DB

NZ

@ R

W0+

d8, r

DB

NZ

@ R

W1+

d8, r

DB

NZ

@ R

W2+

d8, r

DB

NZ

@ R

W3+

d8, r

DB

NZ

@ R

W4+

d8, r

DB

NZ

@ R

W5+

d8, r

DB

NZ

@ R

W6+

d8, r

DB

NZ

@ R

W7+

d8, r

DB

NZ

RW

0+d1

6, r

DB

NZ

RW

1+d1

6, r

DB

NZ

RW

2+d1

6, r

DB

NZ

RW

3+d1

6, r

DB

NZ

RW

0+R

W7,

r

DB

NZ

RW

1+R

W7,

r

DB

NZ

@ P

C+

d16,

r

DB

NZ

@ a

ddr1

6, r

@P

C+d

16

4.3 Instruction Map


Tab

le 4

.3.1

0“e

a” In

stru

ctio

ns

6 (F

irst

byt

e =

75H)

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D

+E

+F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

AD

D

R

0, A

AD

D

R

1, A

AD

D

R

2, A

AD

D

R

3, A

AD

D

R

4, A

AD

D

R

5, A

AD

D

R

6, A

AD

D

R

7, A

AD

D

@R

W0,

A

AD

D

@R

W1,

A

AD

D

@R

W2,

A

AD

D

@R

W3,

A

AD

D @

RW

0+, A

AD

D @

RW

1+, A

AD

D @

RW

2+, A

AD

D @

RW

3+, A

W0+

d8, A

W1+

d8, A

W2+

d8, A

W3+

d8, A

W4+

d8, A

W5+

d8, A

W6+

d8, A

W7+

d8, A

W0+

d16,

A

W1+

d16,

A

RW

2+d1

6, A

RW

3+d1

6, A

AD

D

@R

W0+

RW

7, A

AD

D

@R

W1+

RW

7, A

C+d

16, A

AD

D

a

ddr1

6, A

SU

B

R

0, A

SU

B

R

1, A

SU

B

R

2, A

SU

B

R

3, A

SU

B

R

4, A

SU

B

R

5, A

SU

B

R

6, A

SU

B

R

7, A

SU

B

@R

W0,

A

SU

B

@R

W1,

A

SU

B

@R

W2,

A

SU

B

@R

W3,

A

SU

B @

RW

0+, A

SU

B @

RW

1+, A

SU

B @

RW

2+, A

SU

B @

RW

3+, A

SU

BC

A, R

0

SU

BC

A, R

1

SU

BC

A, R

2

SU

BC

A, R

3

SU

BC

A, R

4

SU

BC

A, R

5

SU

BC

A, R

6

SU

BC

A, R

7

SU

BC

A, @

RW

0

SU

BC

A

, @R

W1

SU

BC

A

, @R

W2

SU

BC

A, @

RW

3

SU

BC

A, @

RW

0+

SU

BC

A, @

RW

1+

SU

BC

A, @

RW

2+

SU

BC

A, @

RW

3+

NE

G

R0

NE

G

R1

NE

G

R2

NE

G

R3

NE

G

R4

NE

G

R5

NE

G

R6

NE

G

R7

NE

G

@

RW

0

NE

G

@

RW

1

NE

G

@

RW

2

NE

G

@

RW

3

NE

G

@R

W0+

NE

G

@R

W1+

NE

G

@R

W2+

NE

G

@R

W3+

AN

D

R

0, A

AN

D

R

1, A

AN

D

R

2, A

AN

D

R

3, A

AN

D

R

4, A

AN

D

R

5, A

AN

D

R

6, A

AN

D

R

7, A

AN

D @

RW

0, A

AN

D @

RW

1, A

AN

D @

RW

2, A

AN

D @

RW

3, A

AN

D@

RW

0+, A

AN

D@

RW

1+, A

AN

D@

RW

2+, A

AN

D@

RW

3+, A

OR

R0,

A

OR

R1,

A

OR

R2,

A

OR

R3,

A

OR

R4,

A

OR

R5,

A

OR

R6,

A

OR

R7,

A

OR

@

RW

0, A

OR

@

RW

1. A

OR

@

RW

2, A

OR

@

RW

3, A

OR

@R

W0+

, A

OR

@R

W1+

, A

OR

@R

W2+

, A

OR

@R

W3+

, A

XO

R

R0,

A

XO

R

R1,

A

XO

R

R2,

A

XO

R

R3,

A

XO

R

R4,

A

XO

R

R5,

A

XO

R

R6,

A

XO

R

R7,

A

XO

R

@R

W0,

A

XO

R

@R

W1,

A

XO

R

@R

W2,

A

XO

R

@R

W3,

A

XO

R

@

RW

0+, A

XO

R

@

RW

1+, A

XO

R

@

RW

2+, A

XO

R

@

RW

3+, A

NO

T

R

0

NO

T

R

1

NO

T

R

2

NO

T

R

3

NO

T

R

4

NO

T

R

5

NO

T

R

6

NO

T

R

7

NO

T

@R

W0

NO

T @

RW

1

NO

T

@R

W2

NO

T

@R

W3

NO

T @

RW

0+

NO

T @

RW

1+

NO

T @

RW

2+

NO

T @

RW

3+

SU

B

@

R

W0+

d8, A

SU

B

@

R

W1+

d8, A

SU

B

@

R

W2+

d8, A

SU

B

@

R

W3+

d8, A

SU

B

@

R

W4+

d8, A

SU

B

@

R

W5+

d8, A

SU

B

@

R

W6+

d8, A

SU

B

@

R

W7+

d8, A

SU

B

@

R W

0+d1

6, A

SU

B

@

R W

1+d1

6, A

SU

B

@

R W

2+d1

6, A

SU

B

@

R W

3+d1

6, A

SU

B

@

R

W

0+R

W7,

A

SU

B

@

R

W

1+R

W7,

A

SU

B

@

P S

UB

ad

dr16

, A

SU

BC

A,

@R

W0+

d8

SU

BC

A,

@R

W1+

d8

SU

BC

A,

@R

W2+

d8

SU

BC

A,

@R

W3+

d8

SU

BC

A,

@R

W4+

d8

SU

BC

A,

@R

W5+

d8

SU

BC

A,

@R

W6+

d8

SU

BC

A,

@R

W7+

d8

SU

BC

A,

@

RW

0+d1

6

SU

BC

A,

@

RW

1+d1

6

SU

BC

A,

@

RW

2+d1

6

SU

BC

A,

@

RW

3+d1

6

SU

BC

A,

@

RW

0+R

W7

SU

BC

A,

@

RW

1+R

W7

SU

BC

A,

@

PC

+d1

6

SU

BC

A,

a

ddr1

6

NE

G

@

RW

0+d8

NE

G

@

RW

1+d8

NE

G

@

RW

2+d8

NE

G

@

RW

3+d8

NE

G

@

RW

4+d8

NE

G

@

RW

5+d8

NE

G

@

RW

6+d8

NE

G

@

RW

7+d8

NE

G

@R

W0+

d16

NE

G

@R

W1+

d16

NE

G

@R

W2+

d16

NE

G

@R

W3+

d16

NE

G

@R

W0+

RW

7

NE

G

@R

W1+

RW

7

NE

G

@P

C+

d16

NE

G a

ddr1

6

AN

D

@

R

W0+

d8, A

AN

D

@

R

W1+

d8, A

AN

D

@

R

W2+

d8, A

AN

D

@

R

W3+

d8, A

AN

D

@

R

W4+

d8, A

AN

D

@

R

W5+

d8, A

AN

D

@

R

W6+

d8, A

AN

D

@

R

W7+

d8, A

AN

D

@

R W

0+d1

6, A

AN

D

@

R W

1+d1

6, A

AN

D

@

R W

2+d1

6, A

AN

D

@

R W

3+d1

6, A

AN

D

@

R W

0+R

W7,

A

AN

D

@

R W

1+R

W7,

A

AN

D

@

P

C+

d16,

A

AN

D

a

ddr1

6, A

OR

@

RW

0+d8

, A

OR

@

RW

1+d8

, A

OR

@

RW

2+d8

, A

OR

@

RW

3+d8

, A

OR

@

RW

4+d8

, A

OR

@

RW

5+d8

, A

OR

@

RW

6+d8

, A

OR

@

RW

7+d8

, A

OR

@

RW

0+d1

6, A

OR

@

RW

1+d1

6, A

OR

@

RW

2+d1

6, A

OR

@

RW

3+d1

6, A

OR

@

R

W0+

RW

7, A

OR

@

R

W1+

RW

7, A

OR

@P

C+

d16,

A

OR

add

r16,

A

W0+

d8, A

W1+

d8, A

W2+

d8, A

W3+

d8, A

W4+

d8, A

W5+

d8, A

W6+

d8, A

W7+

d8, A

W0+

d16,

A

W1+

d16,

A

W2+

d16,

A

W3+

d16,

A

XO

R

@

R

W0+

RW

7, A

XO

R

@

R

W1+

RW

7, A

C+

d16,

A

XO

R a

ddr1

6, A

NO

T

@R

W0+

d8

NO

T

@R

W1+

d8

NO

T

@R

W2+

d8

NO

T

@R

W3+

d8

NO

T

@R

W4+

d8

NO

T

@R

W5+

d8

NO

T

@R

W6+

d8

NO

T

@R

W7+

d8

NO

T @

RW

0+d1

6

NO

T @

RW

1+d1

6

NO

T @

RW

2+d1

6

NO

T @

RW

3+d1

6

NO

T @

RW

0+R

W7

NO

T @

RW

1+R

W7

NO

T @

PC

+d16

NO

T

add

r16

C+

d16,

A

AD

D

@R

AD

D

@R

AD

D

@R

AD

D

@R

AD

D

@R

AD

D

@R

AD

D

@R

AD

D

@R

AD

D

@R

AD

D

@R

AD

D

@R

AD

D

@R

AD

D

@P

XO

R

@

R

XO

R

@

R

XO

R

@

R

XO

R

@

R

XO

R

@

R

XO

R

@

R

XO

R

@

R

XO

R

@

R

XO

R

@

R

XO

R

@

R

XO

R

@

R

XO

R

@

R

XO

R

@

P

4.3 Instruction Map

267

Tab

le 4

.3.1

1“e

a” In

stru

ctio

ns

7 (F

irst

byt

e =

76H)

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D

+E

+F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

AD

DW

A, R

W0

AD

DW

A, R

W1

AD

DW

A, R

W2

AD

DW

A, R

W3

AD

DW

A, R

W4

AD

DW

A, R

W5

AD

DW

A, R

W6

AD

DW

A, R

W7

AD

DW

A

, @R

W0

AD

DW

A

, @R

W1

AD

DW

A

, @R

W2

AD

DW

A

, @R

W3

AD

DW

A, @

RW

0+

AD

DW

A, @

RW

1+

AD

DW

A, @

RW

2+

AD

DW

A, @

RW

3+

AD

DW

A,

@

RW

0+d8

AD

DW

A,

@

RW

1+d8

AD

DW

A,

@

RW

2+d8

AD

DW

A,

@

RW

3+d8

AD

DW

A,

@

RW

4+d8

AD

DW

A,

@

RW

5+d8

AD

DW

A,

@

RW

6+d8

AD

DW

A,

@

RW

7+d8

AD

DW

A,

@R

W0+

d16

AD

DW

A,

@R

W1+

d16

AD

DW

A,

@R

W2+

d16

AD

DW

A,

@R

W3+

d16

AD

DW

A,

@R

W0+

RW

7

AD

DW

A,

@R

W1+

RW

7

AD

DW

A,

@P

C+

d16

AD

DW

A,

addr

16

SU

BW

A, R

W0

SU

BW

A, R

W1

SU

BW

A, R

W2

SU

BW

A, R

W3

SU

BW

A, R

W4

SU

BW

A, R

W5

SU

BW

A, R

W6

SU

BW

A, R

W7

SU

BW

A

, @R

W0

SU

BW

A

, @R

W1

SU

BW

A

, @R

W2

SU

BW

A

, @R

W3

SU

BW

A, @

RW

0+

SU

BW

A, @

RW

1+

SU

BW

A, @

RW

2+

SU

BW

A, @

RW

3+

AD

DC

W

A

, RW

0

AD

DC

W

A

, RW

1

AD

DC

W

A

, RW

2

AD

DC

W

A

, RW

3

AD

DC

W

A

, RW

4

AD

DC

W

A

, RW

5

AD

DC

W

A

, RW

6

AD

DC

W

A,

RW

7

AD

DC

W

A, @

RW

0

AD

DC

W

A, @

RW

1

AD

DC

W

A, @

RW

2

AD

DC

W

A, @

RW

3

AD

DC

W A

, @R

W0+

AD

DC

W A

, @R

W1+

AD

DC

W A

, @R

W2+

AD

DC

W A

, @R

W3+

CM

PW

A

, RW

0

CM

PW

A, R

W1

CM

PW

A, R

W2

CM

PW

A, R

W3

CM

PW

A, R

W4

CM

PW

A, R

W5

CM

PW

A, R

W6

CM

PW

A, R

W7

CM

PW

A

, @R

W0

CM

PW

A

, @R

W1

CM

PW

A

, @R

W2

CM

PW

A

, @R

W3

CM

PW

A, @

RW

0+

CM

PW

A, @

RW

1+

CM

PW

A, @

RW

2+

CM

PW

A, @

RW

3+

AN

DW

A, R

W0

AN

DW

A, R

W1

AN

DW

A, R

W2

AN

DW

A, R

W3

AN

DW

A, R

W4

AN

DW

A, R

W5

AN

DW

A, R

W6

AN

DW

A, R

W7

AN

DW

A

, @R

W0

AN

DW

A

, @R

W1

AN

DW

A

, @R

W2

AN

DW

A

, @R

W3

AN

DW

A, @

RW

0+

AN

DW

A, @

RW

1+

AN

DW

A, @

RW

2+

AN

DW

A, @

RW

3+

OR

W

A

, RW

0

OR

W

A

, RW

1

OR

W

A

, RW

2

OR

W

A

, RW

3

OR

W

A

, RW

4

OR

W

A

, RW

5

OR

W

A

, RW

6

OR

W

A

, RW

7

OR

W

A, @

RW

0

OR

W

A, @

RW

1

OR

W

A, @

RW

2

OR

W

A, @

RW

3

OR

W A

, @R

W0+

OR

W A

, @R

W1+

OR

W A

, @R

W2+

OR

W A

, @R

W3+

XO

RW

A, R

W0

XO

RW

A, R

W1

XO

RW

A, R

W2

XO

RW

A, R

W3

XO

RW

A, R

W4

XO

RW

A, R

W5

XO

RW

A, R

W6

XO

RW

A, R

W7

XO

RW

A

, @R

W0

XO

RW

A

, @R

W1

XO

RW

A

, @R

W2

XO

RW

A

, @R

W3

XO

RW

A, @

RW

0+

XO

RW

A, @

RW

1+

XO

RW

A, @

RW

2+

XO

RW

A, @

RW

3+

DW

BN

Z

RW

0, r

DW

BN

Z

RW

1, r

DW

BN

Z

RW

2, r

DW

BN

Z

RW

3, r

DW

BN

Z

RW

4, r

DW

BN

Z

RW

5, r

DW

BN

Z

RW

6, r

DW

BN

Z

RW

7, r

DW

BN

Z

@R

W0,

r

DW

BN

Z

@R

W1,

r

DW

BN

Z

@R

W2,

r

DW

BN

Z

@R

W3,

r

DW

BN

Z

@R

W0+

, r

DW

BN

Z

@R

W1+

, r

DW

BN

Z

@R

W2+

, r

DW

BN

Z

@R

W3+

, r

SU

BW

A,

@

RW

0+d8

SU

BW

A,

@

RW

1+d8

SU

BW

A,

@

RW

2+d8

SU

BW

A,

@

RW

3+d8

SU

BW

A,

@

RW

4+d8

SU

BW

A,

@

RW

5+d8

SU

BW

A,

@

RW

6+d8

SU

BW

A,

@

RW

7+d8

SU

BW

A,

@R

W0+

d16

SU

BW

A,

@R

W1+

d16

SU

BW

A,

@R

W2+

d16

SU

BW

A,

@R

W3+

d16

SU

BW

A,

@R

W0+

RW

7

SU

BW

A,

@R

W1+

RW

7

SU

BW

A,

SU

BW

A,

add

r16

AD

DC

W

A,

@

RW

0+d8

AD

DC

W

A,

@

RW

1+d8

AD

DC

W

A,

@

RW

2+d8

AD

DC

W

A,

@

RW

3+d8

AD

DC

W

A,

@

RW

4+d8

AD

DC

W

A,

@

RW

5+d8

AD

DC

W

A,

@

RW

6+d8

AD

DC

W

A,

@

RW

7+d8

AD

DC

W

A,

@R

W0+

d16

AD

DC

W

A,

@R

W1+

d16

AD

DC

W

A,

@R

W2+

d16

AD

DC

W

A,

@R

W3+

d16

AD

DC

W

A,

@R

W0+

RW

7

AD

DC

W

A,

@R

W1+

RW

7

AD

DC

W

A,

@P

C+

d16

AD

DC

W

A,

add

r16

CM

PW

A,

@

RW

0+d8

CM

PW

A,

@

RW

1+d8

CM

PW

A,

@

RW

2+d8

CM

PW

A,

@

RW

3+d8

CM

PW

A,

@

RW

4+d8

CM

PW

A,

@

RW

5+d8

CM

PW

A,

@

RW

6+d8

CM

PW

A,

@

RW

7+d8

CM

PW

A,

@R

W0+

d16

CM

PW

A,

@R

W1+

d16

CM

PW

A,

@R

W2+

d16

CM

PW

A,

@R

W3+

d16

CM

PW

A,

@R

W0+

RW

7

CM

PW

A,

@R

W1+

RW

7

CM

PW

A,

@P

C+

d16

CM

PW

A,

add

r16

AN

DW

A,

@

RW

0+d8

AN

DW

A,

@

RW

1+d8

AN

DW

A,

@

RW

2+d8

AN

DW

A,

@

RW

3+d8

AN

DW

A,

@

RW

4+d8

AN

DW

A,

@

RW

5+d8

AN

DW

A,

@

RW

6+d8

AN

DW

A,

@

RW

7+d8

AN

DW

A,

@R

W0+

d16

AN

DW

A,

@R

W1+

d16

AN

DW

A,

@R

W2+

d16

AN

DW

A,

@R

W3+

d16

AN

DW

A,

@R

W0+

RW

7

AN

DW

A,

@R

W1+

RW

7

AN

DW

A,

@

PC

+d1

6

AN

DW

A,

a

ddr1

6

OR

W

A,

@

RW

0+d8

OR

W

A,

@

RW

1+d8

OR

W

A,

@

RW

2+d8

OR

W

A,

@

RW

3+d8

OR

W

A,

@

RW

4+d8

OR

W

A,

@

RW

5+d8

OR

W

A,

@

RW

6+d8

OR

W

A,

@

RW

7+d8

OR

W

A,

@R

W0+

d16

OR

W

A,

@R

W1+

d16

OR

W

A,

@R

W2+

d16

OR

W

A,

@R

W3+

d16

OR

W

A,

@R

W0+

RW

7

OR

W

A,

@R

W1+

RW

7

OR

W

A,

@ P

C+

d16

OR

W

A,

add

r16

XO

RW

A,

@

RW

0+d8

XO

RW

A,

@

RW

1+d8

XO

RW

A,

@

RW

2+d8

XO

RW

A,

@

RW

3+d8

XO

RW

A,

@

RW

4+d8

XO

RW

A,

@

RW

5+d8

XO

RW

A,

@

RW

6+d8

XO

RW

A,

@

RW

7+d8

XO

RW

A,

@R

W0+

d16

XO

RW

A,

@R

W1+

d16

XO

RW

A,

@R

W2+

d16

XO

RW

A,

@R

W3+

d16

XO

RW

A,

@R

W0+

RW

7

XO

RW

A,

@R

W1+

RW

7

XO

RW

A,

@P

C+

d16

XO

RW

A,

add

r16

DW

BN

Z

@ R

W0+

d8, r

DW

BN

Z

@ R

W1+

d8, r

DW

BN

Z

@ R

W2+

d8, r

DW

BN

Z

@ R

W3+

d8, r

DW

BN

Z

@ R

W4+

d8, r

DW

BN

Z

@ R

W5+

d8, r

DW

BN

Z

@ R

W6+

d8, r

DW

BN

Z

@ R

W7+

d8, r

DW

BN

Z @

R W

0+d1

6, r

DW

BN

Z @

RW

1+d1

6, r

DW

BN

Z @

RW

2+d1

6, r

DW

BN

Z @

RW

3+d1

6, r

DW

BN

Z @

RW

0+R

W7,

r

DW

BN

Z @

RW

1+R

W7,

r

DW

BN

Z

@P

C+d

16, r

DW

BN

Z

add

r16,

r

@P

C+d

16

4.3 Instruction Map


Tab

le 4

.3.1

2“e

a” In

stru

ctio

ns

8 (F

irst

byt

e =

77H)

+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

AD

DW

RW

0, A

AD

DW

RW

1, A

AD

DW

RW

2, A

AD

DW

RW

3, A

AD

DW

RW

4, A

AD

DW

RW

5, A

AD

DW

RW

6, A

AD

DW

RW

7, A

AD

DW

@

RW

0, A

AD

DW

@

RW

1, A

AD

DW

@

RW

2, A

AD

DW

@

RW

3, A

AD

DW

@R

W0+

, A

AD

DW

@R

W1+

, A

AD

DW

@R

W2+

, A

AD

DW

@R

W3+

, A

AD

DW

@

R W

0+d8

, A

AD

DW

@

R

W1+

d8, A

AD

DW

@

R

W2+

d8, A

AD

DW

@

R

W3+

d8, A

AD

DW

@

R W

4+d8

, A

AD

DW

@

R

W5+

d8, A

AD

DW

@

R W

6+d8

, A

AD

DW

@

R

W7+

d8, A

AD

DW

@

R W

0+d1

6, A

AD

DW

@

R W

1+d1

6, A

AD

DW

@

R W

2+d1

6, A

AD

DW

@

R W

3+d1

6, A

AD

DW

@

R W

0+R

W7

AD

DW

@

R W

1+R

W7

AD

DW

@

P C

+d1

6, A

AD

DW

a

ddr1

6, A

SU

BW

RW

0, A

SU

BW

RW

1, A

SU

BW

RW

2, A

SU

BW

RW

3, A

SU

BW

RW

4, A

SU

BW

RW

5, A

SU

BW

RW

6, A

SU

BW

RW

7, A

SU

BW

@R

W0,

A

SU

BW

@R

W1,

A

SU

BW

@R

W2,

A

SU

BW

@

RW

3, A

SU

BW

@R

W0+

, A

SU

BW

@R

W1+

, A

SU

BW

@R

W2+

, A

SU

BW

@R

W3+

, A

SU

BC

W

A

, RW

0

SU

BC

W

A

, RW

1

SU

BC

W

A

, RW

2

SU

BC

W

A

, RW

3

SU

BC

W

A

, RW

4

SU

BC

W

A

, RW

5

SU

BC

W

A

, RW

6

SU

BC

W

A

,RW

7

SU

BC

W A

, @R

W0

SU

BC

W A

, @R

W1

SU

BC

W A

, @R

W2

SU

BC

W A

, @R

W3

SU

BC

W A

, @R

W0+

SU

BC

W A

, @R

W1+

SU

BC

W A

, @R

W2+

SU

BC

W A

, @R

W3+

NE

GW

RW

0

NE

GW

R

W1

NE

GW

R

W2

NE

GW

R

W3

NE

GW

R

W4

NE

GW

R

W5

NE

GW

R

W6

NE

GW

R

W7

NE

GW

@R

W0

NE

GW

@R

W1

NE

GW

@R

W2

NE

GW

@R

W3

NE

GW

@

RW

0+

NE

GW

@

RW

1+

NE

GW

@

RW

2+

NE

GW

@

RW

3+

AN

DW

RW

0, A

AN

DW

RW

1, A

AN

DW

RW

2, A

AN

DW

RW

3, A

AN

DW

RW

4, A

AN

DW

RW

5, A

AN

DW

RW

6, A

AN

DW

RW

7, A

AN

DW

@

RW

0, A

AN

DW

@R

W1,

A

AN

DW

@R

W2,

A

AN

DW

@R

W3,

A

AN

DW

@R

W0+

, A

AN

DW

@R

W1+

, A

AN

DW

@R

W2+

, A

AN

DW

@R

W3+

, A

OR

W

R

W0,

A

OR

W

R

W1,

A

OW

R

R

W2,

A

OR

W

R

W3,

A

OR

W

R

W4,

A

OR

W

R

W5,

A

OR

W

R

W6,

A

OR

W

R

W7,

A

OR

W

@R

W0,

A

OR

W

@R

W1,

A

OR

W

@R

W2,

A

OR

W

@R

W3,

A

OR

W @

RW

0+, A

OR

W @

RW

1+, A

OR

W @

RW

2+, A

OR

W @

RW

3+, A

XO

RW

RW

0, A

XO

RW

RW

1, A

XO

RW

RW

2, A

XO

RW

RW

3, A

XO

RW

RW

4, A

XO

RW

RW

5, A

XO

RW

RW

6, A

XO

RW

RW

7, A

XO

RW

@

RW

0, A

XO

RW

@

RW

1, A

XO

RW

@

RW

2, A

XO

RW

@

RW

3, A

XO

RW

@R

W0+

, A

XO

RW

@R

W1+

, A

XO

RW

@R

W2+

, A

XO

RW

@R

W3+

, A

NO

TW

R

W0

NO

TW

R

W1

NO

TW

R

W2

NO

TW

R

W3

NO

TW

R

W4

NO

TW

R

W5

NO

TW

R

W6

NO

TW

R

W7

NO

TW

@

RW

0

NO

TW

@

RW

1

NO

TW

@

RW

2

NO

TW

@

RW

3

NO

TW

@

RW

0+

NO

TW

@

RW

1+

NO

TW

@

RW

2+

NO

TW

@

RW

3+

SU

BW

@

R

W0+

d8, A

SU

BW

@

R

W1+

d8, A

SU

BW

@

R

W2+

d8, A

SU

BW

@

R

W3+

d8, A

SU

BW

@

R

W4+

d8, A

SU

BW

@

R

W5+

d8, A

SU

BW

@

R

W6+

d8, A

SU

BW

@

R

W7+

d8, A

SU

BW

@

R W

0+d1

6, A

SU

BW

@

R W

1+d1

6, A

SU

BW

@

R W

2+d1

6, A

SU

BW

@

R W

3+d1

6, A

SU

BW

@

R W

0+R

W7,

A

SU

BW

@

R W

1+R

W7,

A

SU

BW

S

UB

W

ad

dr16

, A

SU

BC

W

A,

@

RW

0+d8

SU

BC

W

A,

@

RW

1+d8

SU

BC

W

A,

@

RW

2+d8

SU

BC

W

A,

@

RW

3+d8

SU

BC

W

A,

@

RW

4+d8

SU

BC

W

A,

@

RW

5+d8

SU

BC

W

A,

@

RW

6+d8

SU

BC

W

A,

@

RW

7+d8

SU

BC

W

A,

@R

W0+

d16

SU

BC

W

A,

@R

W1+

d16

SU

BC

W

A,

@R

W2+

d16

SU

BC

W

A,

@R

W3+

d16

SU

BC

W

A,

@R

W0+

RW

7

SU

BC

W

A,

@R

W1+

RW

7

SU

BC

W

A,

@P

C+

d16

SU

BC

W

A,

add

r16

NE

GW

@

RW

0+d8

NE

GW

@

RW

1+d8

NE

GW

@

RW

2+d8

NE

GW

@

RW

3+d8

NE

GW

@

RW

4+d8

NE

GW

@

RW

5+d8

NE

GW

@

RW

6+d8

NE

GW

@

RW

7+d8

NE

GW

@R

W0+

d16

NE

GW

@R

W1+

d16

NE

GW

@R

W2+

d16

NE

GW

@R

W3+

d16

NE

GW

@R

W0+

RW

7

NE

GW

@R

W1+

RW

7

NE

GW

@P

C+

d16

NE

GW

add

r16

AN

DW

@

R W

0+d8

, A

AN

DW

@

R W

1+d8

, A

AN

DW

@

R

W2+

d8, A

AN

DW

@

R

W3+

d8, A

AN

DW

@

R

W4+

d8, A

AN

DW

@

R W

5+d8

, A

AN

DW

@

R

W6+

d8, A

AN

DW

@

R

W7+

d8, A

AN

DW

@

R W

0+d1

6, A

AN

DW

@

R W

1+d1

6, A

AN

DW

@

R W

2+d1

6, A

AN

DW

@

R W

3+d1

6, A

AN

DW

@

R W

0+R

W7,

A

AN

DW

@

R W

1+R

W7,

A

AN

DW

@

P C

+d1

6, A

AN

DW

a

ddr1

6, A

OR

W

@

R

W

0+d8

, A

OR

W

@

R

W

1+d8

, A

OR

W

@

R

W

2+d8

, A

OR

W

@

R

W

3+d8

, A

OR

W

@

R

W

4+d8

, A

OR

W

@

R

W

5+d8

, A

OR

W

@

R

W

6+d8

, A

OR

W

@

R

W

7+d8

, A

OR

W

@

R

W

0+d1

6, A

OR

W

@

R

W

1+d1

6, A

OR

W

@

R

W

2+d1

6, A

OR

W

@

R

W

3+d1

6, A

OR

W

@

R

W

0+R

W7,

A

OR

W

@

R

W

1+R

W7,

A

C+

d16,

A

OR

W a

ddr1

6, A

XO

RW

@

R

W0+

d8, A

XO

RW

@

R

W1+

d8, A

XO

RW

@

R

W2+

d8, A

XO

RW

@

R

W3+

d8, A

XO

RW

@

R

W4+

d8, A

XO

RW

@

R

W5+

d8, A

XO

RW

@

R

W6+

d8, A

XO

RW

@

R

W7+

d8, A

XO

RW

@

R W

0+d1

6, A

XO

RW

@

R W

1+d1

6, A

XO

RW

@

R W

2+d1

6, A

XO

RW

@

R W

3+d1

6, A

XO

RW

@

R

W0+

RW

7, A

XO

RW

@

R

W1+

RW

7, A

XO

RW

@

P C

+d16

, A

XO

RW

a

ddr1

6, A

NO

TW

@R

W0+

d8

NO

TW

@R

W1+

d8

NO

TW

@R

W2+

d8

NO

TW

@R

W3+

d8

NO

TW

@R

W4+

d8

NO

TW

@R

W5+

d8

NO

TW

@R

W6+

d8

NO

TW

@R

W7+

d8

NO

TW

@R

W0+

d16

NO

TW

@R

W1+

d16

NO

TW

@R

W2+

d16

NO

TW

@R

W3+

d16

NO

TW

@R

W0+

RW

7

NO

TW

@R

W1+

RW

7

NO

TW

@P

C+

d16

NO

TW

a

ddr1

6

@P

C+d

16, A

OR

W

@

P

4.3 Instruction Map

269

Tab

le 4

.3.1

3 “

ea”

Inst

ruct

ion

s 9

(Fir

st b

yte

= 78

H)

+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

MU

LU

A

, R0

MU

LU

A

, R1

MU

LU

A

, R2

MU

LU

A

, R3

MU

LU

A

, R4

MU

LU

A

, R5

MU

LU

A

, R6

MU

LU

A

, R7

MU

LU

A, @

RW

0

MU

LU

A, @

RW

1

MU

LU

A, @

RW

2

MU

LU

A, @

RW

3

MU

LU A

, @R

W0+

MU

LU A

, @R

W1+

MU

LU A

, @R

W2+

MU

LU A

, @R

W3+

MU

LU

A

,

@R

W0+

d8

MU

LU

A

,

@R

W1+

d8

MU

LU

A

,

@R

W2+

d8

MU

LU

A

,

@R

W3+

d8

MU

LU

A

,

@R

W4+

d8

MU

LU

A

,

@R

W5+

d8

MU

LU

A

,

@R

W6+

d8

MU

LU

A

,

@R

W7+

d8

MU

LU

A

, @

RW

0+d1

6

MU

LU

A

, @

RW

1+d1

6

MU

LU

A

, @

RW

2+d1

6

MU

LU

A

, @

RW

3+d1

6

MU

LU

A

,@

RW

0+R

W7

MU

LU

A

,@

RW

1+R

W7

MU

LU

A

, @

PC

+d1

6

MU

LU

A

,

ad

dr16

MU

LUW

A, R

W0

MU

LUW

A, R

W1

MU

LUW

A, R

W2

MU

LUW

A, R

W3

MU

LUW

A, R

W4

MU

LUW

A, R

W5

MU

LUW

A, R

W6

MU

LUW

A, R

W7

MU

LUW

A

, @R

W0

MU

LUW

A

, @R

W1

MU

LUW

A

, @R

W2

MU

LUW

A

, @R

W3

MU

LUW

A, @

RW

0+

MU

LUW

A, @

RW

1+

MU

LUW

A, @

RW

2+

MU

LUW

A, @

RW

3+

DIV

U

A

, R0

DIV

U

A

, R1

DIV

U

A

, R2

DIV

U

A

, R3

DIV

U

A

, R4

DIV

U

A

, R5

DIV

U

A

, R6

DIV

U

A

, R7

DIV

U

A, @

RW

0

DIV

U

A, @

RW

1

DIV

U

A, @

RW

2

DIV

U

A, @

RW

3

DIV

U A

, @R

W0+

DIV

U A

, @R

W1+

DIV

U A

, @R

W2+

DIV

U A

, @R

W3+

DIV

UW

A, R

W0

DIV

UW

A, R

W1

DIV

UW

A, R

W2

DIV

UW

A, R

W3

DIV

UW

A, R

W4

DIV

UW

A, R

W5

DIV

UW

A, R

W6

DIV

UW

A, R

W7

DIV

UW

A

, @R

W0

DIV

UW

A

, @R

W1

DIV

UW

A

, @R

W2

DIV

UW

A

, @R

W3

DIV

UW

A, @

RW

0+

DIV

UW

A, @

RW

1+

DIV

UW

A, @

RW

2+

DIV

UW

A, @

RW

3+

MU

LUW

A

,

@R

W0+

d8

MU

LUW

A

,

@R

W1+

d8

MU

LUW

A

,

@R

W2+

d8

MU

LUW

A

,

@R

W3+

d8

MU

LUW

A

,

@R

W4+

d8

MU

LUW

A

,

@R

W5+

d8

MU

LUW

A

,

@R

W6+

d8

MU

LUW

A

,

@R

W7+

d8

MU

LUW

A

, @

RW

0+d1

6

MU

LUW

A

, @

RW

1+d1

6

MU

LUW

A

, @

RW

2+d1

6

MU

LUW

A

, @

RW

3+d1

6

MU

LUW

A

,@

RW

0+R

W7

MU

LUW

A

, @

RW

1+R

W7

MU

LUW

A

, M

ULU

W

A,

add

r16

DIV

U

A,

@

RW

0+d8

DIV

U

A,

@

RW

1+d8

DIV

U

A,

@

RW

2+d8

DIV

U

A,

@

RW

3+d8

DIV

U

A,

@

RW

4+d8

DIV

U

A,

@

RW

5+d8

DIV

U

A,

@

RW

6+d8

DIV

U

A,

@

RW

7+d8

DIV

U

A,

@R

W0+

d16

DIV

U

A,

@R

W1+

d16

DIV

U

A,

@R

W2+

d16

DIV

U

A,

@R

W3+

d16

DIV

U

A,

@R

W0+

RW

7

DIV

U

A,

@R

W1+

RW

7

DIV

U

A,

@

PC

+d16

DIV

U

A,

a

ddr1

6

DIV

UW

A,

@

RW

0+d8

DIV

UW

A,

@

RW

1+d8

DIV

UW

A,

@

RW

2+d8

DIV

UW

A,

@

RW

3+d8

DIV

UW

A,

@

RW

4+d8

DIV

UW

A,

@

RW

5+d8

DIV

UW

A,

@

RW

6+d8

DIV

UW

A,

@

RW

7+d8

DIV

UW

A,

@R

W0+

d16

DIV

UW

A,

@R

W1+

d16

DIV

UW

A,

@R

W2+

d16

DIV

UW

A,

@R

W3+

d16

DIV

UW

A,

@R

W0+

RW

7

DIV

UW

A,

@R

W1+

RW

7

DIV

UW

A,

@ P

C+

d16

DIV

UW

A,

add

r16

@P

C+

d16

4.3 Instruction Map


Tab

le 4

.3.1

4M

OV

EA

RW

i, ea

(F

irst

byt

e =

79H)

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D

+E

+F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

MO

VE

A R

W0,

RW

0

MO

VE

A R

W0,

RW

1

MO

VE

A R

W0,

RW

2

MO

VE

A R

W0,

RW

3

MO

VE

A R

W0,

RW

4

MO

VE

A R

W0,

RW

5

MO

VE

A R

W0,

RW

6

MO

VE

A R

W0,

RW

7

MO

VE

AR

W0,

@R

W0

MO

VE

AR

W0,

@R

W1

MO

VE

AR

W0,

@R

W2

MO

VE

AR

W0,

@R

W3

MO

VE

A

R

W0,

@R

W0+

MO

VE

A

R

W0,

@R

W1+

MO

VE

A

R

W0,

@R

W2+

MO

VE

A

R

W0,

@R

W3+

MO

VE

A R

W0,

@

RW

0+d8

MO

VE

A R

W0,

@

RW

1+d8

MO

VE

A R

W0,

@

RW

2+d8

MO

VE

A R

W0,

@

RW

3+d8

MO

VE

A R

W0,

@

RW

4+d8

MO

VE

A R

W0,

@

RW

5+d8

MO

VE

A R

W0,

@

RW

6+d8

MO

VE

A R

W0,

@

RW

7+d8

MO

VE

A R

W0,

@

RW

0+d1

6

MO

VE

A R

W0,

@R

W1+

d16

MO

VE

A R

W0,

@R

W2+

d16

MO

VE

A R

W0,

@R

W3+

d16

MO

VE

A R

W0,

@R

W0+

RW

7

MO

VE

A R

W0,

@R

W1+

RW

7

MO

VE

A R

W0,

@

PC

+d1

6

MO

VE

A R

W0,

a

ddr1

6

MO

VE

A

RW

1, R

W0

MO

VE

A

RW

1, R

W1

MO

VE

A

RW

1, R

W2

MO

VE

A

RW

1, R

W3

MO

VE

A

RW

1, R

W4

MO

VE

A

RW

1, R

W5

MO

VE

A

RW

1, R

W6

MO

VE

A

RW

1, R

W7

MO

VE

AR

W1,

@R

W0

MO

VE

AR

W1,

@R

W1

MO

VE

AR

W1,

@R

W2

MO

VE

AR

W1,

@R

W3

MO

VE

A

RW

1, @

RW

0+

MO

VE

A

RW

1, @

RW

1+

MO

VE

A

RW

1, @

RW

2+

MO

VE

A

RW

1, @

RW

3+

MO

VE

A R

W2,

RW

0

MO

VE

A R

W2,

RW

1

MO

VE

A R

W2,

RW

2

MO

VE

A R

W2,

RW

3

MO

VE

A R

W2,

RW

4

MO

VE

A R

W2,

RW

5

MO

VE

A R

W2,

RW

6

MO

VE

A R

W2,

RW

7

MO

VE

AR

W2,

@R

W0

MO

VE

AR

W2,

@R

W1

MO

VE

AR

W2,

@R

W2

MO

VE

AR

W2,

@R

W3

MO

VE

A

RW

2, @

RW

0+

MO

VE

A

RW

2, @

RW

1+

MO

VE

A

RW

2, @

RW

2+

MO

VE

A

RW

2, @

RW

3+

MO

VE

A

RW

3, R

W0

MO

VE

A

RW

3, R

W1

MO

VE

A

RW

3, R

W2

MO

VE

A

RW

3, R

W3

MO

VE

A

RW

3, R

W4

MO

VE

A

RW

3, R

W5

MO

VE

A

RW

3, R

W6

MO

VE

A

RW

3, R

W7

MO

VE

A

RW

3, @

RW

0

MO

VE

A

RW

3, @

RW

1

MO

VE

A

RW

3, @

RW

2

MO

VE

A

RW

3, @

RW

3

MO

VE

A

R

W3,

@R

W0+

MO

VE

A

R

W3,

@R

W1+

MO

VE

A

RW

3, @

RW

2+

MO

VE

A

R

W3,

@R

W3+

MO

VE

A R

W4,

RW

0

MO

VE

A R

W4,

RW

1

MO

VE

A R

W4,

RW

2

MO

VE

A R

W4,

RW

3

MO

VE

A R

W4,

RW

4

MO

VE

A R

W4,

RW

5

MO

VE

A R

W4,

RW

6

MO

VE

A R

W4,

RW

7

MO

VE

AR

W4,

@R

W0

MO

VE

AR

W4,

@R

W1

MO

VE

AR

W4,

@R

W2

MO

VE

AR

W4,

@R

W3

MO

VE

A

RW

4, @

RW

0+

MO

VE

A

RW

4, @

RW

1+

MO

VE

A

RW

4, @

RW

2+

MO

VE

A

RW

4, @

RW

3+

MO

VE

A R

W5,

RW

0

MO

VE

A R

W5,

RW

1

MO

VE

A R

W5,

RW

2

MO

VE

A R

W5,

RW

3

MO

VE

A R

W5,

RW

4

MO

VE

A R

W5,

RW

5

MO

VE

A R

W5,

RW

6

MO

VE

A R

W5,

RW

7

MO

VE

AR

W5,

@R

W0

MO

VE

AR

W5,

@R

W1

MO

VE

AR

W5,

@R

W2

MO

VE

AR

W5,

@R

W3

MO

VE

A

RW

5, @

RW

0+

MO

VE

A

RW

5, @

RW

1+

MO

VE

A

RW

5, @

RW

2+

MO

VE

A

RW

5, @

RW

3+

MO

VE

A

RW

6, R

W0

MO

VE

A R

W6,

RW

1

MO

VE

A R

W6,

RW

2

MO

VE

A R

W6,

RW

3

MO

VE

A R

W6,

RW

4

MO

VE

A R

W6,

RW

5

MO

VE

A R

W6,

RW

6

MO

VE

A R

W6,

RW

7

MO

VE

AR

W6,

@R

W0

MO

VE

AR

W6,

@R

W1

MO

VE

AR

W6,

@R

W2

MO

VE

AR

W6,

@R

W3

MO

VE

A

RW

6, @

RW

0+

MO

VE

A

RW

6, @

RW

1+

MO

VE

A

RW

6, @

RW

2+

MO

VE

A

W

6, @

RW

3+

MO

VE

A

RW

7, R

W0

MO

VE

A

RW

7, R

W1

MO

VE

A

RW

7, R

W2

MO

VE

A

RW

7, R

W3

MO

VE

A

RW

7, R

W4

MO

VE

A

RW

7, R

W5

MO

VE

A

RW

7, R

W6

MO

VE

A

RW

7, R

W7

MO

VE

AR

W7,

@R

W0

MO

VE

AR

W7,

@R

W1

MO

VE

AR

W7,

@R

W2

MO

VE

AR

W7,

@R

W3

MO

VE

A

RW

7, @

RW

0+

MO

VE

A

RW

7, @

RW

1+

MO

VE

A

RW

7, @

RW

2+

MO

VE

A

RW

7, @

RW

3+

MO

VE

A R

W1,

@

RW

0+d8

MO

VE

A R

W1,

@

RW

1+d8

MO

VE

A R

W1,

@

RW

2+d8

MO

VE

A R

W1,

@

RW

3+d8

MO

VE

A R

W1,

@

RW

4+d8

MO

VE

A R

W1,

@

RW

5+d8

MO

VE

A R

W1,

@

RW

6+d8

MO

VE

A R

W1,

@

RW

7+d8

MO

VE

A R

W1,

@R

W0+

d16

MO

VE

A R

W1,

@R

W1+

d16

MO

VE

A R

W1,

@R

W2+

d16

MO

VE

A R

W1,

@R

W3+

d16

MO

VE

A R

W1,

@R

W0+

RW

7

MO

VE

A R

W1,

@R

W1+

RW

7

MO

VE

A R

W1,

MO

VE

A R

W1,

add

r16

MO

VE

A R

W2,

@R

W0+

d8

MO

VE

A R

W2,

@R

W1+

d8

MO

VE

A R

W2,

@R

W2+

d8

MO

VE

A R

W2,

@R

W3+

d8

MO

VE

A R

W2,

@R

W4+

d8

MO

VE

A R

W2,

@R

W5+

d8

MO

VE

A R

W2,

@R

W6+

d8

MO

VE

A R

W2,

@R

W7+

d8

MO

VE

A R

W2,

@

RW

0+d1

6

MO

VE

A R

W2,

@

RW

1+d1

6

MO

VE

A R

W2,

@

RW

2+d1

6

MO

VE

A R

W2,

@

RW

3+d1

6

MO

VE

A R

W2,

@

RW

0+R

W7

MO

VE

A R

W2,

@

RW

1+R

W7

MO

VE

A R

W2,

@

PC

+d1

6

MO

VE

A R

W2,

a

ddr1

6

MO

VE

A R

W3,

@R

W0+

d8

MO

VE

A R

W3,

@R

W1+

d8

MO

VE

A R

W3,

@R

W2+

d8

MO

VE

A R

W3,

@R

W3+

d8

MO

VE

A R

W3,

@R

W4+

d8

MO

VE

A R

W3,

@R

W5+

d8

MO

VE

A R

W3,

@R

W6+

d8

MO

VE

A R

W3,

@R

W7+

d8

MO

VE

A R

W3,

@

RW

0+d1

6

MO

VE

A R

W3,

@

RW

1+d1

6

MO

VE

A R

W3,

@

RW

2+d1

6

MO

VE

A R

W3,

@

RW

3+d1

6

MO

VE

A R

W3,

@

RW

0+R

W7

MO

VE

A R

W3,

@

RW

1+R

W7

MO

VE

A R

W3,

@

PC

+d1

6

MO

VE

A R

W3,

add

r16

MO

VE

A R

W4,

@

RW

0+d8

MO

VE

A R

W4,

@

RW

1+d8

MO

VE

A R

W4,

@

RW

2+d8

MO

VE

A R

W4,

@

RW

3+d8

MO

VE

A R

W4,

@

RW

4+d8

MO

VE

A R

W4,

@

RW

5+d8

MO

VE

A R

W4,

@

RW

6+d8

MO

VE

A R

W4,

@

RW

7+d8

MO

VE

A R

W4,

@R

W0+

d16

MO

VE

A R

W4,

@R

W1+

d16

MO

VE

A R

W4,

@R

W2+

d16

MO

VE

A R

W4,

@R

W3+

d16

MO

VE

A R

W4,

@R

W0+

RW

7

MO

VE

A R

W4,

@R

W1+

RW

7

MO

VE

A R

W4,

@

PC

+d1

6

MO

VE

A R

W4,

a

ddr1

6

MO

VE

A R

W5,

@

RW

0+d8

MO

VE

A R

W5,

@

RW

1+d8

MO

VE

A R

W5,

@

RW

2+d8

MO

VE

A R

W5,

@

RW

3+d8

MO

VE

A R

W5,

@

RW

4+d8

MO

VE

A R

W5,

@

RW

5+d8

MO

VE

A R

W5,

@

RW

6+d8

MO

VE

A R

W5,

@

RW

7+d8

MO

VE

A R

W5,

@

RW

0+d1

6

MO

VE

A R

W5,

@

RW

1+d1

6

MO

VE

A R

W5,

@

RW

2+d1

6

MO

VE

A R

W5,

@

RW

3+d1

6

MO

VE

A R

W5,

@

RW

0+R

W7

MO

VE

A R

W5,

@

RW

1+R

W7

MO

VE

A R

W5,

@

PC

+d1

6

MO

VE

A R

W5,

ad

dr16

MO

VE

A R

W6,

@

RW

0+d8

MO

VE

A R

W6,

@

RW

1+d8

MO

VE

A R

W6,

@

RW

2+d8

MO

VE

A R

W6,

@

RW

3+d8

MO

VE

A R

W6,

@

RW

4+d8

MO

VE

A R

W6,

@

RW

5+d8

MO

VE

A R

W6,

@

RW

6+d8

MO

VE

A R

W6,

@

RW

7+d8

MO

VE

A R

W6,

@R

W0+

d16

MO

VE

A R

W6,

@R

W1+

d16

MO

VE

A R

W6,

@R

W2+

d16

MO

VE

A R

W6,

@R

W3+

d16

MO

VE

A R

W6,

@R

W0+

RW

7

MO

VE

A R

W6,

@R

W1+

RW

7

MO

VE

A R

W6,

@P

C+

d16

MO

VE

A R

W6,

addr

16

MO

VE

A R

W7,

@

RW

0+d8

MO

VE

A R

W7,

@

RW

1+d8

MO

VE

A R

W7,

@

RW

2+d8

MO

VE

A R

W7,

@

RW

3+d8

MO

VE

A R

W7,

@

RW

4+d8

MO

VE

A R

W7,

@

RW

5+d8

MO

VE

A R

W7,

@

RW

6+d8

MO

VE

A R

W7,

@

RW

7+d8

MO

VE

A R

W7,

@R

W0+

d16

MO

VE

A R

W7,

@R

W1+

d16

MO

VE

A R

W7,

@R

W2+

d16

MO

VE

A R

W7,

@R

W3+

d16

MO

VE

A R

W7,

@R

W0+

RW

7

MO

VE

A R

W7,

@R

W1+

RW

7

MO

VE

A R

W7,

@P

C+d

16

MO

VE

A R

W7,

a

ddr1

6

@P

C+

d16

4.3 Instruction Map

271

Tab

le 4

.3.1

5M

OV

Ri,

ea (

Fir

st b

yte

= 7A

H)

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D

+E

+F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

MO

V

R0,

R0

MO

V

R0,

R1

MO

V

R0,

R2

MO

V

R0,

R3

MO

V

R0,

R4

MO

V

R0,

R5

MO

V

R0,

R6

MO

V

R0,

R7

MO

V R

0, @

RW

0

MO

V R

0, @

RW

1

MO

V R

0, @

RW

2

MO

V R

0, @

RW

3

MO

V R

0, @

RW

0+

MO

V R

0, @

RW

1+

MO

V R

0, @

RW

2+

MO

V R

0, @

RW

3+

MO

V

R

0,

@R

W0+

d8

MO

V

R

0,

@R

W1+

d8

MO

V

R

0,

@R

W2+

d8

MO

V

R

0,

@R

W3+

d8

MO

V

R

0,

@R

W4+

d8

MO

V

R

0,

@R

W5+

d8

MO

V

R

0,

@R

W6+

d8

MO

V

R

0,

@R

W7+

d8

MO

V

R

0,

@R

W0+

d16

MO

V

R

0, @

RW

1+d1

6

MO

V

R

0, @

RW

2+d1

6

MO

V

R

0, @

RW

3+d1

6

MO

V

R

0,@

RW

0+R

W7

MO

V

R

0,@

RW

1+R

W7

MO

V

R

0,

@P

C+

d16

MO

V

R

0,

@ad

dr16

MO

V

R1,

R0

MO

V

R1,

R1

MO

V

R1,

R2

MO

V

R1,

R3

MO

V

R1,

R4

MO

V

R1,

R5

MO

V

R1,

R6

MO

V

R1,

R7

MO

V R

1, @

RW

0

MO

V R

1, @

RW

1

MO

V R

1, @

RW

2

MO

V R

1, @

RW

3

MO

V

R

1, R

1, @

RW

0+

MO

V

R

1, R

1, @

RW

1+

MO

V

R

1, R

1, @

RW

2+

MO

V

R

1, R

1, @

RW

3+

MO

V

R2,

R0

MO

V

R2,

R1

MO

V

R2,

R2

MO

V

R2,

R3

MO

V

R2,

R4

MO

V

R2,

R5

MO

V

R2,

R6

MO

V

R2,

R7

MO

VR

2, @

RW

0

MO

VR

2, @

RW

1

MO

V R

2, @

RW

2

MO

V R

2, @

RW

3

MO

V

R2,

@R

W0+

MO

V R

2, @

RW

1+

MO

V R

2, @

RW

2+

MO

V R

2, @

RW

3+

MO

V

R

3, R

0

MO

V

R

3, R

1

MO

V

R

3, R

2

MO

V

R

3, R

3

MO

V

R

3, R

4

MO

V

R

3, R

5

MO

V

R

3, R

6

MO

V

R

3, R

7

MO

V

R3,

@R

W0

MO

V

R3,

@R

W1

MO

V

R3,

@R

W2

MO

V

R3,

@R

W3

MO

V R

3, @

RW

0+

MO

V R

3, @

RW

1+

MO

V R

3, @

RW

2+

MO

V R

3, @

RW

3+

MO

V

R4,

R0

MO

V

R4,

R1

MO

V

R4,

R2

MO

V

R4,

R3

MO

V

R4,

R4

MO

V

R4,

R5

MO

V

R4,

R6

MO

V

R4,

R7

MO

VR

4, @

RW

0

MO

VR

4, @

RW

1

MO

VR

4, @

RW

2

MO

VR

4, @

RW

3

MO

VR

4, @

RW

0+

MO

VR

4, @

RW

1+

MO

V R

4, @

RW

2+

MO

V R

4, @

RW

3+

MO

V

R5,

R0

MO

V

R5,

R1

MO

V

R5,

R2

MO

V

R5,

R3

MO

V

R5,

R4

MO

V

R5,

R5

MO

V

R5,

R6

MO

V

R5,

R7

MO

V R

5, @

RW

0

MO

VR

5, @

RW

1

MO

VR

5, @

RW

2

MO

VR

5, @

RW

3

MO

V

R5,

@R

W0+

MO

VR

5, @

RW

1+

MO

V

R5,

@R

W2+

MO

V

R5,

@R

W3+

MO

V

R6,

R0

MO

V

R6,

R1

MO

V

R6,

R2

MO

V

R6,

R3

MO

V

R6,

R4

MO

V

R6,

R5

MO

V

R6,

R6

MO

V

R6,

R7

MO

VR

6, @

RW

0

MO

VR

6, @

RW

1

MO

VR

6, @

RW

2

MO

VR

6, @

RW

3

MO

V

R6,

@R

W0+

MO

V

R6,

@R

W1+

MO

V

R6,

@R

W2+

MO

V

R6,

@R

W3+

MO

V

R7,

R0

MO

V

R7,

R1

MO

V

R7,

R2

MO

V

R7,

R3

MO

V

R7,

R4

MO

V

R7,

R5

MO

V

R7,

R6

MO

V

R7,

R7

MO

V R

7, @

RW

0

MO

V R

7, @

RW

1

MO

V R

7, @

RW

2

MO

V R

7, @

RW

3

MO

V

R7,

@R

W0+

MO

V

R7,

@R

W1+

MO

V

R7,

@R

W2+

MO

V

R7,

@R

W3+

MO

V

R

1,

@R

W0+

d8

MO

V

R

1,

@R

W1+

d8

MO

V

R

1,

@R

W2+

d8

MO

V

R

1,

@R

W3+

d8

MO

V

R

1,

@R

W4+

d8

MO

V

R

1,

@R

W5+

d8

MO

V

R

1,

@R

W6+

d8

MO

V

R

1,

@R

W7+

d8

MO

V

R

1, @

RW

0+d1

6

MO

V

R

1, @

RW

1+d1

6

MO

V

R

1, @

RW

2+d1

6

MO

V

R

1, @

RW

3+d1

6

MO

V

R

1,@

RW

0+R

W7

MO

V

R

1, @

RW

1+R

W7

MO

V

R

1, M

OV

R1,

add

r16

MO

V

R

2,

@

RW

0+d8

MO

V

R

2,

@

RW

1+d8

MO

V

R

2,

@

RW

2+d8

MO

V

R

2,

@

RW

3+d8

MO

V

R

2,

@

RW

4+d8

MO

V

R

2,

@

RW

5+d8

MO

V

R

2,

@

RW

6+d8

MO

V

R

2,

@

RW

7+d8

MO

V

R

2,

@R

W0+

d16

MO

V

R

2,

@R

W1+

d16

MO

V

R

2,

@R

W2+

d16

MO

V

R

2,

@R

W3+

d16

MO

V

R

2,

@R

W0+

RW

7

MO

V

R

2,

@R

W1+

RW

7

MO

V

R

2,

@P

C+

d16

MO

V

R

2,

ad

dr16

MO

V

R

3,

@

RW

0+d8

MO

V

R

3,

@

RW

1+d8

MO

V

R

3,

@

RW

2+d8

MO

V

R

3,

@

RW

3+d8

MO

V

R

3,

@

RW

4+d8

MO

V

R

3,

@

RW

5+d8

MO

V

R

3,

@

RW

6+d8

MO

V

R

3,

@

RW

7+d8

MO

V

R

3,

@R

W0+

d16

MO

V

R

3,

@R

W1+

d16

MO

V

R

3,

@R

W2+

d16

MO

V

R

3,

@R

W3+

d16

MO

V

R

3,

@R

W0+

RW

7

MO

V

R

3,

@R

W1+

RW

7

MO

V

R

3,

@P

C+

d16

MO

V

R

3,

addr

16

MO

V

R

4,

@R

W0+

d8

MO

V

R

4,

@R

W1+

d8

MO

V

R

4,

@R

W2+

d8

MO

V

R

4,

@R

W3+

d8

MO

V

R

4,

@R

W4+

d8

MO

V

R

4,

@R

W5+

d8

MO

V

R

4,

@R

W6+

d8

MO

V

R

4,

@R

W7+

d8

MO

V

R

4, @

RW

0+d1

6

MO

V

R

4, @

RW

1+d1

6

MO

V

R

4, @

RW

2+d1

6

MO

V

R

4, @

RW

3+d1

6

MO

V

R

4,@

RW

0+R

W7

MO

V

R

4,@

RW

1+R

W7

MO

V

R

4,

@P

C+

d16

MO

V

R

4,

add

r16

MO

V

R5,

@

RW

0+d8

MO

V

R5,

@

RW

1+d8

MO

V

R5,

@

RW

2+d8

MO

V

R5,

@

RW

3+d8

MO

V

R5,

@

RW

4+d8

MO

V

R5,

@

RW

5+d8

MO

V

R5,

@R

W6+

d8

MO

V

R5,

@

RW

7+d8

MO

V

R5,

@

RW

0+d1

6

MO

V

R5,

@

RW

1+d1

6

MO

V

R5,

@

RW

2+d1

6

MO

V

R5,

@

RW

3+d1

6

MO

V

R5,

@

RW

0+R

W7

MO

V

R5,

@

RW

1+R

W7

MO

V

R5,

@

PC

+d1

6

MO

V

R5,

ad

dr16

MO

V

R6,

@

RW

0+d8

MO

V

R6,

@

RW

1+d8

MO

V

R6,

@

RW

2+d8

MO

V

R6,

@

RW

3+d8

MO

V

R6,

@

RW

4+d8

MO

V

R6,

@

RW

5+d8

MO

V

R6,

@

RW

6+d8

MO

V

R6,

@

RW

7+d8

MO

V

R6,

@R

W0+

d16

MO

V

R6,

@R

W1+

d16

MO

V

R6,

@R

W2+

d16

MO

V

R6,

@R

W3+

d16

MO

V

R6,

@R

W0+

RW

7

MO

V

R6,

@R

W1+

RW

7

MO

V

R6,

@P

C+

d16

MO

V

R6,

addr

16

MO

V

R7,

@

RW

0+d8

MO

V

R7,

@

RW

1+d8

MO

V

R7,

@

RW

2+d8

MO

V

R7,

@

RW

3+d8

MO

V

R7,

@

RW

4+d8

MO

V

R7,

@

RW

5+d8

MO

V

R7,

@

RW

6+d8

MO

V

R7,

@

RW

7+d8

MO

V

R7,

@R

W0+

d16

MO

V

R7,

@R

W1+

d16

MO

V

R7,

@R

W2+

d16

MO

V

R7,

@R

W3+

d16

MO

V

R7,

@R

W0+

RW

7

MO

V

R7,

@R

W1+

RW

7

MO

V

R7,

@P

C+d

16

MO

V

R7,

a

ddr1

6

@P

C+

d16

4.3 Instruction Map


Tab

le 4

.3.1

6M

OV

W R

Wi,

ea (

Fir

st b

yte

= 7

BH)

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D

+E

+F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

MO

VW

RW

0, R

W0

MO

VW

RW

0, R

W1

MO

VW

RW

0, R

W2

MO

VW

RW

0, R

W3

MO

VW

RW

0, R

W4

MO

VW

RW

0, R

W5

MO

VW

RW

0, R

W6

MO

VW

RW

0, R

W7

MO

VW

RW

0, @

RW

0

MO

VW

RW

0, @

RW

1

MO

VW

RW

0, @

RW

2

MO

VW

RW

0, @

RW

3

MO

VW

RW

0, @

RW

0+

MO

VW

RW

0, @

RW

1+

MO

VW

RW

0, @

RW

2+

MO

VW

RW

0, @

RW

3+

MO

VW

RW

0,

@R

W0+

d8

MO

VW

RW

0,

@R

W1+

d8

MO

VW

RW

0,

@R

W2+

d8

MO

VW

RW

0,

@R

W3+

d8

MO

VW

RW

0,

@R

W4+

d8

MO

VW

RW

0,

@R

W5+

d8

MO

VW

RW

0,

@R

W6+

d8

MO

VW

RW

0,

@R

W7+

d8

MO

VW

RW

0,

@R

W0+

d16

MO

VW

RW

0, @

RW

1+d1

6

MO

VW

RW

0, @

RW

2+d1

6

MO

VW

RW

0, @

RW

3+d1

6

MO

VW

RW

0, @

RW

0+R

W7

MO

VW

RW

0, @

RW

1+R

W7

MO

VW

RW

0,

@P

C+

d16

MO

VW

RW

0,

add

r16

MO

VW

R

W1,

RW

0

MO

VW

R

W1,

RW

1

MO

VW

R

W1,

RW

2

MO

VW

R

W1,

RW

3

MO

VW

R

W1,

RW

4

MO

VW

R

W1,

RW

5

MO

VW

R

W1,

RW

6

MO

VW

R

W1,

RW

7

MO

VW

RW

1, @

RW

0

MO

VW

RW

1, @

RW

1

MO

VW

RW

1, @

RW

2

MO

VW

RW

1, @

RW

3

MO

VW

RW

1, @

RW

0+

MO

VW

RW

1, @

RW

1+

MO

VW

RW

1, @

RW

2+

MO

VW

RW

1, @

RW

3+

MO

VW

RW

2, R

W0

MO

VW

RW

2, R

W1

MO

VW

RW

2, R

W2

MO

VW

RW

2, R

W3

MO

VW

RW

2, R

W4

MO

VW

RW

2, R

W5

MO

VW

RW

2, R

W6

MO

VW

RW

2, R

W7

MO

VW

RW

2, @

RW

0

MO

VW

RW

2, @

RW

1

MO

VW

RW

2, @

RW

2

MO

VW

RW

2, @

RW

3

MO

VW

RW

2, @

RW

0+

MO

VW

RW

2, @

RW

1+

MO

VW

RW

2, @

RW

2+

MO

VW

RW

2, @

RW

3+

MO

VW

R

W3,

RW

0

MO

VW

R

W3,

RW

1

MO

VW

R

W3,

RW

2

MO

VW

R

W3,

RW

3

MO

VW

R

W3,

RW

4

MO

VW

R

W3,

RW

5

MO

VW

R

W3,

RW

6

MO

VW

R

W3,

RW

7

MO

VW

R

W3,

@R

W0

MO

VW

R

W3,

@R

W1

MO

VW

R

W3,

@R

W2

MO

VW

R

W3,

@R

W3

MO

VW

R

W3,

@R

W0+

MO

VW

RW

3, @

RW

1+

MO

VW

RW

3, @

RW

2+

MO

VW

RW

3, @

RW

3+

MO

VW

RW

4, R

W0

MO

VW

RW

4, R

W1

MO

VW

RW

4, R

W2

MO

VW

RW

4, R

W3

MO

VW

RW

4, R

W4

MO

VW

RW

4, R

W5

MO

VW

RW

4, R

W6

MO

VW

RW

4, R

W7

MO

VW

RW

4, @

RW

0

MO

VW

RW

4, @

RW

1

MO

VW

RW

4, @

RW

2

MO

VW

RW

4, @

RW

3

MO

VW

RW

4, @

RW

0+

MO

VW

RW

4, @

RW

1+

MO

VW

RW

4, @

RW

2+

MO

VW

RW

4, @

RW

3+

MO

VW

RW

5, R

W0

MO

VW

RW

5, R

W1

MO

VW

RW

5, R

W2

MO

VW

RW

5, R

W3

MO

VW

RW

5, R

W4

MO

VW

RW

5, R

W5

MO

VW

RW

5, R

W6

MO

VW

RW

5, R

W7

MO

VW

RW

5, @

RW

0

MO

VW

RW

5, @

RW

1

MO

VW

RW

5, @

RW

2

MO

VW

RW

5, @

RW

3

MO

VW

RW

5, @

RW

0+

MO

VW

RW

5, @

RW

1+

MO

VW

RW

5, @

RW

2+

MO

VW

RW

5, @

RW

3+

MO

VW

R

W6,

RW

0

MO

VW

RW

6, R

W1

MO

VW

RW

6, R

W2

MO

VW

RW

6, R

W3

MO

VW

RW

6, R

W4

MO

VW

RW

6, R

W5

MO

VW

RW

6, R

W6

MO

VW

RW

6, R

W7

MO

VW

RW

6, @

RW

0

MO

VW

RW

6, @

RW

1

MO

VW

RW

6, @

RW

2

MO

VW

RW

6, @

RW

3

MO

VW

RW

6, @

RW

0+

MO

VW

RW

6, @

RW

1+

MO

VW

RW

6, @

RW

2+

MO

VW

RW

6, @

RW

3+

MO

VW

RW

7, R

W0

MO

VW

RW

7, R

W1

MO

VW

RW

7, R

W2

MO

VW

RW

7, R

W3

MO

VW

RW

7, R

W4

MO

VW

RW

7, R

W5

MO

VW

RW

7, R

W6

MO

VW

R

W7,

RW

7

MO

VW

RW

7, @

RW

0

MO

VW

RW

7, @

RW

1

MO

VW

RW

7, @

RW

2

MO

VW

RW

7, @

RW

3

MO

VW

RW

7, @

RW

0+

MO

VW

RW

7, @

RW

1+

MO

VW

RW

7, @

RW

2+

MO

VW

RW

7, @

RW

3+

MO

VW

RW

1,

@R

W0+

d8

MO

VW

RW

1,

@R

W1+

d8

MO

VW

RW

1,

@R

W2+

d8

MO

VW

RW

1,

@R

W3+

d8

MO

VW

RW

1,

@R

W4+

d8

MO

VW

RW

1,

@R

W5+

d8

MO

VW

RW

1,

@R

W6+

d8

MO

VW

RW

1,

@R

W7+

d8

MO

VW

RW

1, @

RW

0+d1

6

MO

VW

RW

1, @

RW

1+d1

6

MO

VW

RW

1, @

RW

2+d1

6

MO

VW

RW

1, @

RW

3+d1

6

MO

VW

RW

1,@

RW

0+R

W7

MO

VW

RW

1, @

RW

1+R

W7

MO

VW

RW

1, M

OV

W R

W1,

add

r16

MO

VW

RW

2,

@

RW

0+d8

MO

VW

RW

2,

@

RW

1+d8

MO

VW

RW

2,

@

RW

2+d8

MO

VW

RW

2,

@

RW

3+d8

MO

VW

RW

2,

@

RW

4+d8

MO

VW

RW

2,

@

RW

5+d8

MO

VW

RW

2,

@

RW

6+d8

MO

VW

RW

2,

@

RW

7+d8

MO

VW

RW

2,

@R

W0+

d16

MO

VW

RW

2,

@R

W1+

d16

MO

VW

RW

2,

@R

W2+

d16

MO

VW

RW

2,

@R

W3+

d16

MO

VW

RW

2,

@R

W0+

RW

7

MO

VW

RW

2,

@R

W1+

RW

7

MO

VW

RW

2,

@P

C+d

16

MO

VW

RW

2,

add

r16

MO

VW

RW

3,

@

RW

0+d8

MO

VW

RW

3,

@

RW

1+d8

MO

VW

RW

3,

@

RW

2+d8

MO

VW

RW

3,

@

RW

3+d8

MO

VW

RW

3,

@

RW

4+d8

MO

VW

RW

3,

@

RW

5+d8

MO

VW

RW

3,

@

RW

6+d8

MO

VW

RW

3,

@

RW

7+d8

MO

VW

RW

3,

@R

W0+

d16

MO

VW

RW

3,

@R

W1+

d16

MO

VW

RW

3,

@R

W2+

d16

MO

VW

RW

3,

@R

W3+

d16

MO

VW

RW

3,

@R

W0+

RW

7

MO

VW

RW

3,

@R

W1+

RW

7

MO

VW

RW

3,

@P

C+

d16

MO

VW

RW

3, a

ddr1

6

MO

VW

RW

4,

@R

W0+

d8

MO

VW

RW

4,

@R

W1+

d8

MO

VW

RW

4,

@R

W2+

d8

MO

VW

RW

4,

@R

W3+

d8

MO

VW

RW

4,

@R

W4+

d8

MO

VW

RW

4,

@R

W5+

d8

MO

VW

RW

4,

@R

W6+

d8

MO

VW

RW

4,

@R

W7+

d8

MO

VW

RW

4, @

RW

0+d1

6

MO

VW

RW

4, @

RW

1+d1

6

MO

VW

RW

4, @

RW

2+d1

6

MO

VW

RW

4, @

RW

3+d1

6

MO

VW

RW

4, @

RW

0+R

W7

MO

VW

RW

4, @

RW

1+R

W7

MO

VW

RW

4,

@P

C+

d16

MO

VW

RW

4,

add

r16

MO

VW

RW

5,

@R

W0+

d8

MO

VW

RW

5,

@R

W1+

d8

MO

VW

RW

5,

@R

W2+

d8

MO

VW

RW

5,

@R

W3+

d8

MO

VW

RW

5,

@R

W4+

d8

MO

VW

RW

5,

@R

W5+

d8

MO

VW

RW

5,

@R

W6+

d8

MO

VW

RW

5,

@R

W7+

d8

MO

VW

RW

5,

@R

W0+

d16

MO

VW

RW

5,

@R

W1+

d16

MO

VW

RW

5,

@R

W2+

d16

MO

VW

RW

5,

@R

W3+

d16

MO

VW

RW

5,

@R

W0+

RW

7

MO

VW

RW

5,

@R

W1+

RW

7

MO

VW

RW

5,

@P

C+d

16

MO

VW

RW

5,

a

ddr1

6

MO

VW

RW

6,

@R

W0+

d8

MO

VW

RW

6,

@R

W1+

d8

MO

VW

RW

6,

@R

W2+

d8

MO

VW

RW

6,

@R

W3+

d8

MO

VW

RW

6,

@R

W4+

d8

MO

VW

RW

6,

@R

W5+

d8

MO

VW

RW

6,

@R

W6+

d8

MO

VW

RW

6,

@R

W7+

d8

MO

VW

RW

6, @

RW

0+d1

6

MO

VW

RW

6, @

RW

1+d1

6

MO

VW

RW

6, @

RW

2+d1

6

MO

VW

RW

6, @

RW

3+d1

6

MO

VW

RW

6, @

RW

0+R

W7

MO

VW

RW

6, @

RW

1+R

W7

MO

VW

RW

6, @

PC

+d1

6

MO

VW

RW

6,

add

r16

MO

VW

RW

7,

@R

W0+

d8

MO

VW

RW

7,

@R

W1+

d8

MO

VW

RW

7,

@R

W2+

d8

MO

VW

RW

7,

@R

W3+

d8

MO

VW

RW

7,

@R

W4+

d8

MO

VW

RW

7,

@R

W5+

d8

MO

VW

RW

7,

@R

W6+

d8

MO

VW

RW

7,

@R

W7+

d8

MO

VW

RW

7, @

RW

0+d1

6

MO

VW

RW

7, @

RW

1+d1

6

MO

VW

RW

7, @

RW

2+d1

6

MO

VW

RW

7, @

RW

3+d1

6

MO

VW

RW

7,@

RW

0+R

W7

MO

VW

RW

7,@

RW

1+R

W7

MO

VW

RW

7, @

PC

+d16

MO

VW

RW

7,

add

r16

@P

C+d

16

4.3 Instruction Map

273

Tab

le 4

.3.1

7M

OV

ea,

Ri (

Fir

st b

yte

= 7C

H)

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D

+E

+F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

MO

V R

0, R

0

MO

V R

1, R

0

MO

V R

2, R

0

MO

V R

3, R

0

MO

V R

4, R

0

MO

V R

5, R

0

MO

V R

6, R

0

MO

V R

7, R

0

MO

V @

RW

0, R

0

MO

V @

RW

1, R

0

MO

V @

RW

2, R

0

MO

V @

RW

3, R

0

MO

V @

RW

0+, R

0

MO

V @

RW

1+, R

0

MO

V @

RW

2+, R

0

MO

V @

RW

3+, R

0

MO

V

@R

W0+

d8, R

0

MO

V

@R

W1+

d8, R

0

MO

V

@R

W2+

d8, R

0

MO

V

@R

W3+

d8, R

0

MO

V

@R

W4+

d8, R

0

MO

V

@R

W5+

d8, R

0

MO

V

@R

W6+

d8, R

0

MO

V

@R

W7+

d8, R

0

MO

V

@R

W W

0+d1

6, R

0

MO

V

@R

WW

1+d1

6, R

0

MO

V

@R

WW

2+d1

6, R

0

MO

V

@R

WW

3+d1

6, R

0

MO

V

@R

WW

0+R

W7,

R0

MO

V

@R

WW

1+R

W7,

R0

MO

VP

C+

d16,

R0

MO

V

a

add

r16,

R0

MO

V

R0,

R1

MO

V

R1,

R1

MO

V

R2,

R1

MO

V

R3,

R1

MO

V

R4,

R1

MO

V

R5,

R1

MO

V

R6,

R1

MO

V

R7,

R1

MO

V@

RW

0, R

1

MO

V@

RW

1, R

1

MO

V@

RW

2, R

1

MO

V@

RW

3, R

1

MO

V@

RW

0+, R

1

MO

V@

RW

1+, R

1

MO

V@

RW

2+, R

1

MO

V@

RW

3+, R

1

MO

V R

0, R

2

MO

V R

1, R

2

MO

V R

2, R

2

MO

V R

3, R

2

MO

V R

4, R

2

MO

V R

5, R

2

MO

V R

6, R

2

MO

V R

7, R

2

MO

V@

RW

0, R

2

MO

V@

RW

1, R

2

MO

V@

RW

2, R

2

MO

V@

RW

3, R

2

MO

V@

RW

0+, R

2

MO

V@

RW

1+, R

2

MO

V@

RW

2+, R

2

MO

V@

RW

3+, R

2

MO

V

R

0, R

3

MO

V

R

1, R

3

MO

V

R

2, R

3

MO

V

R

3, R

3

MO

V

R

4, R

3

MO

V

R

5, R

3

MO

V

R

6, R

3

MO

V

R

7, R

3

MO

V

@R

W0,

R3

MO

V

@R

W1,

R3

MO

V

@R

W2,

R3

MO

V

@R

W3,

R3

MO

V

@R

W0+

, R3

MO

V

@R

W1+

, R3

MO

V

@R

W2+

, R3

MO

V

@R

W3+

, R3

MO

V

R0,

R4

MO

V

R1,

R4

MO

V

R2,

R4

MO

V

R3,

R4

MO

V

R4,

R4

MO

V

R5,

R4

MO

V

R6,

R4

MO

V

R7,

R4

MO

V@

RW

0, R

4

MO

V@

RW

1, R

4

MO

V@

RW

2, R

4

MO

V@

RW

3, R

4

MO

V@

RW

0+, R

4

MO

V@

RW

1+, R

4

MO

V@

RW

2+, R

4

MO

V@

RW

3+, R

4

MO

V

R0,

R5

MO

V

R1,

R5

MO

V

R2,

R5

MO

V

R3,

R5

MO

V

R4,

R5

MO

V

R5,

R5

MO

V

R6,

R5

MO

V

R7,

R5

MO

V @

RW

0, R

5

MO

V@

RW

1, R

5

MO

V@

RW

2, R

5

MO

V@

RW

3, R

5

MO

V@

RW

0+, R

5

MO

V@

RW

1+, R

5

MO

V@

RW

2+, R

5

MO

V@

RW

3+, R

5

MO

V R

0, R

6

MO

V R

1, R

6

MO

V R

2, R

6

MO

V R

3, R

6

MO

V R

4, R

6

MO

V R

5, R

6

MO

V R

6, R

6

MO

V R

7, R

6

MO

V@

RW

0, R

6

MO

V@

RW

1, R

6

MO

V@

RW

2, R

6

MO

V@

RW

3, R

6

MO

V@

RW

0+, R

6

MO

V@

RW

1+, R

6

MO

V@

RW

2+, R

6

MO

V@

RW

3+, R

6

MO

V

R0,

R7

MO

V

R1,

R7

MO

V

R2,

R7

MO

V

R3,

R7

MO

V

R4,

R7

MO

V

R5,

R7

MO

V

R6,

R7

MO

V

R7,

R7

MO

V @

RW

0, R

7

MO

V @

RW

1, R

7

MO

V @

RW

2, R

7

MO

V @

RW

3, R

7

MO

V@

RW

0+, R

7

MO

V@

RW

1+, R

7

MO

V@

RW

2+, R

7

MO

V@

RW

3+, R

7

MO

V

@

R

W0+

d8, R

1

MO

V

@

R

W1+

d8, R

1

MO

V

@

R

W2+

d8, R

1

MO

V

@

R

W3+

d8, R

1

MO

V

@

R

W4+

d8, R

1

MO

V

@

R

W5+

d8, R

1

MO

V

@

R

W6+

d8, R

1

MO

V

@

R

W7+

d8, R

1

MO

V

@R

W

0+

d16,

R1

MO

V

@R

W

1+

d16,

R1

MO

V

@R

W

2+

d16,

R1

MO

V

@R

W

3+

d16,

R1

MO

V

@R

W

0+

RW

7, R

1

MO

V

@R

W

1+

RW

7, R

1

MO

V M

OV

a

a

ddr1

6, R

1

MO

V

@

R,

W

0+d8

, R2

MO

V

@

R

W1+

d8, R

2

MO

V

@

R

W2+

d8, R

2

MO

V

@

R

W3+

d8, R

2

MO

V

@

R

W4+

d8, R

2

MO

V

@

R

W5+

d8, R

2

MO

V

@

R

W6+

d8, R

2

MO

V

@

R

W7+

d8, R

2

MO

V

@R

W0+

d16,

R2

MO

V

@R

W1+

d16,

R2

MO

V

@R

W2+

d16,

R2

MO

V

@R

W3+

d16,

R2

MO

V

@R

W0+

RW

7, R

2

MO

V

@R

W1+

RW

7, R

2

MO

V

P

C+

d16,

R2

MO

V

a a

ddr1

6, R

2

MO

V

@

R

W

0+d8

, R3

MO

V

@

R

W

1+d8

, R3

MO

V

@

R

W2+

d8, R

3

MO

V

@

R

W

3+d8

, R3

MO

V

@

R

W

4+d8

, R3

MO

V

@

R

W

5+d8

, R3

MO

V

@

R

W

6+d8

, R3

MO

V

@

R

W

7+d8

, R3

MO

V

@R

W 0

+d1

6, R

3

MO

V

@R

W 1

+d1

6, R

3

MO

V

@R

W 2

+d1

6, R

3

MO

V

@R

W 3

+d1

6, R

3

MO

V

@R

W 0

+R

W7,

R3

MO

V

@R

W1+

RW

7, R

3

MO

V

PC

+d1

6, R

3

MO

V

a a

ddr1

6, R

3

MO

V

@

R

W0+

d8, R

4

MO

V

@

R

W1+

d8, R

4

MO

V

@

R,

W

2+d8

, R4

MO

V

@R

,

W3+

d8, R

4

MO

V

@

R

W4+

d8, R

4

MO

V

@R

W

5+d8

, R4

MO

V

@R

W

6+d8

, R4

MO

V

@R

W

7+d8

, R4

MO

V

@R

W 0

+d1

6, R

4

MO

V

@R

W 1

+d1

6, R

4

MO

V

@R

W 2

+d1

6, R

4

MO

V

@R

W 3

+d1

6, R

4

MO

V

@R

W 0

+R

W7,

R4

MO

V

@R

W 1

+R

W7,

R4

MO

VP

C+

d16,

R4

MO

V

a

add

r16,

R4

MO

V

@R

W0+

d8, R

5

MO

V

@R

W

1+d8

, R5

MO

V

@R

W

2+d8

, R5

MO

V

@R

W3+

d8, R

5

MO

V

@R

W

4+d8

, R5

MO

V

@R

W

5+d8

, R5

MO

V

@R

W

6+d8

, R5

MO

V

@R

W7+

d8, R

5

MO

V

@R

W0+

d16,

R5

MO

V

@R

W1+

d16,

R5

MO

V

@R

W2+

d16,

R5

MO

V

@R

W3+

d16,

R5

MO

V

@R

W0+

RW

7, R

5

MO

V

@R

W1+

RW

7, R

5

MO

V

P

C+

d16,

R5

MO

V

a a

ddr1

6, R

5

MO

V

@

R

W0+

d8, R

6

MO

V

@

R

W1+

d8, R

6

MO

V

@

R

W2+

d8, R

6

MO

V

@

R

W3+

d8, R

6

MO

V

@

R

W4+

d8, R

6

MO

V

@

R

W5+

d8, R

6

MO

V

@

R

W6+

d8, R

6

MO

V

@

R

W7+

d8, R

6

MO

V

@R

W

0+d1

6, R

6

MO

V

@R

W 1

+d1

6, R

6

MO

V

@R

W 2

+d1

6, R

6

MO

V

@R

W 3

+d1

6, R

6

MO

V

@R

W 0

+R

W7,

R6

MO

V

@R

W 1

+R

W7,

R6

MO

V

P

C+

d16,

R6

MO

V

a a

ddr1

6, R

6

MO

V

@

R

W0+

d8, R

7

MO

V

@

R

W1+

d8, R

7

MO

V

@

R

W2+

d8, R

7

MO

V

@

R

W3+

d8, R

7

MO

V

@

R

W4+

d8, R

7

MO

V

@

R

W5+

d8, R

7

MO

V

@

R

W6+

d8, R

7

MO

V

@

R

W7+

d8, R

7

MO

V

@R

W 0

+d1

6, R

7

MO

V

@R

W 1

+d1

6, R

7

MO

V

@R

W 2

+d1

6, R

7

MO

V @

RW

3+

d16,

R7

MO

V

@R

W 0

+R

W7,

R7

MO

V

@R

W 1

+R

W7,

R7

MO

V

P

C+d

16, R

7

MO

V

a

addr

16, R

7

PC

+d1

6, R

1

4.3 Instruction Map


Tab

le 4

.3.1

8M

OV

W e

a, R

Wi (

Fir

st b

yte

= 7

DH)

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D

+E

+F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

MO

VW

R

W0

, R

W0

MO

VW

R

W1

, R

W0

MO

VW

R

W2

, R

W0

MO

VW

R

W3

, R

W0

MO

VW

R

W4

, R

W0

MO

VW

R

W5

, R

W0

MO

VW

R

W6

, R

W0

MO

VW

R

W7

, R

W0

MO

VW

@

RW

0,

RW

0

MO

VW

@

RW

1,

RW

0

MO

VW

@

RW

2,

RW

0

MO

VW

@

RW

3,

RW

0

MO

VW

@R

W0+

, R

W0

MO

VW

@R

W1+

, R

W0

MO

VW

@R

W2+

, R

W0

MO

VW

@R

W3+

, R

W0

MO

VW

@

RW

0

+d

8, R

W0

MO

VW

@

RW

1

+d

8, R

W0

MO

VW

@

RW

2

+d

8, R

W0

MO

VW

@

RW

3

+d

8, R

W0

MO

VW

@

RW

4

+d

8, R

W0

MO

VW

@

RW

5

+d

8, R

W0

MO

VW

@

RW

6

+d

8, R

W0

MO

VW

@

RW

7

+d

8, R

W0

MO

VW

@R

W0

+

d1

6, R

W0

MO

VW

@R

W1

+

d1

6, R

W0

MO

VW

@R

W2

+

d1

6, R

W0

MO

VW

@R

W3

+

d1

6, R

W0

MO

VW

@R

W0

+

RW

7, R

W0

MO

VW

@R

W1

+

RW

7,

RW

0

MO

VW

@

PC

+

d

16

, RW

0

MO

VW

ad

dr

16,

RW

0

MO

VW

RW

0, R

W1

MO

VW

RW

1, R

W1

MO

VW

RW

2, R

W1

MO

VW

RW

3, R

W1

MO

VW

RW

4, R

W1

MO

VW

RW

5, R

W1

MO

VW

RW

6, R

W1

MO

VW

RW

7, R

W1

MO

VW

@R

W0

, RW

1

MO

VW

@R

W1

, RW

1

MO

VW

@R

W2

, RW

1

MO

VW

@R

W3

, RW

1

MO

VW

@

RW

0+, R

W1

MO

VW

@

RW

1+, R

W1

MO

VW

@

RW

2+, R

W1

MO

VW

@

RW

3+, R

W1

MO

VW

@

RW

0

+d

8, R

W1

MO

VW

@

R

1+

d8

, RW

1

MO

VW

@

RW

2

+d

8, R

W1

MO

VW

@

RW

3

+d

8, R

W1

MO

VW

@

RW

4

+d

8, R

W1

MO

VW

@

RW

5

+d

8, R

W1

MO

VW

@

RW

6

+d

8, R

W1

MO

VW

@

RW

7

+d

8, R

W1

MO

VW

@R

W0

+

d1

6, R

W1

MO

VW

@R

W1

+

d1

6, R

W1

MO

VW

@R

W2

+

d1

6, R

W1

MO

VW

@R

W3

+

d1

6, R

W1

MO

VW

@R

W0

+R

W7

, RW

1

MO

VW

@R

W1

+R

W7

, RW

1

MO

VW

@

PC

+

d16

, RW

1

MO

VW

ad

dr

16

, R

W1

MO

VW

RW

0,

RW

2

MO

VW

RW

1,

RW

2

MO

VW

RW

2,

RW

2

MO

VW

RW

3,

RW

2

MO

VW

RW

4,

RW

2

MO

VW

RW

5,

RW

2

MO

VW

RW

6,

RW

2

MO

VW

RW

7,

RW

2

MO

VW

@R

W0,

RW

2

MO

VW

@R

W1,

RW

2

MO

VW

@R

W2,

RW

2

MO

VW

@R

W3,

RW

2

MO

VW

@

RW

0+, R

W2

MO

VW

@

RW

1+, R

W2

MO

VW

@

RW

2+, R

W2

MO

VW

@

RW

3+, R

W2

MO

VW

@

RW

0

+d

8, R

W2

MO

VW

@

R

1+

d8,

RW

2

MO

VW

@

RW

2

+d

8, R

W2

MO

VW

@

RW

3

+d

8, R

W2

MO

VW

@

RW

4

+d

8, R

W2

MO

VW

@

RW

5

+d

8, R

W2

MO

VW

@

RW

6

+d

8, R

W2

MO

VW

@

RW

7

+d

8, R

W2

MO

VW

@R

W0

+

d1

6, R

W2

MO

VW

@R

W1

+

d1

6, R

W2

MO

VW

@R

W2

+

d1

6, R

W2

MO

VW

@R

W3

+

d1

6, R

W2

MO

VW

@R

W0

+R

W7,

RW

2

MO

VW

@R

W1

+R

W7,

RW

2

MO

VW

@

PC

+

d

16

, RW

2

MO

VW

ad

dr

16,

RW

2

MO

VW

R

W0,

RW

3

MO

VW

R

W1,

RW

3

MO

VW

R

W2,

RW

3

MO

VW

R

W3,

RW

3

MO

VW

R

W4,

RW

3

MO

VW

R

W5,

RW

3

MO

VW

R

W6,

RW

3

MO

VW

R

W7,

RW

3

MO

VW

@

RW

0, R

W3

MO

VW

@

RW

1, R

W3

MO

VW

@

RW

2, R

W3

MO

VW

@

RW

3, R

W3

MO

VW

@R

W0

+,

RW

3

MO

VW

@R

W1

+,

RW

3

MO

VW

@R

W2

+,

RW

3

MO

VW

@R

W3

+,

RW

3

MO

VW

@

RW

0

+d

8, R

W3

MO

VW

@

RW

1

+d

8, R

W3

MO

VW

@

RW

2

+d

8, R

W3

MO

VW

@

RW

3

+d

8, R

W3

MO

VW

@

RW

4

+d

8, R

W3

MO

VW

@

RW

5

+d

8, R

W3

MO

VW

@

RW

6

+d

8, R

W3

MO

VW

@

RW

7

+d

8, R

W3

MO

VW

@R

W0

+

d16

, R

W3

MO

VW

@R

W1

+

d16

, RW

3

MO

VW

@R

W2

+

d16

, RW

3

MO

VW

@R

W3

+

d16

, RW

3

MO

VW

@R

W0

+R

W7

, RW

3

MO

VW

@R

W1

+R

W7

, RW

3

MO

VW

@

PC

+

d16

, R

W3

MO

VW

ad

dr

1

6, R

W3

MO

VW

RW

0, R

W4

MO

VW

RW

1, R

W4

MO

VW

RW

2, R

W4

MO

VW

RW

3, R

W4

MO

VW

RW

4, R

W4

MO

VW

RW

5, R

W4

MO

VW

RW

6, R

W4

MO

VW

RW

7, R

W4

MO

VW

@R

W0,

RW

4

MO

VW

@R

W1,

RW

4

MO

VW

@R

W2,

RW

4

MO

VW

@R

W3,

RW

4

MO

VW

@

RW

0+

, R

W4

MO

VW

@

RW

1+

, R

W4

MO

VW

@

RW

2+

, R

W4

MO

VW

@

RW

3+

, R

W4

MO

VW

@

RW

0

+d

8, R

W4

MO

VW

@

RW

1

+d

8, R

W4

MO

VW

@

RW

2

+d

8, R

W4

MO

VW

@

RW

3

+d

8, R

W4

MO

VW

@

RW

4

+d

8, R

W4

MO

VW

@

RW

5

+d

8, R

W4

MO

VW

@

RW

6

+d

8, R

W4

MO

VW

@

RW

7

+d

8, R

W4

MO

VW

@R

W0

+

d1

6, R

W4

MO

VW

@R

W1

+

d1

6, R

W4

MO

VW

@R

W2

+

d1

6, R

W4

MO

VW

@R

W3

+

d1

6, R

W4

MO

VW

@R

W0

+R

W7

, RW

4

MO

VW

@R

W1

+R

W7

, RW

4

MO

VW

@

PC

+

d

16

, RW

4

MO

VW

ad

dr

16,

RW

4

MO

VW

R

W0

, RW

5

MO

VW

R

W1

, RW

5

MO

VW

R

W2

, RW

5

MO

VW

R

W3

, RW

5

MO

VW

R

W4

, RW

5

MO

VW

R

W5

, RW

5

MO

VW

R

W6

, RW

5

MO

VW

R

W7

, RW

5

MO

VW

@

RW

0, R

W5

MO

VW

@

RW

1, R

W5

MO

VW

@

RW

2, R

W5

MO

VW

@

RW

3, R

W5

MO

VW

@R

W0

+,

RW

5

MO

VW

@R

W1

+,

RW

5

MO

VW

@R

W2

+,

RW

5

MO

VW

@R

W3

+,

RW

5

MO

VW

@

RW

0+

d8

, R

W5

MO

VW

@

RW

1+

d8

, R

W5

MO

VW

@

RW

2+

d8

, R

W5

MO

VW

@

RW

3+

d8

, R

W5

MO

VW

@

RW

4+

d8

, R

W5

MO

VW

@

RW

5+

d8

, R

W5

MO

VW

@

RW

6+

d8

, R

W5

MO

VW

@

RW

7+

d8

, R

W5

MO

VW

@R

W0

+d1

6,

RW

5

MO

VW

@R

W1

+d1

6,

RW

5

MO

VW

@R

W2

+d1

6,

RW

5

MO

VW

@R

W3

+d1

6,

RW

5

MO

VW

@R

W0

+R

W7

, R

W5

MO

VW

@R

W1

+R

W7

, R

W5

MO

VW

@

PC

+

d1

6,

RW

5

MO

VW

ad

dr

16

, RW

5

MO

VW

RW

0, R

W6

MO

VW

RW

1, R

W6

MO

VW

RW

2, R

W6

MO

VW

RW

3, R

W6

MO

VW

RW

4, R

W6

MO

VW

RW

5, R

W6

MO

VW

RW

6, R

W6

MO

VW

RW

7, R

W6

MO

VW

@R

W0

, RW

6

MO

VW

@R

W1

, RW

6

MO

VW

@R

W2

, RW

6

MO

VW

@R

W3

, RW

6

MO

VW

@R

W0

+,

RW

6

MO

VW

@R

W1

+,

RW

6

MO

VW

@R

W2

+,

RW

6

MO

VW

@R

W3

+,

RW

6

MO

VW

@

RW

0

+d

8, R

W6

MO

VW

@

RW

1

+d

8, R

W6

MO

VW

@

RW

2

+d

8, R

W6

MO

VW

@

RW

3

+d

8, R

W6

MO

VW

@

RW

4

+d

8, R

W6

MO

VW

@

RW

5

+d

8, R

W6

MO

VW

@

RW

6

+d

8, R

W6

MO

VW

@

RW

7

+d

8, R

W6

MO

VW

@R

W0

+

d16

, R

W6

MO

VW

@R

W1

+

d1

6, R

W6

MO

VW

@R

W2

+

d1

6, R

W6

MO

VW

@R

W3

+

d1

6, R

W6

MO

VW

@R

W0

+R

W7

, RW

6

MO

VW

@R

W1

+R

W7

, RW

6

MO

VW

@

PC

+

d16

, RW

6

MO

VW

ad

dr

1

6, R

W6

MO

VW

R

W0

, RW

7

MO

VW

R

W1

, RW

7

MO

VW

R

W2

, RW

7

MO

VW

R

W3

, RW

7

MO

VW

R

W4

, RW

7

MO

VW

R

W5

, RW

7

MO

VW

R

W6

, RW

7

MO

VW

R

W7

, RW

7

MO

VW

@

RW

0,

RW

7

MO

VW

@

RW

1,

RW

7

MO

VW

@

RW

2,

RW

7

MO

VW

@

RW

3,

RW

7

MO

VW

@R

W0

+,

RW

7

MO

VW

@R

W1

+,

RW

7

MO

VW

@R

W2

+,

RW

7

MO

VW

@R

W3

+,

RW

7

MO

VW

@

RW

0+

d8,

RW

7

MO

VW

@

RW

1+

d8,

RW

7

MO

VW

@

RW

2+

d8,

RW

7

MO

VW

@

RW

3+

d8,

RW

7

MO

VW

@

RW

4+

d8,

RW

7

MO

VW

@

RW

5+

d8,

RW

7

MO

VW

@

RW

6+

d8,

RW

7

MO

VW

@

RW

7+

d8,

RW

7

MO

VW

@R

W0

+d

16,

RW

7

MO

VW

@R

W1

+d

16,

RW

7

MO

VW

@R

W2

+d

16,

RW

7

MO

VW

@R

W3

+d

16,

RW

7

MO

VW

@R

W0

+R

W7

, R

W7

MO

VW

@R

W1

+R

W7

, R

W7

MO

VW

@

PC

+

d16

, R

W7

MO

VW

add

r

1

6,

RW

7

4.3 Instruction Map

275

Tab

le 4

.3.1

9C

H R

i, ea

(F

irst

byt

e =

7E

H)

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D

+E

+F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

XC

H

R0,

R0

XC

H

R0,

R1

XC

H

R0,

R2

XC

H

R0,

R3

XC

H

R0,

R4

XC

H

R0,

R5

XC

H

R0,

R6

XC

H

R0,

R7

XC

H R

0, @

RW

0

XC

H R

0, @

RW

1

XC

H R

0, @

RW

2

XC

H R

0, @

RW

3

XC

HR

0, @

RW

0+

XC

HR

0, @

RW

1+

XC

HR

0, @

RW

2+

XC

HR

0, @

RW

3+

XC

H

R

0,

@R

W0+

d8

XC

H

R

0,

@R

W1+

d8

XC

H

R

0,

@R

W2+

d8

XC

H

R

0,

@R

W3+

d8

XC

H

R

0,

@R

W4+

d8

XC

H

R

0,

@R

W5+

d8

XC

H

R

0,

@R

W6+

d8

XC

H

R

0,

@R

W7+

d8

XC

H

R

0,

@R

W0+

d16

XC

H

R

0, @

RW

1+d1

6

XC

H

R

0, @

RW

2+d1

6

XC

H

R

0, @

RW

3+d1

6

XC

H

R

0,@

RW

0+R

W7

XC

H

R

0,@

RW

1+R

W7

XC

H

R

0,

@P

C+

d16

XC

H

R

0,

add

r16

XC

H

R

1, R

0

XC

H

R1,

R1

XC

H

R1,

R2

XC

H

R1,

R3

XC

H

R1,

R4

XC

H

R1,

R5

XC

H

R1,

R6

XC

H

R1,

R7

XC

H

R1,

@R

W0

XC

H

R1,

@R

W1

XC

H

R1,

@R

W2

XC

H

R1,

@R

W3

XC

H R

1, @

RW

0+

XC

H R

1, @

RW

1+

XC

H R

1, @

RW

2+

XC

H R

1, @

RW

3+

XC

H

R2,

R0

XC

H

R2,

R1

XC

H

R2,

R2

XC

H

R2,

R3

XC

H

R2,

R4

XC

H

R2,

R5

XC

H

R2,

R6

XC

H

R2,

R7

XC

H

R2,

@R

W0

XC

H

R2,

@R

W1

XC

H

R2,

@R

W2

XC

H

R2,

@R

W3

XC

H R

2, @

RW

0+

XC

H R

2, @

RW

1+

XC

H R

2, @

RW

2+

XC

H R

2, @

RW

3+

XC

H

R

3, R

0

XC

H

R

3, R

1

XC

H

R

3, R

2

XC

H

R

3, R

3

XC

H

R

3, R

4

XC

H

R

3, R

5

XC

H

R

3, R

6

XC

H

R

3, R

7

XC

H

R

3, @

RW

0

XC

H

R

3, @

RW

1

XC

H

R

3, @

RW

2

XC

H

R

3, @

RW

3

XC

H

R3,

@R

W0+

XC

H

R3,

@R

W1+

XC

H

R3,

@R

W2+

XC

H R

3, @

RW

3+

XC

H

R4,

R0

XC

H

R4,

R1

XC

H

R4,

R2

XC

H

R4,

R3

XC

H

R4,

R4

XC

H

R4,

R5

XC

H

R4,

R6

XC

H

R4,

R7

XC

H

R4,

@R

W0

XC

H

R4,

@R

W1

XC

H

R4,

@R

W2

XC

H

R4,

@R

W3

XC

H R

4, @

RW

0+

XC

H R

4, @

RW

1+

XC

H R

4, @

RW

2+

XC

H R

4, @

RW

3+

XC

H

R5,

R0

XC

H

R5,

R1

XC

H

R5,

R2

XC

H

R5,

R3

XC

H

R5,

R4

XC

H

R5,

R5

XC

H

R5,

R6

XC

H

R5,

R7

XC

H R

5, @

RW

0

XC

H

R5,

@R

W1

XC

H

R5,

@R

W2

XC

H

R5,

@R

W3

XC

H R

5, @

RW

0+

XC

H R

5, @

RW

1+

XC

H R

5, @

RW

2+

XC

H

R5,

@R

W3+

XC

H

R6,

R0

XC

H

R6,

R1

XC

H

R6,

R2

XC

H

R6,

R3

XC

H

R6,

R4

XC

H

R6,

R5

XC

H

R6,

R6

XC

H

R6,

R7

XC

H R

6, @

RW

0

XC

H R

6, @

RW

1

XC

H R

6, @

RW

2

XC

H R

6, @

RW

3

XC

H R

6, @

RW

0+

XC

H R

6, @

RW

1+

XC

H R

6, @

RW

2+

XC

H R

6, @

RW

3+

XC

H

R7,

R0

XC

H

R7,

R1

XC

H

R7,

R2

XC

H

R7,

R3

XC

H

R7,

R4

XC

H

R7,

R5

XC

H

R7,

R6

XC

H

R7,

R7

XC

H

R7,

@R

W0

XC

H

R7,

@R

W1

XC

H

R7,

@R

W2

XC

H

R7,

@R

W3

XC

H R

7, @

RW

0+

XC

H R

7, @

RW

1+

XC

H R

7, @

RW

2+

XC

H R

7, @

RW

3+

XC

H

R

1,

@R

W0+

d8

XC

H

R

1,

@R

W1+

d8

XC

H

R

1,

@R

W2+

d8

XC

H

R

1,

@R

W3+

d8

XC

H

R

1,

@R

W4+

d8

XC

H

R

1,

@R

W5+

d8

XC

H

R

1,

@R

W6+

d8

XC

H

R

1,

@R

W7+

d8

XC

H

R

1, @

RW

0+d1

6

XC

H

R

1, @

RW

1+d1

6

XC

H

R

1, @

RW

2+d1

6

XC

H

R

1, @

RW

3+d1

6

XC

H

R

1,@

RW

0+R

W7

XC

H

R

1, @

RW

1+R

W7

XC

H

R

1, X

CH

R1,

add

r16

XC

H

R

2,

@

RW

0+d8

XC

H

R

2,

@

RW

1+d8

XC

H

R

2,

@

RW

2+d8

XC

H

R

2,

@

RW

3+d8

XC

H

R

2,

@

RW

4+d8

XC

H

R

2,

@

RW

5+d8

XC

H

R

2,

@

RW

6+d8

XC

H

R

2,

@

RW

7+d8

XC

H

R

2,

@R

W0+

d16

XC

H

R

2,

@R

W1+

d16

XC

H

R

2,

@R

W2+

d16

XC

H

R

2,

@R

W3+

d16

XC

H

R

2,

@R

W0+

RW

7

XC

H

R

2,

@R

W1+

RW

7

XC

H

R

2,

@P

C+d

16

XC

H

R

2,

add

r16

XC

H

R

3,

@

RW

0+d8

XC

H

R

3,

@

RW

1+d8

XC

H

R

3,

@

RW

2+d8

XC

H

R

3,

@

RW

3+d8

XC

H

R

3,

@

RW

4+d8

XC

H

R

3,

@

RW

5+d8

XC

H

R

3,

@

RW

6+d8

XC

H

R

3,

@

RW

7+d8

XC

H

R

3,

@R

W0+

d16

XC

H

R

3,

@R

W1+

d16

XC

H

R

3,

@R

W2+

d16

XC

H

R

3,

@R

W3+

d16

XC

H

R

3,

@R

W0+

RW

7

XC

H

R

3,

@R

W1+

RW

7

XC

H

R

3,

@P

C+d

16

XC

H

R

3, a

ddr1

6

XC

H

R

4,

@R

W0+

d8

XC

H

R

4,

@R

W1+

d8

XC

H

R

4,

@R

W2+

d8

XC

H

R

4,

@R

W3+

d8

XC

H

R

4,

@R

W4+

d8

XC

H

R

4,

@R

W5+

d8

XC

H

R

4,

@R

W6+

d8

XC

H

R

4,

@R

W7+

d8

XC

H

R

4, @

RW

0+d1

6

XC

H

R

4, @

RW

1+d1

6

XC

H

R

4, @

RW

2+d1

6

XC

H

R

4, @

RW

3+d1

6

XC

H

R

4,@

RW

0+R

W7

XC

H

R

4,@

RW

1+R

W7

XC

H

R

4,

@P

C+

d16

XC

H

R

4,

add

r16

XC

H

R

5,

@R

W0+

d8

XC

H

R

5,

@R

W1+

d8

XC

H

R

5,

@R

W2+

d8

XC

H

R

5,

@R

W3+

d8

XC

H

R

5,

@R

W4+

d8

XC

H

R

5,

@R

W5+

d8

XC

H

R

5,

@R

W6+

d8

XC

H

R

5,

@R

W7+

d8

XC

H

R

5,

@R

W0+

d16

XC

H

R

5,

@R

W1+

d16

XC

H

R

5,

@R

W2+

d16

XC

H

R

5,

@R

W3+

d16

XC

H

R

5,

@R

W0+

RW

7

XC

H

R

5,

@R

W1+

RW

7

XC

H

R

5,

@P

C+

d16

XC

H

R

5,

a

ddr1

6

XC

H

R

6,

@R

W0+

d8

XC

H

R

6,

@R

W1+

d8

XC

H

R

6,

@R

W2+

d8

XC

H

R

6,

@R

W3+

d8

XC

H

R

6,

@R

W4+

d8

XC

H

R

6,

@R

W5+

d8

XC

H

R

6,

@R

W6+

d8

XC

H

R

6,

@R

W7+

d8

XC

H

R

6, @

RW

0+d1

6

XC

H

R

6, @

RW

1+d1

6

XC

H

R

6, @

RW

2+d1

6

XC

H

R

6, @

RW

3+d1

6

XC

H

R

6,@

RW

0+R

W7

XC

H

R

6,@

RW

1+R

W7

XC

H

R

6, @

PC

+d1

6

XC

H

R

6,

add

r16

XC

H

R

7,

@R

W0+

d8

NO

TW

R7,

@

RW

1+d8

XC

H

R

7,

@R

W2+

d8

NO

TW

R7,

@

RW

3+d8

NO

TW

R7,

@

RW

4+d8

XC

H

R

7,

@R

W5+

d8

XC

H

R

7,

@R

W6+

d8

XC

H

R

7,

@R

W7+

d8

XC

H

R

7, @

RW

0+d1

6

XC

H

R

7, @

RW

1+d1

6

XC

H

R

7, @

RW

2+d1

6

XC

H

R

7, @

RW

3+d1

6

XC

H

R

7, @

RW

0+R

W7

XC

H

R

7,@

RW

1+R

W7

XC

H

R

7,@

PC

+d16

XC

H

R

7,

add

r16

@P

C+d

16

4.3 Instruction Map


Tab

le 4

.3.2

0X

CH

W R

Wi,

ea (

Fir

st b

yte

= 7F

H)

+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

XC

HW

RW

0, R

W0

XC

HW

RW

0, R

W1

XC

HW

RW

0, R

W2

XC

HW

RW

0, R

W3

XC

HW

RW

0, R

W4

XC

HW

RW

0, R

W5

XC

HW

RW

0, R

W6

XC

HW

RW

0, R

W7

XC

HW

RW

0, @

RW

0

XC

HW

RW

0, @

RW

1

XC

HW

RW

0, @

RW

2

XC

HW

RW

0, @

RW

3

XC

HW

RW

0, @

RW

0+

XC

HW

R W

0, @

RW

1+

XC

HW

RW

0, @

RW

2+

XC

HW

RW

0, @

RW

3+

XC

HW

R

W0,

@

RW

0+d8

XC

HW

R

W0,

@

RW

1+d8

XC

HW

R

W0,

@

RW

2+d8

XC

HW

R

W0,

@

RW

3+d8

XC

HW

R

W0,

@

RW

4+d8

XC

HW

R

W0,

@

RW

5+d8

XC

HW

R

W0,

@

RW

6+d8

XC

HW

R

W0,

@

RW

7+d8

XC

HW

R

W0,

@

RW

0+d1

6

XC

HW

R

W0,

@R

W1+

d16

XC

HW

R

W0,

@R

W2+

d16

XC

HW

R

W0,

@R

W3+

d16

XC

HW

R

W0,

@R

W0+

RW

7

XC

HW

R

W0,

@R

W1+

RW

7

XC

HW

RW

0,

@P

C +

d16

XC

HW

R

W0,

add

r16

XC

HW

R

W1,

RW

0

XC

HW

R

W1,

RW

1

XC

HW

R

W1,

RW

2

XC

HW

R

W1,

RW

3

XC

HW

R

W1,

RW

4

XC

HW

R

W1,

RW

5

XC

HW

R

W1,

RW

6

XC

HW

R

W1,

RW

7

XC

HW

RW

1, @

RW

0

XC

HW

RW

1, @

RW

1

XC

HW

RW

1, @

RW

2

XC

HW

RW

1, @

RW

3

XC

HW

RW

1, @

RW

0+

XC

HW

RW

1, @

RW

1+

XC

HW

RW

1, @

RW

2+

XC

HW

RW

1, @

RW

3+

XC

HW

RW

2, R

W0

XC

HW

RW

2, R

W1

XC

HW

RW

2, R

W2

XC

HW

RW

2, R

W3

XC

HW

RW

2, R

W4

XC

HW

RW

2, R

W5

XC

HW

RW

2, R

W6

XC

HW

RW

2, R

W7

XC

HW

RW

2, @

RW

0

XC

HW

RW

2, @

RW

1

XC

HW

RW

2, @

RW

2

XC

HW

RW

2, @

RW

3

XC

HW

RW

2, @

RW

0+

XC

HW

RW

2, @

RW

1+

XC

HW

RW

2, @

RW

2+

XC

HW

RW

2, @

RW

3+

XC

HW

R

W3,

RW

0

XC

HW

R

W3,

RW

1

XC

HW

R

W3,

RW

2

XC

HW

R

W3,

RW

3

XC

HW

R

W3,

RW

4

XC

HW

R

W3,

RW

5

XC

HW

R

W3,

RW

6

XC

HW

R

W3,

RW

7

XC

HW

R

W3,

@R

W0

XC

HW

R

W3,

@R

W1

XC

HW

R

W3,

@R

W2

XC

HW

R

W3,

@R

W3

XC

HW

RW

3, @

RW

0+

XC

HW

RW

3, @

RW

1+

XC

HW

RW

3, @

RW

2+

XC

HW

RW

3, @

RW

3+

XC

HW

RW

4, R

W0

XC

HW

RW

4, R

W1

XC

HW

RW

4, R

W2

XC

HW

RW

4, R

W3

XC

HW

RW

4, R

W4

XC

HW

RW

4, R

W5

XC

HW

RW

4, R

W6

XC

HW

RW

4, R

W7

XC

HW

RW

4, @

RW

0

XC

HW

RW

4, @

RW

1

XC

HW

RW

4, @

RW

2

XC

HW

RW

4, @

RW

3

XC

HW

RW

4, @

RW

0+

XC

HW

RW

4, @

RW

1+

XC

HW

RW

4, @

RW

2+

XC

HW

RW

4, @

RW

3+

XC

HW

RW

5, R

W0

XC

HW

RW

5, R

W1

XC

HW

RW

5, R

W2

XC

HW

RW

5, R

W3

XC

HW

RW

5, R

W4

XC

HW

RW

5, R

W5

XC

HW

RW

5, R

W6

XC

HW

RW

5, R

W7

XC

HW

RW

5, @

RW

0

XC

HW

RW

5, @

RW

1

XC

HW

RW

5, @

RW

2

XC

HW

RW

5, @

RW

3

XC

HW

RW

5, @

RW

0+

XC

HW

RW

5, @

RW

1+

XC

HW

RW

5, @

RW

2+

XC

HW

RW

5, @

RW

3+

XC

HW

R

W6,

RW

0

XC

HW

RW

6, R

W1

XC

HW

RW

6, R

W2

XC

HW

RW

6, R

W3

XC

HW

RW

6, R

W4

XC

HW

RW

6, R

W5

XC

HW

RW

6, R

W6

XC

HW

RW

6, R

W7

XC

HW

RW

6, @

RW

0

XC

HW

RW

6, @

RW

1

XC

HW

RW

6, @

RW

2

XC

HW

RW

6, @

RW

3

XC

HW

RW

6, @

RW

0+

XC

HW

RW

6, @

RW

1+

XC

HW

RW

6, @

RW

2+

XC

HW

RW

6, @

RW

3+

XC

HW

R

W7,

RW

0

XC

HW

R

W7,

RW

1

XC

HW

R

W7,

RW

2

XC

HW

R

W7,

RW

3

XC

HW

R

W7,

RW

4

XC

HW

R

W7,

RW

5

XC

HW

R

W7,

RW

6

XC

HW

R

W7,

RW

7

XC

HW

RW

7, @

RW

0

XC

HW

RW

7, @

RW

1

XC

HW

RW

7, @

RW

2

XC

HW

RW

7, @

RW

3

XC

HW

RW

7, @

RW

0+

XC

HW

RW

7, @

RW

1+

XC

HW

RW

7, @

RW

2+

XC

HW

RW

7, @

RW

3+

XC

HW

R

W1,

@

RW

0+d8

XC

HW

R

W1,

@

RW

1+d8

XC

HW

R

W1,

@

RW

2+d8

XC

HW

R

W1,

@

RW

3+d8

XC

HW

R

W1,

@

RW

4+d8

XC

HW

R

W1,

@

RW

5+d8

XC

HW

R

W1,

@

RW

6+d8

XC

HW

R

W1,

@

RW

7+d8

XC

HW

R

W1,

@R

W0+

d16

XC

HW

R

W1,

@R

W1+

d16

XC

HW

R

W1,

@R

W2+

d16

XC

HW

R

W1,

@R

W3+

d16

XC

HW

R

W1,

@R

W0+

RW

7

XC

HW

R

W1,

@R

W1+

RW

7

XC

HW

R

W1,

XC

HW

R

W1,

add

r16

XC

HW

R

W2,

@R

W0+

d8

XC

HW

R

W2,

@R

W1+

d8

XC

HW

R

W2,

@R

W2+

d8

XC

HW

R

W2,

@R

W3+

d8

XC

HW

R

W2,

@R

W4+

d8

XC

HW

R

W2,

@R

W5+

d8

XC

HW

R

W2,

@R

W6+

d8

XC

HW

R

W2,

@R

W7+

d8

XC

HW

R

W2,

@

RW

0+d1

6

XC

HW

R

W2,

@

RW

1+d1

6

XC

HW

R

W2,

@

RW

2+d1

6

XC

HW

R

W2,

@

RW

3+d1

6

XC

HW

R

W2,

@

RW

0+R

W7

XC

HW

R

W2,

@

RW

1+R

W7

XC

HW

R

W2,

@

PC

+d16

XC

HW

R

W2,

ad

dr16

XC

HW

R

W3,

@R

W0+

d8

XC

HW

R

W3,

@R

W1+

d8

XC

HW

R

W3,

@R

W2+

d8

XC

HW

R

W3,

@R

W3+

d8

XC

HW

R

W3,

@R

W4+

d8

XC

HW

R

W3,

@R

W5+

d8

XC

HW

R

W3,

@R

W6+

d8

XC

HW

R

W3,

@R

W7+

d8

XC

HW

R

W3,

@

RW

0+d1

6

XC

HW

R

W3,

@

RW

1+d1

6

XC

HW

R

W3,

@

RW

2+d1

6

XC

HW

R

W3,

@

RW

3+d1

6

XC

HW

R

W3,

@

RW

0+R

W7

XC

HW

R

W3,

@

RW

1+R

W7

XC

HW

R

W3,

@

PC

+d16

XC

HW

R

W3,

a

ddr1

6

XC

HW

R

W4,

@

RW

0+d8

XC

HW

R

W4,

@

RW

1+d8

XC

HW

R

W4,

@

RW

2+d8

XC

HW

R

W4,

@

RW

3+d8

XC

HW

R

W4,

@

RW

4+d8

XC

HW

R

W4,

@

RW

5+d8

XC

HW

R

W4,

@

RW

6+d8

XC

HW

R

W4,

@

RW

7+d8

XC

HW

R

W4,

@R

W0+

d16

XC

HW

R

W4,

@R

W1+

d16

XC

HW

R

W4,

@R

W2+

d16

XC

HW

R

W4,

@R

W3+

d16

XC

HW

R

W4,

@R

W0+

RW

7

XC

HW

R

W4,

@R

W1+

RW

7

XC

HW

R

W4,

@

PC

+d16

XC

HW

R

W4,

a

ddr1

6

XC

HW

RW

5,

@R

W0+

d8

XC

HW

RW

5,

@R

W1+

d8

XC

HW

RW

5,

@R

W2+

d8

XC

HW

RW

5,

@R

W3+

d8

XC

HW

RW

5,

@R

W4+

d8

XC

HW

RW

5,

@R

W5+

d8

XC

HW

RW

5,

@R

W6+

d8

XC

HW

RW

5,

@R

W7+

d8

XC

HW

RW

5,

@R

W0+

d16

XC

HW

RW

5,

@R

W1+

d16

XC

HW

RW

5,

@R

W2+

d16

XC

HW

RW

5,

@R

W3+

d16

XC

HW

RW

5,

@R

W0+

RW

7

XC

HW

RW

5,

@R

W1+

RW

7

XC

HW

RW

5,

@P

C+d

16

XC

HW

R

W5,

addr

16

XC

HW

RW

6,

@R

W0+

d8

XC

HW

RW

6,

@R

W1+

d8

XC

HW

RW

6,

@R

W2+

d8

XC

HW

RW

6,

@R

W3+

d8

XC

HW

RW

6,

@R

W4+

d8

XC

HW

RW

6,

@R

W5+

d8

XC

HW

RW

6,

@R

W6+

d8

XC

HW

RW

6,

@R

W7+

d8

XC

HW

RW

6, @

RW

0+d1

6

XC

HW

RW

6, @

RW

1+d1

6

XC

HW

RW

6, @

RW

2+d1

6

XC

HW

RW

6, @

RW

3+d1

6

XC

HW

RW

6, @

RW

0+R

W7

XC

HW

RW

6, @

RW

1+R

W7

XC

HW

RW

6, @

PC

+d16

XC

HW

R

W6,

add

r16

XC

HW

R

W7,

@

RW

0+d8

XC

HW

R

W7,

@

RW

1+d8

XC

HW

R

W7,

@

RW

2+d8

XC

HW

R

W7,

@

RW

3+d8

XC

HW

R

W7,

@

RW

4+d8

XC

HW

R

W7,

@

RW

5+d8

XC

HW

R

W7,

@

RW

6+d8

XC

HW

R

W7,

@

RW

7+d8

XC

HW

R

W7,

@R

W0+

d16

XC

HW

R

W7,

@R

W1+

d16

XC

HW

R

W7,

@R

W2+

d16

XC

HW

R

W7,

@R

W3+

d16

XC

HW

R

W7,

@R

W0+

RW

7

XC

HW

R

W7,

@R

W1+

RW

7

XC

HW

R

W7,

@P

C+

d16

XC

HW

R

W7,

a

ddr1

6

@P

C+d

16

5.1 Features

277

Chapter 5:MB90P663A Specifications

The MB90P663A is the one-time PROM version of the MB90660Aseries.

5.1 Features

• 48Kbyte PROM

• Option setting using PROM writer.

• In PROM mode (writing with PROM writer) functions as equivalent to MBM27C1000A.

5.2 PROM Writing Sequence

The MB90P663A in PROM mode has functions equivalent to the MBM27C1000A, and can be connected by appropriately adapter socket for programming with a general-purpose PROM writer.

(1) Set the PROM writer for MBM27C1000A mode.

(2) Load program data to PROM write addresses 1400H to 1FFFFH. When the MB90P6633A is in operating mode, its ROM addresses FF4000H to FFFFFFH correspond to PROM mode addresses 14000H to 1FFFFH.

(3) Place the MB90P663A chip into the adapter socket, and mount the adapter socket onto the PROM writer. Be sure that the device and adapter socket are properly oriented.

(4) Start write operation.

Note 1: Caution is required during setup because option PROM data can be viewed in the area 00000H to 001FH in PROM mode. (See the PROM option bit map in section 5.3.) All addresses not allocated in the program area or the option bit map must be set to ‘FFH’.

* The mask ROM versions (MB90663A/2A) have no PROM mode, and therefore cannot read data from the PROM writer.

(Note 1)

Values must be

Operating mode PROM mode

PROM

1FFFFH

14000H

PROM

FFFFFFH

FF4000H

0001FH

00000HOPTION PROM

set to ‘1’

5.3 PROM Option Settings

278 Chapter 5: MB90P663A Specifications


PROM option writing is performed in the same way as PROM writing, by writing values to designated addresses on the memory map. The following bit map shows the relation between each bit and option setting.

• PROM Option Bit Map

*AU bits have the initial value (when blank) of ‘l.’

Note 1: In the MB90660A series, all pins for which pull-up options are selected are cut off from pull-up resistance in stop mode. (These correspond to circuit type B and E in the “Pin Function Description.”) Note however that pins P44 to P47, RSTX,

D’ITI (corresponding to circuit types D, G in the “Pin Function Description.”) and pins MD1, MD0 are not cut off from pull-up resistance in stop mode.

Note 2: The following table shows the use of pun-up/down resistance with pins MD2, MD1, MD0. Pull-up/down resistance selections apply to all of the two (or three) pins in this set.

Pull-up/down resistance cannot be selected separately for the mode pins MD2, MD1, MD0.

Bit 7 6 5 4 3 2 1 0

00004H P07 Pull-up1 :None0 :Yes

P06 Pull-up1 :None0 :Yes















0000CH P27 Pull-up1 :None0 :Yes
















00014H

Note 1P47 Pull-up1 :None0 :Yes




RSTX Pull-up1 :None0 :Yes

DTTI Pull-up1 :None0 :Yes

Asynchronous receiving of reset signal.

Pull-up1 :None0 :Yes

MD1/MD0 Pull-up1 :None0 :Yes

00018H

Empty









279

Note 3: Addresses not defined in the above tables must be set to the value ‘FFH’

Note 4: The MB90P663A requires eight machine cycles for option setting, and no option settings can be made at power-on until the clock signal feed is provided. (The initial setting is for no pull-up, resistance on all pins, with asynchronous receiving of reset signal input.)

Pin MB90P663A MB90663A/2A MB90V660A

MD2 NonePull-down selection available

None

MD1Pull-up selection available

Pull-up selection available

None

MD0Pull-up selection available

Pull-up selection available

None

Date post:	22-Apr-2020
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