F6 – Basic Circuits

ETIN70 – Modern Electronics: F6 – Basic Circuits

Reading GuideOutline

Problems

Sedra/Smith 7ed int

Sedra/Smith 7ed int

F6 – Basic Circuits

1

• Chapter 1.1-1.6 (circuit analysis recap)

• Chapter 2 (op amp)

• Chapter 3.3 (load line)

• Chapter 13.1 (basic filters)

Lars Ohlsson Fhager

• (P1.6, 1.10, 1.16, 1.21, 1.23, 1.28, 1.59,

1.62, 1.63 for recap of circuit analysis)

• P2.5, 2.20, 2.80

• Elementary components

• Signals (current and voltage) and sources

• Power, matching, efficiency

• Ideal operational amplifier (op amp)

• Ideal characteristics

• Circuit configurations

• Real op amp

• Imperfections

• Example schematic of an IC op amp

• Keysight ADS

2019-09-19


Elementary Components

• Passive sign convention (PSC) for electric energy, 𝑊, voltage, 𝑣, and current, 𝑖

• Energy flows into component: positive power, 𝑃 =𝜕𝑊

𝜕𝑡= 𝑖𝑣 > 0

• Energy flows out of component: negative power, 𝑃 =𝜕𝑊

𝜕𝑡= 𝑖𝑣 < 0

• Passive lossy components dissipate energy

• Resistance (Ohm’s law), 𝑣 = 𝑅𝑖 (and 𝑃 =𝑣2

𝑅)

• Conductance, 𝑖 = 𝐺𝑣 (and 𝑃 =𝑖2

𝐺)

• Passive reactive components store (and return) energy

• Inductance, 𝑣 =𝜕Φ

𝜕𝑖

𝜕𝑖

𝜕𝑡= 𝐿

𝜕𝑖

𝜕𝑡(stored energy 𝑊 = 𝐿 𝑣 𝑖 𝜕𝑖 =

𝐿

2𝑖2)

• Capacitance, 𝑖 =𝜕𝑄

𝜕𝑣

𝜕𝑣

𝜕𝑡= 𝐶

𝜕𝑣

𝜕𝑡(stored energy 𝑊 = 𝐶 𝑣 𝑣 𝜕𝑣 =

𝐶

2𝑣2)

2

𝑖 =𝑄

𝑡𝑣 = 𝑢+ − 𝑢−


Ohm’s Law, Impedance, and Admittance

• Ohm’s law

• Frequency domain immittances (impedance or admittance)

• Impedance, 𝑍 =𝑣 𝑗𝜔

𝑖 𝑗𝜔= 𝑅 + 𝑗𝜔𝐿 = 𝑅 + 𝑗𝑋,

𝑅 denotes resistance and 𝑋 reactance

• Admittance, 𝑌 =𝑖 𝑗𝜔

𝑣 𝑗𝜔= 𝐺 + 𝑗𝜔𝐶 = 𝐺 + 𝑗𝐵,

𝐺 denotes conductance and 𝐵 susceptance

• Generalised signal relations

3

𝑣 = 𝑅𝑖 =𝑖

𝐺⇔ 𝑖 = 𝐺𝑣 =

𝑣

𝑅

𝑣 = 𝑅𝑖 + 𝐿𝜕𝑖

𝜕𝑡⇔ 𝑖 = 𝐺𝑣 + 𝐶

𝜕𝑣

𝜕𝑡Laplace Transform

𝑣 = 𝑍𝑖 =𝑖

𝑌⇔ 𝑖 = 𝑌𝑣 =

𝑣

𝑍

Impedance and admittance

are duals: 𝒁 = 𝟏/𝒀


Kirchhoff’s Circuit Laws

• Kirchhoff’s voltage law (KVL)

• Net loop voltage is zero (energy conservation)

• Kirchhoff’s current law (KCL)

• Net node current is zero (charge conservation)

4

Kirchhoff’s laws are the foundation for circuit analysis.


Series & Parallel Connection, Voltage Division, Current Branching

• Component and circuit laws yield…

• Parallel and series connection formulas

• Voltage division by impedance fraction

• Current branching by admittance fraction

5

𝑣𝑜 =𝑍𝐿

𝑍𝑠𝑒𝑟𝑖𝑒𝑠𝑣𝑖 , where 𝑍𝑠𝑒𝑟𝑖𝑒𝑠 = 𝑍1 + 𝑍2…+ 𝑍𝐿 =

1

𝑌𝑠𝑒𝑟𝑖𝑒𝑠

𝑖𝑜 =𝑌𝐿

𝑌𝑝𝑎𝑟𝑎𝑙𝑙𝑒𝑙𝑖𝑖 , where 𝑌𝑝𝑎𝑟𝑎𝑙𝑙𝑒𝑙 = 𝑌1 + 𝑌2…+ 𝑌𝐿 =

1

𝑍𝑝𝑎𝑟𝑎𝑙𝑙𝑒𝑙

Yields from KCL and KVL.


Single Time Constant (STC) Networks

• Work on board, also available in lecture notes…

6


Single Time Constant (STC) Networks

• Voltage low pass STC networks

• Transfer function, 𝑇 𝑗𝜔 =𝑣𝑜 𝑗𝜔

𝑣𝑖 𝑗𝜔=

𝐾

1+𝑗𝜔/𝜔0= 𝐾

1−𝑗𝜔/𝜔0

1+ 𝜔/𝜔02,

where 𝜏 = 1/𝜔0 = 𝑅𝐶 or 𝐿/𝑅 denotes the time constant

and 𝐾 is the gain at low frequency

• Voltage high pass STC networks

• Transfer function, 𝑇 𝑗𝜔 =𝑣𝑜 𝑗𝜔

𝑣𝑖 𝑗𝜔=

𝐾

1−𝑗𝜔0/𝜔= 𝐾

1+𝑗𝜔0/𝜔

1+ 𝜔0/𝜔2,

where 𝜏 = 1/𝜔0 = 𝑅𝐶 or 𝐿/𝑅 denotes the time constant

and 𝐾 is the gain at high frequency

7

Replacing the capacitor with an inductor in a low pass

network produces a high pass, and vice versa.


Signal Sources – Equivalent Models

• Active source components generate energy

• Thevenin (voltage) source

• Ideal voltage source

• Series resistor

• Norton (current) source

• Ideal current source

• Parallel (shunt) resistor

• Equivalent representations

• Open-circuit voltage, 𝑣𝑜𝑐 = 𝑣𝑠 = 𝑅𝑠𝑖𝑠• Short-circuit current, 𝑖𝑠𝑐 = 𝑖𝑠 = 𝑣𝑠/𝑅𝑠

8

Thevenin and Norton sources are related via Ohm’s law, where

their resistance is invariant and relates the ideal sources.


Given a (Thevenin/ Norton) source, how to select load resistance…

• …to maximize load voltage?

• …to maximize load current?

• …to maximize load power (product of voltage and current)?

9


Maximum Power Transfer Theorem


10


Maximum Power Transfer Theorem

• Thevenin (or Norton) source-load power flow (note: rms signal 𝑣𝑠 =ො𝑣𝑠

2if harmonic sinusoidal)

• Power generated in ideal source, 𝑃𝑠 = 𝑣𝑠 −𝑖𝑠• Power delivered to load resistance, 𝑃𝐿 = 𝑣𝐿𝑖𝑠 (Thevenin source injects all current into load)

• Power dissipated in source resistance, 𝑃𝑑𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑒𝑑 = 𝑃𝑠 – 𝑃𝐿 (power conservation)

• How to match (maximum) available power from source, 𝑃𝑎𝑣𝑠, into load?

• Optimize 𝑃𝐿 w.r.t. 𝑅𝐿 by

𝑓′ =𝜕

𝜕𝑅𝐿𝑃𝐿 = 0 ⇒ 𝑅𝐿 = 𝑅𝑠 (or 𝑍𝐿 = 𝑍𝑠

∗ if complex)

• Identify optimum (max or min?) 𝑃𝐿 w.r.t. 𝑅𝐿 by

𝑓′′ =𝜕2

𝜕𝑅𝐿2 𝑃𝐿 ⇒ ȁ𝑓′′ 𝑅𝐿=𝑅𝑠 < 0, i.e. maximum

• Available power from source

11

Complex conjugate matching maximises

power transfer from source to load.

𝑃𝑎𝑣𝑠 = max 𝑃𝐿 = 𝑃𝐿 𝑍𝐿 = 𝑍𝑠∗ =

𝑣𝑠2

4Re 𝑍𝑠


Common and Differential Mode Signals

• Two signal sources

• 𝑣1: reference voltage

• 𝑣2: reference voltage and an interesting signal component

• Differential mode signal component, 𝑣𝑑 = 𝑣2 − 𝑣1• Typically the “interesting” part of the signal

• Common mode signal component, 𝑣𝑐𝑚 =1

2𝑣1 + 𝑣2

• Typically not desired

• Voltage gain and common mode rejection ratio (CMRR)

• Two-input amplification, 𝑣𝑜 = 𝐴𝑑 𝑣2 − 𝑣1 + 𝐴𝑐𝑚𝑣1+𝑣2

2

• Differential to common mode power gain ratio,

𝐶𝑀𝑅𝑅 = 20 log10𝐴𝑑

𝐴𝑐𝑚

12


Linear Circuit Analysis Techniques

• Simplify sub-circuits

• Voltage division and current branching

• Series impedance and parallel admittance

• Thevenin and Norton source theorems

• Kirchhoff’s laws: nodal analysis by KCL or

loop (mesh) analysis by KVL

• Linear equations system

• Super nodes/ loops

• Dependent nodes/ loops

• Superposition

• Treat one independent source at a time

• Sum up the responses

13

𝑣1 − 𝑣𝑠𝑅1

+𝑣1 − 𝑣2𝑅2

+𝑣1 − 𝑣3𝑍 + 1/𝑌

= 0

𝑣2𝑅3

+𝑣2 − 𝑣1𝑅2

+𝑣2 − 𝑣31/𝑗𝜔𝐶

= 0

𝑔𝑚𝑣1 +𝑣3 − 𝑣1𝑍 + 1/𝑌

+𝑣3 − 𝑣21/𝑗𝜔𝐶

= 0


Non-Linear Circuit Analysis Techniques


14


Non-Linear Circuit Analysis Techniques

• Static load line analysis

• One or many equal non-linear devices

• Typically for finding device bias conditions

• Graphical

• Manual iterative analysis (works but not very fun)

• Numerical analysis

• Automatic iterative analysis using a computer program (ADS, Cadence, Spice, Qucs, …)

• Pros

• Arbitrarily large circuits can be solved rather quickly

• Cons

• Requires device models that are accurate and well behaved

15

We will explore numerical circuit analysis using

Keysight ADS in a circuit simulation project.


Amplifiers

• Amplification of signals (voltage or current) from input to output

• May, or may not, have a common terminal

• May, or may not, show power gain

• Source and load impedances typically affect performance

16


Four Amplifier Types – Equivalent Models


17


Four Amplifier Types – Equivalent Models

• Two signal types – four gain concepts

• Open circuit voltage gain, 𝑣𝑜 = 𝐴𝑣𝑜𝑣𝑖• Short circuit current gain, 𝑖𝑜 = 𝐴𝑖𝑠𝑖𝑖• Short circuit transconductance, 𝑖𝑜 = 𝐺𝑚𝑣𝑖• Open circuit transresistance, 𝑣𝑜 = 𝑅𝑚𝑖𝑖

• Port (input/ output) resistances invariant

(cf. Thevenin and Norton theorems)

• Ideal input and output resistance values

• Voltage input, 𝑅𝑖 = ∞

• Current input, 𝑅𝑖 = 0

• Voltage output, 𝑅𝑜 = 0

• Current output, 𝑅𝑜 = ∞

18

𝑅𝑖𝐴𝑣𝑜 = 𝐴𝑖𝑠𝑅𝑜 = 𝑅𝑖𝐺𝑚𝑅𝑜 = 𝑅𝑚

BJT

MOSFET


Power Supply and Efficiency

• Power flow through active devices

• DC power supply, 𝑃𝑆 = σ𝑉𝑆𝐼𝑆 = 𝑉𝐷𝐷𝐼𝐷𝐷 + 𝑉𝑆𝑆𝐼𝑆𝑆

• Input power, 𝑃𝐼 =𝑣𝐼2

𝑅𝑖𝑛

• Output power, 𝑃𝐿 =𝑣𝑂2

𝑅𝐿

• Dissipated power (heat), 𝑃𝑑𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑒𝑑

• Power conservation, 𝑃𝑆 + 𝑃𝐼 = 𝑃𝐿 + 𝑃𝑑𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑒𝑑

• Power efficiency metrics (NOT IN BOOK)

• Power efficiency (a.k.a. drain efficiency), 𝜂 =𝑃𝐿

𝑃𝑆

• Power added efficiency (PAE), 𝑃𝐴𝐸 =𝑃𝐿−𝑃𝐼

𝑃𝑆= 𝜂

𝐺−1

𝐺

• Total power efficiency, 𝜂𝑡𝑜𝑡𝑎𝑙 =𝑃𝐿−𝑃𝐼

𝑃𝐼+𝑃𝑆

19

𝑃𝐼 𝑃𝐿

𝑃𝑑𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑒𝑑

𝑃𝑆

MOSFET circuits use VDD and VSS whereas BJT circuits

use VCC and VEE to denote voltage supplies.


BREAK

20


Ideal Operational Amplifier (Op Amp)


21


Ideal Operational Amplifier (Op Amp)

• Op amp = differential voltage amplifier for feedback applications

• Ideal characteristics (approximately true for an op amp at low frequencies)

• Infinite input impedance, 𝑅𝑖 = 𝑣𝑖/𝑖𝑖 = 𝑖𝑖 = 0 = ∞

• Zero output impedance, 𝑅𝑜 = 𝑣𝑜/𝑖𝑜 = 𝑣𝑜 = 0 = 0

• Zero common mode (open loop) gain, 𝐴𝐼𝑐𝑚 = 0

• Infinite differential mode (open loop) gain, 𝐴𝐼𝑑 = 𝐴 = ∞

• Infinite bandwidth, 𝐵𝑊 = 𝑓ℎ − 𝑓𝑙 = 𝑓ℎ − 0 = ∞

22

KCL on output node is not useful,

as any current can be supplied.

𝑣𝑜 = 𝐴𝑑 𝑣2 − 𝑣1 + 𝐴𝑐𝑚𝑣2 + 𝑣1

2


Ideal Op Amp Under Feedback


23


Ideal Op Amp Under Feedback

• Positive feedback, +𝛽

• Signal perturbations are magnified

• Rail output or oscillation if unstable

(has its applications, but will not

be considered further today)

• Negative feedback, −𝛽

• Signal perturbations are counteracted

• Typically yields a stable finite output level

• Virtual short circuit between input terminals,

as of the high differential voltage gain

24

𝑣𝑜 = 𝐴 𝑣2 − 𝑣1 ⇔ 𝑣2 − 𝑣1 =𝑣𝑜𝐴= 𝐴 = ∞ = 0

𝑣𝑜 = 𝐴 𝑣2 − 𝑣1 ± 𝛽𝑣𝑜 ⇔ 𝑣𝑜 =𝐴

1 ∓ 𝐴𝛽𝑣2 − 𝑣1

Negative feedback introduces a virtual

short circuit at the op amp input.


Op Amp Configurations

• We will look at a few of the applications suitable for op amps…

• Follower

• Inverting amplifiers

• Non-inverting amplifiers

• Differential amplifiers

• Integrators

• Differentiators

• … and many more not covered here

• You probably encountered op amp configurations before, if not, practice your circuit analysis skills…

25

Note that feedback, negative or

positive, is typically used.


Op Amp Configurations: Voltage Follower

• Follower configuration

• Output voltage equals input

26


Why would one need a voltage follower?

27


Op Amp Configurations: Inverting Amplifier and Weighted Summer


28


Op Amp Configurations: Inverting Amplifier and Weighted Summer

• Inverting configuration

• Amplifies and inverts signal

29

𝐴𝑣 =𝑣𝑂𝑣𝐼

= −𝑅2𝑅1


Weighted Summer Capable of Addition and Subtraction

• Two cascaded op amp inverting amplifiers with multiple inputs (superposition)

30


Op Amp Configurations: Non-Inverting Amplifier

• Non-inverting configuration

• Amplifies signal

31

𝐴𝑣 =𝑣𝑂𝑣𝐼

= 1 +𝑅2𝑅1


Op Amp Sub-Circuits

• Input stage

• Differential amplifier

• Discrimination between differential and

common mode signals

• Intermediate stages (not shown here)

• Additional gain

• Reject noise

• … depends on application

• Output stage

• Output current buffer (voltage follower)

or voltage amplifier

• Controlled load for earlier stages

32

A simplistic, but useful, description.


Example Schematic of an IC Op Amp

• Two-stage CMOS op amp

• Bias circuit

• Input stage

• Active load

• Output stage

• Frequency compensation

33

The functional blocks in this schematic should

be more clear by the end of the course.


Op Amp Imperfections – A Quick Overview

• Ideal op amps are very useful, but a real circuit has various limitations…

• Output offset

• Finite bandwidth

• Signal clipping

• Finite slew rate

• …

• Op amp imperfections yield from…

• Component mismatch

• Large signal operation

• Input/output/bias range

• Bandwidth limitations

• …

34

Origins of op amp imperfections should

be more clear by the end of the course.


SIMULATION PROJECT STARTS NEXT WEEK

• Prepare

• Join a simulation project group on LU Canvas > Modern Electronics > People (2 students per group)

• Read the project instructions beforehand

• Project introduction (2x 4 hours with supervisor Stefan Andric)

• “ADS start-up assistance”

• Project workspace and import of pre-defined component library

• Focus on making the basic simulation setup

• Think about the device or circuit theory later

• Independent project work (~24 h) + supervision (4x 2 hours with supervisor)

• Independent work in computer lab room required

• Supervisor available only at scheduled times

• Debriefing and report (yields 1.5 hp ~ 1 week of work ~ 40 hours)

• Simulation project debriefing by supervisor on October 10 at 8:15-10 in E:2311

• Project report handed in through LU Canvas by midnight on October 14

• Only one (1) single report correction allowed, make sure to amend all comments

35


Keysight ADS – Electronic Design Automation (EDA) Software

• ADS provides a holistic suite of EDA tools

• Technology setup

• Schematic, layout, user-defined models

• Verilog-A hardware models

• EM simulations (planar or 3D)

• DRC (design rule checking)

• AEL (application extension language)

• …

• Keysight ADS is used by professionals in

RFIC, MMIC, and millimetre wave design

• Silicon PDKs include:

Samsung, ST Microelectronics, TSMC, …

• III-V PDKs include:

Northrop Grumman, OMMIC, UMS, …

36

https://www.keysight.com/en/pc-1297113/advanced-

design-system-adsPDK = process design kit

https://www.keysight.com/en/pc-1297113/advanced-design-system-ads

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F6 – Basic Circuits

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