162
Fabrication Technology
Deep-ultraviolet contact photolithography is a simple exposure process in which the mask, with patterned absorber, and resist-coated substrate are brought into intimate contact. In our experiments, the wavelength of the exposing radiation is as short as220 nm and comes from a Hg(Xe) arc lamp. (Courtesy of H. I. Smith)
163
Fabrication Technology
• Sub-100 nm Metrology Using Interferometrically Produced Fiducial Grids
• Nanometer-level Feedback-Stabilized Alignment and X-ray Exposure System
• Deep-Ultraviolet Contact Photolithography
• Environmentally Benign Process Chemistries and Chemical Recycling
• Alternative Chemistries for Wafer Patterning and PECVD Chamber Cleaning
• Layout Pattern Dependencies in Copper Damascene CMP Processes
• Chemical Mechanical Polishing for Shallow Trench Isolation (STI)
• Ultrathin 600°C Wet Thermal Silicon Dioxide
• Low Turn-on Voltage and High Uniformity n-type Silicon Field Emitter Array Fabricationand Characterization
• Molybdenum Field Emitters with Integrated Focusing Electrode
• Field Emitter Arrays with High Aspect Ratio
• Scanned Laser Annealing of Patterned Films
164
continued
The ability to see and measure the results of a process iscritical to advancing fabrication technology. Historically,the development of improved microscopy techniques ledto rapid progress in microfabrication. Thus, the scan-ning-electron microscope was essential to the microelec-tronics revolution. Similarly, the scanning-tunnellingmicroscope is creating a revolution in the study ofinterfaces and nanostructures.
In the past, metrology of microstructures and the mea-surement of workpiece distortion (e.g., a photolitho-graphic reticle or an x-ray mask) has been based onpoint-by-point measurement through an optical micro-scope using an X-Y table monitored by a laser interfer-ometer. Although this approach enables relative dis-tances in a plane to be measured with 1 nm-leveldetectivity, it is expensive, tedious, and subject to anumber of shortcomings, including the necessity ofplacing rather perturbative marks on a workpiece. Wehave initiated a new approach to metrology for the sub-100 nm domain that is based on large-area fiducial gridsproduced by interferometric lithography. This newapproach is complementary to the point-by-pointapproach in much the same way that aerial photogram-metry is complementary to ground-based land surveyingfor the mapping of terrain.
A key element in this new initiative is the holographicphase shifting interferometer (HPSI) interferometer,illustrated in Figure 1. This system, once it is fullydeveloped, will enable us to measure in a global mannerthe in-plane distortion of a workpiece, provided one ofits surfaces contains a shallow fiducial grid. Ideally, thegrid on the workpiece will be created by interferometriclithography or a derivative thereof, such as near-fieldholography.
Sub-100 nm Metrology Using Interferometrically Produced Fiducial Grids
PersonnelC. O. Chen, J. Ferrera, P. Konkola, M. L. Schattenburg(H. I. Smith)
SponsorshipDARPA/ARO
2θ
PIEZOELECTRICTRANSDUCER
+
-
BEAMSPLITTER
SCREEN
LASER BEAM λ = 351 nm
POCKELS CELL
MIRROR MIRROR
BEAMSPLITTER
VARIABLEATTENUATOR
REFLECTEDWAVE
BACK-DIFFRACTEDWAVE
2θ
SUBSTRATE
GRATING
p = λ2 sin θ
Fig. 1: Schematic of the holographic phase-shifting interferometer(HPSI). A spherical wave back-diffracted from a shallow substrategrid, and a second wave specularly reflected, interfere on afluorescent screen at the spatial filter. The fringes are imaged ontoa CCD. By shifting the beam splitter with a piezo, a computergenerates an X-Y map of phase error.
165
continued
As part of this new initiative in sub-100 nm metrology,we are pursuing a variety of approaches to eliminatingthe distortion in interferometrically produced grids,decreasing the coefficient of the hyperbolic phaseprogression (a consequence of creating a grid by inter-fering spherical wavefronts), and increasing the usefularea of fiducial grids. One such approach is scanningbeam interferometric lithography (SBIL), depictedschematically in Figure 2. The concept here is to com-bine the sub-1nm displacement measuring capability oflaser interferometry with the interference of narrowcoherent beams to produce coherent, large-area, lineargratings and grids. Our ultimate goal is to produce suchgratings over areas many tens of centimeter in diameter.
Blowup of BeamInterference Region
GraniteBridge
Air BearingGranite Slab
Interfer-ometer
OpticalBench
Y Direction
X D
irect
ion
ScanningGratingImage
Air-Bear
ing
XY Stage
Resist-CoatedSubstrate
a) Scanning beam interferometer.
b) Grating scanning method.
Laser
XY Stage
Substrate
Fig. 2: Schematic of the scanning beam interference lithography(SBIL) system. A pair of narrow, distortion-free beams overlap andinterfere at the substrate, producing a small grating patch. Thesubstrate is moved under the beams, writing a large area grating.Sophisticated electro-optical components (not shown) ensure phaselocking of the grating during writing.
166
An experimental high-precision, x-ray exposure andalignment system has been constructed that employs“Interferometric Broad-Band Imaging” (IBBI) for align-ment. (Figure 3a). The objective of this system is toachieve ~1nm overlay. The IBBI scheme employsgrating and checkerboard type alignment marks onmask and substrate, respectively, which are viewedthrough the mask from outside the x-ray beam at aLittrow angle of 15 degrees with f/10 optics and a110 mm working distance. Each mark consists of twogratings (or checkerboards) of slightly different periods,p1 and p2, arranged so that p
1 is superimposed over p2,
and p2 over p1 during alignment. Alignment is mea-sured from two identical sets of moiré fringes, projectedonto a CCD, that move in opposite directions as the
Nanometer-Level Feedback-Stabilized Alignment and X-Ray Exposure System
SponsorshipDARPA, SRC through U. C. Berkeley, Suss Advanced Lithography
PersonnelDr. P. N. Everett, E. E. Moon(H. I. Smith)
mask is moved relative to the substrate. The relativespatial phase of the two fringe sets signifies alignment.Experiments depicted schematically in Figure 3b dem-onstrated that the displacement scale observed by IBBI isconsistent with the scale of a calibrated capacitive sensorassociated with a closed-loop piezoelectric drive. Figure4 shows alignment data read simultaneously from twomicroscopes, during times when the piezos werealternately scanning and stationary. The differencebetween the average IBBI reading and the piezo dis-placement was found to be within 1.5%.
Fig. 3: (a) X-ray exposure and alignment system. Mask and wafer are located in a helium ambient and exposed to x-rays. IBBI micro-scopes observe alignment through a viewport before and during exposure. (b) Schematic of displacement experiments monitored by IBBI.Alignment is observed at two marks simultaneously by two microscopes. The relative mask-wafer position is controlled by piezos withintegral capacitive sensors.
continued
167
Experiments showed that IBBI is self-consistent whenviewed by two independent optical systems. Twomicroscopes observed the same mark, as shown inFigure 5, while taking readings alternately. The indepen-dent readings had a mean difference of 0.01 nm and astandard deviation of 0.66 nm.
The ability of IBBI to observe nanometer-level alignmentduring x-ray exposures implies that disturbances can becorrected during the course of an exposure. Figure 6ashows drift and vibration of the exposure/alignmentsystem over a period of several hours, with the systemrunning open loop. Feeding back a correction signal tothe piezos (Figure 6b) results in alignment that is stabi-lized to a mean of 0.0 nm and a standard deviationof 1.4 nm.
The unique capabilities of IBBI alignment are beingemployed in the fabrication of a variety of electronic andoptical devices, including 25 nm effective-channel-lengthn-MOS transistors.
continued
continued
Time (min)
Time (min)
Time (min)
IBB
I & P
iezo
Mea
sure
men
ts (
µm)
Pie
zo -
(IB
BI a
vg.)
(nm
) P
iezo
- 1
.015
*(IB
BI a
vg.)
(nm
)
0
100
200
0
100
200
3.3 6.6 10.0 13.3 16.6 20.0
3.3 6.6 10.0 13.3 16.6 20.0
3.3 6.6 10.0 13.3 16.6 20.0
4
3
2
1
0
Microscope 1
Microscope 2
Piezo
(a)
(b)
(c)
Fig. 4: Agreement between two simultaneous IBBI measurementsand piezo/capacitor drives during 3.7 µm back-and-forth scan ofmask. (a) IBBI measurements and piezo displacements throughoutthree scan/rest cycles. (b) Difference of piezo and average IBBIdisplacement readings, showing residual scale error. (c) Best-fitfound with scale increase of 1.5%. The residual scale error isattributed to flexing of the 10 cm of metal separating mask and piezos,and possible pattern magnification during E-beam mask writing.
168
Fig. 5: Two IBBI microscopes alternately observe thesame alignment mark from opposite directions, with themask locked to the wafer at a 3 µm gap. Measurementsagree to within σ = 0.66 nm.
Mean = 0.0 nm
Std. Dev. = 1.4 nm
Time (hr)
IBB
I Mea
sure
men
t (nm
)
100
50
0
-50
-100
1 2 3 4 5 60
(b)
~ 150 nm drift
Time (hr)
IBB
I Mea
sure
men
t (nm
)
100
50
0
-50
-100
1 2 3 4 5 60
(a)
Fig. 6: Six-hour alignment data. (a) Open-loop operation. (b) Closed-loop operation.
continued
169
A research program in deep-ultraviolet contact photoli-thography was begun this year. The goal of this projectis to demonstrate a lithography process capable ofpatterning sub-100-nm features at high rates(> 3 cm2/sec) on spherical surfaces (radius of curvatureas low as 8 cm). The lithography scheme must also beamenable to precise multilevel alignment, i.e. subse-quently patterned levels must be aligned to previouslevels to within a small fraction of the minimum featuresize. A successful lithography scheme which meetsthese criteria will be used to fabricate a smart, wide-field-of-view camera. This camera will have detectorsand high-speed signal-processing hardware on itscurved focal plane. We believe that contact photolithog-raphy best fulfills these requirements.
Deep-Ultraviolet Contact Photolithography
PersonnelJ. M. Daley, M. K. Mondol, Dr. J. G. Goodberlet (H. I. Smith)
SponsorshipDARPA
The basic approach of contact photolithography isdepicted in Figure 7. An optically-transparent maskwith a patterned absorber is brought into contact with aresist-coated substrate and then exposed with radiation.After exposure, the resist is developed to provide thedesired relief pattern. This method was developedearlier for patterning electrodes on surface-acousticwave devices, which typically had expensive andunconventional substrates. Our initial tasks are toextend the resolution of contact photolithography downto the sub-100-nm regime and then pattern on doubly-curved surfaces. To pattern on the curved surface weplan to use very thin, i.e. 1 to 10 µm thick, conformablemembrane masks.
The practical resolution limit of the contact photolithog-raphy scheme is determined by the mask design andwavelength of the exposing radiation. We have consid-ered three mask designs: the amplitude mask (AM), theembedded amplitude mask (EAM), and the embeddedattenuating phase-shift mask (EAPSM). These designsare depicted in Figure 8. The amplitude mask is theeasiest to fabricate, and we have done preliminaryexposures with this type. The EAM and the EAPSM aredesigns which improve the resolution of the lithographyby taking advantage of the high refractive index of themask substrate. This is because the optical mode whichtraverses the region between absorbers can be confinedmore tightly in the high-refractive index material andpropagate normally rather than decay evanescently.With these masks, the minimum printable feature size isapproximately λ/(2n), where n is the refractive index ofthe mask substrate. For the EAPSM, the absorbertransmits about 18% of the incident radiation andimparts a pi phase shift to it. This design suppressesundesirable lateral-diffraction. Both the embeddedmask designs may be covered with a thin protectivelayer which will facilitate mask cleaning and assist inminimizing any problems due to particles. Particles arehighly problematic for contact photolithography be-
arc lampand
mirrors
mask
resiststack
substrate
Fig. 7: Deep-ultraviolet contact photolithography is a simpleexposure process in which the mask, with patterned absorber, andresist-coated substrate are brought into intimate contact. In ourexperiments, the wavelength of the exposing radiation is as short as220 nm and comes from a Hg(Xe) arc lamp.
170
cause our modeling indicates that for sub-100-nmfeatures, gaps between mask and substrate greater than20 nm cannot be tolerated. With an exposing wave-length of 220 nm and either the EAM or EAPSM, weexpect to print ~70 nm features with broad processlatitude.
To measure the resolution limit of deep-ultravioletcontact photolithography, we have conducted severalpreliminary experiments with 150-µm-thick quartzamplitude masks. In one set of experiments, radiationfrom a Hg lamp ( λ ~ 365 nm ) was used for exposures.In another experiment, a wavelength of 220 nm from aHg(Xe) lamp was used. Figure 9 shows features pat-terned via contact photolithography. The first patternconsists of nested L’s exposed in 60-nm-thick photore-sist. The fidelity of the printed pattern is good andshows no line shortening or corner distortions. Thelinewidths of the L’s are about 145 nm, and the expo-sure rate was 10 cm2/sec. Isolated lines of 100 nmwidth were produced with the 220-nm exposure, but ata much slower rate because of the weak Hg(Xe) lampand a slow-speed resist. ( With the use of a commercialshort-wavelength laser, the exposure rate could beincreased to more than 3 cm2/sec. ) After development,gold was electroplated into the mold formed by theresist. These results give us high confidence that sub-100-nm features can be patterned with deep-ultravioletcontact photolithography using the EAMor EAPSM.
In subsequent experiments, we will compare theresolution-limit of the different mask designs andevaluate process latitude for each. We will also testmulti-level alignment.
transparentmask substrate
absorber pattern
n
n
( a )
attenuating phase shifter
( b )
SiO2
Cr absorber 500 nm
n
( c )
continued
continued
Fig. 8 Close-up views of three mask designs are shown. Details ofthe patterned region of the amplitude mask (AM) (a) and of theembedded attenuating phase-shift mask (EAPSM) (b) are illustrated.The EAPSM suppresses undesirable diffraction effects. A third maskdesign, called the embedded amplitude mask (EAM), has beenfabricated as shown by the SEM image in (c), and is similar to theEAPSM. The EAPSM and EAM improve the resolution of thelithography scheme by taking advantage of the mask substrate’s highrefractive index, n.
171
resist
320 nm
( a )
100 nm
( b )
gold
Fig. 9: These patterns were made with amplitude masks and contactphotolithography. In (a), nested L’s were patterned in 60-nm-thickphotoresist with an exposing wavelength of 365 nm. In (b), 100-nm-wide isolated lines were patterned with an exposing wavelengthof 220 nm, and after development, gold was electroplated into themold formed by resist.
In today’s silicon electronics, control of the surfaceproperties of the starting material, crystalline silicon, isessential for achieving a high process yield for deviceswith submicron dimensions. While wet cleaning cyclescontinue to be used widely in IC processing because oftheir excellent ability to remove particles and nativeoxides, environmental concerns will restrict the use ofchemicals employed in these cleaning processes. It is,therefore, necessary to develop new cleaning processesby understanding the surface chemistries and, based onthis knowledge, develop and evaluate alternativechemistries. We have developed a contactless monitor-ing tool based on the measurement of minority carrierlifetime which is capable of detecting very low levels(108 atoms/cm2, or ppm surface states) of surfacedefects on high quality silicon wafers. This Radio-Frequency PhotoConductance Decay (RF-PCD) mea-surement detects any contaminants that generate mid-gap electronic states, including Si dangling bonds andmetal adsorbates.
We have developed a new cleaning process usingiodine dissolved in alcohol to replace dilute HF as afinal cleaning step prior to gate oxidation or epilayergrowth. In collaboration with a group in the Depart-ment of Chemistry at Stanford University, we havedetermined that iodine radicals catalyze bondingbetween surface silicon atoms and oxygen atoms of thealcohol. Further studies have shown the stability of thispassivation in air to be superior to the stability ofconventional dilute hydrofluoric acid (HF) passivation.We are currently investigating the impact iodine/alcohol passivation has on Gate Oxide Integrity (GOI).
We are studying the processes by which metals insolution contaminate the silicon surface. Using thermo-dynamic data for the formation of metal compounds,we have modeled the impact changes in solutionchemistry have on metal removal capability. Ourresults show that reducing the acid content of a SC-2
Environmentally Benign ProcessChemistries and Chemical Recycling
PersonnelJ. Chan, A. Reddy, and J. Michel (L. C. Kimerling) incollaboration with Millipore and Stanford U.
SponsorshipNSF/SRC Ctr for Environmentally Benign SemiconductorManufacturing and Wafer Engineering and Defect ScienceConsortium
continued
continued
172
0
10
20
30
40
50
60
0 200 400 600 800 1000
Concentration of Cu added (ppt)
bath to 10% of the standard value reduces the Fe solubil-ity by 103. The increase in metal solubility due to thepresence of Cl- has also been studied and is found to havethe greatest impact for concentrated solutions. Both ofthese calculations demonstrate the trade-off betweenchemical consumption and cleaning efficiency.
For contamination from HF solutions, we have used RF-PCD to make in-situ observations of metal deposition.Our results show that dissolved gases strongly effect therate of formation of metal-related surface defects. Forsolutions, which have been saturated with either Ar orO
2, the lifetime degradation due the presence of 1 ppb Cu
is nearly an order of magnitude faster than for air-
saturated solutions. We are currently performing TotalX-Ray Fluorescence (TXRF) measurements at theStanford Synchrotron Radiation Lab (SSRL) to correlateour lifetime observations with surface coverage data.We have extended our lifetime technique to measuremetal contamination in cleaning baths. By measuringchanges in the lifetime of monitor silicon wafer, we canquantify the metal concentration of the solution. Thesecond generation of this monitor has demonstrateddetection of two hundred parts-per-trillion (ppt) of Cu ina dilute HF solution. This monitor is part of point-of-useHF recycling system designed with our collaborators atMillipore Corp.
continued
Fig. 10: Response of our bath contamination monitor to Cu spikes in the200 ppt – 1 ppb range.
173
The goal of this project is to identify possible alternativesfor perfluorocompound chemistries for wafer patterningand PECVD (plasma enhanced chemical vapor deposi-tion) chamber cleaning of silicon dioxide and siliconnitride films that do not pose long term environmentalproblems. The etch viability of a variety of alternatives isbeing determined, and the most promising candidatesfrom the etch viability study are being further tested todefine both an alternative chamber clean and an alterna-tive wafer patterning process. The effluents of bothprocesses are being identified with Fourier TransformInfrared Spectroscopy (FTIR) and Quadrupole MassSpectrometry (QMS) to assess their potential ESHimpact. Finally, beta testing of both alternative processesis being performed at the facilities of industrial collabora-tors.
Most of the experimental work for this phase of theproject has taken place on a high density plasma etchtool at Motorola’s Advanced Products Research andDevelopment Laboratory (APRDL). The work for theoverall project is intended to proceed in three stages foreach candidate chemistry: a preliminary “etch viability”or chemical screening stage, to be followed by process-specific testing for both the wafer patterning and thePECVD chamber cleaning applications. An AppliedMaterials Precision 5000 etch tool housed at MIT’sIntegrated Circuits Laboratory is used for the screeningstage, a high density plasma etcher at Motorola has beenused for the wafer patterning process viability stage, anda Novellus Concept One PECVD tool at MIT is used forthe chamber cleaning process viability experiments.Diagnostic tools include optical emission spectroscopyfor plasma analysis and FTIR spectroscopy and QMS foreffluent analysis.
An oxide via etch process has been developed using 2H-heptafluoropropane that offers equivalent (or better, insome aspects) etch process performance to a typical C
3F
8process with lower emissions of global warming gases
Alternative Chemistries for Wafer Patterning and PECVD Chamber Cleaning
PersonnelS. Karecki, L. Pruette, R. Chatterjee (R. Reif)in collaboration with L. Beu (Motorola APRDL) and B. Pogge (IBM)
SponsorshipNSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
critical dimension, and etch rate lag were all factors inevaluating the process performance of 2H-heptafluoropropane as parameters such as source power,bias power, etch gas flow rate, and temperature werevaried. The process developed offered an overall emis-sions reduction of 42% relative to the C3F8 referenceprocess. The process developed operates in a standardregime for the HDP chamber, and can be considered as adrop-in replacement for C3F8 in this oxide via etchapplication. However, one hurdle presently blocking theimplementation of 2H-heptafluoropropane as an etch gasin manufacturing is its absence from the Toxic Sub-stances Control Act (TSCA) list. Without TSCA listing,most manufacturing facilities will not approve the use of2H-heptafluoropropane for etch processing. Addition-ally, there is no current supplier for this compound insemiconductor-grade purity. It is made in bulk quanti-ties at a lower purity for use as a fire-extinguishing agent.
Figure 1. 0.45 µm (nominal printed CD) via etched in TEOS layer with a 2H-
heptafluoropropane process, stopping on metal.
Fig. 11: 0.45 µm (nominal printed CD) via etched in TEOS layerwith a 2H-heptafluoropropane process, stopping on metal.
continued
174
(Figure 11). Etch rate, photoresist selectivity, anisotropy,Although the etch process developed is both tool andchamber specific, it is likely that processes that demon-strate similarly good performance in combination withreduced emission of global warming gases can bedeveloped using 2H-heptafluoropropane for oxide etchapplications in a variety of high density plasma tools.
An effort has also been made to develop aniodofluorocarbon etch gas, 1 iodoheptafluoropropane, asa process gas for key dielectric etch applications in highdensity plasma etch tools, such as high aspect ratio viaetch. Currently, the best 1-iodoheptafluoropropaneprocess recorded offers very good TEOS etch rate(higher than the C3F8 reference process) and goodsidewall profile. (Figure12) The best emissions reduc-tion relative to the reference process that has beenrecorded in the present study is on the order of 70-80%.While noticeable gains have been made in improvingboth via profile and bulk resist selectivity, the latterparameter is still short of the target for this process.Bulk resist selectivity much greater than 3:1 tends to beaccompanied by buildup of polymer inside the via andetch stopping.
A new phase of the work on this project will involveexploring the etch behavior of a different family ofpotential etch chemistries, specifically inorganic fluo-rine-containing molecules such as NF3. Moving awayfrom fluorocarbon-based etch chemistries offers thebenefit of sharply reducing the possibility of the forma-tion of high global warming potential PFCs as processbyproducts. Although highly fluorinated inorganicmolecules tend to etch oxide isotropically, some havesuggested that the ion bombardment mechanism of theplasma could control an NF3-based etch to behaveanisotropically. An alternative to this approach wouldbe to begin with an inorganic molecule as the mainfluorine source for the etch, and add a minimumamount of a polymerizing gas (such as a hydrocarbon or
a hydrofluorocarbon) to aid in the polymer formationthat is believed to be necessary for high aspect ratioetching. Experimental work on this stage of the projectwill begin during the spring semester of 1999.
Subsequent work is planned to involve more completecharacterization of the effluent of the alternative chemis-tries, including obtaining a halogen mass balance, as wellas further process tests, such as measurement of selectiv-ity to various relevant stop layers and electrical tests tobe carried out after metallization following the etch step.
continued
Figure 2. 0.35 µm via etched in TEOS layer with a 1-iodoheptafluoropropane process.Fig. 12: 0.35 µm via etched in TEOS layer with a 1-iodoheptafluoropropane process.
175
Copper, due to its lower resistivity and higherelectromigration immunity compared with aluminum,is rapidly being adopted for next generation VLSIinterconnect. Copper damascene CMP processes arenow under development in industry to resolve variousissues such as process integration, reliability,defectivity, and yield. The goal of this project is tostudy pattern dependencies of density and pitch (orlinewidth and line spacing) in copper damascene CMPprocesses. The pattern dependent issues includedishing of the copper and erosion of the oxide/copperfilms, as well as yield issues of line continuity andshorting. Experiments are being performed in conjunc-tion with SEMATECH, Applied Materials, andConexant.
There are two phases in this research. In the first phase,we are exploring the effect of pattern density and layoutpatterns on single-level metal polishing. The singlelayer electrical test mask has been designed for probingline thickness loss as a function of layout patterns. Themask contains pitch structures (with fixed local density)and density structures (with fixed local pitch) to charac-terize dishing and erosion, respectively. The maskcontains electrical test structures (serpentine and comb)to measure line resistances and extract line thicknesses,as well as to study yield issues of line continuity andshorting. Experiments using these and earlier CMPcharacterization test masks are underway to supportmodeling of single-layer copper polish pattern depen-dencies.
In the second phase of this work, additional two andthree-layer tests masks are being developed. In the newtwo-level masks (with SEMATECH), we are studyingthe impact of underlying topography on the patterningand polishing of second level copper structures. In thethree-level masks (with Conexant), we are also inter-ested in the impact of topography and pattern depen-
Layout Pattern Dependencies in Copper Damascene CMP Processes
PersonnelT. Park, T. Tugbawa(D. Boning)
SponsorshipSEMATECH, Applied Materials, Conexant
dencies on via formation and reliability. Models andcharacterization methods to address these concerns areimportant for development of advanced multilevelinterconnect technology.
176
Shallow trench isolation (STI) is emerging as theisolation methodology of choice as the drive for devicedensity intensifies. However, solution of layout patterneffects at the CMP planarization phase is critical to cost-effective single-mask STI processes. Pattern effects inSTI are particularly severe and complex; it is firstmanifest at the overburden oxide polish phase resultingin a nonuniform time-to-reach the nitride capping layeracross the die. This necessitates over polishing tocompletely remove the oxide and ensure completenitride stripping. The over polishing together withhigher oxide polish rate results in substantial dishing ofthe trench oxide in dense trench regions and roundingof silicon nitride around the trenches. In order tocontrol and account for the pattern dependencies,understanding of the polish mechanism in both phasesis needed.
In this project, we have characterized and modeled thepattern dependencies exhibited at the two polishstages. Using a dedicated mask to delineate the specificpattern dependencies, we have explored a range ofpolishing process conditions and consumables such aspads and slurries. Different oxide deposition tech-niques have also been examined; in particular, theoxide topography generated by HDP plasma versusTEOS deposition is important. We find that the confor-mal deposition profiles (TEOS) and “pyramidal”profiles (HDP) result in radically different effectivedensities profiles across the die which must be ac-counted for in CMP modeling. Based on such correctedeffective densities, the oxide component of the polishcan be well explained. We have used a simple selectivenitride model with a similar density dependence tostudy the nitride erosion component of the polish. ThisSTI CMP characterization and modeling methodologyis helpful in defining process control windows andrequirements for successful trench formation, and forexploration of process alternatives with decreasedvariation.
Chemical Mechanical Polishing forShallow Trench Isolation (STI)
PersonnelD. Ouma, C. Oji, and B. Lee(D. Boning)
SponsorshipDARPA, Applied Materials, Sandia National Laboratories
Present trends in ultra large-scale integration demandthe development of ultrathin gate silicon dioxide of highquality. Often this requirement is coupled with arestricted thermal budget. Since in small devicesdopant diffusion cannot be tolerated, it is important todevelop new silicon oxidation processes at low tem-peratures. This is a challenge because the quality of anoxide depends strongly on its growth conditions.
The goal of this project is to extend conventional wetthermal oxidation to low temperatures. By establishinga temperature gradient in an oxidation furnace, we wereable to grow oxide films at 600°C while keeping thetemperature at the gas inlet at 750°C necessary for a safeand complete pyrogenic reaction between hydrogenand oxygen. The inset of figure shows a sketch of thetemperature profile.
Using this approach we were able to grow very uniformsilicon dioxide films in the range from 20Å to 60Å. Thegrowth rate in the wet environment was found to be5Å/h to 6 Å/h depending on substrate orientation.Figure 15 shows the leakage current through the oxideas a function of gate voltage for a 25Å, a 28.5Å and a33Å oxide layer. The measured values of current densityare in good agreement with theoretical predictions forhigh temperature gate oxide films indicating the highquality of our wet thermal oxide. In addition, we haveinvestigated the breakdown voltage and interface trapdensity. Breakdown fields were found to be around13 MV/cm and interface trap densities in the low1011 cm-2eV-1 could be achieved by an adequateforming-gas treatment.
In summary, the performed electrical measurementsindicate that wet thermal oxide grown under theconditions described above should be consideredreadily available to grow high quality gate oxide films.
Ultrathin 600°C Wet ThermalSilicon Dioxide
PersonnelJ. Appenzeller (J. A. del Alamo, in collaboration withR. Martel, K. Chan and P. Solomon, IBM)
SponsorshipIBM, Deutsche Forschungsgemeinschaft
continued
177
Fig. 15: Leakage current density for three different oxide thicknessesas a function of gate voltage. The inset shows a sketch of the tempera-ture profile in the oxidation furnace.
continued
Si field emitter array technology is being explored forpotential application in devices such as Field EmissionDisplays (FEDs), sensors, microwave amplifiers andswitches. The technology is amendable to the integra-tion of Si FEAs with MOSFETs to make smart fieldemitters. A typical Si field emitter is made up of amircon-sized cone located within a gate aperture. Anapplied gate voltage establishes potential differencebetween the cone tip and the gate, resulting in highelectric field at the cone tip. Electrons tunnel into thevacuum through the barrier at the tip and are acceler-ated to the anode which is biased at higher voltage thanthe gate.
The objective of the project is to fabricate high perfor-mance Si field emitter arrays using chemical-mechani-cal polishing (CMP) and correlate the current-voltagecharacteristics with the structural parameters (such astip radius and aperture width) and materials param-eters (such as work function). Our initial goal is tofabricate Si FEAs to explore the performance of thedevices when the tip is coated with low workfunctionmaterials such as diamond or AlN. Later, we plan toconduct simultaneous imaging of topology (tip radius)and surface potential (workfunction) using a UHVScanning Maxwell Stress Microcope which is underconstruction.
We report a doped-poly-silicon gate Si Field EmitterArrays (FEAs) fabricated with Chemical MechanicalPolishing (CMP) that have extremely low turn-onvoltage and negligible gate current. Furthermore ourdevices show excellent uniformity for different sizedarrays which are crucial for device reliability and massproduction. We fabricated FEAs with 1-µm aperture on4-inch (100) n-type silicon substrates with dopantconcentration of about 1016 cm-3. SEM analysis indi-cated that the radius of curvature of the tip is about 12.3nm.
Low Turn-on Voltage and HighUniformity n-type Silicon Field EmitterArray Fabrication and Characterization
PersonnelM. Ding (A. I. Akinwande)
SponsorshipDARPA
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An example of the device transfer characteristics for10x10, 20x20, 30x30 and 60x60 FEAs on a single die isshown in Figure 18. The devices were characterized inUHV at an anode voltage of 1000 V. The figure shows theaverage currents per tip as a function of gate voltage.Devices turn on at about 25-30V, however we haveobserved turn-on voltage as low as 20V on some arrays.This is the lowest reported turn-on voltage for 1-µmaperture devices compared to typical 50-60V of metalFEAs before field forming and conditioning. We alsoobserved the negligible gate leakage currents that are 3-4orders of magnitude smaller than emitter current asshown in Figure 18. We attribute the low turn-on voltageto the extremely small radius of curvature of the Si tips.Figure 19 is the Fowler-Nodheim plot of the 4-µm 60x60FEA. The emitted current obey Fowler-Nordheim theory.From the slope of the FN plot, bFN, an effective fieldenhancement, β(E=βVG), where E is the electric field atthe emitter tip) was calculated to be 7x105 cm-1. Using asimple electrostatic argument (β=1/r) we extracted anequivalent tip radius of about 14.3 nm which is in veryclose agreement with the SEM measurement of 12.3 nm.
Currently we are installing the Scanning Maxwell StressMicroscope system to image simultaneously the topol-
ogy and the surface potential of the emitter. We are alsofabricating FEAs with different emitter materials orcoatings and will study how these processes affect theperformance of the devices.
Fig. 18: Average Emitter and Gate Currents as a function ofgate voltagefor 10x10, 20x20, 30x30 and 60 x 60 Si FEAs.
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Fig. 19: Fowler-Nordheim Plot of the average emitter and gatecurrents for a 60x60 4-µm pitch FEA
continued
Being an emissive display, the Field Emission Display(FED) outperforms today’s dominant flat panel displaytechnology, the liquid-crystal display, in the areas ofbrightness, viewing angle and luminous efficiency. Atypical Field Emission Display consists of a base platewith a matrix of field emission arrays and a phosphorcoated screen, separated from the base by insulatingspacers. The breakdown field of these spacers limitsthe ratio of anode voltage to anode/cathode separa-tion. Anode voltages of 5-10 kV are needed to use highvoltage phosphors, whose brightness, luminousefficiency and lifetime characteristics are superior tothose of low voltage phosphors. However, anodevoltages of this magnitude require cathode/anodeseparation of 1-10 mm in order to avoid breakdown ofthe spacers. Since the emitted electron beam has anangular spread, electrons follow parabolic trajectoriesto the anode. Thus, higher cathode/anode separationleads to cross talk between neighboring pixels, whichlowers display resolution. Keeping the cathode-anodeseparation small and thus preserving display resolu-tion permits the use of only low-voltage phosphors,which have lower luminous efficiency, brightness andlifetime. Thus, in today’s FEDs there exists a trade-off:luminous efficiency, brightness and screen lifetime vs.screen resolution.
A way to overcome this tradeoff is to collimate theemitted electron beam by focusing. The goal of ourresearch effort is to simplify beam focusing by usingmicro-fabrication to integrate the focus electrode withthe cathode. This approach, referred to as the Inte-grated Focus Electrode Field Emitter Arrays(IFE-FEAs), can be implemented in four different ways,and shown on Figure 20. Our choice of focusingscheme was based on our analytical model of thedevice. The modeling led to the following two impor-tant, easy to implement conclusions: (i) the mosteffective focusing is achieved when the focus electrodeis positioned above (rather than outside) the gate
Molybdenum Field Emitters withIntegrated Focusing Electrode
PersonnelL. Dvorson(A. I. Akinwande)
SponsorshipDARPA
continued
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electrode and there is one focus electrode per tip (ratherthan per pixel), i.e. the local, out-of-plane configuration(#2 in Figure 20). Since our stated objective was tooptimize focusing, our design and fabrication effortswere concentrated on the out-of-plane, local IFE-FEA(ii) effective focusing calls for minimizing the thicknessof the dielectric between the focus electrode and the gateelectrode (i.e. the vertical separation between the focusand the tip). However, the dielectric strength of theoxide imposes the low limit of about 0.5 microns. Inother words, effective focusing requires the focuselectrode to be as close as possible to the tip, and thiswas implemented in our devices (see Figure 21). On theminus side, the present configuration also maximizesthe reduction of the emission current by the focuselectrode. We argue that this is overcome by operatingat a higher gate voltage.
The IFE-FEAs that we fabricated have gate and focuselectrodes made of doped polysilicon and separated fromeach and from the cathode by insulating layers of silicondioxide. The emission tips were fabricated with a Spindt-type process, utilizing angular evaporation of aluminumparting layer, followed by vertical evaporation of molyb-denum. After the cones are formed, the parting layer islifted off removing unwanted molybdenum. The final de-vice structure is shown in Figure 21.
Local
Global
In-Plane Out-Of-Plane
Global, In-Plane
Local, In-Plane
Global, Out-Of-Plane
Fig. 20: Integrated focusing themes.
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Extensive electrical characterization of the devices wascarried out. The first stage of this study involved taking3-terminal IV characteristics of arrays of different sizes.In the 3-terminal measurements, the gate and focusvoltages were kept equal to each other and were variedtogether. The Fowler-Nordheim plots of the 3-terminalIV data are linear, in agreement with theoretical expecta-tions as shown in Figure 22. Next, we studied the gateand focus transfer characteristics of the devices; e.g., thevariation of the emission current with focus voltage,gate voltage being kept constant. The focus transfercharacteristic is a particularly important parameterbecause it gives an indication of how much the emissioncurrent will be reduced as a result of focusing theemission beam.
Finally, preliminary optical characterization did demon-strate the focusing effect that we aimed for. An instru-mentation setup for quantitative spot size measurementsis currently being developed. However, our deviceswere extremely susceptible to breakdown when operatedin the focusing mode. The breakdown resulted from alarge voltage differential between the gate and focuselectrodes. We plan to overcome this problem by (i)lowering the operating voltage either through improvingthe current process or through making devices withsilicon tips (ii) investigating the breakdown mechanismsand dielectric strength limitations of the insulating oxide.
Fig. 21: An IFE FE cone with dimensions.
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0.006 0.008 0.010 0.012 0.014 0.016
-17
-16
-15
-14
-13
-12
-11
-10
Lo
g(I
/V2
)
1/V
Fig. 22: FN plot of IV data from a single tip(A
FN=-11.56; B
FN=-803 β ≡ E / V ≅ 7.8 x 105 cm-1)
continued
The goal of this project is to improve the performance offield emitter arrays (FEAs) by increasing the deviceaspect ratio (tip height/aperture width). The electricalperformance of FEAs depends on its geometrical param-eters such as radius of curvature, gate aperture and conebase angle. The ideal emitter is a tall vertical pillar witha very sharp top located within a narrow width gateaperture. This shape, high aspect ratio FEA, will yieldlow capacitance, low dynamic power dissipation, fastswitching speed and low leakage currents.
Two areas of benefit of a high aspect ration FEA are (a)driver circuit power dissipation and (b) FEA reliabilityand lifetime. Typical FEAs have aspect ratios of aboutone1eading to high capacitance between the row andcolumn electrodes in a typical display because of thethin insulator. Consequently, FED driver circuit powerdissipation will be reduced as the aspect ratio of the FEAincreases. Another benefit of high aspect ratio FEAs isthat the increase in the insulator thickness reduces theaverage field across the insulator for the same gateoperating voltage. This results in lower electron tunnel-ing through the dielectric (gate current) and hencetrapped charges in the insulator and damage of theinsulator.
Numerical simulations of the cone deposition processindicate that several parameters in the fabricationprocess contribute to the final shape of the cone. Thegeometry of the initial structure (parting layer and initialgate opening radius), various process parameters(temperature, degree of flux collimation), and materialparameters (diffusion coefficients, surface tension) affectthe evolution of the cones with time. One importantresult of the simulations is that the shallower bevel angleof the gate opening results in higher aspect ratio cones.We fabricated FEAs cones with aspect ratios of about 3:1as shown in Figure 23, using gate apertures and partinglayers with shallow bevel angles.
Field Emitter Arrays with HighAspect Ratio
PersonnelZ. Sbiaa(A. I. Akinwande)
SponsorshipDARPA
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183
continued
Patterned polycrystalline films are used to interconnectdevices and as device elements in electronic, magnetic,photonic and microelectromechanical devices andmicrosystems. When patterned feature sizes are compa-rable to the grain sizes of these structures, their proper-ties and reliability can vary dramatically with minorvariations in their grain structures. We have developed aprocess for scanned laser annealing of individual pat-terned structures in order to manipulate grain structuresfor basic studies of structure-property relationships, andto develop an engineering tool for reprocessing ofpatterned structures for performance optimization.
In our apparatus a Nd:YLF laser spot is scanned along afeature by translation of the wafer relative to the fixedlaser beam (see figure24a). We have scanned polycrys-talline films patterned into lines and shown that poly-crystalline structures can be converted to large-grained‘bamboo’ structures with grain boundaries normal to theline axes. These structures can be obtained in lines forwhich conventional uniform anneals would not yieldbamboo structures. We have studied the mechanism forthis structural conversion through simulation of thegrain structure evolution process during scanned anneal-ing. Both simulations and experiments demonstratethree regimes of structure evolution, agglomeration,uniform grain growth and evolution to bamboo struc-tures, depending on the laser power, the scan speed, andthe geometry of the line structure (see figures 24b and24c). Simulations suggest that under appropriateconditions, near-single-crystal structures should beobtained. We are developing thermal models for inputfor simulations of structure evolution, and we arecontinuing experiments on patterned Al films as well asinitiating experiments on patterned Cu.
SponsorshipSRC
PersonnelC. Hau (C.V. Thompson)
continued
Fig. 23: Field Emitter Arrays with high aspect ratios.
Scanned Laser Annealing ofPatterned Films
184
Fig. 24a
Fig. 24b
continued
Fig. 24c
