Fairchild Semiconductor Power Seminar 2007 Appendix A ...

Fairchild Power Seminar 2007

A-1

A-11

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A-65

Table of Contents

Design Considerations for an LLC Resonant Converter

Application Review and Comparative Evaluation of Low-Side MOSFET Drivers

Understanding Diode Reverse Recovery and its Effect on Switching Losses

Low Cost, Isolated Current Source for LED Strings

Design Review: Power Stage Design for a 200W Off-Line Power Supply

Tips and Tricks To Get More Out of Your SPICE Simulations

Fairchild SemiconductorPower Seminar 2007

Appendix A: White Papers

Fairchild Power Seminar 2007

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A-1 Fairchild Power Seminar 2007

Design Considerations for an LLC Resonant Converter

Hangseok Choi Fairchild Semiconductor

82-3, Dodang-dong, Wonmi-gu Bucheon-si, Gyeonggi-do, Korea

Abstract: Recently, the LLC resonant converter has drawn

a lot of attention due to its advantages over the conventional series resonant converter and parallel resonant converter: narrow frequency variation over wide load and input variation and Zero Voltage Switching (ZVS) of the switches for entire load range. This paper presents an analysis and reviews practical design considerations for the LLC-type resonant converter. It includes designing the transformer and selecting the components. The step-by-step design procedure explained with a design example will help engineers design the LLC resonant converter easily.

I. INTRODUCTION

The growing demand for higher power density and low profile in power converter designs has forced designers to increase switching frequencies. Operation at higher frequencies considerably reduces the size of passive components such as transformers and filters. However, switching losses have been an obstacle to high frequency operation. In order to reduce switching losses, allowing high frequency operation, resonant switching techniques have been developed [1-7]. These techniques process power in a sinusoidal manner and the switching devices are softly commutated. Therefore, the switching losses and noise can be dramatically reduced. Conventional resonant converters use an inductor in series with a capacitor as a resonant network. Two basic configurations are possible for the load connection; series connection and parallel connections.

For the series resonant converter (SRC), the rectifier-load network is placed in series with the L-C resonant network as depicted in Fig.1 [2-4]. From this configuration, the resonant network and the load act as a voltage divider. By changing the frequency of driving voltage Vd, the impedance of the resonant network changes. The input voltage will be split between this impedance and the reflected load. Since it is a voltage divider, the DC gain of an SRC is always lower than 1. At light load condition, the impedance of the load will be very large compared to the impedance of the resonant network; all the input voltage will be imposed on the load. This makes it difficult to regulate the output at light load. Theoretically, frequency should be infinite to regulate the output at no load.

For parallel resonant converter, the rectifier-load network is placed in parallel with the resonant capacitor as depicted in Fig. 2 [5-7]. Since the load is connected in parallel with the resonant network, there inevitably exists large amount of

circulating current. This makes it difficult to apply parallel resonant topologies in high power applications.

+

VO

-

Ro

Q1

Q2

n:1Ip

Lr

Lm

CrIds2

Vd

Vin

resonant network

Fig.1. Half-bridge series resonant (SR) converter

+

VO

-

Ro

Q1

Q2

n:1Ip

Llkp

Cr

Ids2

Vd

Vin

resonant network

Fig.2. Half-bridge parallel resonant (PR) converter

In order to solve the limitations of the conventional resonant

converters, the LLC resonant converter has been proposed [8-12]. The LLC-type resonant converter has many advantages over conventional resonant converters. First, it can regulate the output over wide line and load variations with a relatively small variation of switching frequency. Second, it can achieve zero voltage switching (ZVS) over the entire operating range. Finally, all essential parasitic elements, including junction capacitances of all semiconductor devices and the leakage inductance and magnetizing inductance of the transformer, are utilized to achieve ZVS.

This paper presents an analysis and design considerations for a half-bridge LLC resonant converter. Using the fundamental approximation, the voltage and current waveforms are analyzed and the gain equations are obtained. A design for DC/DC converter with 120W/24V output has been selected as a typical example for describing the design procedure.


II. OPERATION PRINCIPLES AND FUNDAMENTAL APPROXIMATION

Fig. 3 shows the simplified schematic of half-bridge LLC resonant converter and Fig. 4 shows its typical waveforms. In Fig. 3, Lm is the transformer magnetizing inductance and Llkp and Llks are the leakage inductances on the transformer primary and secondary sides respectively. Operation of the LLC resonant converter is similar to that of the conventional LC series resonant converter. The only difference is that the value of the magnetizing inductance is relatively small and therefore the resonance between Lm+Llkp and Cr affects the converter operation. Since the magnetizing inductor is relatively small, there exists considerable amount of magnetizing current (Im) as illustrated in Fig. 4.

In general, the LLC resonant topology consists of three stages as shown in Fig. 3; square wave generator, resonant network and rectifier network.

- The square wave generator produces a square wave voltage, Vd by driving switches, Q1 and Q2 with alternating 50% duty cycle for each switch. The square wave generator stage can be built as a full-bridge or half bridge type.

- The resonant network consists of a capacitor, leakage inductances and the magnetizing inductance of the transformer. The resonant network filters the higher harmonic currents. Thus, essentially only sinusoidal current is allowed to flow through the resonant network even though a square wave voltage is applied to the resonant network. The current (Ip) lags the voltage applied to the resonant network (that is, the fundamental component of the square wave voltage (Vd) applied to the half-bridge totem pole), which allows the MOSFET’s to be turned on with zero voltage. As can be seen in Fig. 4, the MOSFET turns on while the current is flowing through the anti-parallel diode and the voltage across the MOSFET is zero.

- The rectifier network produces DC voltage by rectifying the AC current with rectifier diodes and capacitor. The rectifier network can be implemented as a full-wave bridge or center-tapped configuration with capacitive output filter.

+

VO

-

Ro

Q1

Q2

n:1Ip

Llkp

Lm

CrIds2

VdLlks

Im

IDVin

Square wave generator

resonant network Rectifier network

Io

Fig. 3. A schematic of half-bridge LLC resonant converter

Ip

Ids2

Vd(Vds2)

Vgs2

Im

Vin

ID

Vgs1

Fig. 4. Typical waveforms of half-bridge LLC resonant converter

The filtering action of the resonant network allows us to use the classical fundamental approximation to obtain the voltage gain of the resonant converter, which assumes that only the fundamental component of the square-wave voltage input to the resonant network contributes to the power transfer to the output. Because the rectifier circuit in the secondary side acts as an impedance transformer, the equivalent load resistance is different from actual load resistance. Fig. 5 shows how this equivalent load resistance is derived. The primary side circuit is replaced by a sinusoidal current source, Iac and a square wave of voltage, VRI appears at the input to the rectifier. Since the average of Iac is the output current, Io, Iac is obtained as

sin( )2

oac

II t

π ω⋅= (1)

And VRI is given as

sin( ) 0

sin( ) 0RI o

RI o

V V if t

V V if t

ωω

= + >= − <

(2)

where Vo is the output voltage.

Then, the fundamental component of VRI is given as 4

sin( )F oRI

VV tω

π= (3)

Since harmonic components of VRI are not involved in the power transfer, AC equivalent load resistance can be calculated by dividing VRI

F by Iac as

2 2

8 8FoRI

ac oac o

VVR R

I Iπ π= = = (4)


Considering the transformer turns ration (n=Np/Ns), the equivalent load resistance shown in the primary side is obtained as

2

28ac o

nR R

π= (5)

By using the equivalent load resistance, the AC equivalent circuit is obtained as illustrated in Fig. 6, where Vd

F and VROF

are the fundamental components of the driving voltage, Vd and reflected output voltage, VRO (nVRI), respectively.

+VRI

-

Io

+

VO

-

Iac

pkacI

Iac

VRI

4sin( )F o

RI

VV wt

π=

Vo

)sin(2

wtI

I oac

⋅= π

Ro

VRIF

Fig. 5 Derivation of equivalent Load resistance Rac

VO

Lm

LlkpCr

Ro

Vin

VdF

VROF

Lm

LlkpCr

Rac

Llks

n:1

n2Llks

Vd

+

-

2

2

8ac o

nR R

π=

+

-

VRI

+

-

(nVRIF)

--

+ +

Fig. 6 AC equivalent circuit for LLC resonant converter

With the equivalent load resistance obtained in (5), the characteristics of the LLC resonant converter can be derived. Using the AC equivalent circuit of Fig. 6, the voltage gain, M

is obtained as

2

2 22

2 2

4sin( ) 2

4sin( )

2

(1 ) ( ) (1 )

oF F

RO oRIF F

ind d in

m ac r

m lks aco p

n VtV n Vn V

MVV V Vt

L R C

j L n L R

ωπ

ωπ

ωω ωωω ω

⋅⋅⋅= = = =

=⋅ − ⋅ + + −

(6)

where 2

2

2

8

1 1,

, //( )

ac o

o p

r r p r

p m lkp r lkp m lks

nR R

L C L C

L L L L L L n L

π

ω ω

=

= =

= + = +

As can be seen in (6), there are two resonant frequencies. One is determined by Lr and Cr while the other is determined by Lp and Cr. In actual transformer, Lp and Lr can be measured in the primary side with the secondary side winding open circuited and short circuited, respectively.

One important point that should be observed in (6) is that the gain is fixed at resonant frequency (ωo) regardless of the load variation, which is given as

2

@ o

m m lks

p r m

L L n LM

L L Lω ω=+= =

− (7)

Without considering the leakage inductance in the transformer secondary side, the gain in (7) becomes unity. In previous research, the leakage inductance in the transformer secondary side was ignored to simplify the gain equation [8-12]. However, as observed, there exists considerable error when ignoring the leakage inductance in the transformer secondary side, which generally results in an incorrect design.

By assuming that Llkp=n2Llks, the gain in (6) can be simplified as

2

2

2 2 2

2 2

( )12

( 1)( ) (1 ) (1 )

2 1

pO

in

o o p

k

kn VM

kVj Q

k

ωω

ω ω ωω ω ω

+⋅= =+⋅ − ⋅ + −+

(8)

where m

lkp

Lk

L= (9)

/r r

ac

L CQ

R= (10)

The gain at the resonant frequency (ωo) of (7) can be also simplified in terms of k as


2

@

1o

m lkpm lks

m m

L LL n L kM

L L kω ω=

++ += = = (11)

While the gain is expressed in terms of k in (8), a gain expressed with Lp and Lr is preferred when handling an actual transformer since these values can be easily measured with a transformer. Expressing Lp and Lr in terms of k, we can obtain

( 1)p m lkp lkpL L L k L= + = + (12)

// (1 )1r lkp m lkp lkp

kL L L L L

k= + = +

+ (13)

Using (12) and (13), (8) becomes

2

2

2 2

2 2

( )2

( ) (1 ) (1 )

p r

p pO

pin

o o r p

L L

Ln VM

LVj Q

L

ωω

ω ω ωω ω ω

−

⋅= =⋅ − ⋅ + −

(14)

(11) can be also expressed in terms of Lp and Lr as

@

1o

p

p r

LkM

k L Lω ω=+= =

− (15)

By using the gain at the resonant frequency of (15) as a virtual gain of the transformer, the AC equivalent circuit of LLC resonant converter of Fig. 6 can be simplified in terms of Lp and Lr as shown in Fig. 7.

VO

Lm

LlkpCr

Ro

Vin

VinF VRO

F

Lp-Lr

LrCr

Llks

n:1

Vd

+

--

+

VRI

+

-

1: p

p r

L

L L−

2//( )

//r lkp m lks

lkp m lkp

L L L n L

L L L

= +

= +

p lkp mL L L= +

acR

ideal transform er +

--

+

(nVRIF)

Fig. 7 Simplified AC equivalent circuit for LLC resonant converter

The gain of (8) is plotted in Fig. 8 for different Q values with k=5, fo=100kHz and fp=55kHz. As observed in Fig. 8, the LLC resonant converter shows characteristics which are almost independent of the load when the switching frequency is

around the resonant frequency, fo. This is a distinct advantage of LLC-type resonant converter over the conventional series-resonant converter. Therefore, it is natural to operate the converter around the resonant frequency to minimize the switching frequency variation at light load conditions.

The operating range of the LLC resonant converter is limited by the peak gain (attainable maximum gain), which is indicated with ‘*’ in Fig. 8. It should be noticed that the peak voltage gain does not occur at fo nor fp. The peak gain frequency where the peak gain is obtained exists between fp and fo as shown in Fig. 8. As Q decreases (as load decreases), the peak gain frequency moves to fp and higher peak gain is obtained. Meanwhile, as Q increases (as load increases), the peak gain frequency moves to fo and the peak gain drops. Thus, the full load condition should be the worst case for the resonant network design.

Another important factor that determines the peak gain is the ratio between Lm and Llkp which is defined as k in (9). Even though the peak gain at a given condition can be obtained by using the gain in (8), it is difficult to express the peak gain in explicit form. Moreover, the gain obtained from (8) has some error at frequencies below the resonant frequency (fo) due to the fundamental approximation. In order to simplify the analysis and design, the peak gains are obtained using simulation tool and depicted in Fig. 9, which shows how the peak gain (attainable maximum gain) varies with Q for different k values. It appears that higher peak gain can be obtained by reducing k or Q values. With a given resonant frequency (fo) and Q value, decreasing k means reducing the magnetizing inductance, which results in increased circulating current. Accordingly, there is a trade-off between the available gain range and conduction loss.

LLC resonant Converter

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

40 50 60 70 80 90 100 110 120 130 140

freq (kHz)

Gain

Q = 1

Q= 0.8

Q= 0.6

Q= 0.4

Q= 0.2

fofp

1 p

p r

LkM

k L L

+= =−

Q=0.2

Q=1

/r r

ac

L CQ

R=

Fig. 8 Typical gain curves of LLC resonant converter

(k=5 and fo=100kHz)


1

1.2

1.4

1.6

1.8

2.0

2.2

2.4

0.2 0.4 0.6 0.8 1 1.2 1.4

k=1.5

k=1.75

k=2

k=2.5

k=3

k=4k=5k=7

Q

Pea

k G

ain

k=9

Fig. 9 peak gain (attainable maximum gain) versus Q for different k values

III. DESIGN PROCEDURE

In this section, a design procedure is presented using the schematic of Fig.10 as a reference. A dc/dc converter with 125W/24V output has been selected as a design example. The design specifications are as follows:

- Input voltage: 380Vdc (output of PFC stage) - Output: 24V/5A (120W) - Holdup time requirement: 17ms - DC link capacitor of PFC output: 100uF

VO+

-

Ro

Q1

Q2

Np:NsIp

Llkp

Lm

CrIds2

VdLlks

Im

ID

PFC

VDL

CDL

DC/DC

Fig.10 Schematic of half-bridge LLC resonant converter with power

factor pre-regulator

[STEP-1] Define the system specifications

As a first step, the following specification should be defined.

-Estimated efficiency (Eff): The power conversion efficiency must be estimated to calculate the maximum input power with a given maximum output power. If no reference data is available, use Eff = 0.88~0.92 for low voltage output applications and Eff = 0.92~0.96 for high voltage output applications. With the estimated efficiency, the maximum input power is given as

o

in

ff

PP

E= (16)

-Input voltage range (Vinmin and Vin

max) : Typically, it is assumed that the input voltage is provided from Power Factor Correction (PFC) pre-regulator output. When the input voltage is supplied from PFC output, the minimum input voltage considering the hold-up time requirement is given as

min 2.

2 in HUin O PFC

DL

P TV V

C= − (17)

where VO.PFC is the nominal PFC output voltage, THU is a hold up time and CDL is the DC link bulk capacitor. The maximum input voltage is given as

max.in O PFCV V= (18)

(Design Example) Assuming the efficiency is 95%,

120

1260.95

o

in

ff

PP

EW= = =

min 2.

32

6

2

2 126 17 10380 319

100 10

in HUin O PFC

DL

P TV V

C

V−

−

= −

⋅ ⋅ ×= − =×

max. 380in O PFCV V V= =

[STEP-2] Determine the maximum and minimum voltage

gains of the resonant network

As discussed in the previous section, it is typical to operate the LLC resonant converter around the resonant frequency (fo) in normal operation to minimize switching frequency variation. When the input voltage is supplied from the PFC output, the input voltage has the maximum value (nominal PFC output voltage) in normal operation. Designing the converter to operate at fo for the maximum input voltage condition, the minimum gain should occur at the resonant frequency (fo). As observed in (11), the gain at fo is a function of the ratio (k=Lm/Llkp) between the magnetizing inductance and primary


side leakage inductance. Thus, the value of k should be chosen to obtain the minimum gain. While a higher peak gain can be obtained with a small k value, too small k value results in poor coupling of the transformer and deteriorates the efficiency. It is typical to set k to be 5~10, which results in a gain of 1.1~1.2 at the resonant frequency (fo).

With the chosen k value, the minimum voltage gain for maximum input voltage (Vin

max) is obtained as

2min

max

1

2

m lkpRO m lks

in m m

L LV L n L kM

V L L k

++ += = = = (19)

Then, the maximum voltage gain is given as max

max minmin

in

in

VM M

V= (20)

(Design Example) The ratio (k) between Lm and Llkp is chosen as 7, which results in the minimum and maximum gains as

minmax

1 7 11.14

2 7RO

in

V kM

V k

+ += = = =

maxmax min

min

3801.14 1.36

319in

in

VM M

V= = ⋅ =

fo

11.14

kM

k

+= =

fs

Gain (M)

Mmin

Mmax for Vinmin

for Vinmax

1.36

1.14

Peak gain (available maximum gain)

Fig. 11 Maximum gain and minimum gain

[STEP-3] Determine the transformer turns ratio (n=Np/Ns)

Since the full-wave bridge rectifier is used for the rectifier network, the transformer turns ratio is given as

maxmin

2( 2 )p in

s o F

N Vn M

N V V= = ⋅

+ (21)

where VF is the secondary side rectifier diode voltage drop.

(Design Example)

max

min

3801.14 8.6

2( 2 ) 2(24 2 0.6)p in

s o F

N Vn M

N V V= = ⋅ = ⋅ =

+ + ⋅

[STEP-4] Calculate the equivalent load resistance (Rac)

With the transformer turns ratio obtained from (21), the equivalent load resistance is obtained as

22

2

8 oac ff

o

VnR E

Pπ= (22)

(Design Example)

22 2 2

2 2

8 8 8.6 24288

120o

aco

VnR

Pπ π⋅ ⋅= = = Ω

⋅

[STEP-5] Design the resonant network

With k chosen in STEP-2, read proper Q value from the peak gain curves in Fig. 9 that results in enough peak gain. 10~15% margin on the peak gain is typical. Then, the resonant parameters are obtained as

1

2ro ac

CQ f Rπ

=⋅ ⋅

(23)

2

1

(2 )ro r

Lf Cπ

= (24)

2( 1)

(2 1)p r

kL L

k

+=+

(25)

(Design Example) As calculated in STEP-2, the maximum voltage gain (Mmax) for the minimum input voltage (Vin

min) is 1.36. With 10% margin, a peak gain of 1.5 is required. k has been chosen as 7 in STEP-2 and Q is obtained as 0.43 from the peak gain curves in Fig. 12. By selecting the resonant frequency as 85kHz, the resonant components are determined as

3

1 1

2 2 0.43 85 10 288

15

ro ac

CQ f R

nF

π π= =

⋅ ⋅ ⋅ ⋅ × ⋅=

2 3 2 9

1 1

(2 ) (2 85 10 ) 15 10

234

ro r

Lf C

uH

π π −= =⋅ × ⋅ ×

=

2( 1)998

(2 1)p r

kL L uH

k

+= =+


1

1.2

1.4

1.6

1.8

2.0

2.2

2.4

0.2 0.4 0.6 0.8 1 1.2 1.4

k=1.5

k=1.75

k=2

k=2.5

k=3

k=4k=5k=7

Q

Pea

k G

ain

k=9

Fig. 12 Resonant network design using the peak gain (attainable maximum gain) curve for k=7

[STEP-6] Design the transformer

The worst case for the transformer design is the minimum switching frequency condition, which occurs at the minimum input voltage and full load condition. To obtain the minimum switching frequency, plot the gain curve using the gain equation of (8) and read the minimum switching frequency. Then, the minimum number of turns for the transformer primary side is obtained as

minmin

( 2 )

2o F

ps e

n V VN

f B A

+=⋅∆ ⋅

(26)

where Ae is the cross-sectional area of the transformer core in m2 and ∆B is the maximum flux density swing in Tesla. If there is no reference data, use ∆B =0.25~0.30 T.

Then, choose the proper number of turns for the secondary side that results in primary side turns larger than Np

min as

minp s pN n N N= ⋅ > (27)

(Design Example) EER3541 core (Ae=107mm2) is selected for the transformer. From the gain curve of Fig .13, the minimum switching frequency is obtained as 66kHz. Then, the minimum primary side turns of the transformer is given as

6min

min

3 6

min

( 2 ) 10

2

8.6 25.251.1

2 66 10 0.3 107 10

8.6 6 51.6

o Fp

s e

p s p

n V VN

f B A

turns

N n N N

−

+ ×=∆ ⋅

×= =⋅ × ⋅ ⋅ ×

∴ = ⋅ = × = >

Choosing Ns as 6 turns, Np is given as

min8.6 6 51.6 52p s pN n N N= ⋅ = × = ⇒ >

Fig. 13 Gain curve

[STEP-7] Transformer Construction

Parameters Lp and Lr of the transformer were determined in STEP-5. Lp and Lr can be measured in the primary side with the secondary side winding open circuited and short circuited, respectively. Since LLC converter design requires a relatively large Lr, a sectional bobbin is typically used as shown in Figure 14 to obtain the desired Lr value. For a sectional bobbin, the number of turns and winding configuration are the major factors determining the value of Lr, while the gap length of the core does not affect Lr much. Whereas, Lp can be easily controlled by adjusting the gap length. Table 1 shows measured Lp and Lr values with different gap lengths. With a gap length of 0.15mm, the desired Lp and Lr values are obtained.


Np=52T Ns1=Ns2=7TBifilar

Fig. 14 Sectional bobbin

Table. 1 Measured Lp and Lr with different gap lengths

Gap length Lp Lr

0.0 mm 5,669 µH 237 µH

0.05 mm 2,105 µH 235 µH

0.10 mm 1,401 µH 233 µH

0.15 mm 1,065 µH 230 µH

0.20 mm 890 µH 225 µH

0.25 mm 788 µH 224 µH

0.30 mm 665 µH 223 µH

0.35 mm 623 µH 222 µH

Even though the integrated transformer approach in LLC resonant converter design can implement the magnetic components in a single core and save one magnetic component, the value of Lr is not easy to control in real transformer design. Thus, the resonant network design sometimes requires iteration with an actual Lr value after the transformer is actually built. Or, an additional resonant inductor can be added in series with the resonance capacitor to obtain the desired Lr value.

[STEP-8] Select the resonant capacitor

When choosing the resonant capacitor, the current rating should be considered since a considerable amount of current flows through the capacitor. The RMS current through the resonant capacitor is given as

2 2( 2 )[ ] [ ]2 2 4 2r

RMS o o FC

o m

I n V VI

n f L

π + ⋅≅ + (28)

Then, the maximum voltage of the resonant capacitor in normal operation is given as

maxmax 2

2 2r

RMSin Cr

Co r

V IV

f Cπ⋅≅ +

⋅ ⋅ ⋅ (29)

(Design Example)

2 2

2 2

6 3

( 2 )[ ] [ ]2 2 4 2

5 8.6 (24 1.2)[ ] [ ]2 2 8.6 4 2 873 10 85 10

0.87

r

RMS o o FC

o m

I n V VI

n f L

A

π

π−

+ ⋅≅ +

⋅ ⋅ += +⋅ ⋅ × ⋅ ×

=

maxmax

3 9

2

2 2

380 2 0.916343

2 2 85 10 15 10

r

RMSin Cr

Co r

V IV

f C

V

π

π −

⋅≅ +⋅ ⋅ ⋅

⋅= + =⋅ ⋅ × ⋅ ×

IV. CONCLUSION

This paper has presented the design of an LLC resonant converter utilizing the leakage inductance and magnetizing inductance of transformer as resonant components. The leakage inductance in the transformer secondary side was also considered in the gain equation.

V. REFERENCES

[1] Robert L. Steigerwald, “A Comparison of Half-bridge resonant

converter topologies,” IEEE Transactions on Power Electronics, Vol. 3, No. 2, April 1988.

[2] A. F. Witulski and R. W. Erickson, “Design of the series resonant converter for minimum stress,” IEEE Transactions on Aerosp. Electron. Syst., Vol. AES-22, pp. 356-363, July 1986

[3] R. Oruganti, J. Yang, and F.C. Lee, “Implementation of Optimal Trajectory Control of Series Resonant Converters,” Proc. IEEE PESC ’87, 1987.

[4] V. Vorperian and S. Cuk, “A Complete DC Analysis of the Series Resonant Converter,” Proc. IEEE PESC’82, 1982.

[5] Y. G. Kang, A. K. Upadhyay, D. L. Stephens, “Analysis and design of a half-bridge parallel resonant converter operating above resonance,” IEEE Transactions on Industry Applications Vol. 27, March-April 1991 pp. 386 - 395

[6] R. Oruganti, J. Yang, and F.C. Lee, “State Plane Analysis of Parallel Resonant Converters,” Proc. IEEE PESC ’85, 1985.

[7] M. Emsermann, “An Approximate Steady State and Small Signal Analysis of the Parallel Resonant Converter Running Above Resonance,” Proc. Power Electronics and Variable Speed Drives ’91, 1991, pp. 9-14.

[8] Yan Liang, Wenduo Liu, Bing Lu, van Wyk, J.D, " Design of integrated passive component for a 1 MHz 1 kW half-bridge LLC resonant converter", IAS 2005, pp. 2223-2228

[9] B. Yang, F.C. Lee, M. Concannon,"Over current protection methods for LLC resonant converter" APEC 2003, pp. 605 - 609


[10] Yilei Gu, Zhengyu Lu, Lijun Hang, Zhaoming Qian, Guisong Huang, "Three-level LLC series resonant DC/DC converter" IEEE Transactions on Power Electronics Vol.20, July 2005, pp.781 - 789

[11] Bo Yang, Lee, F.C, A.J Zhang, Guisong Huang, "LLC resonant converter for front end DC/DC conversion" APEC 2002. pp.1108 – 1112

[12] Bing Lu, Wenduo Liu, Yan Liang, Fred C. Lee, Jacobus D. Van Wyk, “Optimal design methology for LLC Resonant Converter,” APEC 2006. pp.533-538

Hang-Seok Choi received the B.S., M.S. and Ph.D degrees in electrical engineering from Seoul National University, in 1996, 1999 and 2002, respectively. He is currently working for Fairchild Semiconductor in Bucheon, Korea as a system and application engineer. His research interests include soft-switching technique, and modeling and control of converters. He has published 15 papers in IEEE conferences and transactions and 10 application notes in Fairchild semiconductor.




Application Review and Comparative Evaluation of Low-Side MOSFET Drivers

Mark Dennis

Abstract — Power MOSFETs require a gate drive circuit to

translate the on/off signals from an analog or digital controller into the power signals necessary to control the MOSFET. This paper provides details of MOSFET switching action in applications with clamped inductive load, when used as a secondary synchronous rectifier, and driving pulse/gate drive transformers. Potential driver solutions including discrete and integrated driver designs are discussed. MOSFET driver datasheet current ratings are examined and circuits are presented to assist users in evaluating the performance of drivers on the lab bench.

I. INTRODUCTION

In many low to medium power applications a low-side (ground referenced) MOSFET is driven by the output pin of a PWM control IC to switch an inductive load. This solution is acceptable if the PWM output circuitry can drive the MOSFET with acceptable switching times without dissipating excessive power. As the system power requirements grow the number of switches and associated drive circuitry increases. Also, as control circuit complexity increases, it is becoming more common to omit onboard drivers because of grounding and noise problems. When the onboard driver does not offer acceptable performance (or is not included) external driver circuits are needed.

Synchronous rectifiers (SRs) are increasingly used to replace standard rectifiers when high efficiency and increased power density are important. It is common for isolated power stages delivering tens of amps to parallel two or more low resistance MOSFETs in each rectifying leg, and these devices require current pulses reaching several amps to switch the devices in the sub-100ns time frame desired. External drivers can provide these high current pulses and also provide a means to implement timing to eliminate shoot through and optimize efficiency to control the SR operation. In addition, drivers can translate logic control voltages

to the most effective MOSFET drive level. Low-side drivers are also used to drive

transformers which provide isolated MOSFET gate drive circuits or to provide communication across the power supply isolation boundary. In these applications a driver is required to handle concerns specific to transformer drive as discussed later.

Low-side drivers may seem to be a mundane topic, and several papers have been written on the subject. Though often presented as an ideal voltage source that can source or sink current determined by the circuit’s series impedance, the current available from a driver is in fact limited by the discrete or integrated circuit design. This topic will review the basic requirements of drivers from an application viewpoint, and then investigate methods for testing and evaluating the current capability of drivers on the lab bench.

II. CLAMPED INDUCTIVE SWITCHING

The simplified boost converter in Fig. 1 provides the schematic for a typical power circuit with a clamped inductive load. When the MOSFET Q is turned on the input voltage VIN is applied across inductor L and the current ramps up in a linear fashion to store energy in the inductor. When the MOSFET turns off the inductor current flows through diode D1 and delivers energy to COUT and RLOAD at voltage VDC. The inductor is assumed to be large enough to maintain the current at a constant level during the switching interval.


VDCL

VDD

VIN

RG

CBYP

VOUT

D1

Q

RLOADCOUT

IG

Fig. 1. Simplified boost converter

The circuit waveforms for a MOSFET that is turning on into a clamped inductive load are illustrated in Fig. 2.

VDD

VPL

VTH

IL

t4t3t2t1

VDS

IDS

VGS

IG

time

VO

IPK

IPL

Fig. 2. MOSFET turn on with inductive load

Fig. 3 (a)-(d) indicates the gate current paths which are active during the individual intervals of the MOSFET turn on process.

(a) (b)

(c) (d)

CGD

CGS

D1

CDS

IL

RG

RDS

VINVDCD

S

IG

VDD

CGD

CGS

D1

CDS

IL

RG

IDS

VINVDCD

S

IG

VDD

CGD

CGS

D1

CDS

IL

RG

IDS

VINVDCD

S

IG

VDD

CGD

CGS

D1

CDS

IL

RG

IG

VIN VDCD

S

VDD

RHI

RHI RHI

RHI

Fig. 3. Current paths during MOSFET turn on

RG represents the series combination of the MOSFET internal gate resistance along with any series gate resistor. RHI represents the driver’s internal resistance whose effective value changes throughout the switching interval. As shown below, the driver current IG can be determined by combining information presented in [1] and [2].

During interval t1 IG increases quickly and charges the combination of CGS and CGD to the gate threshold voltage VTH through the path shown in Fig. 3(a). In this interval the MOSFET carries no inductor current.

As interval t2 begins the MOSFET starts to conduct current in the linear mode

)( THGSmD VVgI −= (1)

through the current paths shown in Fig. 3(b). The parallel combination of CGD and CGS are charged from the threshold voltage to a plateau level given by

THm

DPL V

g

IV += (2)

as the drain current rises from zero to IL. QGS2 is the charge needed during this transition and can be determined from the MOSFET datasheet characteristic curves as illustrated in the application example presented later in this section. QGS2 allows us to calculate the time required for this transition as


G

GSriseIDS I

QTt 2

,2 == . (3)

Throughout t2 VDS remains at VOUT, clamped by diode D. At the end of t2 the MOSFET conducts the full IL current and the diode commutates.

As interval t3 commences the gate current flows through CGD and the MOSFET channel as shown in Fig. 3(c). All of IG is used to discharge CGD as VGS remains at VPL, and VDS begins to fall with a time period given by

G

GDfallVDS I

QTt == ,3 . (4)

In interval t4 IG flows through a combination of CGS, CGD, and the decreasing channel resistance RDS as shown in Fig. 3(d). During t4 the gate-source voltage rises from the plateau level to VDD. This allows one to determine the total gate charge QG,T required to turn on the MOSFET.

As the drain current rises during t2 and VDS falls during t3 the MOSFET has simultaneous high voltage across it and high current flowing through it, so the instantaneous power can be very high. An equation relating IG to the switching loss during the turn on interval is

( )

+

×=

3,2,

2, 2 tG

GD

tG

GSSW

LOADINONSW I

Q

I

QF

IVP . (5)

This equation clearly shows the importance of the magnitude of IG in relation to the switching losses. Unfortunately, there are no formal equations to calculate the current available from a given driver as the output voltage swings throughout its range. Empirical methods that allow users to determine the value of IG at different driver output voltage levels will be presented in section VII.

For a practical example, the Gate-Source Voltage versus Total Gate Charge is reproduced from the Fairchild FCP20N60 power MOSFET datasheet in Fig. 4. The curve was produced using a test circuit that drives the gate of the DUT (Device Under Test) with a small current source of 3 mA. In this example, the gate charge needed to reach the threshold voltage of 3V is approximately 7 nC. The charge required during interval t2, QGS2, is found to be 14 nC – 7 nC = 7 nC. In interval t3 the value of

QGD is found to be Qgd = 46 nC – 14 nC = 32 nC. In this typical case the effect of QGD on the switching loss is seen to be more significant than the contribution resulting from QGS2.

t4t3t2t1

FCP20N60

Fig. 4. Vgs versus Qg for FCP20N60

With VGS at the final drive level the value for QG,total is known. This allows one to find the average current required from the bias supply

SWGDD fQI ⋅= . (6)

where fsw is the switching frequency of the power stage. With the average current requirement known, the input power drawn from the VDD bias supply can be found as

SWGDDDDDDdr fQVIVP ⋅⋅=⋅= . (7)

The circuit waveforms and current paths during inductive load turn off are similar to those for turn on, but taken in a reverse order. For brevity, the circuit waveforms are indicated in Fig. 5 but the current paths are not shown.


t8t7t6t5

time

VDD

VPL

VTH

IL

Vo

-IPK

-IPL

VDS

IDS

VGS

IG

Fig. 5. MOSFET turn off with Inductive load

In the t5 interval IG rises to discharge VGS from VDD to the plateau level defined by (2). In the t6 interval VGS remains at the plateau voltage while VDS rises to the off state voltage. The t6 interval lasts for a time approximated by

G

GDriseVDS I

QTt == ,6 . (8)

In interval t7 the drain current IDS falls from the value of IL to 0 while VGS falls from VPL to VTH. This time interval is given by

G

GSfallIDS I

QTt 2,

,7 == . (9)

In the t8 interval VGS is discharged from the threshold voltage to zero.

An equation relating IG to the switching loss during the turn off interval is given as

( )

+

⋅⋅

×=

7,

2

6,

. 2

tG

GS

tG

GD

SWLOADIN

OFFSW

I

Q

I

Q

FIV

P

. (10)

III. SYNCHRONOUS RECTIFIER OPERATION

A MOSFET operated as a synchronous rectifier (SR) experiences a switching interval that is significantly different from the case of a clamped inductive load. Fig. 6 shows a simplified forward converter power stage with a synchronous rectifier QSR in place of the freewheel diode.

VIN

VDC

IGVDD

ControlCircuit

ISOLATION

QSR

L

Q1

VSEC

PWM

SR

D1

VOUT

Fig. 6. Simplified forward converter

In this example an SR signal generated by the control circuit crosses the isolation boundary to keep the synchronous rectifier QSR on while Q1 is off. However, the SR signal should command QSR to turn off before Q1 turns on to apply positive voltage to the transformer. Figure 7 shows four intervals that are used to illustrate the turn off sequence of the synchronous rectifier.


(a) (b)

(c) (d)

CGD

CGS

CDS

IL

RG

VDC

DBD

RLOW

VSEC

-+D

S

CGD

CGS

IL

RG

VSEC VDC

DBD

RLOW

-+

IG

RDS

S

D

VDC

CGD

CGS

CDS

IL

RG

VDC

DBD

RLOW

CGD1

CGS

CDS

IL

RGDBD

RLOW

IG

VSEC- +

VSEC

- +D D

S S

Fig. 7. SR MOSFET turn off

Prior to turn off the MOSFET conducts load

current IL through the resistive channel RDS and the drain to source voltage is negative. In Fig. 7(a) the output of the driver is low and the combination of CGD and CGS are discharged in parallel in a time interval given by

G

SRQoff I

Qt ,= , (11)

where QQSR is defined in [3] to be

DDSRGDGSSRQ VCCQ ⋅+= )( ,, . (12)

Also in [3] CGS,SR is estimated as

DD

SPECDSSPECRSSSRGD V

VCC

⋅⋅⋅=

5.02 ,

,, . (13)

From standard MOSFET nomenclature

RSSISSGS CCC −= . (14)

In Fig. 7(b) the MOSFET is fully off and IL flows through the body diode and the VSEC polarity has not changed. When VSEC changes polarity as shown in Fig. 7(c) current flows from VSEC to recover the body diode stored charge and the diode commutates. In Fig. 7(d) the body diode has been fully recovered and VDS rises quickly. The high dV/dT on the

MOSFET’s drain can cause a capacitive current to flow through the CDS/CGS voltage divider, so a driver with strong current sink capability is essential to hold the gate voltage below the threshold voltage.

In the synchronous rectifier application IG does not affect switching losses as it did in the clamped inductive load application. However, the paralleled MOSFETS used in SR applications require high current pulses to switch them effectively, and high current drivers are often located in close proximity.

IV. TRANSFORMER DRIVE APPLICATIONS

In power converters such as a half-bridge, full-bridge, two-switch forward converters, and active clamp forward converters there are high side switches or a combination of high/low switches that must be controlled. If galvanic isolation is not needed between the control and the power switches the MOSFETs may be driven with a semiconductor half-bridge gate driver, but the inherent propagation delay must be considered in the design. For circuits that do need isolation or can benefit from short propagation delays the venerable gate drive transformer should be considered as a potential solution.

In a related application, it is often necessary to provide high speed communication between the primary and secondary sides of an isolated converter. This can be accomplished by using technologies such as opto-isolators with digital outputs or magnetic pulse transformers. These pulse transformers are similar to the gate drive transformer but they are only required to transmit logic signals instead of delivering the high current pulses to turn a power MOSFET on and off.

The simplified circuit of Fig. 8 will be used to illustrate the basic operation of a low side driver and pulse transformer used in a communication circuit. The transformer is shown as ideal transformer with turns ratio NP:NS = 1:1 in parallel with magnetizing inductance LMAG. In both cases, the dc blocking capacitor CC is large enough so that its voltage is approximately constant.


R

CC

VDDT1

NP:NS

VS

-

+

VP

+

-

+

-

VOUT

IR

IDR

IMAG

IN LMAG

Fig. 8. Simplified pulse transformer circuit

In Fig. 9 the circuit is modified so that the resistor is replaced by the gate to source terminal of a MOSFET located on the high side of a bridge circuit.

CC

VDD T1NP:NS

VS

-

+

VP

+

-

+

-

VOUT

IGIDR

IMAG

IN LMAG

+Bulk

Fig. 9. Simplified gate drive transformer circuit

Fig. 10(a) shows the operational waveforms for the pulse transformer circuit while Fig. 10(b) shows operation in a gate drive application.

VOUT

IDR

IG

IMAG

VS

VP

VOUT

IDR

IR

IMAG

VS

VP

TSW

TON

TSW

TON

(a) (b)

Fig. 10(a) Pulse transformer waveforms and (b) Gate drive transformer waveforms

The output of the driver swings from 0 V to VDD producing a DC component equal to VDD x duty cycle. If this voltage was applied directly to the primary winding of T1, the transformer would saturate and not be able to transmit useful information. To prevent this from occurring coupling capacitor CC is inserted in series with the primary winding to block the DC voltage while passing the AC portion of the VOUT signal. Transformers designed for pulse and gate drive applications usually specify a voltage-time product that the device can withstand without saturating the transformer.

In many cases the same transformer could be used as either a pulse transformer operation or a gate drive transformer. In Fig. 10 the major difference between the two applications is found in the current waveforms. With a constant drive voltage and magnetizing inductance LMAG the magnetizing current IMAG is the same in both circuits. In the pulse transformer waveforms shown in 10(a) the resistor current IR follows the secondary voltage VS, and the driver supplies a current that is the sum of these two components. In the MOSFET gate drive waveforms shown in Fig. 10(b) the gate current IG is seen to be positive pulses at turn on and negative pulses at turn off. As in the first example


the driver supplies a current that is the sum of these two components, but the waveform has a larger RMS value due to the high current pulses.

It is important to examine the direction of current flow between driver and transformer for the examples of Fig. 10. When VOUT swings high as shown Fig. 11(a), one might expect the driver to immediately source current. However, the magnetizing current is negative, and if the load current is not larger than the magnetizing current the driver must sink current until IDR goes positive. The opposite situation exists in Fig. 11(b) when VOUT goes from high to low and the driver must source current when expected to operate as a current sink. Figure 11(c) shows additional diodes that provide a current path if the driver cannot sink current when VOUT is high or source current when VOUT is low, as found in drivers with a bipolar output stage.

VOUT

IDR

VOUT

IDR

Pulse transformer Gate transformer

(a)

(b)

VOUT

IDR

VOUT

IDR

Pulse transformer Gate transformer

(c)

R

CC

VDD

T1NP:NS

VS

-

+

VP

+

-

+

-

VOUTIR

IDR

IMAG

IN LMAG

Fig. 11. Current Flow and diode clamp circuit for transformer driver

If the transformer is designed with low leakage inductance the propagation delays through the transformer can be less than 50 ns. The GT03 series of transformers from ICE Components [4] is an example of devices that have leakage inductance of a few hundred nanoHenries. This low value is obtained by using tightly coupled windings on a small ferrite core.

In the previous transformer examples the positive and negative peaks vary with duty cycle while the secondary voltage VS swings around zero volts. In a pulse transformer application, the pulses might feed circuits that cannot accept the negative going pulses. The circuit in Fig. 12 incorporates a clamp circuit consisting of a second coupling capacitor CCS and a diode which restores the DC level of the secondary


voltage.

CCRS

VDD T1NP:NS

VS

-

+

CCS

VSIG

+

-

Fig. 12. Pulse transformer with DC restore circuit

Series resistor RS serves to damp the initial transient at startup when CCS is initially uncharged, and is often a discrete resistor in addition to the internal driver impedance. From classical RLC circuit theory a value of RS for critical damping is approximately

CC

MAGS C

LR ⋅= 2 , (15)

where LMAG is the magnetizing inductance of the transformer.

Fig. 13 shows a gate drive application circuit that utilizes the DC restore circuit of the previous example along with some additional modifications.

Vdd

CC

CCS

RS

Fig. 13. Improved gate drive transformer circuit

The PNP transistor added at the gate of the MOSFET is turned on when the secondary voltage goes negative to speed up the turn off time of the MOSFET. Reference [3] offers further information on transformer coupled gate drives, and should be consulted for detailed design methodology beyond the scope of the present topic.

V. DISCRETE OR INTEGRATED DRIVERS

External drivers can be designed using discrete transistors or by using integrated circuit solutions which come as predesigned blocks. In order to select a solution the designer must evaluate the competing size, features, cost and the overall range of applications to be covered. Regardless of the

driver selection there are some common requirements. Integrated or discrete-design drivers need a local bypass capacitor to supply the high current pulses delivered during the switching intervals, and might include a resistor between the driver and the PWM supply VDD. In general, drivers have the greatest impact when located close to the MOSFET gate-source connections to minimize parasitic inductance and resistance effects.

Discrete solutions can be designed using bipolar transistors as shown in Fig. 14. The NPN/PNP totem pole features a non-inverting configuration that is driven by the PWM output. This circuit prevents shoot-thru in the bipolar stage because only one of the totem pole devices can be forward biased at a time. In the bipolar common emitter configuration the driving signal must have fast edges to provide fast switching, and it should be noted that the MOSFET gate is not ohmically connected to the rail when high or low.

RGATERBPWM

VDDRFILTER LOAD

Fig. 14. Discrete bipolar transistor drive circuit

The PMOS/NMOS version shown in Fig. 15 has a natural inversion and would require an inverter to follow the PWM signal polarity. This circuit offers rail to rail operation, but shoot-thru is a problem that must be considered in design because both devices can conduct when the common gate node voltage is in the middle part of the VDD range.


RGATEPWM

VDD

RFILTER

PossibleInversion

LOAD

Fig. 15. Discrete PMOS/NMOS drive circuit

Using the discrete driver approach leads to a higher component count that requires more pcb board space along with more assembly and test time. The higher component count can lead to more procurement costs along with more reliability concerns. If the input signal comes from a logic circuit or a low voltage PWM the discrete driver requires additional circuitry to translate from the logic levels to power drive levels.

Integrated circuit drivers offer significant benefits in addition to large pulse current capability. New integrated dual drivers in 3x3 mm packages and single drivers in 2x2 mm packages include a thermal pad for heat removal. These devices require less board space than discrete solutions while offering enhanced thermal performance, so they are well-suited for the most dense power designs. Features integrated into the device such as an enable function and UVLO create ease of use, and less component-level design is required by users. It has been common practice to offer drivers with TTL compatible input thresholds that can accept inputs ranging from logic-level signals up to the VDD range of the device. Drivers utilizing CMOS input thresholds (2/3 Vdd = high, 1/3Vdd = low) can be used to alleviate noise issues or to set more accurate timing delays at the input of the driver.

VI. DRIVER DATASHEET CURRENT RATINGS

Driver datasheet current ratings and test conditions can lead to confusion. Many users consider the gate driver to be a near ideal voltage source that can instantly deliver current as determined by the circuit series resistance, and this is not necessarily true. Usually, the current available from a driver is limited by the internal circuit design

regardless of the semiconductor technology used. This self-limiting nature should not be confused with self-protecting, however, because if a driver output is shorted high or low the device is likely to fail.

Here are some common methods used for driver datasheet current ratings:

1. Peak current available from device, usually at initial turn on at max VDD

2. Current available with the output clamped at a specific voltage, often around VDD/2

3. Current available with low value resistance to rails (perhaps 0.5 ohm, even short circuit)

4. Current measured with a current probe

Integrated MOSFET drivers are commonly available in one of three technologies, either primarily MOSFET, bipolar, or a combination of the two technologies often referred to as compound devices. The MOSFET and bipolar versions are similar to the discrete solutions previously mentioned, while the compound design combines features from both technologies.

For low-side drivers built with a MOS output state (PMOS high side and NMOS low side, similar to the discrete circuit illustrated in Fig. 15) the datasheet current rating is generally specified as the peak current available from the part, often specified with VDD near the maximum rating of the part. Fig. 16 shows the output current and voltage for a 4 Amp driver using test methods detailed in section VII. This testing shows that the internal circuitry limits the peak output current to a value near the rated 4 Amps with no external resistor.

Vout@2V/div

Iout @ 1 A/div

IN @ 5V/div

Time = 200ns/div

Fig. 16. PMOS/NMOS driver Vout and Iout


The PMOS/NMOS drivers usually specify the driver output resistance when it is sinking or sourcing a specified current such as 100 mA. It is interesting to note that the MOS-type driver does not attain the RO,high or RO,low resistance values immediately when the device begins switching. For example, 4 Amp drivers commonly specify a value for RO,high or RO,low from 1 ohm to 2 ohms. If the devices reached this low resistance value instantaneously the peak currents would be more than seven amps with VDD = 15 V.

In compound devices, bipolar and MOSFET devices are combined in a parallel configuration such as the one shown in Fig. 17, where the power output devices are shaded. The bipolar transistors are able to deliver high sink and source current while the output voltage swings through the middle part of the output range. The PMOS and NMOS operate in parallel with the bipolar devices to pull the output voltage to the positive or negative rail as required.

Inputstage

VDD

VOUT

Fig. 17. Compound driver output stage

For compound drivers the output current is often specified with the output voltage at a specified voltage such as VDD/2 to highlight the current that is available during the Miller plateau region of the VGS waveform. In tests performed using the methods described in sec VII the peak output current is generally seen to be higher than the current specified at VDD/2. Fig. 18 shows the sink current

capability of a 4 Amp compound driver (FAN3224C) to be 4.76 Amps while the output is at 6.1 V, after reaching a peak just under 6 Amps. Thus, a compound driver rated at 4 Amps might deliver a higher peak current than a comparably rated PMOS/NMOS driver. This type of information is practically impossible to obtain from the driver datasheets, so specific test methods are required.

Iout @ 2 A/div

Vout @ 5 V/div

INPUT @ 10 V/div

Time = 200ns/div

Fig. 18. Compound driver current sink waveform

VII. EVALUATING DRIVERS ON THE BENCH

Real-world driver comparisons are difficult to perform in the lab because the fast signal ramp rates cause complex interactions between the inductive and capacitive circuit components. These fast edge rates can introduce overshoots and undershoots of several volts, and some examples to help quantify this effect in power circuits can be found in [5]. Although the parasitic inductance varies according to specific circuit layout and ground structure, [6] gives an approximate value of 10 nH/inch (4nH/cm) for microstrip on FR-4 with the trace exposed to air on one side. This provides an estimate that can be used with the circuit capacitance to calculate a damping resistor when needed.

It is difficult to compare competing devices using only datasheets which offer information produced using different test conditions. Competing technologies used in integrated circuit solutions further complicate device comparison. In the following paragraphs several circuits that can be used to test and compare drivers on the bench are presented.

Fig 19 shows a circuit that can be used to test the


pulsed current source capability of a driver by clamping VOUT to a level equal to VDSCH + VDZEN when the output is high. To minimize power dissipation the input is driven with a 200 ns positive-going pulse (for non-inverting driver) with a 2% duty cycle. In this circuit the positive-going voltage across RCS is used to monitor the current sourced out of the driver. In order to change the value of the output clamping voltage, the voltage rating of DZEN must be changed.

VDD

RCS

VPULSE

DZEN

DSCH

VCS

+

-

CBYP

VOUT

Fig. 19. Current source test circuit with clamped Vout

Fig. 20 shows a circuit used to test the pulsed current sink capability of a driver with the output voltage clamped at a level VADJ-VDSCH. Here, the input is driven with a 200 ns negative-going pulse (for a non-inverting driver) with a 2% duty cycle. In this circuit the negative-going voltage across RCS is used to monitor the current that the driver is sinking.

VDD

RCS

VPULSE

C1

DSCH

VADJ

VCS

+

-

CBYP

VOUT

Fig. 20. Current sink test circuit with clamped Vout

In both of these circuits there is a voltage transient that may last for 50-100ns as the current increases to the limits of the driver. A compact layout using surface mount components will help to keep the loop area small to minimize the parasitic inductance.

The two previous circuits require a unique surface

mount layout. It is possible to evaluate driver current capability by connecting a relatively large capacitive load on the output of a driver with the simple circuit shown in Fig 21.

CLOAD

VDD=12V

IPRB

VOUT

CBYP

Fig. 21. "Large" load test circuit

For a starting point, CLOAD is chosen to be 100 times larger than the load used for rise and fall time measurements, and the input is driven with a 1 kHz square wave. On typical datasheets, 2 Amp drivers are specified with 1 nF load for the rise and fall time specs, so CLOAD would be selected to be 0.1uF. This relatively large load prevents the output from changing rapidly, allowing the driver output current to reach its internal limiting value. A current probe IPRB can be used to monitor the output current along with the output voltage VOUT on an oscilloscope. This allows one to plot the output current available at the corresponding output voltage. Bench comparisons have shown that the current measurement obtained using this method agrees closely with that obtained using the clamp circuits in Figs 19 and 20. In addition, the slower current rise and fall times allow the current measurements to be made comfortably within the bandwidth limits of a current probe. Fig. 22 shows the waveforms obtained using the test circuit shown in Fig. 21 to evaluate a 2 Amp sink / 1.5 Amp source driver (FAN3227C) with a compound output stage. When the driver input Vin goes high, there is a transient glitch on the Vout trace as the output current quickly increases to 3 Amps through the inductance of the current probe loop. After approximately 70 ns the current has reached its peak value and the voltage spike across the parasitic inductances vanishes. With Vout = 6 V the output current is measured as 1.5 Amps (source current).


Iout @ 2 A/div

Vout @ 5 V/div

INPUT @ 10 V/div

Time = 200ns/div

Fig. 22. Compound driver current source waveforms

Fig. 22 shows the leading spike across the inductance introduced by the wire loop inserted in the circuit to enable use of a current probe. If the wire loop is removed and the 0.1uF surface mount capacitor is installed in a layout with minimal parasitic inductance, the waveforms shown in Fig. 23 are obtained. In short intervals where the voltage waveform is approximately linear the basic relation

⋅=

dT

dVCI OUT

LOAD (16)

can be applied to provide an estimate of the current.

Vout @ 2 V/div

INPUT @ 10 V/div

Time = 200ns/div

Fig. 23. Compound driver current estimation

The oscillogram in Fig. 23 allows one to calculate current during the cursor interval as

Ans

VuFI 8.2

6.40

131.11.0 =

⋅= , (17)

providing close agreement with the peak value seen in the IOUT trace in Fig. 22. A similar calculation around VOUT = 6 V provides a current estimation of 1.5 Amps, nearly identical to the result obtained with direct current measurement using a current probe. The close agreement between the current

measurement techniques using the large load helps to develop confidence in the results obtained.

VIII. SUMMARY

Low-side drivers are used to drive power MOSFETs in applications including clamped inductive load switching, synchronous rectifier circuits, and pulse/gate transformer drive circuits. The relationship of gate drive current to the MOSFET switching and transition intervals has been detailed during the prominent MOSFET switching intervals. Potential driver solutions including discrete components, integrated PMOS/NMOS, and compound drivers were examined. Some of the non-ideal characteristics of the various driver circuits were highlighted.

There has not been a simple unified method to characterize the output current sink and source capability of the many types of drivers available in the market. The test circuits presented in this topic can be used to investigate the VOUT versus IOUT capability of discrete and integrated circuit drivers, enabling users to evaluate and compare drivers for a range of applications.

REFERENCES [1] 2006 Fairchild Power Seminar Topic, “Understanding Modern Power

MOSFETs,” available on the fairchildsemi.com website at the link: http://www.fairchildsemi.com/powerseminar/pdf/understanding_modern_power_mOSFETs.pdf

[2] Oh, K. S., “MOSFET Basics”, July, 2000, available as AN9010 from the fairchildsemi.com website.

[3] Balogh, L. “Design and Application Guide for High Speed MOSFET Gate Drive Circuits,” Power Supply Design Seminar SEM-1400, Topic 2, Texas Instruments Literature No. SLUP169.

[4] ICE Components Gate Drive Transformer Datasheet “GT03.pdf” dated 10/06, available from www.icecomponents.com.

[5] 2006 Fairchild Power Seminar Topic, “Practical Power Application Issues for High Power Systems,” available on the fairchildsemi.com website at the link: http://www.fairchildsemi.com/powerseminar/pdf/practical_power_high_power_systems.pdf

[6] Johnson, H. Dr, “High-Speed Digital Design On-Line Newsletter,” Vol. 3 Issue 8, www.sigcon.com/Pubs/news/3_8.htm

Mark Dennis was born in Troy, NC, and received the Bachelor of Engineering degree from Duke University in 1983. After graduation he has worked in industries encompassing power electronics applications such as offline and DC to DC power supply design for telecom and computer systems, high voltage supplies for electrostatic precipitators, and

online UPS systems. For over eight years Mark has been working in the semiconductor industry and he is employed by Fairchild Semiconductor as a Staff Engineer working in High Power Systems.


Understanding Diode Reverse Recovery and its Effect on Switching Losses

Peter Haaf, Senior Field Applications Engineer, and Jon Harper, Market Development Manager, Fairchild Semiconductor Europe

Abstract — Half-bridge structures are extensively used in

power electronics applications: lighting, power supplies, UPS and motor drives. When these half-bridge circuits are hard switched, the low side diode reverse recovery affects system performance. This paper reviews the principle of diode reverse recovery and how this affects the semiconductor switch performance. Practical tests showing how di/dt and temperature affect performance are presented. Finally measurements using different devices are compared showing the curves for fast and soft recovery diodes, showing that in some cases, efficiency can be improved by adding capacitance in parallel with the diode.

I. INTRODUCTION

Half-bridge structures having two semiconductor switches with anti-parallel diodes are extensively used in power applications. Examples include motor drives, solar inverters, welding equipment and general AC/DC power supplies.

This paper focuses on how the choice of diodes affects the total switching losses. The effect of diode reverse recovery is introduced, showing how this generates losses in both the diode and the switch which is commutating that diode.

The paper moves on to practical considerations made from experimental measurements. Interesting effects relating to die size, temperature, di/dt and additional node capacitance are quantified. The limitations of the predictive ability of the formulae are highlighted.

By combining technical and practical considerations, this paper should provide the practicing engineer with an understanding of how to select the right diode for a given application.

II. SWITCHING LOSSES

Switching losses occur when a switching element in a circuit transitions from one state to another. The

voltage and current transitions can take several forms. Figure II-1 shows three possible linearized transitions of voltage and current waveforms and how the energy of the transition is calculated.

These basic formulae are used in the following discussion. Further, they are important in understanding the effect of capacitance on turn off losses in a later section of this paper.

t

V

I

0

E=1/2VIt E=1/6VItE=1/3VIt

t t t Figure II-1: Calculation of switching losses for various overlapping current and voltage waveforms

MOSFET switching losses have been extensively covered in [1]. We will review the switching losses caused by forced commutation of a diode.

If a diode is forced to turn off by another semiconductor switch, the diode will see switching losses. Additional losses will be generated in the semiconductor switch.

In simple terms, the reason for extra switching losses in a diode can be explained as follows. Figure II-2 shows the charge distributions for a diode in the conducting and the non-conducting states [2]. Here we are showing a p-n junction for illustrative


purposes, rather than the p-i-n junction used in power diodes.

P-type N-type

xx=0

Minority carrier concentrationnear the junction

x

Minority carrier concentrationnear the junction

Electronconcentrationin P-type region

Holeconcentrationin N-type region

Electronconcentrationin P-type region

Holeconcentrationin N-type region

P-type N-type

x=0

Diode conducting Diode blocking

Figure II-2: Charge distributions for a diode in the conducting and blocking states

For the diode to transition from the conducting to the non-conducting state, the charge distribution must change. This can only happen with a movement of charge, which is a flow of current. In some cases, such as a silicon carbide diode, the charge distribution difference is caused solely by the junction capacitance: again a movement of charge occurs when moving from the conducting to the non-conducting state.

The distribution curves show minority carrier density as a parameter. So, the larger the active junction area (other parameters being held constant), the larger the charge difference. Therefore devices in the same family with larger die sizes, represented by higher current ratings, will have a larger reverse recovery charge.

If the movement of charge between the non-conducting and conducting states happens during the same switch state, there is no additional loss. For example, in a discontinuous mode boost converter, the current in the diode drops to zero while the power switch is in the off state.

However, if an external switch forces the diode to change from the conducting to the non-conducting state (“forced commutation”) extra current is required to change the states, causing dissipation in both the diode and the switch.

Figure II-3 and Figure II-4 show the reverse recovery behavior of a diode under forced commutation.

DC Bus

Reference GND

Switch

IL IDIODE

ISWITCH

VDD

VSWITCH

VDIODE+

+

-

-

DC Bus

Reference GND

Switch

IL IDIODE

ISWITCH

VDD

VSWITCH

VDIODE+

+

-

-

Figure II-3: Circuit to show the effect of diode reverse recovery on the diode and on the semiconductor switch

t

iSWITCH

VDD

iDIODE

IL

0

IL + IRRM

IRRM

-VDD

vSWITCH

vDIODE

tA tBtR

t

iSWITCH

VDD

iDIODE

IL

0

IL + IRRM

IRRM

-VDD

vSWITCH

vDIODE

tA tBtR

Figure II-4: Effect of diode reverse recovery on the diode and on the semiconductor switch

The plot starts with the turn on of the lower switch. After the gate voltage on the lower switch reaches the Vth level, the lower switch builds up current in the saturation mode, causing a linear increase in the switch current, and a linear decrease in the diode current, as the inductor current is constant.

The diode temporarily conducts in the reverse direction. The maximum current (IRRM) is the reverse recovery current, and is specified in the diode datasheet. It increases greatly with temperature. It increases with di/dt. As will be shown later, it increases with current.


Time interval tA is defined as the time between the zero crossing of the current and the peak reverse current. Time interval tB is defined as the time between the peak of the reverse current and the time where the current falls to zero (or a pre-defined low level). The sum of tA and tB is called the reverse recovery time, tRR.

The switching power dissipation in the diode is given by:

RRMDDBDIODEON IVt61

E = (1)

where VDD is the bus voltage. The power

dissipation during time tA is considered to be part of the conduction losses of the diode.

The reverse recovery current also induces extra losses in the semiconductor switch. The total switch on loss is given by the following formula:

BRRMLDDARRMLDD

RLDD SWITCHON

tIIVtIIV

tIVE

)3

1

2

1()

2

1(

2

1

++++

= (2)

where IL is the load current and tR is the time interval between the start of switching and when the semiconductor switch provides the full load current.

By setting tA and IRRM to zero, the equation for on-losses in the absence of reverse recovery is readily obtained:

BLDDRLDD SWITCHON tIVtIVE )21

(21 += (3)

where in this case tB is the time interval between

when the semiconductor switch provides the full load current and when the voltage across the switch has dropped to the minimum value.

The extra EON loss attributable to the diode can be calculated by subtracting the two equations:

BRRMDDARRMLDD EXTRAON tIVtIIVE )31

()21

( ++= (4)

Noting that IRRM can often exceed the normal forward rated current of the diode, these extra switching losses and their impact are significant.

For a normal diode, tB is much smaller than tA. For a soft recovery diode, tB is larger than tA. For a given reverse recovery time, tRR (= tA + tB), the equation above shows that the semiconductor switch losses when using a soft recovery diode are less than the losses caused by a normal diode, as:

RRMRRML III31

21 >+ (5)

However, the switching loss generated in the

diode itself (equation 1) is proportional to tB. As a soft recovery diode has a larger tB value than a normal diode, the diode losses will be higher. Nevertheless, accounting for these losses in the above equation shows that there is still a clear benefit for the overall system efficiency.

The important conclusion is that the use of a soft recovery diode will introduce more switch-on losses in the diode itself, but save additional losses in the semiconductor switch. When evaluating the performance of a new diode, it is therefore necessary to look at both the diode and semiconductor switch performance, not just the diode performance.

Another benefit of a soft switching diode is that the dv/dt rate during time tB is much lower than for a normal diode because tB is longer. High dv/dt can cause ringing losses and extra EMI in a circuit.

Finally, soft recovery diodes generally have a lower IRRM than normal diodes.

In the absence of reverse recovery, equation (3) can be rearranged in terms of the applied di/dt and dv/dt in the system:

dtdv

VI21

dtdi

IV21

E

2DDL

2LDD

SWITCHON += (6)

This equation will be used in later discussions. Finally, it is important to note the effect of


temperature on IRRM and tRR. While the forward voltage of a diode decreases as temperature increases, the parameters affecting switching characteristics, IRRM and tRR, both increase with temperature. With reference to Figure II-2, the minority charge concentration will increase with temperature, so it is to be expected that both IRRM and tRR will also increase with temperature.

Figure II-5 demonstrates these results for two industry standard diodes.

Results for Tj = 25°C

di/dt=200A/ms, Vdd=400V, If=8A, Tj=25°C

Two industry standard diodes

Results for Tj = 125°CResults for Tj = 25°C

di/dt=200A/ms, Vdd=400V, If=8A, Tj=25°C

Two industry standard diodes

Results for Tj = 125°C

Figure II-5: Comparison of reverse recovery performance for two industry standard diodes at Tj=25ºC and at Tj =125ºC. Upper curve: ISL9R860P2, lower curve: 8A/600V competitor part.

III. EXPERIMENTAL SETUP AND BASIC MEASUREMENTS

In principle, it is possible to estimate many of the

factors affecting switching losses in a circuit. For IGBT’s, EON and EOFF are normally specified in the datasheet for a specific set of conditions. For MOSFET’s, these values can be calculated from the circuit parameters. The additional effect of the diode on switching losses can be estimated using the formulae from the previous section.

In practice, it is important to assess the performance in a real circuit. First, it is important to verify the performance compared with the theoretical framework. Second, effects which are difficult to quantify, such as the beneficial effect of node capacitance on the turn off performance, need to be considered.

The objective of our experiments was to compare the performance of different types of diodes using one type of MOSFET. We chose diodes of all

speeds with ratings from 4A to 15A. All tests were performed at a current of 4A.

Figure III-1 shows the experimental setup. The diode under test is on the high side. The MOSFET (or IGBT) is on the low side. Figure III-2 shows the waveforms needed to operate the circuit, taken when using an FQP9N50C MOSFET.

First, the MOSFET is turned on until the test current level in the inductor is reached. The MOSFET is then switched off, causing the test current to flow through the diode. Shortly afterwards, the MOSFET is switched on to measure the switch-on losses, and then switched off to measure the switch-off losses. As the MOSFET was only switched on for a very short time, the test results apply to a junction temperature close to the ambient room temperature of 25ºC.

The construction of the test set-up was on a standard prototype board having no copper plating. The devices under test were placed in sockets. The sockets were connected together with short, low impedance connections. The results obtained are comparable with those of a standard printed circuit board layout.

Figure III-1: Circuit diagram of test setup


Figure III-2: Drive waveforms for test circuit. Channel 1 is the drain voltage, channel 2 is the gate voltage, and channel 4 is the drain current. MOSFET: FQP9N50C.

For slow di/dt testing we used a CD4000 series

logic gate with external P-channel and N-channel MOSFET’s. In the course of the experiment, we found that the speed was insufficient for high speed testing, so we replaced the circuit with a 12V low voltage driver circuit (FAN5009) which has approximately 1 ohm output resistance when turning on.

Figure III-3: Waveforms measured during switch on

Figure III-3 shows a typical set of plots for EON measurement. The parts used are the FQP9N50C MOSFET and the FFP08H60S diode. Channel 1 shows the voltage on the switching node. Before switching, the switching node voltage is high, here

300V. Channel 4 shows the current through the low side switch. When the MOSFET is switched on, the current rises with a di/dt influenced by the MOSFET gate charge characteristics and the driver circuit component values. Before switching, the current value is zero. After completion of switching, the current value is 4A in the example. The instantaneous power is calculated by the oscilloscope on Channel M2. The area under M2 represents the switching energy which in this case is 32.6 uJ (noting that 1W = 1J/s).

The maximum value of the current, minus the steady state current is equal to the reverse recovery current of the diode. In this case, this is 7.9A – 4A = 3.9A.

Figure III-4: Waveforms measured during turn off

Similarly, Figure III-4 shows a typical set of plots for EOFF measurement. The turn-off transition is not discussed in detail here because diode forward recovery, which occurs during turn-off, usually produces much smaller losses than reverse recovery during turn-on. Again, Channel 1 shows the voltage on the switching node, Channel 4 shows the current through the low side switch and Channel M2 shows the instantaneous power.

Note that there is a small level of ringing. Further, there is a small voltage spike caused by the forward recovery of the diode.


IV. SWITCHING LOSS BEHAVIOR UNDER DIFFERENT TEST

CONDITIONS AND USING DIFFERENT DEVICES

In this section we review the effect of the diode

on the switching losses seen during switch turn on. As the switching losses seen in the diode are much smaller, as discussed in Section II, these are not reviewed.

The first evaluation was to look at the effect of

input voltage on the turn-on and turn-off losses. For the first stage of this experiment, we compared two diodes from the same family. The results are shown in Figure IV-1.

Eon and Eoff losses of the FET - FQP9N50C vs Input Voltage

0

5

10

15

20

25

30

35

40

45

50

0 50 100 150 200 250 300 350

Input Voltage [V]

Eo

n a

nd

Eo

ff L

oss

es [

uJ]

Eon @ ISL9R1560

Eoff @ ISL9R1560

Eon @ ISL9R460

Eoff @ ISL9R460

Figure IV-1: Comparison of EON and EOFF losses against voltage for 4A and 15A Stealth™ diodes

There are several important conclusions to be

made. First, switching losses will always rise with input voltage. During the current ramp up phase, the losses are proportional to the product of the bus voltage and the load current, so a strong linear relationship is to be expected. Second, the EON losses are higher for a larger die device of the same family, than they are for a smaller die, or a lower current rated device. Third, the EOFF losses are lower for a larger device of the same family than they are for a smaller device. Finally, the EON losses dominate, being approximately twice the EOFF losses.

The next stage of the experiment was to compare the EON losses for a greater variety of 600V diodes

rated in the range of 4A to 15A. Figure IV-2 shows the results, followed by a table describing the part numbers.

Eon losses of the FET - FQP9N50C vs Input Voltage

0

10

20

30

40

50

60

70

80

90

0 50 100 150 200 250 300 350

Input Voltage [V]

Eon

Los

ses

[uJ]

Eon @ MUR1560

Eon @ RURP860

Eon @ RURD660

Eon @ FFPF10UP60

Eon @ ISL9R1560

Eon @ RHRP860

Eon @ ISL9R860

Eon @ ISL9R460

Eon @ SIC 6A

Figure IV-2: EON losses versus voltage for a wide range of diodes

TABLE I DIODES AND MOSFET BODY DIODES USED IN THE EVALUATION

Part Number Description

FCP11N60F Fast recovery diode from 11A, 600V superjunction MOSFET

FQP5N50CF Fast recovery diode from 5A, 500V planar MOSFET

MUR1560 15A, Ultrafast (low speed) 600V Diode RURP860 8A, Ultrafast (low speed) 600V Diode RURD660 6A, Ultrafast (low speed) 600V Diode

FFPF10UP60 10A, Ultrafast (low speed) 600V Diode ISL9R1560 15A, Stealth (soft, high speed) 600V Diode RHRP860 8A, Hyperfast (medium speed) 600V Diode ISL9R860 8A, Stealth (soft, high speed) 600V Diode ISL9R460 4A, Stealth (soft, high speed) 600V Diode

SiC 6A 6A, Silicon Carbide, 600V Diode

The lowest EON losses in the experiment came

from the silicon carbide and Stealth (highest speed) diodes. The Hyperfast (medium speed) diodes were next lowest, followed by the Ultrafast (lower speed) diodes. As predicted by theoretical analysis, for a given class of diodes, higher current rated devices (which have larger dies) had higher EON losses.

One interesting practical aspect is the effect of switching speed in this application. As discussed earlier, a certain amount of energy is needed to turn-on the semiconductor switch:


dtdv

VI21

dtdi

IV21

E

2DDL

2LDD

SWITCHON += (6 repeated)

At 160 A/us, 20000V/us, 300V and 4A, the EON

required just to turn-on the switch is 24uJ. With reference to Figure IV-2 this accounts for a large part of the losses for the best devices at 300V.

In many applications, the switching di/dt and dv/dt is limited by EMI constraints. Better efficiency can be obtained by using a faster switching diode, as the results show. However, at current prices, the incremental cost of moving to silicon carbide is very high. If system requirements limit di/dt to say 200A/us, from a switching perspective, silicon carbide diodes offer only a slight improvement in performance. For applications where much higher di/dt is permissible, silicon carbide diodes offer a definite benefit.

Another clear observation from the test results is that the benefit of a fast diode increases with voltage, shown by the increased spreading of the curves at higher voltage. The benefit of using a Stealth diode in a system using a 450V bus voltage is more than that at 300V.

The second evaluation was to look at the effect of input current on the turn-on and turn-off losses. For this experiment, we compared different diodes including MOSFET body diodes. The results are shown in Figure IV-3

Eon and Eoff losses of the FET - FQP9N50C vs Current

0

20

40

60

80

100

120

140

160

180

200

0 1 2 3 4 5 6 7

Current [A]

Eon

an

d E

off

Lo

sses

[uJ]

Eon @FCP11N60F

Eon @ FQPF5N50CF

Eon @ RURD660

Eon @ RHRP860

Eon @ ISL9R460

Eoff @ ISL9R460

Figure IV-3: Comparison of EON and EOFF losses against current for various diodes and for the body diodes in the FCP11N60F and FQPF5N50CF MOSFET’s

As expected from the theoretical analysis (equation 2), there is a strong linear dependence on the current. This results from the higher current flowing through the MOSFET. However, as will be shown shortly, the loss contribution from the diode is not strongly dependent on current for fast recovery diodes.

The third evaluation was to look at the effect of input current and input voltage on the maximum reverse recovery current. For this experiment, we compared different diodes including MOSFET body diodes. The results are shown in Figure IV-4 and Figure IV-5.

Irr, Reverse Recovery Peak Current of the Diode vs Current

0

2

4

6

8

10

12

14

0 1 2 3 4 5 6 7

Current [A]

Rev

erse

Rec

ove

ry C

urr

ent

[A

]

Irr @ FCP11N60F

Irr @ FQPF5N50CF

Irr @ RURD660

Irr @ RHRP860

Irr @ ISL9R460

Figure IV-4: Comparison of IRRM against load current for various diodes including MOSFET body diodes


Irr, Reverse Recovery Peak Current of the Diode vs. Input Voltage

0

1

2

3

4

5

6

7

0 50 100 150 200 250 300 350

Input Voltage [V]

Rev

erse

Rec

ove

ry C

urr

ent

Irr

[A]

Irr @ MUR1560

Irr @ RURD660

Irr @ FFPF10UP60

Irr @ ISL9R1560

Irr @ RHRP860

Irr @ ISL9R860

Irr @ ISL9R460

Irr @ SIC 6A

Figure IV-5: Comparison of IRRM against voltage for various diodes including MOSFET body diodes

Two important conclusions come out from the experimental results. First, the IRRM level is not strongly dependent on voltage and current for the faster diodes in the selection. We have seen in Section II that temperature has a larger effect. We will review the effect of di/dt shortly. Second, the reverse recovery current of fast recovery MOSFET’s is very high, even exceeding the nominal rated current of the devices.

The fourth evaluation was to look at the effect of di/dt. Increasing di/dt will reduce the turn-on losses in the MOSFET’s. However as a side effect, both IRRM and tRR will increase with increasing di/dt.

Reverse Recovery Current Irr of the Diode vs dI/dt @ V = 300V @ dI/dt = 4A

0

1

2

3

4

5

6

7

8

9

10

0 200 400 600 800 1000 1200 1400 1600

dI/dt [A/us]

Rev

erse

Rec

over

y C

urr

ent

Irr

[A

]

Eon @ ISL9R3060

Eon @ FFP08H60S

Eon @ RHRP860

Eon @ ISL9R860

Eon @ ISL9R460

Figure IV-6: Effect of di/dt on reverse recovery current (IRRM)

Figure IV-6 shows the effect of di/dt on reverse recovery current. Taking a simplified approach based on Figure II-4, the value 0.5tAIRRM is equal to the reverse recovery charge for a hard switching diode, and IRRM/tA is equal to di/dt. So if the reverse recovery charge remains constant, we would expect IRRM to increase with increasing di/dt, as seen in the graph. A detailed analysis of the results shows that IRRM increases more than expected from this simplistic analysis. This is seen in datasheets as a higher reported reverse recovery charge for different di/dt conditions, other parameters being held the same.

So increasing di/dt will increase diode induced switching losses in the diode and in the semiconductor switch, and decrease switching losses caused by the overlap of the rising current and steady voltage waveforms. It is therefore important to assess which factor dominates.

Figure IV-7 shows the effect of increased di/dt on EON losses. Here we see a clear benefit of higher di/dt on EON losses despite the higher diode induced switching losses. To get 400A/us, we used a 30 ohm gate resistor on the FQP9N50C driven by a FAN5009 1 ohm driver. For 600A/us we used FDD6N50C with a 30 ohm resistor. Values of 10 ohm and 3 ohm gave di/dt of 1400 A/us and 1600 A/us respectively.

Eon losses of the FET vs dI/dt @ V = 300V @ dI/dt = 4A

0

5

10

15

20

25

30

35

40

45

0 200 400 600 800 1000 1200 1400 1600

dI/dt [A/us]

Eon

Los

ses

[uJ] Eon @ ISL9R3060

Eon @ FFP08H60S

Eon @ RHRP860

Eon @ ISL9R860

Eon @ ISL9R460

Figure IV-7: Effect of di/dt on EON losses


The final evaluation was to consider the effect of additional capacitance on the overall losses.

Figure IV-8: No capacitance: ISL9R460 diode, 300V, 4A

Figure IV-9: 470pF capacitance: ISL9R460, 300V, 4A

Figure IV-10: 1nF capacitance: ISL9R460, 300V, 4A

The figures show the different turn off curves for

a circuit with no parallel capacitance (Figure IV-8), 470pF parallel capacitance (Figure IV-9) and 1nF parallel capacitance (Figure IV-10). As the

capacitance increases, EOFF decreases. In the case of no parallel capacitance, the voltage

rises before the current falls. With reference to Figure II-1, the formula is 1/2VI for this case (26uJ from the scope measurement). When 470pF is added, the voltage rises while the current is still falling, so the formula is 1/6VI, resulting in approximately 1/3 of the loss (8uJ). Further, the curves are smoother, moving away from the simple linearized approximation. In the final case, the overlap is very small (5uJ).

The addition of extra capacitance will cause a large increase in the turn-on losses. We show the 470nF turn-on example below:

Figure IV-11: 470pF capacitance: turn-on performance

If extra capacitance increases the EON losses but reduces the EOFF losses, then there is the possibility an optimum point. We conducted experiments with different capacitor values and came up with the results in Figure IV-12. Based on these results, the addition of a small amount of extra capacitance does indeed make sense for the particular configuration used. As it is difficult to quantitatively predict the effect of capacitance on EOFF losses, such evaluation requires experimentation.


Eon and Eoff losses with a snubber Capacitance

0

10

20

30

40

50

60

70

80

90

100

0 100 200 300 400 500 600 700 800 900 1000

Capacitance parallel to the Diode [pF]

Eto

t / E

on

/ Eo

ff lo

sses

[u

J] Etot at 300V

Etot at 200V

Etot at 100V

Eoff at 300V

Eon at 300V

Eoff at 200V

Eon at 200V

Eoff at 100V

Eon at 100V

Figure IV-12: Effect of adding parallel capacitance on EON, EOFF and total losses

V. PACKAGE RECOMMENDATIONS

The package size and type is an important parameter for the selection of diodes. While it is beyond the scope of this paper to cover detailed thermal design, we would like to cover a couple of points.

The maximum permissible junction temperature is always specified for power switches and diodes, and generally is 150ºC. In practice, designers will design to 125ºC maximum junction temperature to provide a safety margin for increased system robustness and reliability.

Combining this information with experience on how packages are used with heatsinks, we provide the following table as a guideline, for applications not using fans or forced convection:

Package and mounting Max Power TO247 with isolated foil on heatsink 30W TO220 with isolated foil on heatsink 10W TO263 on printed circuit board 1W

VI. CONCLUSION

Reverse recovery in diodes introduces small losses in the diode but larger losses in the MOSFET or IGBT which is switching the diode. These losses are influenced by the two reverse recovery parameters IRRM and tRR.

From a system design perspective, there are three aspects influencing the optimization of a half-bridge structure: di/dt, diode choice and the possible inclusion of a parallel capacitor.

Higher di/dt results in lower EON losses in the circuits tested, noting that higher di/dt increases IRRM losses less than it decreases the normal switching losses. So from perspective of switch and diode losses, increasing di/dt is beneficial despite the increase in IRRM.

The use of fast recovery diodes improves switching losses, but generally worsens conduction losses. Larger current rated diodes of the same family have higher IRRM resulting in higher EON, and a larger capacitance, resulting in lower EOFF. Over-dimensioning of the diodes is not recommended as this leads to higher total switching losses.

Addition of extra capacitance increases EON losses but decreases EOFF losses. There is the possibility that an optimum total loss point will exist, meaning that the addition of extra capacitance will reduce total losses. Designers of circuits using half-bridges should consider this possibility in their applications: inclusion of a low cost capacitor may help improve efficiency.

REFERENCES [1] J. P. Harper, “Understanding Modern Power MOSFET’s” Fairchild

Semiconductor Power Seminar 2006, www.fairchildsemi.com [2] J. Millman, Microelectronics: Digital and Analog Circuits and

Systems, McGraw Hill, p42, 1979.


Peter Haaf studied Elektrotechnik at the University of Karlsruhe, Germany. After graduation in 1992, Peter joined the R&D department of Vossloh-Schwabe on power applications, becoming a design team leader. Since 2001, he has been a senior field application engineer for Fairchild Semiconductor in Germany focusing on power supply and high power applications.

Jon Harper After completing a BSc/MEng degree at the University of Bath, England, Jon started as an applications engineer for microcontrollers at National Semiconductor in Germany. He completed an MBA degree at Warwick Business School in 1996 and joined the refounded Fairchild Semiconductor as a marketing engineer. Since 2002, Jon has covered technical marketing for industrial and white goods products,

focusing on power electronics.




Low Cost, Isolated Current Source for LED Strings

Stephan Klier, Lab Engineer, Fairchild Semiconductor Europe

Abstract This article describes the design of an isolated

constant current source to drive high power LED’s from an AC power line. The constant current source is built using a flyback topology and has an efficiency greater than 80%. Conventional current sources need many components for this. This application is a low-cost solution based on an innovative circuit (patent filed) using a Fairchild Power Switch (FPS). The converter is primary side regulated removing the need for an optocoupler and other additional components.

I. INTRODUCTION

Designers of lighting applications are making wider use of light emitting diodes (LED’s) which combine high luminous efficiency with low energy consumption. High Power (high luminosity) LED’s are now available in a compact package which is easy to mount in lighting applications. Application examples include traffic lights and street lighting, medical applications and consumer electronics such as cabinet lighting and table lamps. LED’s are driven with a constant current. For low power LED’s this is generated by a constant voltage source and a series resistor. High Power LED’s need a constant current source: resistors would dissipate too much power.

II. CONSTANT CURRENT, CONSTANT VOLTAGE

AND CONSTANT POWER SOURCES

A constant current source is a source that always supplies the same output current. The output conductance of the power source is zero. As a result its output resistance is infinitely high. Constant current sources are used if a change of the load must not change the output current.

LED’s are diodes which are operated in the forward direction. They are driven with constant current for two reasons. First, this keeps the light output at a constant level. Second, if LED’s were to be operated with constant voltage, any temperature

rise would increase the mobility of charge carriers within the junction and the current would rise exponentially, destroying the device.

The circuit described in this paper can be used to implement a constant current source, a constant power source and a constant current source with foldback.

For ideal current sources the output current is constant for all output voltages. However for real current sources, the output voltage is limited as shown in the V-I characteristic plot in Figure II-1.

0

0,2

0,4

0,6

0,8

1

1,2

0 0,2 0,4 0,6 0,8 1 1,2

Output Current [normalised]

Ou

tpu

t Vo

ltag

e [n

orm

alie

d]

Figure II-1: Current and voltage curve of an idealized current source with a voltage limit

Unlike the output voltage of a constant current

source, the output voltage of a constant power source decreases as the current increases. The product of output voltage and output current, or the output power, remains constant. This results in the hyperbolic characteristic shown in Figure II-2.


0

0,2

0,4

0,6

0,8

1

1,2

0 0,2 0,4 0,6 0,8 1 1,2

Output Current [normalised]

Ou

tpu

t Vo

ltag

e [n

orm

alis

ed]

Figure II-2: Constant power characteristics

The following figure shows a typical foldback characteristic (Figure II-3). Once the maximum (nominal) output current is reached, additional reductions of the load resistance lead to reduction of both the output voltage and the output current. If the load is short-circuited, only a minimal current flows in the load.

0

0,2

0,4

0,6

0,8

1

1,2

0 0,2 0,4 0,6 0,8 1 1,2

Output Curent [normalised]

Ou

tpu

t Vo

ltag

e [n

orm

alis

ed]

Figure II-3: Foldback characteristics

III. THE FAIRCHILD POWER SWITCH: FPS

The FPS is a solution for switch mode power supplies, requiring few external components. It integrates the pulse width modulator (PWM) and SenseFET into one package. The PWM block works in current mode, by measuring the current through the SenseFET and using this information to regulate the pulse width. The peak current through the SenseFET is proportional to the voltage at the feedback pin. Here the peak current is the maximum value of the current through the primary side of the flyback transformer, specifically ignoring capacitive turn-on effects masked by the leading-edge blanking circuit.

The isolated power supply presented in this paper

uses the adjustable current limit feature of the FPS. An external resistor can be used to adjust the maximum permissible peak current in the integrated SenseFET.

R102R102

Figure III-1: Block diagram of current limit and feedback section of FPS

With reference to Figure III-1, the non inverting input of the PWM comparator is connected to an internal voltage divider network, which is fed by an internal current source. An additional resistance at the current limit pin thus forms a parallel connection to the internal resistance network. The voltage drop over this network caused by the current of the internal current source affects the PWM comparator. The latter compares the signals of the current limit pin (and feedback pin) with the current through the SenseFET and regulates the pulse width. The value of the resistance can be determined with the following equation:

LIMITLIMITFPS

LIMITFPS

IIIR

102R−

×= (1)

Here ILIMIT is the current limit desired by the

designer, ILIMITFPS is the current limit specified in the FPS datasheet and RFPS is sum of the two internal resistances, specified in the FPS datasheet. For example, RFPS is 2kohm + 0.8kohm = 2.8kohm for the device shown in Figure III-1 which is the FSDH321BM. Both ILIMITFPS and RFPS are device specific.

The FPS has other features relevant to this application. First, it has an internal start-up circuit, removing the need for an external one. Second, the switching frequency is modulated over a limited


range, reducing peak EMI values as the spectrum of the conducted noise is spread over a range of frequencies. Further features include under-voltage lock out (UVLO), leading edge blanking (LEB), thermal shutdown (TSD), abnormal over current protection (AOCP). Compared with the controller and MOSFET solutions for switch mode power supplies, solutions using the FPS reduce the number of additional components, decreasing the design size and weight, and increasing efficiency, productivity and reliability. At light loads, the FPS operates in burst mode to improve efficiency.

IV. FLYBACK CONVERTERS

The flyback converter (Figure IV-1) is the most frequently used topology for switch mode power supplies in household and consumer electronics.

The main elements on the primary side are an input rectifier (D101, C102), a transformer (T1) to transfer energy and a switch (integrated in the FPS, IC101).

R101, C103 and D102 form a snubber network to limit the voltage spikes on the FPS drain generated by the leakage inductance of the transformer when the FPS MOSFET is switched off. The snubber reduces the voltage stress on the drain.

The FPS bias voltage comes from an auxiliary winding of the transformer, D105 being the output diode and C105 the output capacitor on the primary side of the transformer.

The signal measuring the output state is fed back to the primary side using an optocoupler.

The energy is transferred from the magnetizing inductance to the secondary side during the OFF state of the SenseFET. D201 is the flyback output diode. C201 is the output capacitor.

In this circuit the regulation is based on a measurement made on the secondary side. The error amplifier is also on the secondary side. IC201 combines an optocoupler and an industry standard FAN431 circuit which in effect combines an error amplifier with a reference.

Figure IV-1: Voltage output flyback converter with secondary side regulation

The voltage divider (R203 and R204) sets the output voltage. The optocoupler LED is biased using R201. The reference circuit is biased using R202. The full circuit with the addition of R205 and C202 forms a Type 2 compensator (integrator, gain, and pole-zero pair) to compensate the power supply.

An alternative, lower cost possibility (not shown) is to put a suitably dimensioned Zener diode in series with the optocoupler LED and a bias resistor. However, the high variability of the Zener diode and the absence of a compensator with an integrator term make the system regulation less accurate and less stable.

Primary side regulation can be realized with fewer components. In this case there is no need for an optocoupler, even for a fully isolated power supply.

Figure IV-2 Voltage output flyback converter with primary side regulation

Figure IV-2 shows an isolated flyback design using primary side regulation. Winding W3 (between pins 4 and 5) of transformer T1 is used to generate the feedback signal. The voltage on this winding is proportional to the voltage on winding W2 (between pins 7 and 6), as long as the two windings are coupled very well. An increase in the

+ C102

-2

~3

~4

+1

D101

AC Line

AC Line

D105

+ C201R101

+ C105

D102

C104

VStr5

Dra

in7

Dra

in8

GN

D1

Vcc2

VFb3

Dra

in6

Ipk

4

IC101

FSDH321BM

2

1

9

5

10

3

4 6

7

8

T1

R102

D201

C103R109

GND

+ Output

IC201FOD2741BTV

R201 R202 R203

R204

R205C202

D105

+ C201

R110

R104

R101

D106+ C105

D102

C104

VStr5

Dra

in7

Dra

in8

GN

D1

Vcc2

VFb3

Dra

in6

Ipk

4

IC101

FSDH321BM

2

1

9

5

10

3

4 6

7

8

T1

R102

D201

C103R109

Q101

+ Output

GND


load results in a reduction in the current in D106. This results in a lower base current for Q101. This decreases IC of Q101, so VFB increases. The controlled peak current in the SenseFET increases, which results in an increase in the duty cycle and therefore the output voltage. R110 is the bias resistor for the Zener diode and R104 is the base resistor for Q101.

C104 reduces the noise on the feedback pin and influences the control loop transfer function.

An additional function of C104 is to set the turn off delay in case of an output overload condition. An overload condition will tend to drive the voltage on the feedback pin high. If the voltage on the feedback pin is 4V (nominal), the PWM controller operates at the maximum duty cycle specified in the datasheet. If the voltage on C104 exceeds this level, the PWM controller continues to operate at maximum duty cycle. Above 4V, C104 is charged by an internal current source of around 5uA. If the overload condition persists, the voltage on C104 will sooner or later exceed the shutdown feedback voltage, around 6V. In this case, the FPS is shut down. By dimensioning the output capacitor, the time during which overload conditions is tolerated can be adjusted. The power supply can support temporary overload conditions but will shut down after longer overload conditions.

Figure IV-3: Constant current output, secondary side regulated flyback converter

A flyback converter can be used to implement a constant current source as shown in Figure IV-3. This is achieved by introducing a measurement resistor R201. The voltage across this resistor is proportional to the load current. So regulating the voltage across this resistor in a similar way to that of a voltage output flyback circuit results in a regulated output current. Since the VBE of Q1 is around 0.7 V, the power dissipation in R201 (measure resistance) is very high with large output current. Further as Q1’s VBE is temperature dependent, an NTC (negative temperature coefficient) resistor (R202) is required. This kind of regulation is not very exact, because of the thermal variations. The efficiency of this circuit depends on the preset output current. In order to achieve a good performance for larger output currents an operational amplifier circuit (Figure IV-4) must be used. We note that both circuits need optocouplers.

As the intention is to describe a simpler circuit, the function of the circuit in Figure IV-4 will not be explained here in detail.

Figure IV-4: High constant current output, secondary side regulated flyback converter

23

1

IC202KA431LZ

+ 400 VDC

GND

D105

+C201

R101

+ C105

D102

C104

VStr5

Dra

in7

Dra

in8

GN

D1

Vcc2

VFb3

Dra

in6

Ipk

4

IC101

FSDH321BM

2

1

9

5

10

3

4 6

7

8

T1

R102

D201C103

R109

GND

+ Output

R209

R203

R202

R206

R205

C203

R201

R204

R202

+3

-2

V+8

V-4

OUT1

IC203A

+5

-6

V+8

V-4

OUT7

IC203BR207

R208

D202

+ C202

1

23

4

IC201H11A817C

D6

D7 C204

+ 400 VDC

GND

D105

+C201

R101

+ C105

D102

C104

VStr5

Dra

in7

Dra

in8

GN

D1

Vcc2

VFb3

Dra

in6

Ipk

4

IC101

FSDH321BM

2

1

9

5

10

3

4 6

7

8

T1

R102

D201

C103R109

+ Output

GND

IC201FOD2741BTV

R204 R205 R206

R207

R208C202

R201

Q201 R203

R202


V. CONSTANT CURRENT OUTPUT PRIMARY SIDE REGULATED FLYBACK CONVERTER

Figure V-1: Constant current output primary side regulated flyback converter

Figure V-1 shows the circuit of a primary side

regulated constant current output flyback power supply.

The components required for the primary side regulation can be split into two blocks. Block 1 is similar to the primary side regulation circuit described earlier, with the inclusion of R103 and D104. Block 2 is added to provide the constant current output function.

The function of Block 1 is explained first. For low load currents, the output voltage is constant as described earlier. An increase in load results in a lower output voltage and consequently a lower voltage on winding W3 (pins 4 and 5). This is because W3 is well coupled to the secondary output winding W2 (pins 6 and 7). The voltage on C107 is equal to VBE of Q101 plus the Zener voltage of D106. A reduction in this voltage results in a lower current through D106, leading to a lower base current in Q101. So voltage VFB rises, increasing the duty cycle and ultimately the output voltage.

When the current limit set by R102 is reached, the peak current is constant and the output voltage sinks

with increasing load current. This results in a constant power V/I characteristic.

For discontinuous conduction mode (DCM) operation, this can easily be shown. The power transferred from the primary to the secondary (and leakages) is:

SW2

PEAKPO fIL21

P = (2)

where LP is the primary inductance, IPEAK is the peak current and fSW is the switching frequency. So if IPEAK is limited, the power transfer is limited, resulting in a constant power characteristic.

The analysis for continuous conduction mode (CCM) operation is more complex and beyond the scope of this paper. The conclusions of the analysis and the experimental results show an almost constant power characteristic.

R103 in Block 1 disables the overload circuit protection described earlier, which is not explicitly needed in a constant current output application. Without R103 in constant power mode, the voltage on the feedback would rise to the shutdown voltage

Block 1

Block 2

+ 400 VDC

GND

D105

+ C201

R110

R103

D107

D104 R104

R101

D106

D103 + C105

D102

R108

C104

VStr5

Dra

in7

Dra

in8

GN

D1

Vcc2

VFb3

Dra

in6

Ipk

4

IC101

FSDH321BM

2

1

9

5

10

3

4 6

7

8

T1

C107 C108

R102

R106

R107

D201

C103R109

Q101

R105


level and switch off the power supply.

10,0

15,0

20,0

25,0

30,0

35,0

0 100 200 300 400 500

Output Current [mA]

Ou

tpu

t Vo

ltag

e [V

]

Figure V-2: Primary side controlled constant current output circuit with Block 1 activated (R102 = 1500 ohms)

The above figure shows the effect just described. At low currents, the circuit operates in constant voltage mode. Above 200mA output current, the circuit operates in constant power mode.

To turn the circuit into a constant current source, the components shown in Block 2 are required. Block 2 performs input line regulation and load regulation. The negative part of the voltage Vcc on W3 is rectified by D107 and filtered by R107 and C108. The resulting voltage is negative with respect to ground, and is proportional to the line input voltage. Additionally it generates a negative bias voltage needed for load regulation. As a precaution, a diode D104 is included in Block 1 to protect Q101 against possible negative base bias.

At light loads, the circuit operates in constant voltage mode. At the point where constant power mode is reached, the voltage on the anode of D106 will drop. An additional current therefore flows through the current limit pin through R105, so that the current limit is reduced further. This results in a positive feedback signal. The desired characteristics can be achieved by modifying resistor R105: a large value is used for constant current mode and a lower one for foldback operation.

R108 is used to compensate the output current for variations in the input voltage, which would otherwise increase the power output. An increase in input voltage, results in an increased current flow from the current limit pin, which ultimately reduces the power output.

D105, C105 and R109 form the bias power supply

for the FPS. D103 is needed if the voltage used for the regulation is higher than the desired power supply level for the FPS.

VI. DESIGN GUIDELINES

There are design tools for the dimensioning a flyback design on the internet homepage of Fairchild Semiconductor: www.fairchildsemi.com. These tools simplify the calculation of the transformer as well as the snubber network and components on the secondary side. If there is a wide range of output voltages, Vcc should be selected in such a way that its value is in the middle of this range. If the value of Vcc is too high for the supply of the FPS, the Zener diode D103 will be required. Otherwise, an additional auxiliary winding is necessary.

When using the design tools from Fairchild Semiconductor, the input voltage, output voltage and output current must be specified. As a rule of thumb use 2-3 µF/W for the DC link capacitor. The next step is to choose a value for voltage VRO, the reflected output voltage. The sum of VRO, the maximum input voltage and the snubber voltage should not exceed 80-90% of the rated voltage for the switching element.

The next steps are to insert the switching frequency, the adjusted current limit and the ripple factor into the calculation sheet. In DCM, the ripple factor is set to 1.

For the transformer design, it is useful in some applications to use a larger core than needed to keep the current stress on the FPS and on the secondary side lower. For the individual windings the value for the current density is considered to be 5 A/mm2. After that the number of parallel wires and their diameters can be determined easily.

Select output diodes with a voltage rating equal to 1.5 to 2 times that calculated for voltage stress. The output capacitors should have a very low impedance (low ESR) to reduce output voltage spikes.

For the snubber calculation assume 2.5% of primary inductance as the value for the leakage inductance. Set the snubber capacitor voltage to 1.5 VRO.


The feedback signal in this application, as already described, is generated by the current source of the FPS.

Output current is adjusted by resistors R102, R105, and R108.

The value of the peak current limit to be used for a particular output current is found as follows. The constant current operation occurs at the transition between the constant output voltage mode and constant output power mode. This occurs when:

SW2

PEAKPOO fIL21

IV = (3)

where VO is the output voltage limit required by

the system design and IO is the output current. An initial value for R102 may be calculated by

solving (3) for IPEAK, then substituting this result for ILIMIT in (1). This result for R102 must then be increased to compensate for the currents drawn by R105 and R108.

In practice, R102, R105 and R108 are determined by experimentation. R105 adjusts the current difference during minimum and maximum output voltage. The effect of the line input voltage is adjusted with R108. Table A-2 in the Appendix shows the incremental approach used to determine these values.

As a rule of thumb R102 is in the range of 1 to 5 kilohm, R105 in the 10 to 50kohm and R108 in the 100 to 200 kilohm range.

The output voltage limit is set by the Zener diode voltage (D106):

)(2

3FO

S

SFBEZ VV

n

nVVV +=++ (4)

where VZ is the Zener diode voltage, VBE is the operating base-emitter voltage of Q101, VF is the forward conducting voltage of D107 and D201, nS2 is the number of turns on the secondary output and nS3 is the number of turns on the auxiliary output.

VII. TEST RESULTS

The results presented here are for an application to drive high power OSRAM LED’s having a forward voltage of around 3V driven at a current of 700mA. These LED’s are very bright. Do not look at the LED’s when they are switched on. The output voltage of the current source can vary between 12V and 22V depending on how many LED’s are connected in series.

0.00

0.20

0.40

0.60

0.80

1.00

180 190 200 210 220 230 240 250 260 270

Input Voltage [Vrms]

Sta

nd

by

Po

wer

[W

]

Figure VII-1: Standby power versus input voltage

Figure VII-1 shows the standby power versus input voltage for no load.

80.0

82.0

84.0

86.0

88.0

90.0

180 190 200 210 220 230 240 250 260 270


Eff

icie

ncy

[%

]

Figure VII-2: Efficiency versus input voltage

The constant current source was driven at the maximum power and the efficiency was measured for a range of input voltages.

For measuring the V/I characteristics, the output voltage was varied and the output current was measured. These tests were performed using an input voltage of 230Vrms.


90.0

95.0

100.0

105.0

110.0

12 14 16 18 20 22

Output Voltage [V]

Reg

ula

tio

n [

% o

f n

om

inal

]

Figure VII-3: Regulation versus load (output voltage)

The constant current plot shows that the current level stays within 5% of the nominal except at very light loads, showing excellent performance.

In comparison with Figure II-1, we show the

constant current characteristic of the test circuit. Figure VII-4 shows the plot when R105 and R108 have the values specified in the schematic of Figure A-2. R102 is not mounted, so the internal current limit of the FPS is used for this purpose. The voltage limit between 23V and 25V dominates the curve.

10,0

15,0

20,0

25,0

30,0

35,0

0 100 200 300 400 500 600 700 800

Output Current [mA]

Ou

tput

Vo

ltag

e [V

]

Figure VII-4: V/I characteristic for primary side regulated constant current source

By adjusting the resistors, a foldback

characteristic can be obtained. Here R102 was set to 2 kilohm, which sets the maximum current at just over 200mA, and R105 set to 15 kilohm, which is a low resistor value forcing the foldback. R108 was not mounted.

10,0

15,0

20,0

25,0

30,0

35,0

0 50 100 150 200 250

Output Cuurent [mA]

Ou

tpu

t Vo

ltag

e [V

]

Figure VII-5: Foldback characteristic

Finally the EMI plot was measured at maximum load and at nominal input current. The results show that there is no problem to meet EN55011/22 Class B EMI limits.

Figure VII-6: EMI plot for test circuit

VIII. CONCLUSION

In comparison with other isolated flyback constant current output power supplies, the reviewed circuit using the FPS has fewer components offering a lower cost system solution. It offers an ideal solution for driving high intensity LED’s.

REFERENCES [1] Fairchild Semiconductor Application Note AN4105: Design

considerations for Switched Mode Power Supplies Using A Fairchild Power Switch (FPS) in a Flyback.

[2] Fairchild Semiconductor Application Note AN4137: Design Guidelines for Off-line Flyback Converters Using Fairchild Power Switch (FPS)

[3] Fairchild Semiconductor Application Note AN4141: Troubleshooting and Design Tips for Fairchild Power Switch (FPS) Flyback Applications


Stephan Klier is a Lab Engineer, working for Fairchild Semiconductor for over two years in the Global Power Resource Center in Fürstenfeldbruck,

Germany. Stephan graduated as ‘Staatlich geprüfter Techniker in Elektrotechnik’ at the technician school Munich in July 2004.


APPENDIX

Figure A-1: Top and bottom views of primary side regulated constant current source

Top view Bottom view

Dimensions: 65.5mm x 47.0mm x 25.0 mm (Lx B x H)

Figure A-2: Circuit diagram

Table A-1: Demo Board Specification

Minimum Input Voltage 185 VRMS Maximum Input Voltage 265 VRMS Frequency 50 Hz Output Voltage and Current 12 V – 22 V / 700 mA constant current

D104FDLL4148

C10733nF

R109

1000.6W

R104

47K0.6W

+

C1014.7uF400V

+

C1024.7uF400V

C202

2.2nF250V

D10618V

C1032.2nF1000V

R107470.125W

R101100k0.6W

D201ES2D

C1081uF50V

D10316V

D105MMBD1503A

D107MMBD1503A

VStr5

Dra

in7

Dra

in8

GN

D1

Vcc2

VFb3

Dra

in6

Ipk

4

IC101FSDH321L

Vcc

1

2

CONN101B2P3-VH

D102RS1K

+ C10510uF50V

R103820K

C10468nF

R102open

R10539k0.6W

R108160K0.6W

12

CONN201B2P-VH

R10610k0.6W

2

1

9

5

10

3

4 6

7

8

T1EF20 12V / 700mA

185 - 265 Vrms

-4

~1

~2

+3

D101MB8S

Q101BC847B

+ C201330uF35V

LF1

2 x 47mH, 0.25A


Table A-2: Example of experimental step-by-step adjustment to obtain constant output current

VINMIN VINNOM VINMAX R102 R105 R108 at VOUTLOW at VOUTHIGH X Open 62 k 140 k 741 mA 671 mA X Open 62 k 140 k 701 mA 640 mA X Open 62 k 140 k 684 mA 626 mA

X Open 39 k 150 k 703 mA 708 mA X Open 39 k 150 k 665 mA 674 mA X Open 39 k 150 k 654 mA 664 mA

X Open 39 k 160 k 730 mA 733 mA X Open 39 k 160 k 703 mA 704 mA X Open 39 k 160 k 693 mA 697 mA

Table A-3: Transformer Specification

Name Pinning Layers Diameter Turns Construction Material

W1a 3 →2 2 1 x 0.18 mm 52 Solenoid CuLL W2 7 →6 2 1 x 0.5 mm 19 Solenoid CuLL

W1b 2 →1 2 1 x 0.18 mm 52 Solenoid CuLL

W3 5 →4 1 1 x 0.15 mm 15 Spaced CuLL *CuLL is copper wire with two thin insulation layers Core: E20 Material: N27 (Epcos) or equivalent Bobbin: E20 vertical / 10 pins Gap in center leg: approximately 0.34 mm for AL of 135nH/Turns2

Figure A-3: Transformer Construction

Table A-4: Transformer Characteristics Parameter Pins Specification Conditions Primary Inductance 1 → 3 1459 µH +/- 5% 10 kHz, 100 mV, all secondaries open

Leakage inductance 1 → 3 73 µH maximum 10 kHz, 100 mV, all secondaries short




Design Review: Power State Design for a 200W Off-Line Power Supply

Michael Weirich, Lab Manager, Fairchild Semiconductor Germany

ABSTRACT

This paper describes the design of the power train of a two switch forward power supply with a continuous PFC front end based on the FAN4800. Design choices for such a power supply are reviewed. Practical topics including power device selection, magnetic design, layout and EMI are discussed with the aim of helping practicing engineers to accelerate and improve their designs.

1 Introduction

New AC power supply designs, in the range of 200W - 500W, increasingly require power factor correction (PFC) which reduces the energy wasted in the power utility supply lines and increases the maximum power which can be drawn from a power outlet.

This article describes the design and construction of a 200W power supply intended for use in an LCD TV, so a lot of attention has been paid to achieve high efficiency, standby power below 1W, small form factor, especially a height of 25mm, simple cooling without a fan and last but not least, low cost. These features are indispensable for the intended application.

2 Circuit Description and Design

The specifications for this design are: • AC Input Voltage: 85 – 265VRMS • Power-Factor: > 0.95 • Total Output Power: 200W • Three DC Outputs: 5V/0.3A,

12V/5A, 24V/6A

The power supply consists of two units.

The first power supply incorporates a PFC circuit, built around the FAN4800 PFC/PWM combo controller and generates the 24V/6A and the 12V/5A outputs. This device contains an average current-mode PFC controller and a PWM controller able to work in both voltage and current mode. In the presented application, the PWM works in current mode and controls a two switch forward converter. This converter generates a regulated 24V output. The 12V output is generated with a buck converter controlled by an MC34063A PWM controller. This additional block improves regulation of the 12V

output and reduces cross-regulation problems, which is always a problem with a multiple output forward converter when loads vary over a wide range. The additional converter cost is not very high if one keeps in mind the more complex and larger coupled inductor for a dual output forward converter.

The second power supply is a flyback converter based on the Fairchild Power Switch (FPS) FSD210B that generates both the 5V output and the supply voltage for the FAN4800. This power supply is the one that is active in standby mode and its no load power consumption is below 500mW. Therefore, it is possible to meet the 1W limit for standby consumption even with a small load in an active power save mode.

For simplicity, the design calculations and schematics will be given for each block individually. The complete schematic and layout can be found in the appendix.

3 Power Factor Correction

This section reviews the selection of the power devices used in the PFC circuit. The dimensioning of the low power parts that set up the operating point of the multiplier and the gain and frequency compensation of the error amplifiers is reviewed in [1]. Figure 1 shows the schematic.

3.1 Rectifier

Since the main power supply is designed to deliver an output power of 200W, the total input power, Pin, assuming an efficiency of 90% for the PFC and an efficiency of 90% for the forward converter, including output stage will be:

WW

PIn 2479.09.0

200 =⋅

= (1)

With the minimal input voltage of 85VRMS one gets a maximum input current of:

AV

WI RMSIn 9.2

85

247, == (2)

The common mode choke of the EMI filter has to cope with this current and must at the same time have a high inductance of 10mH. There are a few chokes on the market, that combine high current, high inductance and low profile, namely from EPCOS and TDK. The actual value and type of the choke has to be determined with


EMI testing and, depending on the operating conditions, might differ from the filter that is proposed in this paper.

The negative temperature coefficient thermistor (NTC) in series with the input limits the inrush current, but is not really necessary for the operation of the power supply.

The rectifier could be selected according to IIn,RMS, but noting that diodes with higher current ratings normally have a lower voltage drop at a given current, it is favorable to use a rectifier bridge with a slightly higher current rating. For the actual design, a 6A/800V bridge GBU6K has been chosen.

The rectifier loss can be estimated in the well known manner approximating the diode forward characteristic by a constant forward voltage plus a series resistance. The forward voltage VF and the series resistance RS have to be estimated from the datasheet as 0.8V and 0.03Ω respectively for the GBU6K. The loss equation then becomes:

W

I

VI

RIVIP

RMSIn

RMSIn

DSDRMSDFDAVGBRLoss

7.4

)03.02

8.045.0(4

)(4

2

,

,

,2

,,,1,

=

Ω⋅

+

⋅⋅⋅=⋅+⋅⋅=

(3)

If one assumes an absolute maximum junction temperature TJ of 150°C and a maximum ambient temperature TA of 50°C then the maximum thermal resistance (case to ambient) of the heatsink for BR1 should be

WWW

P

TTR

BRLoss

AJBR

C12

C0.75

7.4

C50-C1501,

max,max,1,

°≈

°−°°=

−=Θ

(4)

n.a. = not assembled denotes SMD

-+

~ ~

BR1GBU6K

D15FDLL4148

D1ISL9R460P2

R810K

D101N4148

D111N4148

C2470nF

D121N4148

Ieao1

Iac2

Isense3

Vrms4

Ss5

Vdc6

Ramp17

Ramp28

Ilim9

GND10

Vo211

Vo112

Vcc13

Ref14

Vf b15

Veao16

IC1

FAN4800

C62.2nFR1c

390K

R2427k

C16680pF

R3110K

R7b1MR1a

390K

D16

FDLL4148

C23100nF

R2a620K

R2b620K

+ C5c82uF

C12470nF

C14100nF

R1247K

C2680nF

C13470nF

NTC12R

C2481nF

R7a620K

+ C5b82uF

R1b390K R4

18K

R11820K

C1

680nF

C7220pF

R234.7K

LF110mH

C1522nF

1 2

R50.15

C8100nF

+ C5a82uF

R35100

816

L11.0mH

L3FERRITE BEAD

250V

/

J1GSF1.1001.31

C3100nF

C910nF

R1522

Q1FCP16N60

Vcc

HB_InISense

0

Vbus

Vfb Figure 1: Schematic of the PFC stage with part numbers aligned with FAN4800 application note [1] for convenience

3.2 Inductor L1

In the presented design the amplitude of the ripple current through L1 was chosen to be 20% of the input

current. With this choice, the inductance can be calculated according to the following equation [1]:


( )

mHWkHzV

VVV

PdIfV

VVVL

InSOut

InInOut

08.1247%20100400

85)285400(

2

2

2min,min,

1

=⋅⋅⋅

⋅⋅−=

⋅⋅⋅⋅⋅−

=

(5)

giving an inductance of almost exactly 1mH. The peak current of L1 is

A

I

II

III

RMSIn

RMSInRMSIn

RippleRMSInLPeak

5.4

1.12

222.02

22

,

,,

,1,

=⋅⋅=

⋅⋅+⋅=

+⋅=

(6)

while the RMS current is equal to the RMS input current. With this current and a current density of 5A/mm2 the necessary copper area is about 0.58mm2. Since the high frequency current is only 20% of the input current, skin- and proximity effect are not very distinct. Three or four thinner wires in parallel, having in sum the required area, are sufficient. In the actual design three wires of 0.5mm diameter have been used, leading to a current density slightly below 5A/mm2.

The core size of L1 is chosen with the help of the so-called core area product AP, which is the product of the effective magnetic cross section and the winding area (of the bobbin). This product can easily shown to be

CuPeak

CuPeakweP fB

AILAAA

⋅⋅⋅=⋅= (7)

where ACu is the copper area, BPeak is the saturation flux density (≤0.35T for most ferrites) and fCu the copper fill factor, which is about 0.5 for a simple inductor and about 0.4 for a transformer with several windings. With these data the necessary AP for L1 is

42

149145.035.0

58.05.41mm

T

mmAmHAP =

⋅⋅⋅= (8)

Based on the observance that for most cores the magnetic cross section and the winding area are very similar, one looks for a core with

Pe AA = (9)

So for our application, a suitable core should have an Ae of about 122mm2. While it is not difficult to find cores with this magnetic cross section, the height of the inductor is limited to 25mm by the application. Therefore, after some careful searching of core and bobbin datasheets, an EER3542 core was chosen, with an Ae of 107mm2 and an AW of 154mm2, giving an AP of about 16500mm4

An approximate length s of the gap in the center leg is given by:

−⋅⋅⋅≈

0,

114.0

LLe AA

As π (10)

where AL,0 is the AL of the ungapped core (given in the core’s datasheet) and the AL of the gapped core is 1mH/1242 = 65nH. If the latter two values are in nH and Ae is given in mm2, the gap length s is in mm. In this particular case the gap length is about 2 mm.

3.3 Q1 and D1

Since the maximum rated input voltage is 265VRMS, maximum drain voltage of 500V for Q1 seems to be sufficient. It is nevertheless recommended to use a 600V rated MOSFET, since experience shows that a 600V MOSFET is able to withstand the surge test according to IEC 61000-4-5 without damage, while a 500V type needs additional surge voltage limiters. The same is valid for boost diode D1. This is due to the fact that the electrolytic cap C5 is able to absorb a lot of energy, protecting a 600V device but not a 500V device.

The peak currents of Q1 and D1 are identical to that through L1 i.e. 4.5A, while the RMS current of Q1 is given by:

A

V

VA

V

VII

Out

MinInRMSInQRMS

5.24003

852819.2

3

281 ,

,1,

=⋅⋅

⋅⋅−⋅=

⋅⋅⋅

−⋅=

π

(11)

and that of D1 is:

A

V

VA

V

VII

Out

MinInRMSInDRMS

46.14003

85289.2

3

28 ,,1,

=⋅⋅

⋅⋅⋅=

⋅⋅⋅

⋅=

π

. (12)

Especially for the MOSFET, low losses and not the peak current is the important factor for selecting a certain device. After some calculations the SUPERFETTM FCP16N60 with a maximum RDSon of about 0.45Ω @ 100°C has been chosen. The total losses of Q1 have to be divided into conduction and switching losses. The conduction losses are:

W

RIP QDSONQRMSCond

QLoss

8.2

1,2

1,1, max

=

⋅= (13)

Switching losses are further divided into losses due to the discharge of the Drain-Source capacitance (plus parasitic capacitances e.g. of the L1 and PCB), losses due to the overlap of voltage and current during the switching process and losses due to reverse recovery of D1. All three terms are not known exactly


but have to be estimated with the following expressions:

( )

W.

kHzns.VA..

ftVI.P

W.

kHzVpF.

fVCC.P

ScrossoverOutRMS,InCross

Q,Loss

SOutexteff,OSSCap

Q,Loss

62

100505040092906

190

12

10040026050

50

1

2

21

=⋅⋅⋅⋅⋅=

⋅⋅⋅⋅⋅≈

=⋅⋅⋅=

⋅⋅+⋅≈

(14)

WPrrQ,Loss 21 ≈ (15)

COSS,eff of the FCP16N60 is 110pF, while the parasitic capacitances Cext have been estimated to be 150pF. 50ns for the crossover time tcrossover is a reasonable estimate and was confirmed by measurement. The loss induced by the diode reverse recovery losses is estimated to be 2W.

Finally, the total loss of Q1 is:

W.P Q,Loss 591 ≈ (16)

The maximum thermal resistance of a heatsink for Q1 therefore is about 10ºC/W.

Conduction losses of D1 are calculated in a similar manner as those of BR1:

W

AVA

RIVV

P

RIVIP

DSDRMSDFOut

Out

DSDRMSDFDAVGCond

DLoss

9.0

08.047.13.156.0 2

1,2

1,1,

1,2

1,1,1,1,

=

Ω⋅+⋅=

⋅+⋅⋅

=

⋅+⋅≈

η (17)

Switching losses of D1 are estimated to be around

2W, confirmed by measurement. The total loss of the diode will be

WP DLoss 9.21, ≈ (18) A suitable heatsink for this diode should have a

thermal resistance of no more than 25ºC/W.


4 Two Switch Forward Converter

Figure 2 shows the two switch forward converter stage. In this application, the PWM section of the FAN4800 operates in current mode and controls a two switch forward converter. This topology is basically identical to the well known single transistor forward converter. But it has the advantage that each of the two transistors only needs a maximum drain voltage equal

to the DC output voltage of the PFC. The standard forward converter in comparison needs double that value, requiring a rated drain voltage of 800 – 900V. Moreover, in the two switch version, the transformer construction is simpler and cheaper since it does not need a reset winding.


24V

R242n.a.

C2491nF

R24633

Q211FCP7N60

12

CONN5

R22522

R20513k

R20210k

C235100nF

R2451.5K

C1522nF

TR1

R241n.a.

C16680pF

+

C247n.a.

12

R2330.47

R2427k

R240n.a.

D216RS1K

+ C246680uF

OC1FOD2741BTV

R234.7K

Ieao1

Iac2

Isense3

Vrms4

Ss5

Vdc6

Ramp17

Ramp28

Ilim9

GND10

Vo211

Vo112

Vcc13

Ref14

Vf b15

Veao16

IC1ML4800IS

R24733

D220FYP2010DN

R22622

D14FDLL4148

C23115nF

L540uH9A

D224n.a.

C238470pF

C239220nF

C2501nF

+ C245680uFQ212

FCP7N60

D217UF5407

Q210n.a.

+C244680uF

D218UF5407

D219FYP2010DN

C12470nF

D13FDLL4148

VCC1

HIN2

LIN3

COM4

LO5

VS6

HO7

VB8

IC4

FAN7382N

R204180K

R234220

C230n.a.

Vbus

Vcc

Vcc

Figure 2: Schematic of the Forward Converter

There are of course disadvantages to be considered:

the proposed topology needs two transistors instead of one and the gate signal of one of them is floating at a high voltage. If one has a closer look, these issues are not that big as the on resistance of Power MOSFET is proportional to the drain voltage to the power of 2 to 2.5. That means that two transistors with half the drain voltage and half the on resistance – in order to get same conduction loss – use in sum less silicon.

So the cost of either solution is similar. As the gate driver FAN7382 is used, the second

drawback disappears as well. This device contains one low-side and one high-side gate driver which are completely independent. That is important since in the two switch forward both transistors are turned off and on at the same time. When both are on, the energy is

transferred to the secondary, when both are off, the transformer is de-magnetized via reset diodes D217 and D218.

The main design equations for the two switch and the single switch forward are identical and therefore Fairchild Application Note AN-4137 and its associated spreadsheet shown in Figure 3 [2] can be used for calculation after a few changes have been considered.

Since the converter DC voltage is generated by a PFC pre-regulator, the line voltages entered into the spreadsheet have to be chosen appropriately in order to get the right DC link voltage. In this application 284VRMS are used for both the minimum and maximum line voltage. The line frequency does not influence the


calculation. For forward converter with reset winding

Blue cell is the input parametersRed cell is the output parameters

1. Define specifications of the SMPSMinimum Line voltage (V_line.min) 284 V.rmsMaximum Line voltage (V_line.max) 284 V.rmsLine frequency (fL) 50 Hz

Vo Io Po KL1st output for feedback 24 V 8.5 A 203 W 1002nd output 0 V 0 A 0 W 03rd output 0 V 0 A 0 W 04th output 0 V 0 A 0 W 0Maximum output power (Po) = 202.8 WEstimated efficiency (Eff) 90 %Maximum input power (Pin) = 225.3 W

2. Determine DC link capacitor and the DC voltage rangeDC link capacitor 1000 uFDC link voltage ripple = 4 VMinimum DC link voltage = 397 VMaximum DC link voltage = 402 V

3. Determine the maximum duty ratio (Dmax)Maximum duty ratio 0.45Turns ratio (Np/Nr) 1 >Maximum nominal MOSFET voltage = 803 V

0.82

Figure 3: Excerpt of the Excel sheet belonging to AN-4134

Next, a huge DC link capacitor (e.g. 1000uF) should be entered pro forma, since, due to the PFC, the ripple voltage across the real DC link capacitor is quite small.

The maximum duty cycle has to be strictly below 0.5 to allow transformer de-magnetization. In order to leave some margin a value of 0.45 for the maximum duty cycle has been chosen.

Since the sheet was developed for a single transistor forward, the np/nr (Excel: Np/Nr) ratio and the maximum nominal MOSFET voltage can be ignored.

The choice of the current ripple factor KRF for the output filter inductor L5 is normally an iterative process. On the one hand, one would like to make this factor as small as possible to reduce the RMS and peak values of the primary and secondary side currents. On the other hand, L5 shall not be too large. As a consequence, start with a certain ripple factor and then check whether the resulting configuration of L5 is acceptable. In the present design a value of 0.21 has been used for KRF, a value that results in an inductance of 40µH for L5. The calculated windings will fill an EER2828 core completely. With the mentioned choice of KRF the RMS and peak values of the current through Q205 and Q206 are:

AI

AI

SwRMS

SwPeak

9.0

6.1

,

,

==

(19)

As already mentioned a maximum drain voltage slightly bigger than 400V would be sufficient, effectively leading to the use of 500V rated MOSFET. Again, the use of 600V MOSFET is recommended instead of a surge voltage limiter at the input and the SUPERFETTM FCP7N60 having the following data

Aatnst

Aatnst

pFC

CatR

f

r

effOSS

DSON

775

7120

60

1001.1

max,

max,

,

max,

==

=°Ω=

(20)

was chosen. The loss calculation can be easily done similar to the one for Q1.

( )

WP

W

kHznsVA

ftt

VIP

W

kHzVpF

fVCCP

W

A

RIP

TotQLoss

Sfr

OutQPeakCross

QLoss

SOutexteffOSSCap

QLoss

SwDSONSwRMSCond

SwLoss

7.3

4.1

1007

6.1

2

751204006.1

2

2.1

1004001205.0

5.0

9.0

1.19.0

205,

205,205,

2

2,205,

2

,2

1,, max

≈

=

⋅⋅+⋅⋅=

+⋅⋅≈

=⋅⋅⋅=

⋅⋅+⋅≈

=Ω⋅=

⋅=

(21)

This gives an upper limit for the losses. In practice, the resonance of the magnetizing inductance and the node output capacitance will reduce the value of the voltage below 400V.

The loss of Q206 is of course identical. A heatsink with a maximum thermal resistance of 20ºC/W should be used for each MOSFET.

The value of the current sense resistor R233 is chosen such, that a maximum peak current of more than 1.6A is possible. With a value of 0.56Ω, this condition is fulfilled but there is no margin left. For that reason, a value of 0.47Ω has been chosen, which results in a maximum peak current of 2.1A.

As inductor L5, the transformer, secondary rectification and filtering can be calculated with the Excel sheet.

With the help of the formula for the AP of the transformer given in the worksheet, an EER2834 core has been chosen for the transformer, winding data can be found in the appendix.

The calculated reverse voltage of the rectifier diodes is 57V and it is recommended to use ones with a specified maximum voltage of at least 100V. To reduce both conduction and switching losses, it is favorable to use Schottky diodes. The RMS current load is given in the spreadsheet and can be used to determine suitable diodes; the actual selection is two FYP2010DN diodes.

The average current of the rectifier diodes D219 and D220 is given by:


A

A

DII OutrectAvg

7.4

55.05.8

)1( max,

=⋅=

−⋅=

(22)

and the losses are determined in a similar manner as has been done for BR1 and D1.

W

AVA

RIVIP ctSrectRMSctFrectAvgrectLoss

5.2

04.07.525.07.4 2

Re,2

,Re,,,

=Ω⋅+⋅=

⋅+⋅≈

(23)

Again, a heatsink of not more than 20ºC/W should be used for each diode.

Due to the fast switching of the Schottky diodes, parasitic oscillations are excited that must be damped by the RC networks R246/C250 and R247/C249. While

there are a lot of formulae in the literature how to determine the values of these networks, experience shows the calculated values are only a starting point for experimental optimization.

It is possible in principle to use the two diodes contained in one FYP2010, but in that case the loss per package is doubled and cooling is complicated. Another reason to use two diodes instead of one is, that the PCB is prepared for the assembly of a self driven synchronous rectifier (not shown) that needs two single diodes.


R26680

C252100nF

R32

Q212BC858C

Q211BC848B

12

CONN4

1

2

3

45

6

7

8SWc

SWe

Ct

GndFB

Vcc

Ipk

DRc

IC5MC34063AD

+ C18680uF

R221.5K

C19100pF

L6100uH

1

23

Q209FQP47P06

R2513K

R29

D223MBR745

R21680

R330.12R

+ C251470uF

12V/5A

12V

24V

0

Figure 4: Schematic of the Buck Converter 24V -> 12V

5 DC/DC Converter

The Buck converter shown in Figure 4 operates in continuous mode and is controlled by the simple but effective PWM controller MC34063 operating at 100 kHz. Due to the open collector output a driver consisting of Q211/212 is used to drive a p-channel MOSFET. Peak current through Q209, D223 and L6 is 6.3A. Losses can easily be determined as already shown. Just the result is given here:

, 209

, 223

3.1

2.4Loss Q

Loss D

P W

I W

=

= (24)

Both devices need heatsinks having a thermal resistance of less than 25ºC/W.

6 Standby power supply

The flyback type power supply (Figure 5) driven by the FSD210B generates not only the 5V output voltage but the supply for FAN4800 and FAN7382 as well. By means of OC2 the main power supply is completely switched off during standby and only this power supply still operates.

Principally there is nothing special about this power supply and it can be easily designed with the help of AN-4137 and the related spreadsheet or with the SMPS Design Tool [3].

The actual design is for an output voltage of 5V and a current of 0.3A, but with the mentioned tool it is not an issue to change the design to a different output voltage and a power up to about 6W. Due to the use of the FOD2711BTV an output voltage down to 3.3V is no problem as well.


D208SB380

C236220nF

OC3FOD2711BTV

R23575

+ C214.7uF

1

23

4

OC2H11A817A.W

D61N4148

R2291K

1

34

5

6

8

TR2Stdby Transformer

C2222nF

R3147

R2301.5K

D22518V

C237220nF

+ C232100uF

R2271K

C202.2nF

12

CONN6

D5UF4007

R3075k

R2283.3K

C2534.7nF

VC

C5

DR

AIN

7

VS

TR

8G

ND

1

GN

D2

GN

D3

VF

B4

IC6FSD210BM

12

CONN1

+ C233100uF

L422uH

Standby ON/OFF

5V


Vbus

0

Vcc

Figure 5: Schematic of Standby power supply


Figure 6: Layout and photo of finished board. Dimensions are 170mm x 156mm x 25mm (L x W x H)


7 PCB Layout and Mechanical Construction

In the literature [4] one will find layout rules for power electronics layout rules saying that the enclosed area of loops with high di/dt and the copper area of nodes with high dv/dt must be as small as possible. Both rules are intended to minimize EMI. Further, the source pin of Q1, the ground connection of R233, right hand side of R5 and ground pin of FAN4800 should be connected in form of a star in order to minimize the negative effect of common impedance coupling.

In practice there are the problems that the PCB will be larger for higher output powers and the power semiconductors have to be attached to big heatsinks. As a result, it is often not possible to make the loops as small as they should be, while combining the current density rules the copper area of traces and a real star would spoil the complete PCB. Therefore a PCB of a high power power supply sometimes is a compromise, especially in the case of a single sided PCB. The latter has been chosen for cost reasons.

If one takes a close look at the actual PCB, one will recognize that some of the less critical signals are not necessarily routed to the shortest path. This enables the large ground plane that emulates the star like connection. Moreover, using the minimum possible spacing between ground plane and hot signals (for reliability reasons this is about 2mm for the given voltage level), minimizes loops.

Again for cost reasons, a simple heatsink consisting of a sheet of aluminum with 2mm thickness, bent into the form of a ‘U’ has been used on primary and secondary side. Only Q1, which dissipates more power, needs an additional heatsink.

8 Test Results

A detailed test report is available for this board. Here three of the test results are shown.

8.1 Standby Power vs. Input Voltage

0.0

0.1

0.2

0.3

0.4

0.5

0.6

85 110 135 160 185 210 235 260


Sta

ndby

Pow

er [W

]

Figure 7: Standby Power versus input voltage

8.2 Full Load Efficiency vs. Input Voltage

75.0

77.0

79.0

81.0

83.0

85.0

87.0

89.0

85 110 135 160 185 210 235 260


Effi

cien

cy [%

]

Figure 8: Efficiency versus input voltage The efficiency is well above the projected 81%

above 110VRMS. At smaller voltages, figures could be improved with a lower resistance EMI filter and by removing NTC1.

8.3 Power Switch and Diode Waveforms

Figure 9: Q212 drain current and voltage.


The left hand side of Fig. 9 shows the drain current (lower trace) and voltage (upper trace) of Q212. From the current it is obvious the PSU works in CCM. The drain voltage is well clamped to the DC supply voltage when the MOSFET is turned off. After de-magnetization of the transformer the voltage starts to drop. The slope is determined by the resonance of the transformers magnetizing inductance and CDS of the MOSFETs. By chance the drain voltage is close to minimum when the MOSFET is switched on, but this may differ from board to board due to the high tolerance (+/- 30%) of the magnetizing inductance.

Figure 10: D219 current and voltage.

The diode waveforms in Fig. 10 clearly show the

parasitic oscillations when the diode turns off.

REFERENCES [1] Application Note AN-6032 “FAN4800 Combo Controller

Applications”, Fairchild Semiconductor 2006 [2] Application Note AN-4134 “Design Guidelines for Off-line

Forward Converters Using Fairchild Power Switch (FPS™)”, Fairchild Semiconductor 2003

[3] http://www.fairchildsemi.com/designcenter/acdc/SMPSDT16_Install.zip

[4] J. P. Harper & V. Niemela, “Practical Power Application Issues for Switch-Mode Power Supplies” Fairchild Semiconductor Power Seminar 2006, www.fairchildsemi.com

Dr. Michael Weirich

Is the head of the Global Power Resource Center Europe. After finishing his Ph.D. thesis in solid state physics at the University des Saarlandes, Germany he started as a designer for analog and power electronics at the Siems & Becker GMBH, Bonn. Before he joined Fairchild in 2003, he worked several years as engineering manager in the design of fluorescent lamp ballasts at the OSRAM GmbH, Munich.


APPENDIX

Figure A-1 Complete Schematic Diagram

LF1

10m

H

D20

8S

B3

80

L5 40u

H

R2

2622

C23

1

15n

F

R26

680

0.25

W

C23

622

0nF

D14

FD

LL41

48

D11

1N

4148

C23

100n

F

D1

5FD

LL41

48

R16

620

K

VC

C1

HIN

2

LIN

3

CO

M4

LO5

VS

6

HO

7

VB

8

IC4

FAN

7382

N

R2

390K

C1

522

nF

C2

5210

0nF

OC

3FO

D27

11B

TV

R32

0.12

R

+C

5 82uF

R14

18K

C10

10n

F

R18

10K

Q21

2B

C85

8C

R24

27k

R12

620K

R23

5

75

C9

100n

F

Q21

1B

C84

8B

C3

100

nF C13

470n

F

C8

2.2

nF

12

CO

NN

4

R20

820

K

NTC

12

R 1

2A

OC

1FO

D2

741B

TV

D21

6R

S1K

C23

84

70pF

1 2 3 45678

SWc

SWe

Ct

Gnd

FB

Vcc

Ipk

DRc

IC5

MC

3406

3AD

R2

0513

k

R3

510

00.

6W

R17

1M

+C

21 4.7

uF

C1

668

0pF

D2

19FY

P201

0D

N

C2

491n

F

D21

7U

F54

07

+C

18 680u

F

R2

451.

5K

R20

210

k

+C

246

680u

F

C12 470n

F

R24

733 2W

R2

21.

5K

-+

~ ~

BR

1G

BU

6K

C25

0

1nF

1 234

OC

2H

11A

817

A.W

D6

1N41

48

R23

4.7

K

C1

910

0pF

R24

6

33 2W

D10

1N

4148

816

L1 1.0m

H

R22

91K

Q20

5

FCP7

N60

12

CO

NN

5

1 3 4 5

68

TR

2S

tdb

y T

ran

sfor

mer

D13

FD

LL41

48

L6

100

uH

+C

245

680

uF

C1

680

nF

+C

244

680

uF

R1

390K

1

23

Q20

9FQ

P47P

06

C4

470

nFC

2222

nF

R31

47

L3 FER

RIT

E B

EAD

R23

0

1.5

K

D22

518

V0.

5W

+C

247

n.a

.

R2

513

K

C23

7

220n

F

Q1

FCP1

6N

60C

Q20

6

FCP7

N60

R29

0.1

2R

1 2

R23

30.

47

Q21

0n.

a.

D1

ISL9

R46

0P2

R11

620K

R23

422

0

+C

232

100

uF

D22

4n.

a.

R13

110K

D22

3M

BR

745

R22

71

K

R21

680

0.25

W

R24

1

n.a

.

C20 2.2n

F

12

CO

NN

6

C7

220p

F

D16FD

LL41

48

C24

81n

F

C23

510

0nF

12

R7

0R1

52W

C14

100

nF

D5

UF4

007

R2

40n.

a.

R3

390K

C23

922

0nF

R30

75k R

330.

12R

R22

83.

3K

R19

47K

TR1

Mai

n T

rans

form

er

+C

558

2uF

C25

34.

7nF

VCC5

DRAIN7

VSTR8

GND1

GND2

GND3

VFB4

IC6

FSD

210B

M

D21

8U

F540

7

R24

2n.

a.

1 2

CO

NN

1

R22

5

22 0.25

W

D22

0FY

P20

10D

N

D12

1N

4148

+C

251

470

uF

+C

56 82u

F

R15

22 0.6W

+C

233

100u

F

C23

0n

.a.

L4 22uH

3.2A

R20

4

180K

HB

_In

ISen

se

HB

_In

ISen

se

Vcc

Vcc

Vbu

s

Vbu

s

5V/0

.3A

Sta

ndb

y O

N/O

FF

24V

/6A

12V

/5A

C2

680

nF

Ieao

1

Iac

2

Isen

se3

Vrm

s4

Ss

5

Vdc

6

Ram

p17

Ram

p28

Ilim

9

GN

D10

Vo2

11

Vo1

12

Vcc

13

Ref

14

Vfb

15

Vea

o16

IC1

ML

4800

IS

12V

n.a. = not assembled

denotes SMD

250V

/J1 G

SF1

.100

1.31

?A

24V

5V


Table A-1: Bill of Materials Item Qty Reference Specification Manufacturer/Type

1 1 BR1 GBU6K Fairchild Semiconductor

2 1 CONN1 B2B-XH-A JST XH Series

3 3 CONN4,CONN5,CONN6 B2P-VH JST VH Series

4 1 C1 680nF \ 275V EPCOS B32922 Series

5 1 C2 220nF \ 400V EPCOS B32562 Series

6 1 C3 100nF \ 50V AVX MLC X7R

7 1 C4 470nF \ 16V AVX MLC X7R

8 3 C5,C55,C56 82uF \ 450V Rubycon USG Series

9 1 C7 220pF \ 25V AVX MLC X7R

10 1 C8 2.2nF \ 25V AVX MLC X7R

11 5 C9,C14,C23,C235,C252 100nF \ 25V AVX MLC X7R

12 1 C10 10nF \ 25V AVX MLC X7R

13 1 C12 470nF \ 50V KEMET CK06

14 1 C13 470nF \ 16V AVX MLC X7R

15 2 C15,C22 22nF \ 25V AVX MLC X7R

16 1 C16 680pF \ 25V AVX MLC X7R

17 1 C18 680uF \ 16V Nichicon PW Series

18 1 C19 100pF \ 50V AVX MLC X7R

19 1 C20 2.2nF \ 1000V Murata DE

20 1 C21 4.7uF \ 50V SAMWHA SD

21 1 C230 n.a. AVX MLC X7R

22 1 C231 15nF \ 25V AVX MLC X7R

23 1 C232 100uF \ 16V Nichicon PW Series

24 1 C233 100uF \ 16V SAMWHA SD

25 1 C236 220nF \ 630V Arcotronics R60 Series

26 2 C237,C239 220nF \ 16V AVX MLC X7R

27 1 C238 470pF \ 25V AVX MLC X7R

28 2 C242,C243 n.a. AVX MLC X7R

29 3 C244,C245,C246 680uF \ 35V Nichicon PW Series

30 1 C247 n.a. SAMWHA SD

31 1 C248 1nF \ 25V AVX MLC X7R

32 2 C249,C250 1nF \ 630V Arcotronics R76 Series

33 1 C251 470uF \ 35V Rubycon ZL Series

34 1 C253 4.7nF \ 250V Murata DE Series

35 1 D1 ISL9R460P2 Fairchild Semiconductor

36 1 D5 UF4007 Fairchild Semiconductor

37 4 D6,D10,D11,D12 1N4148 Fairchild Semiconductor

38 4 D13,D14,D15,D16 FDLL4148 Fairchild Semiconductor

39 1 D208 SB380 Fairchild Semiconductor

40 1 D216 RS1K Fairchild Semiconductor

41 2 D217,D218 UF5407 Fairchild Semiconductor

42 2 D219,D220 FYP2010DN Fairchild Semiconductor

43 2 D221,D222 n.a.

44 1 D223 MBR745 Fairchild Semiconductor

45 1 D224 n.a.

46 1 D225 18V \ 0.5W Fairchild Semiconductor

47 1 IC1 ML4800IS Fairchild Semiconductor

48 1 IC4 FAN7382N Fairchild Semiconductor

49 1 IC5 MC34063AD Fairchild Semiconductor

50 1 IC6 FSD210BM Fairchild Semiconductor


51 1 J1 GSF1.1001.31 Schurter

52 1 LF1 2 x 10mH EPCOS B82733 Series

53 1 L1 1.0mH See Specification

54 1 L3 FERRITE BEAD

55 1 L4 22uH Coilcraft RFB0810

56 1 L5 40uH See Specification

57 1 L6 100uH See Specification

58 1 NTC1 2R EPCOS

59 1 OC1 FOD2741BTV Fairchild Semiconductor

60 1 OC2 H11A817A.W Fairchild Semiconductor

61 1 OC3 FOD2711BTV Fairchild Semiconductor

62 1 Q1 FCP16N60 Fairchild Semiconductor

63 2 Q205,Q206 FCP7N60 Fairchild Semiconductor

64 3 Q207,Q208,Q210 n.a.

65 1 Q209 FQP47P06 Fairchild Semiconductor

66 1 Q211 BC848B Fairchild Semiconductor

67 1 Q212 BC858C Fairchild Semiconductor

68 2 R1,R2 390K \ 0.125W Any

69 1 R3 390K \ 0.6W Any

70 1 R7 0R15 \ 2W Any

71 2 R11,R12 620K \ 0.125W Any

72 1 R13 110K \ 0.125W Any

73 1 R14 18K \ 0.125W Any

74 1 R15 22 \ 0.6W Any

75 1 R16 620K \ 0.6W Any

76 1 R17 1M \ 0.6W Any

77 2 R18,R202 10k \ 0.125W Any

78 1 R19 47K \ 0.125W Any

79 1 R20 820K \ 0.125W Any

80 2 R21,R26 680 \ 0.25W Any

81 3 R22,R230,R245 1.5K \ 0.125W Any

82 1 R23 4.7K \ 0.125W Any

83 1 R24 27k \ 0.125W Any

84 2 R25,R205 13k \ 0.125W Any

85 3 R29,R32,R33 0.12R \ 1W Any

86 1 R30 75k \ 0.6W Any

87 1 R31 47 \ 0.125W Any

88 1 R35 100 \ 0.6W Any

89 1 R204 180K \ 0.125W Any

90 2 R225,R226 22 \ 0.25W Any

91 2 R227,R229 1K \ 0.125W Any

92 1 R228 3.3K \ 0.125W Any

93 1 R233 0.47 \ 2W Any

94 1 R234 220 \ 0.125W Any

95 1 R235 75 \ 0.125W Any

96 6

R236,R237,R238,R239, R240, n.a. \ 0.125W Any

97 1 R242 n.a. \ 0.6W Any

98 2 R246,R247 33 \ 2W Any

99 1 TR1 Main

Transformer See Specification

100 1 TR2 Stdby

Transformer See Specification


Table A-2: Specifications for wound components

Standby Transformer Specification

Winding Details

Name Pins (Start

→End) # of

Layers Strands x

Wire ø Turns Construction Material

W1a 3 →2 2 1 x 0.15 mm 91 spaced

winding CuLL

W3 8 →6 1 1 x 0.5 mm 8 spaced

winding Triple

insulated

W1b 2 →1 2 1 x 0.15 mm 91 spaced

winding CuLL

W2 4 →5 1 1 x 0.15 mm 24 spaced

winding CuLL

W2

5

4

3

1

8

W3

2

W1b

W1a

6

= 3 Layers of Tapee.g. 3 M 1350

= 1 Layer Tapee.g. 3 M 1350

Layers not to scale !

W1a

W3

W1b

W2

3 2

1

4 5

8

2

6

Schematic Construction

Electrical Characteristics

Parameter Pins Specification Conditions

Primary Inductance 1 →

3 5.85 mH +/- 5% 10kHz, 100mV, all secondaries open

Leakage inductance 1 →

3 290 uH maximum 10kHz, 100mV, all secondaries short

Core and Bobbin

Core: EF 20 Material: FI325 (Vogt) or equivalent Bobbin: EF20 / 10 Pin / Horizontal / Increased creepage Gap in center leg: approx. 0.2 mm for AL of 177 nH/Turns2

Safety

High voltage test: 3000Vrms for 1 minute between primary (pins 1 to 5 ) and secondary (pins 6 to 8)


Main Transformer Specification

Winding Details

Name Pins (Start

→End) Layers

Strands x Wire ø

Turns Construction Material

W1a 6 →3 1 1 x 0.5 mm 39 perfect

solenoid CuLL

W3 10,11,12 →7

,8,9 2 3 x 0.7 mm 11

perfect solenoid

Triple insulated

W1b 3 →1 1 1 x 0.5 mm 38 perfect

solenoid CuLL

6

1

Layers not to scale !

3W1a

W2

W1b

6 3

1

= 3 Layers of Tapee.g. 3M 1350

W1b

W1a

3

10,11,12 7,8,9

101112

789

Schematic Construction



Primary Inductance 1 →

6 13 mH +/- 30% 10kHz, 100mV, all secondaries open

Leakage Inductance 1 →

3 500 uH maximum 10kHz, 100mV, all secondaries short

Core and Bobbin

Core: EER2834 Material: PC40 (TDK) or equivalent Bobbin: EER2834 / 12 Pin / Horizontal e.g. Pin Shine P-2809 Gap in center leg: 0 mm

Safety

High voltage test: 3000Vrms for 1 minute between primary (pins 1 to 6 ) and secondary (pins 7 to 12)


PFC Choke

Winding Details

Name Pins (Start

→End) Layers

Strands x Wire ø


W1 8 →16 6 3 x 0.5 mm 124 perfect

solenoid CuLL



Inductance 8 →

16 1000 uH +/- 5% 10kHz, 100mV

Core and Bobbin

Core: EER3542 Material: PC40 (TDK) or equivalent Bobbin: EER3542 / 16 Pin / Horizontal e.g. Pin Shine P-3508 Gap in center leg: approx. 2.0 mm for an AL of 65 nH/Turns2

Choke 40uH / 9A (L5)

Winding Details

Name Pins (Start

→End) Layers

Strands x Wire ø


W1 1,2,3,4,5

→8,9,10,11,12 6

5 x 0.71 mm

15 perfect

solenoid CuL



Inductance 1 →

5 40 uH +/- 5% 10kHz, 100mV

Core and Bobbin

Core: EER2828 Material: PC40 (TDK) or equivalent Bobbin: EER2828 / 12 Pin / Horizontal e.g. Pin Shine P-2816 Gap in center leg: approx. 0.4 mm for an AL of 230 nH/Turns2


Choke 100uH / 6A (L6)

Winding Details

Name Pins (Start

→End) Layers

Strands x Wire ø


W1 1,2,3,4,5

→8,9,10,11,12 5 x 0.56mm 25

perfect solenoid

CuL



Inductance 1 →

5 100 uH +/- 5% 10kHz, 100mV

Core and Bobbin

Core: EER2828 Material: PC40 (TDK) or equivalent Bobbin: EER2828 / 12 Pin / Horizontal e.g. Pin Shine P-2816 Gap in center leg: approx. 0.45 mm for an AL of 205nH/Turns2


Tips and Tricks to Get More Out of Your SPICE Models Scott Pearson, Alain Laprade

Abstract — Circuit simulation tools are useful supplements

to breadboarding for gaining fast and detailed design insight. A collection of simulation tips and tricks used by our applications support group is presented. Fairchild Semiconductor offers interactive on-line design simulation tools and device models for off-line simulations.

I. INTRODUCTION

The various simulation tips presented demonstrate methods to accomplish simulations not possible using only native models included with the ORCAD® simulator. Examples are a resistor with dynamic temperature feedback, voltage controlled reactive models (capacitors and inductors) and analog behavioral models for complex waveforms. Also included in this paper is a discussion of the thermal model and its importance to the designer. Use of the thermal model will give an indication of the junction temperature ensuring device specification are not exceeded. Detailed instructions on how to use the models provided by Fairchild Semiconductor will be provided. Models and instructions given here are applicable for ORCAD® simulation products, but assistance with other simulation tools is available. Another option offered to designers is on-line simulation tools such as FETBench®, which will be introduced here.

Finally, circuit simulation convergence can be a frustrating issue. Tips are described which can minimize such issues. Fixes which improve convergence can also result in reduced simulation times.

II. A PSPICE RESISTOR MODEL HAVING

DYNAMIC TEMPERATURE CAPABILITY

Use of dynamic temperature information within a closed loop system simulation can run into algorithm limitations with some simulation software such as PSPICE. The SPICE resistor model may be set to have temperature dependence as in the listing from Table I. PSPICE will only run simulations at a single temperature defined in the simulation setup menu, and this temperature setting cannot be varied

dynamically during the simulation. A temperature sweep will perform independent static simulations at various temperatures.

TABLE I RESISTOR TEMPERATURE COEFFICIENT SPICE LISTING Rvtemp 18 19 RvtempMOD 1 MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6)

The ability to describe the value of a resistor and

its temperature coefficients as an analog behavioral model (ABM) referenced to a voltage node (making use of electrical thermal analogy) is necessary to express dependence on operating temperature. Voltage node references within PSPICE resistor models are not permitted. Dynamic temperature dependence of resistive elements (expressed as separate lumped elements) cannot be implemented without a resistor ABM.

This limitation is overcome with a voltage-controlled current source ABM expression (Fig. 1). By using the nodes of the current source for voltage control, resistor behaviour may be expressed as a current source as in (1). Resistance R(Td) is replaced with a behavioral mode analytical expression that is a function of the electrical analogy voltage node Td as shown in the next section. The form for the ABM netlist expression is described in Table II.

)T(RV

Id

= (1)

I=V/R(Td)

+

-

I

+

-

Fig. 1 Implementing a voltage dependent ABM resistor model. TABLE II Voltage Dependent ABM resistor model netlist. G_Resistor Node1 Node2 Value=V(node1,Node2)/ +function(V(Td))


III. THERMAL MODELING

Semiconductor devices often operate at high junction temperatures. Understanding their thermal limitations is important to achieve good device reliability and system performance targets. Circuit designers are responsible for performing junction temperature calculations to verify that their devices operate within manufacturer specifications.

Measurement of semiconductor thermal response involves a calibrated power pulse. Power dissipated within a device causes a junction temperature rise because of the thermal impedance from the die and package. (2) describes thermal impedance as the result of a change in junction temperature divided by power dissipation.

D

JJ

D

JJC P

)0(T)t(TP

)t(T)t(Z

−=∆=θ (2)

A basic semiconductor thermal model and its

electrical analogue is shown in Fig.2. Heat is generated at the device junction and flows through the silicon to the case, and finally to the heat sink.

PowerDissipation

G_Pdiss

ZθJC ZθSAZθCS

Die

Transistor

Tcase

Heat sink

Tambient

Insulator &interface

Tjunction Tsink

PowerDissipation

G_Pdiss

ZθJC ZθSAZθCS

Die

Transistor

Tcase

Heat sink

Tambient

Insulator &interface

Tjunction Tsink

Fig. 2 Semiconductor thermal impedance model.

Junction temperature information is determined

by the inclusion of the device’s thermal network ZθJC and current source G_PDISS. The thermal network parameters are supplied in Fairchild Semiconductor data sheets. G_PDISS is the semiconductor’s instantaneous operating loss, and expresses the result in the form of a current. This is

a circuit form representation of the junction temperature as expressed in (3).

)ZZZ(Pdiss_GTT SACSJCambientJ θθθ ++•+= (3)

where

TJ = junction temperature G_Pdiss = instantaneous power loss ZθJC = thermal impedance junction-to-case ZθCS = thermal impedance case-to-heat sink ZθSA = thermal impedance heat sink-to-ambient.

The unit conversion for the electrical analogy of the thermal system is listed in Table III. ZθJC is provided in manufacturer data sheets using the single pulse normalized thermal impedance curve as in Fig. 3. ZθJC may be represented using an equivalent electrical analogy model as in Fig. 4. TABLE III ELECTRICAL/THERMAL ANALOGY

Electrical ⇔ Thermal Ohm (resistance) oC/Watt (thermal resistance) Farad (capacitance) Joules/oC (thermal capacitance) Amp (current) Watt (power) Volt (voltage) oC (temperature)

Fig. 3 Normalized maximum transient thermal impedance.

Fig. 4 Semiconductor thermal impedance model. When model parameters are unavailable, they may be derived from the datasheet RθJC and from the single pulse normalized thermal transient impedance curve data points. The electrical analog model may be expressed as in (4). The R-C parameters may be obtained by using curve fitting software such as TableCurve 2D® [15].

)e1(R)e1(R)t(Z 6611 CR

t

6CR

t

1⋅

−⋅

−

−⋅++−⋅= Κ (4)


Knowing operating waveforms and system level

thermal impedance information, thermal response to complex waveforms may be analyzed. An example circuit and simulation result for a MOSFET operated under continuous conduction is shown in Fig. 5, where a 60A/40ms current pulse is applied to an FDB8445 MOSFET [12] having a case temperature of 120oC. The simulation is in closed loop form. The temperature dependent RDS(on) and junction temperature responses are shown in Fig. 6.

Fig. 5 Electrical analogy of system losses.

0

10

20

30

40

50

60

70

0 5 10 15 20 25 30 35 40 45 50

Time (ms)

Cu

rren

t (A

)

100

120

140

160

180

200

220

240

Tem

per

atu

re (o

C)

I(I4) (A) V(Tjunction) (C)

0

5

10

15

20

25

0 5 10 15 20 25 30 35 40 45 50

Time (ms)

Res

ista

nce

(mO

hm

s)

V(Vds)/ I(V4) (mOhms)

Fig. 6 Simulation results.

The FDB8445 MOSFET thermal impedance

model is provided by an RC ladder network (R1-R6, C1-C6). The MOSFET RDS(on) is modeled with a voltage dependent current source ABM model G6.

Instantaneous power dissipation information is evaluated with ABM current source G8 by multiplying the drain-source voltage with current I(V4) flowing through the MOSFET resistance. (Zero-volt source V4 is included to measure current.) Case temperature is set with voltage source Vcase. A more detailed system level thermal impedance network could be implemented in place of Vcase. Instantaneous junction temperature information Tjunction is the result from the closed loop simulation.

IV. SIMPLE VOLTAGE CONTROLLED REACTIVE

MODELS

In this section, simple non-linear inductor and capacitor SPICE model implementations are described. These models are most suited when device non-linear performance characteristics are known, but their non-linear physical characteristics are difficult to derive. PSPICE includes in its ANL_MISC.LIB library a 5-terminal non-linear inductor model ZX (Fig. 7) and a non-linear capacitor model YX. The ZX and YX node definitions are listed in Tables IV and V. Functional blocks from these library models were recreated in Figs 8 and 10 using available PSPICE symbols to facilitate the numerical derivation of the library functions. Node numbers 1 through 5 are marked to facilitate functional reference with the existing PSPICE ZX and YX library files. Node 5 would normally be connected to a load. With a device specific behavioral voltage source model, the ZX and YX models can be made to operate non-linearly with the use of voltage dependent input nodes 1 and 2 which multiply the voltage from node 3.

Fig. 7 PSPICE ANL_MISC.LIB ZX Symbol

A. Non-Linear Inductance Model.

Power supply filter inductors and solenoid coil inductance are examples of devices having non-linear properties.


The equivalent schematic representation of the non-linear inductance model ZX is shown in Fig. 8. Model response to a sudden change of inductance value is shown in Fig. 9. The simulation consists of an AC voltage source connected in parallel to a non-linear 1µH inductor having a series resistance of 0.01Ω. Rin is used to aid with convergence.

Fig. 8 Voltage-controlled inductance model.

TABLE IV ZX MODEL NODE DEFINITION

1: control input voltage (+) 2: control input voltage (-) 3: reference inductor/resistor (connect other lead to ground) 4: output (floating impedance) 5: output (floating impedance)

Fig. 9 Voltage-controlled inductor model response.

When an inductor is energized, current cannot change instantaneously. By Faraday’s law:

td

idLrefV Lref

3 ⋅= (5)

By substitution (Fig. 8),

3control4 VVV ⋅= (6)

td

id)LrefV(V Lref

control4 ⋅⋅= (7)

RinductorLref ii = (8)

td

id)LrefV(V Rinductor

control4 ⋅⋅= (9)

The simulated inductor voltage drop VL corresponds to the total voltage drop between nodes 4a and 5 (to include winding resistance Rinductor).

RinductorRinductor

controlL iRinductortd

id)LrefV(V ⋅+⋅⋅= (10)

where VL = voltage across the non-linear inductor iRinductor = non-linear inductor current 0 < Vcontrol < 1.

B. Non-Linear Capacitor Model

Capacitor models that can be expressed using a non-linear model include certain ceramic capacitor types and MOSFET capacitance which have non-linear voltage dependent properties. The equivalent schematic representation of the non-linear capacitor model YX is shown in Fig. 10. Model response to a sudden change of capacitance value is shown in Fig. 11. The simulation consists of an AC voltage source connected in parallel to a non-linear 1µF capacitor. Rin is used to aid with convergence.

Fig. 10 Voltage-controlled capacitor model YX.

-2.0-1.5-1.0-0.50.00.51.01.52.0

140 145 150 155 160 165

Time (µs)

Vo

ltag

e o

r C

urr

ent

I(Rinductor) (A) V(4a) (V)

0.00

0.25

0.50

0.75

1.00

1.25

140 145 150 155 160 165

Time (µs)

Indu

ctan

ce (

µH)

V(4a)/d(I(Rinductor)) (uH)

L = 0.25µH

L = 1µH

Vcontrol = 0.25VVcontrol = 1.0V


TABLE V YX MODEL NODE DEFINITION

1: control input voltage (+) 2: control input voltage (-) 3: reference capacitor (connect other lead to ground) 4: output (floating impedance) 5: output (floating impedance)

Fig. 11 Voltage-controlled capacitor model response. Capacitor voltage may be expressed as

∫ ⋅⋅= tdiCref

1V CrefCref (11)

FCOPYCREF ii =

∫ ⋅⋅= tdiCref

1V FCOPYCref (12)

4Cref VVcontrolV ⋅= (13)

∫ ⋅⋅⋅

= tdiCrefVcontrol

1V FCOPY4 (14)

where V4 = non-linear capacitor voltage iFCOPY = non-linear capacitor current 0 < Vcontrol < 1

V. USING BEHAVIORAL MODELING FOR

COMPLEX WAVEFORM CIRCUITS

Evaluating device performance with non-repetitive waveform topologies can be a daunting task. In situations in which IGBT and diode losses require accurate modeling, meaningful results may be a difficult to obtain. Device models, if existent, may have limited accuracy. Simulations required to

achieve steady state information may also require significant run-time. Through the use of characterization data selected under relevant operating conditions, device behavioral models may be prepared. These models may then be used as building blocks for complex topologies.

A. Complex Waveform Circuit

Application of modern high speed IGBTs in SMPS circuits can provide cost and conduction loss advantages. In PFC circuits (Fig. 12), each switching operation occurs at a different current and duty cycle. IGBT losses (Fig. 13) are a non-linear function of the collector current, collector voltage and junction temperature. The loss plane represents IGBT turn-off losses at a single clamp voltage (400 VDC).

Current Sense Resistor

D1 D2

D3 D4

VacInput

VacABS Vout

C1IGBT

Boost DiodeBoost Inductor

PFC ControlCircuit

IL1

390Vdc

90 Vrms50Hz

Fig. 12 Boost PFC circuit block diagram.

Eoff (µ joules)

Tj (oC)

Icollector (amps)

Fig. 13 Three-dimensional Eoff plot.

A behavioral modeling technique for determining losses and junction temperature of an IGBT operating in a switched mode power circuit is described. Full PFC circuit implementation in

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0 5 10 15 20 25

Time (µs)

Vo

ltag

e o

r C

urr

ent

I(V2) V(4)

0

200

400

600

800

1000

1200

0 5 10 15 20 25

Time (µs)

Cap

acit

ance

(n

F)

(1/V(4))*S(I(Fcopy))

C = 0.25µH

C = 1µFVcontrol = 0.25V

Vcontrol = 1.0V


closed loop form using behavioral modeling for switching information, loss calculations and control are described in detail in [2, 4]. The transistor transient thermal impedance model is used within this feedback loop.

B. Behavioral Model Equations

Techniques expressing empirical IGBT test data into loss equations are described in [1]. The on-state voltage (VCE(sat)), turn-off loss (Eoff) and turn-on loss (Eon) expressions are described in equations (15)–(17) for typical performance of the HGTG12N60A4D IGBT [3].

( )( )( )( )

+⋅+⋅

+⋅+⋅+⋅

+⋅⋅+⋅+⋅

=

a9Tja82Tja7

a11Ia6Tja52Tja4

Ia10ea3Tja22Tja1

I,TjVsat (15)

( )

( )( )( )

⋅+⋅

+⋅⋅+

+⋅⋅⋅+

⋅⋅+⋅

=

TjbIb

ITjbb

IbeTjbb

IbbclampV

,I,TjclampVEoff

726

54

321

98400

(16)

( ) ( )( )

⋅+⋅⋅++⋅+⋅+⋅⋅+⋅

=⋅

Tj8cITj7c6cI5cTj4ce3c2cV1c

TjIVEon2Tj10c

9c

),,(

(17)

Turn-off expression (16) and coefficients b1 through b7 correspond to IGBT performance in a clamped inductive turn-off switching circuit. Expression (17) describes the hard-switched Eon2 turn-on losses with the IGBT which includes losses from an external diode (equivalent to that in the co-packaged version of the IGBT) reverse recovery current. The junction temperature of this external diode is assumed to correspond to that of the co-packaged HGT12N60A4D IGBT (a semiconductor characterization practice). The loss coefficients were developed using a 15V IGBT gate drive waveform. These equations may be used to represent other IGBT types by developing a new set of coefficients [1]. The outputs of (16) and (17) are the IGBT turn-off and turn-on losses in joules per switching-cycle. Coefficient values are provided in [3].

C. IGBT Behavioral Model Input Voltages and Currents

To demonstrate the SPICE implementation of (15)-(17), an HGTP12N60A4D IGBT behavioral model was developed [2] using the Intusoft SPICE simulator “B” function as shown in Fig. 14. A basic sub-circuit avgIGBT was developed to provide an effective means of adding additional IGBT model types. The sub-circuit was designed to receive six inputs and provide three outputs, all referenced to Tcase. Two bi-directional terminals, Tj and Zjc, provide a circuit interface to the IGBT's thermal impedance model. A schematic symbol avgIGBT was generated to provide a simple method of implementing this component in a SPICE schematic. Model and symbol input are defined as: Iton = Load current at IGBT turn-on Ion = Average IGBT collector current during conduction Itoff = Collector current at IGBT turn-off Tj = IGBT and clamp diode junction temperature Vton = IGBT collector voltage at turn-on Vtoff = IGBT collector clamp voltage at turn-off

Output Eon represents the Eon2 turn-on energy loss (J) for the Iton, Vton and Tj input values. Output Eoff represents the turn-off energy loss (J) for the Itoff, Vtoff and Tj input values. Output Vsat is the saturated on-state voltage for the Ion and Tj inputs. The IGBT’s junction to case thermal impedance is represented as a multi-stage RC ladder network internally connected between Zjc and Tcase. Whereas the Tj schematic-symbol terminal is provided for open-loop simulation, the Zjc terminal is used for closed-loop simulation by connecting it to Tj and supplying this node with a current equal to total IGBT losses (W). Because the thermal impedance network is internally connected between Zjc and Tcase, the voltage at terminal Zjc is equal to the IGBT junction temperature (1V = 1oC) as long as Tcase is set to a voltage equal to the case temperature.


6 Eoff

2

1

Icollector

Tjunction 5 Vsat

4

7 Eon

Ion

Iton

Itof f

Vton

Tj

Eon

Eof f

Vsat

Vtof f Tcase

Zjc

X2HGTP12N60A4

V3 V5390

V6

Turn-Off Loss (joules)

Turn-On Loss (joules)

Vsat (volts)

Icollector (amps)

Tjunction (degrees C)

V(1)

Tran

21.0

-1.003.000 tim e

V(2)

Tran

127

72.53.000 time

V(5)

Tran

2.03

621M3.000 time

V(6)

Tran

434U

-18.7U3.000 time

V(7)

Tran

635U

-20.5U3.000 time

Fig. 14 Basic IGBT behavioral model avgIGBT.

45

23

42A

B

A/B

1

9

PACKAGE

5

4

28

15

17

24

22

SwitchingFreq

Pk toPkRippleI

SwitchingFreq

VacInput

Ccase_sink5.75E-1

Rsink_amb1.15

Rcase_sink.55

X25

G11

Csink_amb1

ON_STATE_LOSS

Tjunc tion

Eon_Joules

Duty_Cycle

VAC_IN

Eoff_Joules

VCE_ON

TURN_OFF_LOSS

DutyCycle

DutyCycle

VinABS

21

Vout390

Vout

Vout

V_Initial_Temp110V

SUM2

K1

K2

18

36

X8K1 = 1K2 = 0.5

SUM2

K1

K2

X15K1 = -0.5K2 = 1

PktoPkRippleI

PktoPkRippleI

EonWatts

Turn_On_Loss

Iton

Itoff

Ion

26

X9SWITCH

V6

DutyCycle

T_Sink

Ion

Iton

Itoff

Vton

Tj

Eon

Eoff

Vsat

Vtoff Tcase

Zjc

X2HGTP12N60A4

AC Input Voltage

AC Input Current1 Volt per Amp

ABS6

X3ABS

ABS

X17ABS

A

B

A/B

X12DIVIDE

SUM2

K1

K2

X11K1 = 1K2 = -1

VacABS

IGBT Duty Cycle

Switching Frequency1 Volt/Hz

Av erage On-State Current1V/amp

Vpout500V

Power Out1V=1W

Pout

Vrms90

VinRMS

Vrms Input1V=1V

V9

1.4142 Vpeak50Hz

A

B

K*A*B

X10MULK = 1Vref

A

B

A/B30

X13DIVIDE A

B

K*A*B

X18MULK = 1

A

B

K*A*B

X19K = 1

A

B

K*A*B

X20K = 1

Value of Boost Inductor1V=1Henry

Vamb50Vdc

T_Case

Ambient Temp1V=1 degree C

Peak-to-PeakBoost InductorRipple Current

Ripple_Current

Tj

Junction Temperature

VacABS

DC Output Voltage

VL1500uV

Vfreq100kV

A

B

K*A*B

X5K = 1

A

B

K*A*B

X6K = 1

EoffWatts

A

B

C

K*A*B*C

X1K = 1

OnStateWatts

SUM3

K1

K2

K3

X7K1 = 1K2 = 1K3 = 1

Total IGBT Losses

DUTY CYCLE

Tran

1.02

657M500M480M time

V(18)

Tran

8.25

-393M500M480M time

RIPPLE_CURRENT

Tran

1.80

-85.7M500M480M time

V (5)

Tran

39.1

-264M500M480M time

TJ

Tran

113

104500M480M time

VA CABS

Tran

134

-6.36500M480M time

Fig. 15 PFC behavioral model implementation.


D. Behavioral Model Implementation

In Fig. 14, a 0 to 20V 1Hz ramp is applied to the model Iton, Ion and Itoff terminals representing a 0 to 20A 1Hz collector current. The junction temperature is stepped from 75 to 150oC 1.5 seconds into the simulation while the turn-on (Vton) and turn-off (Vtoff) voltages are maintained at 390V. Analysis of the wave shapes on the right side of the schematic reveal the impact the current and temperature changes have on the model outputs. Fig. 15 illustrates a closed loop form implementation of the behavioral model within a power factor controller circuit. Functional description is provided in [2]

VI. DIODE REVERSE RECOVERY CURRENT

WAVEFORMS: ACCURACY LIMITATIONS

Diode reverse recovery current (IRM) is an included function with each of Fairchild’s MOSFET PSPICE models. It is modeled with a diode in PSPICE. The simulated reverse recovery for the FDB8441 40V 2.5mΩ MOSFET [14] at 25oC for a slew rate of 100A/µs is shown in Fig. 16. Measured results are shown in Fig. 17. Simulated reverse recovery time trr is 50.5ns (di/dt = 100A/µs, 25oC) while the data sheet typical is 52ns thus showing good agreement. While it is accurate under data sheet conditions it may not track over a wide range of operating conditions.

Time

1.95us 2.00us 2.05us 2.10us 2.15us 2.20us 2.25us 2.30usI(X1:s)

-5A

0A

5A

10A

15A

20A

25A

Fig. 16 Simulated FDB8441 diode reverse recovery waveform at 25oC, 100A/µs.

Fig. 17 Measured FDB8441 diode reverse recovery waveform at 25oC, 100A/µs. The vertical scale is 5A per division.

A limitation of this diode model is that there is little trr variation as a function of operating conditions, and simulations at various forward conduction currents show little change in the reverse recovery waveform. For many real devices, however, trr becomes significantly longer at higher forward current, higher di/dt, and higher temperature. Results are summarized in tables VI and VII.

TABLE VI DIODE REVERSE RECOVERY AT VARIOUS TEMPERATURES

ISD=20A, di/dt=100A/µs

Temp (°C) Trr (ns) Irm (A) 25 simulated 50.50 -3.40 25 measured 56 -2.4 125 simulated 49.44 -3.27 125 measured 58 -2.8

TABLE VII SIMULATED DIODE REVERSE RECOVERY AT VARIOUS CURRENTS

Temp=25°C, di/dt=100A/µs

ISD (A) Trr (ns) Qrr (nC) Irm (A) 15 50.39 81.70 -3.45 35 49.70 81.14 -3.54 50 49.35 80.57 -3.53 75 49.51 80.73 -3.52

While these intrinsic body diode models provide

good results, it is important to be aware of their limitations. In practice, the reverse recovery is modeled under data sheet conditions.

These limitations are due to the diode models as implemented in SPICE. The SPICE primitive diode


model is limited in its ability to represent minority charge concentration under operating conditions. Therefore, all SPICE MOSFET intrinsic body diodes and diode models will have these limitations regardless of device manufacturer. Other simulators (e.g. Saber) may overcome these problems but that has not been explored at this time.

VII. CONVERGENCE ISSUES

There are many issues that can lead to simulation convergence problems. Complexity of the circuit being simulated can be a leading cause. As the circuit becomes more complex there are more node voltages and device currents that need to be calculated. Not only can convergence be a problem, but long run times can be a problem with highly complex circuits. One solution here is to simplify the circuit whenever possible. Can the circuit be implemented with a simplified model instead of a detailed complex model? For instance, if one is only concerned with on-state circuit losses, a MOSFET model could be replaced with an ABM resistor model (previously described). The ABM resistor would be modeled to describe the RDS(on) vs. temperature characteristics of the MOSFET. This ABM model could then replace the complex MOSFET model.

Careful placement of large value resistors around parasitic elements can help overcome convergence issues. In circuits where layout parasitic elements must be simulated, placing a 1MΩ in parallel with parasitic capacitors or inductors is recommended. OrCAD® recommends that all inductors have a parallel resistor [5]. Doing so models eddy current losses and bandwidth limitations of inductors at high frequencies. (18) describes the recommended parallel resistance value for a given inductance, where fq is the roll-off frequency resulting from the inductor’s interwinding capacitance.

L*f*2R qπ= (18)

Simulation time and convergence may also be

improved by defining circuit initial conditions. Both capacitors and inductors have initial condition parameters that may be defined. By setting these conditions to the expected operating values, convergence can be greatly improved. Setting

proper initial conditions can also reduce the number of cycles necessary to reach a steady state solution. In some circumstances, a significant reduction in simulation time to reach steady state may be achieved.

Adjusting simulation tolerance settings can also help. These can be set in the simulation profile under the options tab shown in Fig. 18. DC convergence problems can be reduced by selecting the GMIN stepping option.

Fig. 18 PSPICE simulation profile.

Other frequently adjusted options are ABSTOL

and VNTOL. ABSTOL is the accuracy of currents. In most circuits using power devices, accuracy down to the default value 1pA is not required. This can be set to 1µA to improve convergence and simulation time with no noticeable degradation of the simulation output. VNTOL is the accuracy of voltages. The default value of 1µV is generally a good setting. VNTOL can also be relaxed to improve convergence.

Accuracy of charges is defined with CHGTOL. Its default value of 0.01pC can be relaxed to 1.0pC and give good simulation results.

Increasing the various iteration limits ITL1, ITL2 and ITL4 can also be helpful. Each of these can be set to 150 for improved results with complex circuits.

Perhaps the biggest improvement in simulation and convergence can be realized by using Fairchild’s new Bsim3 MOSFET models [13]. The Bsim3 uses a greatly reduced sub circuit macro model to represent the MOSFET. The previous


generation Fairchild Semiconductor SPICE level 1 model has a component count of 36 compared to 14 used in the Bsim3. When running a simplified DC-DC converter, simulation time was reduced by 52%.

VIII. MOSFET SYMBOL USAGE

Fairchild Semiconductor provides MOSFET symbols for use in OrCAD® schematic capture tools. A link to the symbol files can be found in [6]. The symbols files provided are for either OrCAD® Capture or OrCAD® Schematic. The file should be saved in the directory where model library files are located.

From an open schematic, select the icon or menu item to place a new part. The Place Part window is shown in Fig. 19.

Fig. 19 Place Part menu. In this window select Add Library. Browse to

and open the symbol file that was downloaded, and saved to the working directory. From this new library, select the symbol Fairchild MOS Std and place into schematic. Once the MOSFET symbol has been placed the model name will need to be changed. Double click Fairchild MOSFET on symbol just placed and enter the model name to be simulated.

The final step is to add the library to the simulation profile. Within Capture open a

simulation profile and select Configuration Files tab and category Library as shown in Fig. 20.

Fig. 20 Simulation settings menu.

Select the Browse button to locate the library file containing the model to be simulated. Next select the Add to Design button to make the model ready for simulation.

If a different model is to be used at a later point in time, not all of these steps are required. From the schematic, simply change the name of the MOSFET model. Then add the library file to the simulation profile if this has not been previously added.

Alternatively, a library can be added globally to Capture. When adding the library file to the simulation profile shown in Fig. 20 select the Add as Global button. This library file will then be available for all designs in Capture.

IX. FAIRCHILD SEMICONDUCTOR ON-LINE TOOLS

FETBench® is a Fairchild Semiconductor SPICE based design aide that helps designers shorten design times and reduce time to market. This design tool incorporates a wide range of Fairchild low-voltage MOSFETs targeting computing and ultra-portable applications. FETBench® can save, recall and share design simulations. MOSFET models are based on Berkeley SPICE BSIM3 version 3.1 device models, offering broad simulator compatibility. This tool (Fig. 21) may be found on-line [7].

Design activity may be saved for future use. Key FETBench features include:


- MOSFET device selection - Application analysis - Thermal simulation

Fig. 21 Web site FETBench menus

A. Device Analysis Module

This module offers a search capability based on either prior knowledge of an existing device of interest, or on required parametric characteristics. (While this search is limited to MOSFETs suitable for computing and ultra-portable applications, all Fairchild MOSFETs may be searched by selecting “MOSFETs” on the Fairchild home page.) Once a device has been selected, a device analysis menu can perform a number of types of analysis. This module offers:

- Curve Tracer Analysis

i. ID vs VDS (vary VGS, TJ)

ii. RDS(on) vs ID (vary VGS, TJ)

iii. Gate charge vs VGS (vary VDS)

iv. RDS(on) vs VGS (vary ID, TJ)

v. Reverse conduction characteristics ID vs VDS (vary VGS)

- Dynamic Characteristics

i. Switching characteristics

ii. Reverse recovery characteristics

B. Application Analysis Module

Applications analysis along with device selection is made within this module. Key features include:

- Circuit selection

i. Synchronous rectifier buck

ii. Synchronous rectifier buck with FAN5236 controller

iii. Boost converter

iv. Load switch

v. Bi-directional load switch

- Input and output requirement definitions.

- Device selections (device combinations may are permissible)

- In-circuit device analysis

C. Thermal Analysis Module

Once inputs to the Application Analysis Module have been completed and the average power dissipation in each device of interest has been determined, a thermal analysis may be performed with the use of the Thermal Analysis module (Fig. 22). Key features include:

Fig. 22 Example FETBench thermal analysis menus

- Definition of the thermal environment

- Definition of the multilayer PCB design

- Definition of airflow


- Placement of power dissipating components.

X. SUMMARY

Electrical and thermal simulation models as well as behavioral models are useful tools in the hands of the design engineer to gain further design insight. Understanding methods to model real device characteristics not captured in the basic models, plus methods to improve simulation convergence, can increase the value of simulation in the design process. Ultimately improved design robustness can be achieved.

REFERENCES [1] R. H. Randall, A. Laprade, B. Wood "Characterizing IGBT Switching

Losses for Switched Mode Circuits", PCIM Europe 2000, pp. 269-275, June 2000.

[2] R. H. Randall, A. Laprade, A. Craig, "Analyzing IGBT Losses by Translating Empirical Data Into SPICE Behavioral Models", PCIM Europe 2000, pp. 263-268, June 2000.

[3] Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet HGTP12N60A4D, http://www.fairchildsemi.com.

[4] R. H. Randall, A. Laprade, “Behavioral Model Analyzes IGBT Losses in Sinusoidal Circuits“ PCIM Europe 2001, pp. 165-170, June 2001.

[5] “Exploring the Nature of Spice Convergence Problems”, OrCAD Design Network, 5/99.

[6] http://www.fairchildsemi.com/models/PSPICE/Discrete/MOSFET.html [7] http://www.fairchildsemi.com/designcenter/index.html [8] http://www.transim.com/fairchild/index.html [9] http://www.fairchildsemi.com/whats_new/spm_tool.html [10] http://www.fairchildsemi.com/whats_new/offline_smps_toolkit.html [11] http://www.fairchildsemi.com/whats_new/pfc_toolkit.html [12] Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet

FDB8445, http://www.fairchildsemi.com. [13] http://www.fairchildsemi.com/models/Pspice_Bsim3.1/Discrete/MOSF

ET.html [14] Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet

FDB8441, http://www.fairchildsemi.com. [15] http://www.systat.com/products/TableCurve2D/

Scott Pearson has worked in the semiconductor industry for the past 17 years. For the past 12 years Scott has been involved in MOSFET characterization, testing and Spice modeling. He has been with Fairchild Semiconductor since May 1989. Scott obtained his B. Eng. from Penn State University. Alain Laprade has worked as a power supply designer for 14 years in applications including computer power, high power telecommunications and space designs. He has been with Fairchild Semiconductor Corporation since February 1998 working in industrial, cell phone and automotive applications. Alain obtained his B.Eng. from McGill University in 1982 and his M.Eng. from McGill

University in 1984.

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