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Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 11
ELEC 5970-001/6970-001(Fall ELEC 5970-001/6970-001(Fall 2005)2005)
Special Topics in Electrical EngineeringSpecial Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits
Dynamic PowerDynamic PowerVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor
Department of Electrical and Computer Department of Electrical and Computer EngineeringEngineering
Auburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849http://www.eng.auburn.edu/~vagrawalhttp://www.eng.auburn.edu/~vagrawal
[email protected]@eng.auburn.edu
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 22
CMOS Dynamic PowerCMOS Dynamic PowerDynamic Power = Σ 0.5 αi fclk CLi VDD
2
All gates i
≈ 0.5 α fclk CL VDD2
≈ α01 fclk CL VDD2
where α average gate activity factorα01 = 0.5α, average 0→1 trans.fclk clock frequencyCL total load capacitanceVDD supply voltage
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 33
Example: 0.25Example: 0.25μμm CMOS m CMOS ChipChip
f = 500MHzf = 500MHz Average capacitance = 15 fF/gateAverage capacitance = 15 fF/gate VVDDDD = 2.5V = 2.5V 101066 gates gates PowerPower = = αα0101 f Cf CLL VVDDDD
22
= = αα0101×500×10×500×1066×(15×10×(15×10-15-15×10×1066) ) ×2.5×2.522
= 46.9W, for = 46.9W, for αα0101 = 1.0 = 1.0
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 44
Signal Activity, Signal Activity, αα
T=1/f
Clock α01= 1.0
α01= 0.5
α01= 0.5
Comb.signals
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 55
Reducing Dynamic PowerReducing Dynamic Power
Dynamic power reduction isDynamic power reduction is Quadratic with reduction of supply Quadratic with reduction of supply
voltagevoltage Linear with reduction of capacitanceLinear with reduction of capacitance
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 66
0.250.25μμm CMOS Inverter, m CMOS Inverter, VVDD DD
=2.5V=2.5V0
-4
-8
-12
-16
-20
Vin (V)
Vou
t (V
)
Vin (V)
2.5
2.0
1.5
1.0
0.5
00 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5
Gai
n =
dV
out /
dVin
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 77
0.250.25μμm CMOS Inverter, m CMOS Inverter, VVDD DD << 2.5V2.5V
0.2
0.15
0.1
0.05
0
Vin (V)
Vou
t (V
)
Vin (V)
2.5
2.0
1.5
1.0
0.5
00 0.5 1.0 1.5 2.0 2.5 0 0.05 0.1 0.15 0.2
Vou
t (V
)
Gain = -1
Vth = 0.4 V
Similar to analog amplifier
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 88
Low Voltage Operation (Low Voltage Operation (VVDDDD > > VVthth))
Reduced dissipation, increased Reduced dissipation, increased delay.delay.
Operation sensitive to variations in Operation sensitive to variations in device parameters like device parameters like VVthth . .
Reduced signal swing reduces Reduced signal swing reduces internal noise (crosstalk), increases internal noise (crosstalk), increases sensitivity to external noise.sensitivity to external noise.
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 99
Impact of Impact of VVDDDD on on PerformancePerformance CLVDD
Inverter delay = K ─────── , Power ~ CLVDD2
(VDD – Vth )α
0.4V 1.45V 2.5V VDD
Power
Delay
40
30
20
10
0
Del
ay (
ns)
VDD=Vth
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 1010
Optimum Power × DelayOptimum Power × Delay VDD
3
Power × Delay, PD = constant × ─────── (VDD – Vth)α
For minimum power-delay product, d(PD)/dVDD = 0
(VDD – Vth)α 3VDD2 – VDD
3 α (VDD – Vth)α – 1
———————————————————— = 0(VDD – Vth)2α
3VDD – 3Vth = α VDD
VDD = 3 Vth / (3 – α)
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 1111
Optimum Power × Delay Optimum Power × Delay (Cont.)(Cont.)
For minimum power-delay product, d(PD)/dVDD = 0
3VthVDD = ───
3 – α
For long channel devices, α = 2, VDD = 3Vth
For very short channel devices, α = 1, VDD = 1.5Vth
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 1212
Very Low Voltage OperationVery Low Voltage Operation VVDDDD < < VVthth
Operation via subthreshold current.Operation via subthreshold current. Small currents have long charging Small currents have long charging
and discharging times – very slow and discharging times – very slow speed.speed.
Increasing sensitivity to thermal Increasing sensitivity to thermal noise.noise.
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 1313
Lower Bound on Lower Bound on VVDDDD
For proper operation of gate, maximum gain For proper operation of gate, maximum gain (for Vin = V(for Vin = VDDDD/2) should be greater than 1./2) should be greater than 1.
Gain = - (1/Gain = - (1/nn)[exp()[exp(VVDD DD / 2/ 2ΦΦTT) – 1] = - 1 ) – 1] = - 1 nn = 1.5 = 1.5 ΦΦT T = = kT/q = kT/q = 25 mV at room temperature25 mV at room temperature VVDDDD == 48 mV48 mV
VVDDminDDmin > 2 to 4 times > 2 to 4 times kT/qkT/q or ~ 50 to 100 mV or ~ 50 to 100 mV at room temperature (27at room temperature (27ooC)C)
Ref.:Ref.: J. M. Rabaey, A. Chandrakasan and B. Nikolić, J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Digital Integrated CircuitsIntegrated Circuits, , A Design Perspective, Second EditionA Design Perspective, Second Edition, , Upper Saddle River, New Jersey: Pearson Education, 2003, Upper Saddle River, New Jersey: Pearson Education, 2003, Chapter 5.Chapter 5.
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 1414
Capacitance ReductionCapacitance Reduction
Transistor sizing forTransistor sizing for PerformancePerformance PowerPower
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 1515
Basics of Sizing (Basics of Sizing (SS = Scale = Scale Factor)Factor)
Sizing a gate by factor Sizing a gate by factor SS means all means all transistors in that gate have their transistors in that gate have their widths widths WW changed to changed to WS. WS. Lengths (Lengths (LL) ) of transistors is left unchangedof transistors is left unchanged.. On resistance of the scaled transistor is On resistance of the scaled transistor is
reduced as 1/reduced as 1/SS Gate capacitance is scaled asGate capacitance is scaled as S S
Next we consider the delay and Next we consider the delay and power of the original and scaled power of the original and scaled gates.gates.
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 1616
A Standard Inverter, A Standard Inverter, SS = 1 = 1
CCgg = input capacitance = input capacitance RReqeq = on resistance= on resistance CCintint = intrinsic output capacitance = intrinsic output capacitance ≈ ≈ CCgg
Cg CLCint
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 1717
Transistor Sizing for Transistor Sizing for PerformancePerformance
Problem: If we increase Problem: If we increase W/LW/L to make the to make the charging or discharging of load charging or discharging of load capacitance faster, then the increased capacitance faster, then the increased WW increases the load for the driving gateincreases the load for the driving gate
Cin=Cg CL+SCg
Increase W for faster charging of CL
Faster charging
Slower chargingMore power
Req /S
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 1818
Delay of a CMOS GateDelay of a CMOS Gate
CMOSgate CLCg
Cint
Propagation delay through the gate:
tp = K 0.69 Req (Cint + CL)
≈ K 0.69 ReqCg (1 + CL /Cg)
= tp0 (1 + CL /Cg)
where K depends upon VDD, Vth, etc.
Gate capacitance Intrinsic capacitance
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 1919
RReq eq , , CCg g , , CCint int , , andand Width Width SizingSizing
RReq eq : equivalent resistance of “on” transistor, : equivalent resistance of “on” transistor, proportional to proportional to L/W; L/W; scales as scales as 11/S, S /S, S = width = width sizing factorsizing factor
CCg g : gate capacitance, proportional to : gate capacitance, proportional to CCoxoxWLWL; ; scales as Sscales as S
CCint int : intrinsic output capacitance : intrinsic output capacitance ≈ ≈ CCg g , for , for submicron processessubmicron processes
ttp0 p0 : intrinsic delay = : intrinsic delay = KK 0.69 0.69RReqeqCCg g , , independent of sizingindependent of sizing
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 2020
Effective Fan-out, Effective Fan-out, FF Effective fan-out is defined as the Effective fan-out is defined as the
ratio between the external load ratio between the external load capacitance and the input capacitance and the input capacitance:capacitance:
FF == CCL L /C/Cgg
ttpp == ttp0 p0 (1 + (1 + F F ))
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 2121
Sizing Through an Inverter Sizing Through an Inverter ChainChain
Cg1 Cg2 CL
1 2 N
Cg2 = f2 Cg1
tp1 = tp0 (1 + Cg2/Cg1)
tp2 = tp0 (1 + Cg3/Cg2)N N
tp = Σ tpj = tp0 Σ (1 + Cgj+1/Cgj)j=1 j=1
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 2222
Minimum Delay SizingMinimum Delay SizingEquate partial derivatives of tp with respect
to Cgj to 0, for all j
1/Cg1 – Cg3 /Cg22 = 0, etc.
or Cg22 = Cg1× Cg3, etc.
or Cg2/Cg1 = Cg3 /Cg2, etc.
i.e., all stages are sized up by the same
factor f with respect to the preceding stage:
CL/Cg1 = F = f N, tp = Ntp0(1 + F1/N )
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 2323
Minimum Delay SizingMinimum Delay SizingEquate partial derivatives of tp with respect to N to 0:
dNtp0(1 + F1/N) ───────── = 0
dN
i.e., F1/N – F1/N(ln F)/N = 0, or ln (f N) = N
or ln f = 1 → f = e = 2.7 and N = ln F
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 2424
Further ReadingFurther Reading
B. S. Cherkauer and E. G. Friedman, “A Unified DesignMethodology for CMOS Tapered Buffers,” IEEE Trans.VLSI Systems, vol. 3, no. 1, pp. 99-111, March 1995.
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 2525
Sizing for Energy Sizing for Energy MinimizationMinimization
Main idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing.
Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić,Digital Integrated Circuits, Second Edition, Upper SaddleRiver, New Jersey: Pearson Education, 2003.
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 2626
Sizing for Energy Sizing for Energy MinimizationMinimization
Cg1 CL
tp = tp0 [(1+ f ) + (1+ F/f )] = tp0(2 + f + F/f )
F = CL/Cg1 , effective fan-out
tp0 ~ VDD /(VDD – Vth) for short channel
Energy dissipation, E = VDD2Cg1(2 + 2f + F )
f1Minimum sized gate
Cg1 fCg1 fCg1Req /f
Req
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 2727
Holding Delay ConstantHolding Delay Constant Reference circuit: Reference circuit: ff = 1, supply voltage = = 1, supply voltage =
VVrefref
Size the circuit such that the delay of the Size the circuit such that the delay of the new circuit is smaller than or equal to new circuit is smaller than or equal to the reference circuit:the reference circuit:
ttpp t tp0 p0 (2+(2+ff++F/f F/f ) ) V VDD DD VVref ref - V- Vth th 2+2+ff++F/fF/f── ── == ──────── ──────── == ── ──── ───── ── ──── ───── == 11ttpref pref ttp0ref p0ref (3(3 ++F F ) ) V Vref ref VVDDDD- V- Vth th 3+3+FF
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 2828
Supply Voltage Vs. SizingSupply Voltage Vs. Sizing
1 2 3 4 5 6 f
VD
D (
volts
)3.5
3.0
2.5
2.0
1.5
1.0
F=1
2
5
10
fopt ≈ √F
Vref = 2.5VVth = 0.5V
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 2929
EnergyEnergy
E VDD2 2 + 2f + F
── = ─── ──────Eref Vref
2 4 + F
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 3030
Normalized Energy Vs. Normalized Energy Vs. SizingSizing
1 2 3 4 5 6 f
Nor
mal
ized
Ene
rgy
1.5
1.0
0.5
F=1
2
5
10
fopt ≈ √F
Vref = 2.5VVth = 0.5V
Fall 06, Sep 19, 21Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6ELEC5270-001/6270-001 Lecture 6 3131
SummarySummary
Device sizing combined with supply voltage Device sizing combined with supply voltage reduction reduces energy consumption.reduction reduces energy consumption.
For large fan-out energy reduction by a For large fan-out energy reduction by a factor of 10 is possible.factor of 10 is possible.
An exception is An exception is F F = 1 case, where the = 1 case, where the minimum size device is also the most minimum size device is also the most effective one.effective one.
Oversizing the devices increases energy Oversizing the devices increases energy consumption.consumption.