March 2014

New Allegro TimingVision Environment: Up to 67% Faster Timing Closure

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• Market demands products that are faster, have more bandwidth, and use less power

• Increasing use of standards-based interfaces– DDR2 DDR3 DDR4– PCI Express Gen1 Gen2 Gen3– Supply voltage: 1.8V 1.5V 1.2V

• Increasingly sensitive signals– Ripples through power supply– Crosstalk

Complex set of electrical and layout implementation constraints

Motivation: timing closure on advanced high-speed interfaces is iterative, frustrating, and time-consuming

DIMM

DIMM

Differential Clock

Address / Command / Control

Address / Command / Control

Differential Clock

VTT

VTT

VTTVTT

VTT

VTT

Data Bytelane (5)

Data Bytelane (5)

Differential Clock

Differential Clock

Data Bytelane (4)

Data Bytelane (4)

MEMCTRLR

3 © 2013 Cadence Design Systems, Inc. All rights reserved.Disclaimer: All Information Contained in this Document is Public Domain and for Reference Only.

Requires PCB designers to go back and forth between design canvas and Allegro® Constraint Manager

Timing closure is an iterative process—fix one byte lane, then fix another, then back to the first one

Feedback provided on a matched group level− All signals have to meet timing for the group to go green

All interdependencies and margins between groups are calculated by the PCB designer manually

Current: timing closure challengesDRC mode

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How Allegro TimingVision environment accelerates timing closureGreen is good Red is short Yellow is longStripes indicate the target net

1. Embedded timing engine‒ Analyzes signal

interdependencies to develop SMART delay and phase targets

‒ Helps designers develop strategy to address timing issues

2. Real-time visual feedback on design canvas– Shows color-coded timing and

phase information– Provides custom data tips– Allows users to see beyond

physical routing

3. Auto-interactive technologies‒ Significantly reduce manual

work with Auto-interactive Delay Tuning (AiDT) and Auto-interactive Phase Tuning (AiPT)

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Allegro TimingVision guiding AiDT

All nets in the byte lane are tuned!

Select complete interface for

Allegro TimingVision environment

Select abyte lane to tune

AiDT addstuning

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• Meet differential-pair phase requirements easily

• Static and dynamic phase compensation

• User-driven controlled compensation techniques

Allegro TimingVision guiding AiPT

Out of phase

Phase adjustment

Phase bumpsadded

7 © 2013 Cadence Design Systems, Inc. All rights reserved.Disclaimer: All Information Contained in this Document is Public Domain and for Reference Only.

• Allegro TimingVision environment with Cadence Sigrity® power-aware SI analysis can rapidly implement and assure compliance with memory interface specifications– Modeling SSN necessary for accurate

timing analysis

• Unmatched integrated signal and power integrity simulation solutions– Power-aware signal integrity ensures

accuracy and QoR– Multi-gigabit serial link solution predicts

BER– Full power integrity suite enables PI

signoff– Package and model extraction for

system-level analysis

Assure compliance with memory I/F specifications

8 © 2013 Cadence Design Systems, Inc. All rights reserved.Disclaimer: All Information Contained in this Document is Public Domain and for Reference Only.

• Innovative, unique environment within the Allegro PCB Designer solution accelerates timing closure by up to 67%

• Assures compliance with interface specifications in conjunction with Sigrity® power-aware SI analysis

• Cadence: Only EDA vendor to enable product creation from IP into SoC package PCB, with system predictably and cost effectiveness

• Learn more at: http://www.cadence.com/cadence/Allegro/autointeractive/Pages/default.aspx

Summary – Allegro TimingVision environment

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