Fatigue Crack Growth Behavior of Nanocrystalline Copper for Chip-to-Package Interconnects Cody Jackson* Dr. Ashok Saxena** (advisor), Rahul Rajgarhia** (graduate student) *Arkansas Tech University, **University of Arkansas, Fayetteville Mechanical Engineering REU project presentation, July 23 2007
Transcript
Slide 1
Fatigue Crack Growth Behavior of Nanocrystalline Copper for
Chip-to- Package Interconnects Cody Jackson* Dr. Ashok Saxena**
(advisor), Rahul Rajgarhia** (graduate student) *Arkansas Tech
University, **University of Arkansas, Fayetteville Mechanical
Engineering REU project presentation, July 23 2007
Slide 2
Outline Background and Problem Statement Proposed Solution
Experimental Procedure Research Results Discussion Conclusions
Slide 3
pitch Source: Garner et al., Intel Technology Journal, v9, n4
(2005). Due to the mismatch in the CTE of substrate and chip,
interconnects experience cyclic stress (fatigue) due to
fluctuations in current. In mobile electronics (laptops etc.) there
is a greater demand for reliable interconnects due to possible
damage when devices are dropped. From the above discussion, the
electrical and mechanical properties of interconnects determine
their feasibility for an application. Under fill Substrate
Chip-to-package interconnect Silicon Interconnects in Flip-Chip
height
Slide 4
Current Technology Lead solder is being gradually phased out
due to environmental and legal requirements. Aluminum cannot meet
the electrical requirements for fine pitch interconnects. Lead free
solder also cannot meet the challenges of mechanical reliability
and electrical conductivity for pitch sizes ~ 20m (Aggarwal et al.,
2002) There is a need to address the future challenges of reduced
size of electronic packaging, specifically: 1. Mechanical
reliability due the reduced size and increased stress 2. Electrical
conductivity (current density, efficiency) 3. Environmental
concerns and 4. Reduced cost Source: A. O. Aggarwal, P. Markondeya
Raj, R. J. Pratap, A. Saxena, and R. R. Tummala, "Design and
fabrication of high aspect ratio fine pitch interconnects for wafer
level packaging," 2002 IEEE Conference at Singapore, pp. 229-34
(2003)
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Proposed solution Nanocrystalline copper with grain size <
100nm Higher mechanical strength than lead free solder and high
cycle fatigue resistance. Very good electrical conductivity Source:
S. Bansal, "Characterization of Nanostructured Metals and Metal
Nanowires for Chip-To-Package Interconnections," in Materials
Science and Engineering. Ph.D. dissertation, Atlanta: Georgia
Institute of Technology, (2006). Zama, S., D. F. Baldwin, et al.
"Flip chip interconnect systems using copper wire stud bump and
lead free solder." Electronics Packaging Manufacturing, IEEE
Transactions on 24(4): 261-268 (2001). Coarse grained Cu
Nanocrystalline Cu N f (cycles to failure) Ultrafine grained Cu 0
100 200 300 400 500 00.0050.010.0150.02 Strain (mm/mm) Stress (MPa)
nanocrystalline copper microcrystalline copper Stress (MPa) Tensile
test High-cycle fatigue resistance
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The Problem For nanocrystalline Cu to be a potential material
for interconnects, it is critical to evaluate its performance under
cyclic stress. Fatigue crack growth (FCG) behavior of
nanocrystalline Cu is not yet known. Also, compare the results to
FCG rate of microcrystalline Cu
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Research Fatigue testing was conducted on Cu101 (99.99%) and
nanocrystalline (NC) copper in a 2.2 kiP servo-hydraulic machine
made by Test Resources. Cu101 was annealed at 500 o C for 50 min to
normalize it. Nanocrystalline Cu was produced using Equal Channel
Extrusion Process Tests were conducted as per E647-05 Standard Test
Method for Measurement of Fatigue Crack Growth Rates, ASTM
International (2005). v 03.01.
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Test specimen The specimen type is Compact Tension (CT).
Specimens were designed as to ASTM E647. a W = 0.8, B = 0.4, a/W =
0.25 1.25W B
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Research cont. The waveform used was sinusoidal. All samples
were pre-cracked to produce a sharper initial crack. Crack mouth
opening (v) is measured using an extensometer. Compliance is
calculated from the unloading portion of the v/P plot using about
35 data points. Crack size (a) is calculated using the measured
compliance as per ASTM E647. An average of 75 such crack size
measurements is taken for each data point recorded. Crack
increments (a) of 0.25 mm are recorded. Resolution = 0.001mm Range
= + 2 mm Load, kN Time, ms
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vs K plot is known as Paris Law. When plotted on a log scale,
there is a linear segment known as the Paris regime which allows
the stress intensity factor (K) to be related to the sub-critical
crack growth independent of the specimen geometry. Using this plot,
you can estimate the life remaining in components due to fatigue
cracking. Research cont. Source:
http://www.kuleuven.be/bwk/materials/Teaching/master/wg12/l1300.htm
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Research cont. Samples were pre-cracked at constant load.
Fatigue crack growth tests were conducted using decreasing K
method. K = K max K min (applied stress intensity parameter) K o =
intial K (constant for a test) a = a o a (crack increment) = -0.08
mm -1 (normalized K gradient)
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Data Analysis The a vs. N plot was used to calculate da/dN.
da/dN was then plotted against the calculated K values. N a
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Results
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Comparison
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Crack Size Correction To account for crack tunneling, the crack
was visually measured. The visual measurement was compared with the
compliance measurement.
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Conclusion Due to increased demand for smaller, more portable
electronic devices, current interconnect technology is not
sufficient. To meet mechanical and electrical property requirements
new materials are needed for interconnects. Nanocrystalline copper
has a higher strength than microcrystalline copper and appears to
be a material which can meet the new demands. Threshold values are
very important because a common form of current technology (e.g.
laptops and cell phones) will normally undergo a number of fatigue
cycles that are in the threshold regime. For example, a laptop may
be turned on/off twice a day, five days a week, for five years.
This is a total of ~2600 cycles, on interconnects 25 x 10 -3 mm.
This gives an approximate da/dN value of 9.6 x 10 -6 mm.
Manufacturers can take estimates similar to this and compare to
current interconnect sizes to determine the estimated life of
certain components in their products. Based on scenarios as before
mentioned, it is important to know that through fatigue crack
growth testing, nanocrystalline copper has shown increased
resistance to fatigue crack growth, but with a slightly lower
threshold value.
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Acknowledgments Dr. Saxena (advisor) Rahul Rajgarhia (graduate
student) Jeff Evans Sau Wee Koh Jeff Knox Dr. Zou Henry Wang