IEEE TRANSACTIONS ON COMPUTERS, VOL. c-23, NO. 4, APRIL 1974

Fault Detection of Binary Sequential Machines

Using R-Valued Test Machines

DONALD A. SHEPPARD, MEMBER, IEEE, AND ZVONKO G. VRANESIC, MEMBER, IEEE

Abstract-An improved method for detection of faults in com-pletely specified synchronous sequential machines is described. Thetechnique is algorithmic, based on the concept of embedding thegiven binary machine into an easily testable R-valued machine.Hleuristic optimization of additional permutation inputs is shown tolead to considerable reduction in the length of the fault sequence.A bound on the sequence length is derived, which in most cases issignificantly lower than those of comparable methods.

Index Terms-Fault detection, many-valued logic, permutationinputs, synchronous sequential machines, test machines.

I. INTRODUCTION

THE DESIGN of synchronous sequential machineswhose correct operation may easily be verified has

been a subject of recent research interest. The questionto be answered is: what minimum stimulus will generatesufficient response to ensure that the machine is correctlyimplementing the desired state table? The stimulusnormally consists of the application of a sequence of sym-bols from the input alphabet, and the resulting response iscompared to a known correct output. Such tests are calledchecking (or fault detection) experiments. The usualcriterion of efficiency is the length of the test, i.e., thenumber of input symbols applied.While a large number of papers on this topic can be

found in the literature, most results have been improve-ments upon Hennie's transition checking approach [1].His procedure attempts to force each state table transition,and then validates this action with a previously testeddistinguishing sequence. This approach is heavily de-pendent upon the existence of a distinguishing sequence ifthe length of the test is to be within some practicallimits. Gonenc [2] formalized this method by introducinggraph theoretic techniques, resulting in an algorithmictest generation scheme.

In order to deal effectively with machines which do nothave a distinguishing sequence, it is necessary to considerthe possibility of augmenting the original machine withsome additional logic circuitry. Kohavi and Lavallee[3] proposed the addition of output logic. Murakami

Manuscript received December 11, 1972; revised July 18, 1973.This work was supported in part by the National Research Councilof Canada under Grant A-5280.D. A. Sheppard is with Cybernetic Services, Canadian National

Railway, Montreal, P. Q., Canada.Z. G. Vranesic is with the Electrical Engineering and Computer

Sciences Departments, University of Toronto, Toronto, Ont.,Canada.

TABLE I

Given Machine Test Machine

M = (I,0,Q,,6) M' = (I,Q, )

where

I = {xl,X 2 *'xm 2 I' = {Xl)X2 m".**JXm}R

0 = {z 2' zp2' = {z lZ21-''zp p Ro

Q = 2ql 2.*qn12

0(t) = X(I(t),Q(t)) 0'(t) = '(I'(t),Q'(t))

Q(t+1) = 6(I(t),Q(t)) Q(t*1) = 6'(I'(t),Q(t))

et al. [4] modified the input logic by adding a permutationinput that can provide a homogeneous distinguishingsequence. Kane and Yau [5] improved upon this with amore suitable output assignment under the permutationinput. They also considered using additional inputs toprovide transitions needed to transform the cell graph intoan Eulerian circuit.

In this paper we show an improved procedure, based onthe additional input logic [4], [5], which makes use ofgraph theoretic techniques [2].As in previous papers, it will be assumed that only

terminal measurements are possible. It will also bepostulated that faults do not occur during the test, thatthey last at least the length of the test, and that the statecount is not increased as a result of a fault.

II. TERMINOLOGY AND GENERAL APPROACH

The procedure that follows embeds the given binarymachine (M) into an easily testable R-valued machine(M'), where R > 2. The test sequence is developed for thelatter and the resultant machine may then be implementedeither in a many-valued or some encoded form.

Let the machines be described as in Table I whereI}K indicates an alphabet in base K. The machine Mis assumed to be finite-state, deterministic, synchronous,and described in Mealy form. It is noted that, practicallyspeaking, these restrictions do not limit the usefulness ofthe technique. The bases of the input and output alphabetsof the test machine will not be restricted to a particular

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SHEPPARD AND VRANESIC: BINARY SEQUENTIAL MACHINES

value for test generation purposes, i.e., Rf 2 2 andRo . 2.A sequence is denoted by S = (sis... s), where the

symbols are those of Table I. The sequence of checkingsymbols will be referred to as the fault sequence (FS),and it will be of the preset type (i.e., completely de-termined prior to the application of the test). Othersequences, such as the distinguishing sequence (DS),the homogeneous DS (HDS), the homing sequence(HS), and the synchronizing sequence (SS) are definedin the standard manner [6]. The length of any sequenceS is indicated by L(S), and the aim will be to minimizeL (FS) at the least possible cost.

Let a cell be defined, in the manner of Gonenc [2], asthe input sequence (xiXd) applied to the test machine inany state qj, where Xd represents theDS used for transitionvalidation purposes. The state table and graph associatedwith such cells are of interest and will be referred to as thecell table and graph, respectively.

Test procedures using the transition checking approachare usually broken into three subtests. The first, aninitializing sequence (IS), maneuvers the test machineinto the desired starting state. Next, a permutationsequence (PS), consisting of repeated applications of aDS, is applied in order to count the states and check theoutputs associated with DS cells. Finally, a set of transi-tion checking segments (i.e., cells) is added to the FS.These cells must be linked into a continuous sequence,and it is found that additional transitions between cellsare usually required to link disjoint groups of cells (i.e.,paths on the cell graph). In order to formalize theseconsiderations (following the model of [2]) it is useful todefine the following.

Definition 1: A path link (PL) is a transfer sequencebetween two disjoint paths (each path containing one ormore cells).

Definition 2: The total path link (TPL) represents theset of PL's required to link all paths associated with aparticular machine into an Eulerian graph.

Definition 3: An easily testable sequential machine isone which possesses a minimal length HDS for the givenalphabet, and for which L(TPL) is minimal.The complete sequence of cells plus PL's will be re-

ferred to as the cell sequence (CS). The three subtests,when concatenated, form the FS, so that

FS=IS 11 PS 11 CS.

III. MACHINE AUGMENTATION

Three possibilities are evident for the reduction ofL(FS). 1) Shorten L(Xd) since it is applied once for eachcell in the CS. 2) Make Xd a HDS in order to allow over-lapping in the PS, and ensure its cyclic character in orderto eliminate transfer sequences in the PS. 3) MinimizeL(TPL) in order to shorten the CS. Moreover, the FSshould be designed to eliminate transfer sequences(other than PL's) whenever possible.

A. The Permutation InputThe second possibility stated above was implemented

by Murakami et al. [4] through introduction of thepermutation input x,, such that:

6'(xr,qi) = qi+l,' (x, q.) = ql.

Furthermore, their output assignment under x, was

X' (x,,qj) = 0,

X' (xrn) = 1.

Thus, a HDS consisting of n applications of x7 is created.Kane and Yau [5] pointed out that a shorter HDS can

be obtained if the output assignment under xr (whenp < n) corresponds to a p-ary shift register sequenceof length n and minimum degree, which may be foundusing Smith's algorithm [7].We note that the above choice of state transitions under

x, is not essential for it is only necessary to provide acyclic format. It will be shown later how this flexibilitycan be used to advantage.The length of the DS may be reduced by expanding

the output alphabet to equal the number of states, when-ever necessary. Thus p' > n, and a unique output symbolcan be assigned to each transition of the permutationinput. This reduces Xd to a single symbol (Xd = x7)and yields a cell length of 2. This is obviously minimal,because at least one forcing and one checking symbol willalways be required. Since the design of the FS is inde-pendent of the particular output assignment used, circuitcost may be reduced by properly choosing the outputs.Such assignments may also be used to alter the form of theoutput sequence. It should be emphasized, however, thatexpansion of the output alphabet may be objectionablefrom a practical point of view. This may particularly be soif outputs are binary coded, although the increase incomponent cost is often small.

In view of the current developments in many-valuedlogic realizations, it is reasonable to expect that many-valued circuits can be used effectively for simple functionssuch as the ones arising from simple output assignments.This is particularly promising due to the fact that theoutput function under x, is used for simple matchingpurposes only (during the test); hence most level tolerancedifficulties normally involved in construction of complexmultistage circuits (requiring considerable driving cap-ability) are not a significant problem. Furthermore, itshould be pointed out that such functions are well suitedfor realization with multithreshold elements which havebeen reported recently [8], [9].

B. The Weight Table

It is known from graph theory [2], [5] that the nodesof a graph can be partitioned into the following three sets:

E = {qicQ TI, = TOiJ

353

. . . - 1172, M

i = 112, 0 0 0M 1

IEEE TRANSACTIONS ON COMPUTERS, APRIL 1974

N = {qiEQ TI1 < TOi}

P = qieQITI > TOi}

where

TIi the number of transitions entering state qiTOi the number of transitions leaving state qi,

andE+N+P = Q.

A graph of transition testing cells may be defined for anygiven machine. A path in such a graph is a series of con-catenated cells; a covering is a set of disjoint paths in whichall cells are represented once and only once; and a circuitis a covering consisting of a single path beginning andending at the same node.Our aim will be to generate an Eulerian cell graph, for

which a circuit may be found from any starting state.Modifications will be made by adding PL's until this con-dition is obtained. It will, in general, be necessary to addK path links, where K = El (TIi - TOi) = EN (TOt -

TIi), in order to accomplish the desired alteration. It is inthe generation of short PL sequences that changes in thepermutation input have a marked effect.To illustrate more clearly the possibilities involved we

shall make use of a weight table, an example of which isgiven in Fig. 2 for machine M1 (Fig. 1). The weight tableis an enumeration of the transitions into and out of eachstate. It is readily seen that K = 2W, where Wzi=ln Wi and wi = TI - TOi is the weight associatedwith the ith state. It should be noted that each PL willcause a transition from a positive weight to a negativeweight.

Analogously, a cell weight table may be constructedfor the cell graph. The weights due to transitions resultingfrom input sequences (xiXd), as opposed to single symbol(xi) inputs, may also be determined from the state weighttable. The transition due to (Xd) for each state is repre-sented as a directed arc from the initial to the final state.The difference, (TItail - TOhead), forms the weight of thestate pointed at by the arc. Fig. 3 illustrates this formachine M1 and the permutation input (x,) given.

Theorem 1: For a completely specified sequentialmachinp the weights of the cell graph are a permutationof the weights on the corresponding state diagram.

rProof: Consider any three states qi,qj, and qk suchthat the transitions on the cell graph are

XiXd XjXdqi -qj- qk.

From the state diagram we obtain the state weights

wi= TIi - TO

W= TIj - TOjwk= TIk - TOk.

Similarly, for the cell weights,

wj' = TI, - TOjWkf= TIj - TOk.

A

B

C

D

E

F

0

%,o

F,1

BJO

B,0

E,1

C,1

E,O

E,0

D,0

A,1

B,1

B,0

Fig. 1. Machine M1.

State Transition

TI. - TO.1 1

5 2

3 2

F

State Weight

w.

-1

3

-1 K = 4

-1

I

1 2 -1

W=8

Fig. 2. Weight table for M1.

Since the machine is completely specified it follows thatTOi = TOj = TOk = m, and therefore wj' = wi andw = wj. Thus the weights associated with states q,and qk on the cell table are equal to those of qi and qj,respectively, on the state table and are simply shifted.Similar reasoning may be applied to all other states, thusproving the theorem. The following corollary followsimmediately.

Corollary 1: If a cell graph of a completely specifiedsequential machine is not Eulerian for any given permu-tation input, then it is not Eulerian for all possible permu-tation inputs.

Therefore, in case of completely specified machines, theonly advantages to be gained from permutation inputdesign lie in the reduction of the number of PL symbolsused to modify the cell graph.

C. Permutation Input OptimizationVariations in permutation input format can be bene-

ficial in L(FS) reduction. Clearly, it is possible to con-struct a tree of all possible state cycles and use it to de-termine the optimum permutation input. However, suchexhaustive enumeration is practical only for machineswith a relatively small number of states. A more usefulalternative is to devise a heuristic procedure which reducesthe computational effort and leads to nearly optimalsolutions. One such procedure is described in the re-mainder of this section.The optimization problem can be reduced to a process of

reordering the state weights. Since our goal is to minimizeL (TPL), we shall attempt to find a permutation input X.

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SHEPPARD AND VRANESIC: BINARY SEQUENTIAL MACHINES

State Transition Cell Weight

qi TI. - TO.. w!1 1

A 1 2

B 5 2

X =(x )1 2

D 1 2

E 3>2

-l

3

-1

- 1

-1

W=8

w.1

ql = A -1i;

q2 = B 3

q3 = C -l

q4 = D -1

q5 = E 1

q6 F-1(a)

Fig. 3.

WiR

ql = A -l1

q2 = B l 3

q' = C -1

q' = D -1)

q5l = P \-l1

q6 = E 1

(b)Fig. 4.

which minimizes distances between positive and negativeweights. The distance is the number of applications. ofx7 necessary to cause the transition from a state cor-

responding to a positive weight to a state correspondingto a negative weight.The effect of the permutation input can be represented

with directed arcs on the weight vector. For example we

can represent the effect of x, from Fig. 3 as shown inFig. 4(a). In order to facilitate calculation of distances itis convenient to represent xr in cyclic form as indicatedin Fig. 4(b), which is done by reordering the weights cor-

responding to the given states. Note that in our exampleA B -> C -* D -> F -> E -* A, as indicated by the

cyclic weight vector WiR.

From WiR it is readily seen that four path links are

needed as indicated with dotted arcs in Fig. 4(c). It alsofollows directly that in our example L (TPL) = 7.

Thus, WiR provides a simple means of determiningL (TPL). However, the actual path links cannot befound directly from WiR and must be obtained from thecell weight vector wi'.The following heuristic procedure has been found ef-

fective in the formation of wiR leading to nearly optimalpermutation inputs.

Procedure 1

Step 1: Enter all zero weights at the top of the WiRvector.

Step 2: Match pairs of equal positive and negativeweights, adding each such pair to WiR (with positiveweights uppermost). Process the wi list sequentially fromthe top, accepting the first suitable weights.

Step 3: Add the remaining weights in positive andnegative groups such that the distance is minimized.Process these weights in descending order, and pnterpositive before negative groups.

The above steps can be justified by the following con-

siderations. Each PL is required to generate a transitionfrom a positive weight to a negative weight. Since zero

weights cannot be initial or terminal nodes of a PL theyshould not be embedded into one, and this is ensured bytheir removal in Step 1. Similarly matched pairs are re-

moved in Step 2 as they form self-contained paths and

should be excluded from other PL's. In Step 3 the largestpositive and negative weights are arranged in closestproximity in order to minimize the length of the greatestnumber of PL's.

Application of the above procedure to the state weightsof Fig. 1 (for machine' M1) yields the result given in Fig. 5.This is seen to lead to the permutation input of Fig. 3.It should be noted that wiR does not necessarily give a

unique X,. For example, the WiR in Fig. 4 may also give riseto the permutation input A -> B ->F >D -* C ->E ->A.

D. Alternate Sources for Path Links

In Section III-C the permutation input was optimizedin order to reduce L(TPL). Since transfer sequences

generated by any DS can, at worst case, be n-1 symbolsin length, it is worthwhile investigating alternate sources.

Any one PL can be eliminated by the use of a pseudo-Eulerian graph (i.e., a graph where K = 1 and thestarting state is fixed). This, however, restricts the CSstarting state which will often necessitate additionalsymbols in the IS. Secondly, it is often possible to findsuitable transfer sequences in the given machine thatcould be used effectively, although there is no guaranteethat these will exist. Furthermore, such sequences mustbe tested prior to being used, which reduces the flexibilityin the generation of CS. A third possibility, suggested byKane and Yau [5], is to introduce PL cells under new

inputs. Such sequences are self-checking (since theypossess the form (xiXd) and have a maximum length ofL(DS) + 1.

IV. TEST MACHINE AND FAULT SEQUENCEGENERATION

In the previous section the possibility of optimizingthe permutation input was discussed. It was also suggestedthat the output alphabet may be expanded for testingpurposes, in order to reduce the length of DS. Thisclearly involves considerable tradeoff between the lengthof the test and the cost of added hardware. We feel thatthe importance of such tradeoffs cannot be overem-

phasized, hence rigid rules should be avoided.

xr

Bz

C,z2D,z3

F,z4FJ4A,z5E 6ZE'Z6

A

B

C

D

E

F

WiR

/ 3 ,

I1 1 J. \I/

/

A\ -14 11

1

(e)

355

IEEE TRANSACTIONS ON COMPUTERS, APRIL 1974

The following procedure for generation of easily testablemachines and the resultant test sequence is an improve-ment of Kane and Yau's method [5]. In order to presentit as clearly as possible, we will consider the reductionof L(FS) as the main objective, and illustrate the costtradeoff by means of an example. Thus, any PL of lengthgreater than L(DS) + 1 is implemented through ad-ditional inputs. It should be noted that if an additionalinput is used to realize a PL, it may also be used to providea reset mechanism. For example, let the input x,+1 inFig. 6(a) be used in realization of a single PL cell. Then,it will likely be advantageous to make use of this inputfor initial synchronization to state B, as indicated inFig. 6(b).

Procedure 2

Step 1: Determine the optimal (or nearly optimal)permutation input for the given machine using Procedure1 (for completely specified M) or exhaustive examination(for incompletely specified M). Add the transitions thusderived to M under a new input symbol x, to form amachine Mr.

Step 2: Assign output symbols to each transition underxr. If the allowable output alphabet p' > n, then eachtransition yields a distinct output. For this case Xd =(xr) and L(DS) = 1. Otherwise Smith's algorithm maybe used. Then Xd = (x7x,..*), where Xr is repeatedL(DS) =[logp' n] times. (It should be noted thatSmith's algorithm is subject to lengths restrictions [7],however this is not a hinderance for practical machines.)

Step 3: Form a cell table (and cell graph G) for Ml,deleting permutation input cells, and find the cell weightvector. If W = 0 go to Step 6.

Step 4: Determine the path links required from theweight table. Generate these using repeated applicationsof x.. Replace any PL's that are of length greater thanL (DS) + 1 with cell PL's added under new input symbols(Xr+±,Xr+2 ). Thus the augmented machine M' is pro-duced, and the TPL set determined.

Step 5: Add the set of PL's to the cell graph G, thusforming a modified graph G' possessing an Euleriancircuit.

Step 6: Generate an Eulerian circuit of G' beginning atthe required starting state (xd successor of the synchroni-zation) to obtain the CS.

Step 7: Append the PS subtest consisting of n +L(DS)x, symbols to the beginning of the CS, arrangingthe final state to coincide with the first state of the CS.

Step 8: Complete the FS by adding an IS to the begin-ning of the PS of Step 7.

V. EXAKIPLE

Consider the machine M1 given in Fig. 1. Let the outputalphabet be 0' = f0,1,2}.

Step 1: The permutation input is derived from the stateweights using Procedure 1 as shown in Fig. 5. The resultantwiR implies xr= 2: A -+B -* C -* D -- F -* E -* A.

wiR

E

A

B

C

D

F

1N

3-.-

-1w 1 2

- 1 *1, /

-1 e'-F1*- - 5.

Fig. 5.

x r+1

A

C B-

(a)

A

B

C

D

E

F

L (TPL) = 7

xr+1

A B, -

B B, -

C B, -

bD B,-

(b)Fig. 6.

0 1 x =2r

B,0 E,O B,0

F,1 E,0 C,2

B,O D,O D,2

B,O A,1 F,1

E,1 B,1 A,0

C,1 B,O E,2

Fig. 7. Machine Mir.

Xd = (22)

Step 2: Since p' = 3 < n, use Smith's algorithm to findthe output assignment under x,. as shown in Fig. 7.

Step 3: A cell table is formed, deleting all xr cells. Thisis shown in Fig. 8, along with the corresponding cellweight vector. (Note that the cell weight pattern merelyfollows the Xd - successor pattern of state weights).It is seen that W = 8 5 0.

Step 4: The following PL's are required:

2

2

22

222D----A.

All PL's should be implemented under xr, and Mit is infact the final augmented machine M1 .

Step 5: The above set of PL's is added to the cellgraph to form G' as in Fig. 9.

Step 6: A circuit of G' may now be generated with the

356

SHEPPARD AND VRANESIC: BINARY SEQUENTIAL MACHINES

022 122 TI! - TO! = w !1 1 1

following as one

state D):

1

3

5

1

2 -1

2 1N \ 31 1 1

2 -1 /

2 3 <.,-4

2 -1-2 ' 1/

2 -1 '

of the possible solutions (starting in

A

B

C

D

E

F

0 1 2.x 3'r

5.0 E,0 B,z _

F,1 E,O C,z2 -

B,O D,0 D,z3 F,-

1,6 A,1 F,z44

E,l 5,1 A,z5z

C,1 5,0 E,z6

Fig. 10. Alternative test machine for M1.

In order to illustrate the tradeoffs involved, let us againconsider the machine M1, but without the previous re-striction on the output alphabet size (hence needing sixdistinct output symbols). Applying the Procedure 2 wefind that the PL of length 3 can be replaced by a cell underthe new input xr+± = 3, giving the augmented test machineshown in Fig. 10. The resultant FS consists of 42 symbols.

Let us next consider a tighter restriction on the outputalphabet, so that 0' = {0,1}. In this case L(Xd) 3,the only additional input is x, = 2, and L(FS) = 69.It is of interest to compare this with a test machinegenerated using Kane and Yau's method, where fouradditional inputs are needed and L(FS) = 78.

VI. CONCLUSIONSThe proposed technique is a significant improvement

over currently available methods of similar type. Theresultant fault sequences are in most cases considerablyshorter than those obtainable with Kane and Yau's [51method, without corresponding increase in circuit com-plexity.

X: 0 2 2 1 2 2 0 2 2 2CS = Q: [D]B C D A B C B C D F

Z: 0 2 2 1 0 2 0 2 2 1

0 2 2 1 2 2 0 2 2 1 2E A B E A B F E A E A1 0 0 0 0 0 1 2 0 0 0

The starting state for the CS is the Xd-successor of thesynchronization.

Step 7: The n + L(DS) x7's are next appended to thebeginning of the CS, so that

2 2 2 2 2 2 2 2PS=[B]C D F E A B C D

2 2 1 2 0 0 2 2.

Step 8: Finally, the IS should be appended to thebeginning. For M1 it is possible to have a preset IS sinceit possesses a synchronizing sequence, thus:

1 1 0 1IS = [qi]-- - B

Therefore, the length of FS is 56 symbols.

0 2 2 1 2 2 2 2EC D F B C D F E

1 2 1 0 2 2 1 2

2 2 1 2 2 1 2 2 2 2 2 0 2 2B C D F E B C D F E A B C D0 2 0 1 2 1 2 2 1 2 0 0 2 2.

A bound on the test length is readily derived:

L (FS) = L (IS) + L (PS) + L (CS)

(n) + (n + s) + [mn(s + 1)8+1

+ m(s + 1) (n-s- 2) + m Sii=l

8+1

< 2n+s+m(s+ 1)(2n-s-2) +m i

where s = L (DS). It is also noted that at mostm(n - 1) - 1 input symbols must be added.

There are two disadvantages of the proposed technique.Firstly, the properties of the given machine are not

A

B

C

D

E

F

D,022

A,120

D,022

D,022

B,100

F, 121

B,000

B,000

E,012

C, 102

D,122

D,022

W=8

Fig. 8. Cell table and weights for M1r.

Fig. 9. Cell graph G'.

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IEEE TRANSACTIONS ON COMPUTERS, VOL. c-23, NO. 4, APRIL 1974

always employed efficiently. Thus the possibility of usingtransfer sequences from the given machine is ignored aswell as the use of multiple overlapping distinguishingsequences.

Secondly, augmentation of input and output logic mayrequire a number of additional leads, particularly inbinary coded implementation. Clearly, the limitation ismost severe in cases of single-input-single-output machineswith a large number of states. This provides the incentivefor the use of many-valued logic, which is particularlyattractive in the pin-limited environment of integratedcircuits.

However, we feel that the algorithmic nature of thetechnique and the reduced length of tests far outweighthe above mentioned drawbacks.

Finally, it is important to emphasize the tradeoffbetween the test length and circuit complexity of the testmachine.

REFERENCES[1] F. C. Hennie, "Fault detecting experiments for sequential

circuits," in Proc. 6th Annu. Symp. Switching Theory and LogicalDesign, Princeton, N. J., Nov. 1964, pp. 113-115.

[2] G. Gonenc, "A method for the design of fault detection experi-ments," IEEE Trans. Comput. (Short Notes), vol. C-19, pp.551-558, June 1970.

[3] Z. Kohavi and P. Lavallee, "Design of sequential machines withfault-detection capabilities," IEEE Trans. Electron. Comput.,vol. EC-16, pp. 473-484, Aug. 1967.

[4] S.-I. Murakami, K. Kinoshita, and H. Ozaki, "Sequentialmachines capable of fault diagnosis," IEEE Trans. Comput.,vol. C-19, pp. 1079-1085, Nov. 1970.

[5] J. R. Kane and S. S. Yau, "On the design of easily testablemachines," in Proc. IEEE 12th Annu. Symp. Switching andAutomata Theory, Oct. 1971, pp. 38-42.

[6] Z. Kohavi, Switching and Finite Automata Theory. New York:McGraw-Hill, 1970.

[7] A. R. Smith, III, "General shift-register sequences of arbitrarycycle length," IEEE Trans. Comput. (Short Notes), vol. C-20,pp. 456-459, Apr. 1971.

[8] R. Mori, "On an extended threshold logic as a unit cell of arraylogics," in 1972 Fall Joint Comput. Conf., AFIPS Conf. Proc.,vol. 41. Washington, D. C.: Spartan, 1972, pp. 353-366.

[91 A. Druzeta, A. Sedra, and Z. G. Vranesic, "Integratable multi-threshold circuits for realization of many-valued logic," to bepublished.

Donald A. Sheppard (M'72) was born inMontreal, P. Q., Canada, on March 25,1948. He received the B.Eng.(Elec.) degreefrom McGill University, Montreal, P. Q.,Canada, in 1969, and the M.A.Sc. degreefrom the University of Toronto, Toronto,Ont., Canada, in 1972.From June 1969 to September 1970 he

worked for C. P. Telecommunications. Heis presently a Communication Engineer forthe Canadian National Railway. He is in-

volved in the implementation of the CNR TRACS computersystem. His interests are in reliability, fault diagnosis and, many-valued switching systems.

Zvonko G. Vranesic (S'67-M'69) was bornin Zagreb, Yugoslavia, on October 4, 1938.He received the B.A.Sc. degree in 1963, theM.A.Sc. degree in 1966, and the Ph.D. de-gree in 1968 in electrical engineering fromthe University of Toronto, Toronto, Ont.,Canada.From 1963 to 1965, he was with the

Northern Electric Co., Ltd., Bramalea,Ont., Canada. In 1968 he joined the facultyof the Departments of Electrical Engineering

and Computer Science at the University of Toronto, where he isnow an Associate Professor. His research interests include many-valued switching systems, fault tolerant computing, computerarchitecture, and heuristic programming.

Testing for Faults in Wiring NetworksWILLIAM H. KAUTZ

Abstract-An algorithm is derived for multiprobe testing forshorts, opens, and wiring errors in any multiterminal wiring net-work, such as a printed circuit board, wiring harness, multiconductorcable, or backplane wiring board. For behavioral testing the mini-mum number of tests required, always achievable, is equal top - 1 + rlog2ql, where p is the number of terminals in the largestinterconnected cluster in the network, and q is the total number ofclusters, including isolated terminals. For structural testing the

Manuscript received July 3, 1972; revised January 29, 1973.The author is with the Stanford Research Institute, Menlo Park,

Calif.

number of tests required is less, and can be as small as Flog2ql + 1depending upon the assumptions made regarding the types of faultsthat can occur.

Index Terms-Behavioral testing, faults, structural testing,switching circuits, wiring networks.

INTRODUCTION

HUNDREDS of technical papers have appeared in theH U. S. in the last decade on the subject of fault testing

358