Fault Diagnosis in Sequential CircuitsMay 01, 2020 · Fault diagnosis includes both fault...

Department of Electronics and Communication Engineering, VBIT

Fault Diagnosis in Sequential Circuits

P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)


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➢ Circuit Test Approach, Transition Check Approach – State identification

and fault detection experiment, Machine identification, Design of fault

detection experiment.

VIDYA SAGAR P2

CONTENT

https://potharajuvidyasagar.wordpress.com/



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Fault Diagnosis of Digital Systems

➢ Digital systems, even when designed with highly reliable components, do not

operate for ever without developing some faults

➢ When a system ultimately does develop a fault it has to be detected and located

so that its effect can be removed

➢ Fault diagnosis includes both fault detection and fault location

➢ Fault detection means the discovery of something wrong in a digital system or

circuit

➢ Fault location means the identification of the faults with components, functional

modules or subsystems, depending on the requirements

VIDYA SAGAR P3




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TESTING OF SEQUENTIAL CIRCUITS

➢ Test generation for sequential circuits is extremely

difficult because the behavior of a sequential circuit

depends both on the present and on the past input

values. The mathematical model of a synchronous

sequential circuit is usually referred to as a

sequential machine or a finite state machine.

VIDYA SAGAR P4

➢ Henceforth, a synchronous sequential circuit will be

referred to as a sequential circuit.

➢ If there are m secondary input variables in a sequential circuit,

then the circuit can be in any one of 2m different present

states. The outputs of the combinational part of the circuit are

divided into two sets. The primary outputs are available to

control operations in the circuit environment, whereas the

secondary outputs are used to specify the next state to be

assumed by the memory. It takes an entire sequence of inputs

to detect many of the possible faults in a sequential circuit.




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Test Generation for Sequential Logic Circuits

➢ There two distinctly different approaches to the problem of finding tests

for sequential circuits:

1. By converting a given synchronous sequential circuit into a one

dimensional array of identical combinational circuits. Most techniques for

generating tests for combinational circuits can then be applied.

2. By verifying whether or not a given circuit is operating in accordance

with its state table

VIDYA SAGAR P5




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Circuit Test Approach :

VIDYA SAGAR P6




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Transition Check Approach:

VIDYA SAGAR P7




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State Table Verification

• In this approach a sequential machine is tested by performing an “experiment”

on it, i.e. by applying an input signal and observing the output

• Hence, the testing problem may be stated as follows: given the state table of a

sequential machine, find an input/output sequence pair (X, Z) such that the

response of the machine to X will be Z if and only if the machine is operating

correctly.

VIDYA SAGAR P8




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VIDYA SAGAR P9

Checking experiment

• Checking experiment: The application of input sequence X and the observation

of the response, to see if it is Z.

• It is customary to distinguish between two types of experiments:

1. simple experiments, which are performed on a single copy of the machine;

2. multiple experiments, which are performed on two or more identical copies of the machine.

• Checking experiments are classified either as “adaptive” or “preset”.

• In “adaptive” experiments the choice of the input symbols is based on the

output symbols produced by a machine earlier in the experiment

• In “preset” experiments the entire input sequence is

completely specified in advance

• A measure of efficiency of an experiment is its “length”,which is the total

number of input symbols applied to the machine during the execution of an

experiment




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The derivation of “checking sequence”

➢ The derivation of “checking sequence” is based on the following assumptions:

1. The network is fully specified and deterministic. In a deterministic machine the

next state is determined uniquely by the present state and the present input.

2. The network is strongly connected, i.e. for every pair of states qi and qj of the

network, there exists an input sequence that takes the network from qi to qj.

3. The network in the presence of faults has no more states than those listed in its

specification. In other words, no fault will increase the number of states.

VIDYA SAGAR P10




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Example: Draw the successor tree for machine(m/c) M1 whose table is shown below

➢ For example, suppose that we apply an input symbol 1 to machineM1 and that in

response it produces the output symbol 0. We may conclude that M1 was initially in

state C, since only from that state is a response of 0 to input symbol 1 possible. The

final state in this case is B. However, suppose the response of M1 to input symbol 1 is

1; then all we can say regarding the final state of the machine is that it may be any of

the states D, A, or C, depending on whether the initial state was A, B, or D, respectively.

The set of states (ACD) thus represents the uncertainty regarding the final state of M1

after the application of the input symbol 1.

VIDYA SAGAR P11

PS x = 0 x = 1

A C/0 D/1

B C/0 A/1

C A/1 B/0

D B/0 C/1

In general, the uncertainty regarding the state of M after the application of X is a specific

subset of the X-successors of the states contained in the initial uncertainty. The elements of

the uncertainty are not necessarily distinct.




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➢ Singleton: A component having a single state without duplication. Ex: (A), or (B). Note:

(AA) is not a singleton.

➢ Homogeneous: A component having only one state, with or without duplications. Ex:

(A), or (AA), or (BBB). Note: (AAB) is not homogeneous.

➢ Nonhomogeneous: A component containing at least two non-identical states. Ex: (AB)

or (AAB) or (AAAC) or (AABC). Note: A component is either homogeneous or

nonhomogeneous.

➢ Multiple: A component containing duplicate states. Ex: (AA) or (AAB) or (AAA) or

(AABB) or (AABC).

➢ Trivial vector: All components are singletons. Ex: (A)(B)(C) or (A)(A)(B) or (C)(C)(C).

➢ Homogeneous vector: All components are homogeneous. Ex: (AA)(BBB)(C) or

(AA)(B)(C) or (A)(B)(C) or (AA)(A)(B).

DEFINITONS




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Terminal node

• A node becomes a terminal if either:

1. The node is associated with an uncertainty vector whose non-

homogenous components are associated with the same node at preceding

levels

2. The node is associated with an uncertainty vector containing a

homogenous non-trivial component

3. The node is associated with a trivial uncertainty vector

VIDYA SAGAR P13




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The successor tree

➢ The successor tree for the machine M1 and an initial uncertainty (ABCD) is shown in

Fig.. It contains four levels numbered 0 through 3. Each branch is labeled with the

input symbol that it represents, and every node is associated with the corresponding

uncertainty vector. The highest node is associated with the initial uncertainty while the

nodes in level 1 are associated with its 1- and 0-successors, and so on

VIDYA SAGAR P14

PS x = 0 x = 1

A C/0 D/1

B C/0 A/1

C A/1 B/0

D B/0 C/1




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Homing experiment

Homing sequence: (ones and zeros that define the final states)An input is said to

homing sequence for a machine if the machine response to the sequence is always

sufficient to determine uniquely it’s final states

•Homing experiment: Apply input sequence + observe output sequence +Draw

conclusion about final state.

• Example : For machine M1, 0,1 defines the final state sequence for final state:

Initial state Response to 0,1 Final state

A 0,0 B

B 0,0 B

C 1,1 D

D 0,1 A

➢ Homing tree: its a truncated version of the successor tree.

VIDYA SAGAR P15

PS x = 0 x = 1

A C/0 D/1

B C/0 A/1

C A/1 B/0

D B/0 C/1




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Example

➢ For the following machine define the final state sequence for final state

VIDYA SAGAR P16

PS x = 0 x = 1

A B,0 D,0

B A,0 B,0

C D,1 A,0

D D,1 C,0




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Distinguishing experiment

• Distinguishing sequence: (ones and zeros that will lead to the initial states) An input

sequence which when applied to a machine will produce different output sequence for

each choice of initial state.

• Distinguishing experiment: (defines the initial state)Apply input sequence + observe

output sequence +Draw conclusion about initial state.

(from machine M1, 111 is a distinguishing sequence)

VIDYA SAGAR P17

Distinguishing tree: truncated version of successor tree




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Example

➢ For the following machine define distinguishing sequence

VIDYA SAGAR P18

PS x = 0 x = 1

A A,0 C,1

B B,0 D,1

C A,1 C,0

D D,0 B,0




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Example:

➢ For machine M2 shown below, find the shortest homing sequence and determine

whether or not a distinguishing sequence exist and if any do exist, find the shortest one

state table of machine M2

VIDYA SAGAR P19




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Solution (Successor tree)

➢ The shortest sequence is 010

• The machine has no distinguishing sequence

VIDYA SAGAR P20




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Synchronizing experiment& Synchronizing tree

➢ It defines the final state regardless of the output or the initial state

• Synchronizing sequence: ones and zeros that define the experiment

• Ex. The synchronizing tree for machine M2

VIDYA SAGAR P21




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Machine identification :

➢ The machine identification problem is essentially that of experimentally determining the

state table of an unknown machine. In its most general form, when no information is

available on the unknown machine, this problem cannot be solved for several reasons.

First, the experimenter must have complete information regarding the input alphabet of

the machine, since otherwise he or she can never be sure that the next input symbol will

not reveal new information regarding the machine.

➢ As an example, suppose that a machine is known to have two states and that its

response to input sequence X is output sequence Z, as shown below. Thus, the above

experiment is an identification experiment for a machine M3.

Time: t1 t2 t3 t4 t5 t6 t7 t8

Input, X: 1 1 1 0 1 0 1

Output, Z: 0 1 0 0 1 0 0

VIDYA SAGAR P22




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VIDYA SAGAR P23

suppose that, at the start of the experiment, the machine was in state A. The

application of an input symbol 1 results in an output symbol 0 and a transition that is

yet to be determined. However, since the second input symbol is also a 1 but the

response is 1, the machine must have been in a state other than A at t2. Hence, the

experimenter may conclude that at t2 the machine was in state B.

Since state A is the only state which responds to an input symbol 1 by producing an

output symbol 0, it is evident that at t3 the machine was in state A. At t4, it was again

in state B, since it has already been verified (at t2) that an input symbol 1 causes a

transition from state A to B. In a similar manner, it is easy to show that at t5 the

machine was again in state B, which, in turn, implies (see t3) that at t6, it was in state

A. Finally, at t7, it must have been in state A, since this is the only state in which the

machine produces a 0 output symbol as a response to a 1 input symbol.

Time: t1 t2 t3 t4 t5 t6 t7 t8

Input, X: 1 1 1 0 1 0 1

Output, Z: 0 1 0 0 1 0 0



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Transfer Tree

➢ It is often necessary to take the circuit into a predetermined state, after the homing

sequence has been applied. This is done with the help of a transfer sequence, which

is the shortest input sequence that takes a machine from state Si to state Sj .

➢ Example: for the following machine: we want to drive the machine from state B to

state C.

➢ Shortest path is the input sequence 00



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Designing checking Experiments

➢ The checking experiment can be divided into three phases:

1. Initialization phase. During the initialization phase, the circuit under test is taken

from an unknown initial state to a fixed state by the following method:

a. Apply a homing sequence to the circuit and identify the current state of the circuit.

b. If the current state is not the desired state, apply a transfer sequence to move the

circuit from the current state to the desired state.

2. State identification phase: During this phase, an input sequence is applied so as to

cause the circuit to visit each of its states and display its response to the distinguishing

sequence.

3. Transition verification phase. During this phase, the circuit is made to go through

every state transition; each state transition is checked by using the distinguishing

sequence.



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➢ First, we consider machines that possess at least one

distinguishing sequence. In subsequent sections, we shall relax

this restriction and discuss machines that have no

distinguishing sequence. Note that these experiments are

intended to detect the presence of one or more faults but will

not locate or diagnose them. We will make the assumption that

the machine either has a synchronizing sequence or a reset

input that can transfer it to the initial state.

VIDYA SAGAR P26




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Example

➢ Consider FSM

Successor Tree

(ABCD)

0

(BC)1(AB)0

1

(AD)1(AC)0

(B)1(A)0(AB)0

0 1

(D)1(A)0(D)1(C)0

Distinguishing

(BC)1(B)1(B)0

(A)1(C)0(AC)0

0 1

Therefore, sequence 01 is HS and DS



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Example (cont.)

1. Initialization phase:

Response Table

Init. State Response to 0 1 Final State Output Sequence

A B , 1 D ,1 D 1 1

B A , 0 C , 0 C 0 0

C B , 0 D , 1 D 0 1

D C , 1 A , 0 A 1 0



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Example (cont.)

2.Identification Phase:

Time

Input

State

Output

1 2 3 4 5 6 7 8 9 10 11

0 1 0 1 0 0 1 0 1 0 1

A D A B C D A

1 1 1 0 1 0 0 0 1 1 0



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Example (cont.)

3.Transition Verification Phase:

➢ Check transition from A to B with input 0,

then apply distinguishing sequence 01.

➢ Check transition from C to B with input 0 and

from C to A with input 1, and so on. The entire checking test

Input

State

Output

0 01 0 01 1 01 1 01 0 01 1 1 01 1 0 1 01 0 0 01 1

A B C B C A D A D C D A C D A B D A B A D A

1 00 0 00 0 11 1 11 1 01 1 0 01 1 1 1 10 1 0 11 1

All Possible Transitions



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5/1/202031


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