Fault Isolation and Diagnosis Techniques for Mixed - Signal Circuits

7/30/2019 Fault Isolation and Diagnosis Techniques for Mixed - Signal Circuits

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Fault Isolation and Diagnosis Techniques for

Mixed-Signal Circuits

A ThesisPresented to

The Academic Faculty

By

Sasikumar Cherubal

In Partial Fulfillment

of the Requirements for the Degree of

Doctor of Philosophy in Electrical and Computer Engineering

School of Electrical and Computer Engineering

Georgia Institute of Technology

April 2002

Copyright 2002 by Sasikumar Cherubal


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Fault Isolation and Diagnosis Techniques for

Mixed-Signal Circuits

Approved:

^ ~~\

Dr. Abhijit Chatterje$ Chairman Dr. David E. Schimmel

. /7

Dr. 0o\? Laskar Dr./Ze/freTA. bav^T

V T-

Dr. Umaki shore Ramachandran

Date Approved L^lo- aoo^


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Acknowledgments

I would like to express my deepest gratitude to Professor Abhijit Chatterjee for being

the advisor to my research. His constant support, passionate enthusiasm and motivating

guidance have been invaluable during the course of my doctoral studies. His knowledge

and insight in a wide variety of subjects, as well as his philosophies on research and life,

have helped me become a better researcher.

Thanks are also due to Professors David E. Schimmel, Joy Laskar, Jeffrey A. Davis

and Umakishore Ramachandran for serving on my dissertation committee. Their insight

ful suggestions and have led to a number of improvements in this research. I am also

indebted to all the professors at Georgia Tech and Indian Institute of Technology, Chen-

nai, who have taught me everything I know in the field of Electrical and Computer Engi

neering.

I would also like to thank Nash Khouzam of National Semiconductor for giving me

the opportunity to interact with the best minds in this field of research.

My friends have always been there to support me through all the good and the hard

times. I would like to thank all my office mates: Pramod, Pankaj, Junwei, Rajesh, Ramki,

Alfred, Xiangdong and Andy. A special thanks is due to Pramod who helped me with

admission into the graduate school at Georgia Tech, and became my mentor during my

time here. My friends from my previous schools, Ajay, Srikrishna and Damu have pro

vided much-needed encouragement and support over the last few years. I would also like

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to thank my ex-roommates Ramana Rao, Vijay and Ramanarayanan for being the best

roomies in town.

Above all, the encouragement and support of my family have made the pursuit of my

Ph.D possible. My parents and my elder brother Ravi, who would be very proud today,

have always been there for me in every walk of my life.

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Table of Contents

ACKNOWLEDGMENTS . I

TABLE OF CONTENTS , Ill

LIST OF FIGURES ,. IX

LIST OF TABLES XIV

SUMMARY XV

ACRONYMS AND VARIABLE NAMES XVI

I. INTRODUCTION 1

1.1 Motivation 1

1.2 State-of-the-Art in Test and Diagnosis of Mixed-Signal Circuits 3

1.2.1 Production Testing of Analog and Mixed-Signal Circuits 3

1.2.2 Fault Isolation and Diagnosis in Analog and Mixed-Signal Circuits 3

1.2.3 Yield Analysis and Yield Management for lCs 5

1.3 Limitations of Current Diagnosis Methodologies 5

1.4 Contributions of Dissertation 7

1.5 Dissertation Overview. 8

II. PARAMETRIC FAULT DIAGNOSIS FOR ANALOG CIRCUITS 10

2.1 Previous Work 10

2.2 Overview 11

2.3 Robust Diagnosability Conditions for Analog Circuits 13

2.3.1 Classical Diagnosability Analysis 13

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2.3.2 Diagnosability Analysis 15

2.3.3 Ambiguity Groups and Diagnosability 19

2.4 Measurement Selection for Diagnosis 20

2.4.1 Node and Signal Selection 22

2.4.2 Augmenting the Measurement Set 24

2.5 Regression Model Construction... 25

2.6 Diagnosis Procedure 26

2.6.1 Dependent Input Variables 27

2.6.2 Convergence of N-R 28

2.6.3 On-line Computation Requirements 30

2.7 Results 30

2.7.1 On-line Computational Requirements 34

2.8 Summary 34

III. AUTOMATIC TEST GENERATION FOR DIAGNOSIS IN ANALOG CIR

CUITS 35

3.1 Previous Work 35

3.2 Overview 37

3.3 Comparing Tests for Diagnostic Ability 39

3.3.1 Test Cost Description... 40

3.4 Genetic Algorithms for Test Optimization 41

3.5 Results 43

3.5.1 Results ITC Test BenchMark Opamp.. 45

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3.5.2 Results for a Low-Voltage Power Amplifier 49

3.6 Summary 51

IV. PROCESS PARAMETER DIAGNOSIS FOR ANALOG ICS 53

4.1 Introduction 53

4.2 Semiconductor Manufacturing and Testing 54

4.2.1 Yield loss in Analog and Mixed-Signal ICs 55

4.2.2 Current Yield Management Methodologies 56

4.2.2.1 Design for Manufacturability Methods 57

4.2.2.2 Yield Diagnosis Techniques 57

4.3 Limitations of Current Methods 59

4.4 Proposed Approach 60

4.5 Semiconductor Process Modeling 63

4.5.1 Modeling Mismatches Using Independent Variables 65

4.5.2 Finding Significant Device Parameters 68

4.6 Cause-Effect Analysis 68

4.7 Results 69

4.7.1 ITC Benchmark Opamp 70

4.7.2 Power Amplifier 73

4.7.3 Low-Power CMOS Opamp 75

4.8 Summary 83

V. OPTIMAL LINEARITY TESTING OF ANALOG-TO-DIGITAL CONVERT

ERS 85

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5.1 Introduction 85

5.2 Review of Techniques for Estimation INL and DNL 87

5.2.1 Servo-loop Technique for Measuring Linearity Metrics 88

5.2.2 Linearity Estimates Using Histogram Techniques 89

5.2.3 Use of Linear Models in ADC Testing 90

5.3 Overview 92

5.4 Improved estimation Linearity 94

5.4.1 Test Length Selection 97

5.5 Methodology for Predicting Variance of Measurement Error in CT Estimates ....98

5.5.1 Computation of oeyfo r Ramp Signal 103

5.5.2 Computation of c^for Sine Wave Input Signal 104

5.6 Practical Considerations 104

5.7 Results 106

5.7.1 Verification ofseg Estimates via Simulation 106

5.7.2 Selection of Test Length 110

5.7.3 Test Set-up 112

5.7.4 Hardware Measurements for a Linear ramp input signal 113

5.7.5 Simulation Results for a Sine Wave Input Signal 116

5.8 Summary 117

VI. HIERARCHICAL FAULT ISOLATION FOR ANALOG AND MIXED-SIG

NAL BOARDS 118

6.1 Overview 118

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6.2 Automated hierarchical circuit partitioning 121

6.2.1 Hypergraph modeling of CUT and hierarchical partitioning 122

6.2.2 Effects of Loading 123

6.3 Regression Model Construction 125

6.4 Hierarchical fault Isolation 127

6.4.1 Tolerance Effects 128

6.5 Results 128

6.5.1 State variable Filter 129

6.5.2 Leapfrog Filter 130

6.5.3 PLL based FM demodulator 131

6.5.4 Results for fault isolation 131

6.6 Summary 132

VII. FAULT SIMULATION AND FAULT ISOLATION FOR MIXED-SIGNAL ICS

USING ERROR WAVEFORMS 133

7.1 Introduction 133

7.2 Overview 137

7.3 Fault Models 139

7.4 Fault Effect Characterization and Fault Clustering 140

7.4.1 Fault Syndrome Extraction Using LPC 140

7.4.2 Fault Syndrome Clustering 141

7.5 Case Study 142

7.5.1 Results 144

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7.6 Fault Isolation 146

7.6.1 Effects of Tolerances. 146

7.6.2 Nearest Neighbor Approach 147

7.6.3 Failures in ADC 148

7.7 Case Study 2: Charge-Pump PLL 149

7.8 Summary 151

VIII. CONCLUSIONS AND FUTURE WORK 152

8.1 Future Work 153

REFERENCES I

VITAE I

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List of Figures

Figure 1.1 Applications of Diagnosis 2

Figure 2.1 Overview of fault diagnosis methodology 12

Figure 2.2 Illustrating the Effect of Measurement Noise 14

Figure 2.3 State Variable Filter 21

Figure 2.4 Measurement Selection Methodology 22

Figure 2.5 Overview of diagnosis procedure 27

Figure 2.6 Leap-Frog Filter 30

Figure 2.7 8-bit Ladder Digital -to-Anal og Converter 31

Figure 2.8 Prototype of Leapfrog filter 32

Figure 3.1 Overview of Test Generation Methodology 37

Figure 3.2 Automatic Test Generation 38

Figure 3.3 Successive Approximation GA 44

Figure 3.4 MiST Benchmark opamp 45

Figure 3.5 Test Configuration for CMOS opamp 46

Figure 3.6 Optimized test and Response for CMOS opamp 46

Figure 3.7 Comparison of Simulated and Computed Device Parameters for CMOS

opamp 48

Figure 3.8 LM386 Low-Voltage Power Amplifier 49

Figure 3.9 Diagnostic Test Configuration for LM386 50

Figure 3.10 Test Stimuli for the LM386 50

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Figure 3.11 Response of LM386 to Diagnostic Tests 51

Figure 3.12 Diagnosis Results for the LM386 Power Amplifier 52

Figure 4.1 Semiconductor Manufacturing and Test 54

Figure 4.2 Yield Loss in ICs 56

Figure 4.3 DfM Methodologies 57

Figure 4.4 Yield Management Methodologies 58

Figure 4.5 Model for IC Manufacturing Process 60

Figure 4.6 Overview of Diagnosis Methodology..... 61

Figure 4.7 Process Modeling Methodology 65

Figure 4.8 Simple Sub-circuits to Illustrate the Modeling process 67

Figure 4.9 Effect of change in Device Parameters on Opamp Performance Parameters

71

Figure 4.10 Cause Effect Analysis of Slew Rate for Opamp 71

Figure 4.11 Cause Effect Analysis of PSRR for Opamp 72

Figure 4.12 Cause Effect Analysis of Supply Current for Opamp 72

Figure 4.13 Cause Effect Analysis of Large Signal Gain for Opamp 73

Figure 4.14 Normal and Modified Specifications for LM386 74

Figure 4.15 Cause-Effect Analysis of Low-Frequency Gain for LM386 74

Figure 4.16 Cause-Effect Analysis of High-Frequency Gain for LM386 75

Figure 4.17 Cause-Effect Analysis of Supply Current for LM386 75

Figure 4.18 Cause-Effect Analysis ofTHD for LM386 76

Figure 4.19 Test Configuration for Opamp 76

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Figure 4.20 Stimuli and Opamp Response for Common-Mode Stimuli 77

Figure 4.21 Stimuli and Opamp Response for Power Supply Stimuli 77

Figure 4.22 Stimuli and Opamp Response for Combination of Common-Mode and

Differential-Mode Stimuli 78

Figure 4.23 Correlation Coefficients Between Simulated and Diagnosed Parameters.78

Figure 4.24 Specification Distributions for Operational Amplifier 80

Figure 4.25 Cause-Effect Analysis of CMRR for Low-Power Opamp 81

Figure 4.26 Cause-Effect Analysis of Vos for Low-Power CMOS Opamp 81

Figure 4.27 Cause Effect Analysis of PSRR for CMOS Opamp 82

Figure 4.28 Cause-Effect Analysis of Supply Current for CMOS Opamp 82

Figure 4.29 Cause-Effect Analysis for Gain for CMOS Opamp 83

Figure 4.30 Cause-Effect Analysis of Voltage Swing for CMOS Opamp 83

Figure 4.31 Cause-Effect Analysis of Slew Rate for CMOS Opamp 84

Figure 5.1 Proposed ADC Test Strategy 94

Figure 5.2 Model for Computing oey 99

Figure 5.3 Output of ADC in Response to Linear Ramp Input 100

Figure 5.4 Errors in Histogram 101

Figure 5.5 Simulation Model for ADCs 107

Figure 5.6 Comparison of Theoretical and Simulated aey for a Ramp Signal 107

Figure 5.7 Comparison of Error in oey forProposed Approach vs. Earlier Approaches

[89] 108

Figure 5.8 Comparison of Theoretical and Simulated cey fora Sine Wave Signal ..108

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Figure 5.9 Comparison of Theoretical and Simulated w.c Geyfor Sine Wave Signal

109

Figure 5.10 Variation in cey vs. Test Length for a Ramp Signal 110

Figure 5.11 Variation in cey\s. Test Length for a Sine Wave Signal Il l

Figure 5.12 Experimental Set-up for ADC Measurements 112

Figure 5.13 Comparison of Predicted and TRUE INL for a Ramp Input 113

Figure 5.14 Comparison of Predicted and TRUE DNL for a Ramp Input 114

Figure 5.15 R.M.S Error in INL and DNL 114

Figure 5.16 Error in Peak INL and DNL 115

Figure 5.17 Comparison of Measured and TRUE INL for a Sine Wave Input 116

Figure 5.18 Comparison of Measured and TRUE DNL for a Sine Wave Input 116

Figure 5.19 R.M.S and Error in Peak of Estimated INL and DNL 117

Figure 6.1 Overview of fault isolation technique..... 119

Figure 6.2 Hierarchical Circuit Partitions 120

Figure 6.3 A simple Circuit and its hypergraph representation 122

Figure 6.4 Hypergraph partitioning 122

Figure 6.5 Example circuits to illustrate the effects of loading..... 124

Figure 6.6 Methodology for building regression functions 126

Figure 6.7 Hierarchical Partitions for State Variable filter 129

Figure 6.8 Hierarchical Partitions for leapfrog filter 130

Figure 6.9 PLL based FM demodulator 131

Figure 6.10 Hierarchical Partitions for PLL based FM demodulator 132

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Figure 7.1 Representation of fault effects using error waveforms 137

Figure 7.2 Fault Simulation methodology 138

Figure 7.3 Example circuit 142

Figure 7.4 (a)Anti-Aliasing Filter (b) A/D converter and (c) Digital Filter 143

Figure 7.5 (a)Fault-free response ofsystem, (b) FFT of Fault-free response 143

Figure 7.6 Error waveforms for (a) Biq Filter (b) A/D converter and (c) Digital filter..

144

Figure 7.7 Fault Syndromes for (a) Biquad filter and (b) A/D Converter 145

Figure 7.8 Fault syndromes for digital filter 145

Figure 7.9 Analog/digital partitioning for the A/D converter 148

Figure 7.10 Charge-pump PLL 149

Figure 7.11 Sub-circuits of PLL (a) VCO (b) Charge Pump and (c) Phase Detector. 149

Figure 7.12 Fault-free output of PLL 150

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List of Tables

Table 0.1 Acronyms Used xvi

Table 0.2 Variable Naming Conventions in Equations xvi

Table 2.1 Parameters of the three circuits 31

Table 2. 2: Accessible Nodes and Test Signals for the three Circuits 31

Table 2. 3: Nodes and Test Signals Chosen 32

Table 2. 4: Diagnosis Results 33

Table 2. 5: CPU time Required for diagnosis 34

Table 3.1 Device parameters for CMOS opamp 45

Table 3. 2: Device parameters of LM386 49

Table 6.1 Results for fault isolation. 132

Table 7.1 Results for fault clustering 146

Table 7. 2: Fault diagnosis using nearest neighbor for example circuit 148

Table 7. 3: Fault Clustering results for PLL 150

Table 7. 4: Fault isolation using nearest neighbor for PLL 151

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Summary

Algorithms for the diagnosis of parametric faults in analog and mixed-signal circuits

were proposed. The effects of measurement noise and other inaccuracies that accompany

analog measurements, on the accuracy of the diagnosed parameters, was analyzed. A

methodology for approximating the relationship between the circuit parameters to be diag

nosed and the measurements made on the circuit, using nonlinear regression techniques,

was proposed. This results in significant reduction in the computational work required for

diagnosis. In cases that complete diagnosis was not possible, a procedure to generate opti

mized tests to aid diagnosis was proposed. The test generation methodology explicitly

accounts for the effects of measurement noise for robust test generation. The algorithms

for diagnosis and test generation were applied to the problem of diagnosing the causes of

parametric yield loss in analog integrated circuit manufacturing. The algorithms were also

applied to reducing the production test time for analog-to-digital converters.

To extend the proposed algorithms to larger systems, two heuristic-based approaches

were explored. A methodology to model the fault-free behavior of parts of the circuit, to

isolate faults, was proposed. Methods to model fault effects in mixed-signal systems using

error waveforms were also proposed for isolating faults to either the digital or the analog

portion of a mixed-signal circuit. Experimental results to verify the methods are presented

and avenues for future research are discussed.

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Acronyms and Variable Names

Table 0.1: Acronyms Used

Acronym Expansion

ADC Analog-to-Digital Converter

BIST Built-In-Self-Test

CMRR Common-Mode-Rejection-Ratio

CMOS Complimentary Metal Oxide Semiconductor

CUT Circuit-Under-Test

DfM Design-for-Manufacturability

DfT Design-for-TestabiJity

DNL Differential Non-linearity

DUT Device-Under-Test

ET Electrical Test

FV Fault Verification

GA Genetic Algorithm

IC Integrated Circuit

INL Integral Non-linearity

MARS Multivariate Adaptive Regression Spline

PI Parameter Identification

PLL Phase-Locked Loop

PSRR Power-Supply-Rejection-RatioPWB Printed Wiring Board

SAT Simulation-After-Test

SBT Simulation-Before-Test

SoC System-on-Chip

SVD Singular Value Decomposition

Table 0.2: Variable Naming Conventions in Equations

Naming Convention Meaning

Italics (a, b) Scalar

Italics, bold, over-line {a, b) Vector

Bold (A, B) Matrix

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CHAPTER I

INTRODUCTION

Electronic systems with computational, multi-media and communication capabilities

are driving today's consumer electronics market. These systems require both digital and

analog functionality. Shrinking device geometries and advances in design methodologies

have made possible the integration of whole systems, once manufactured as discrete com

ponents, onto a single chip. These mixed-signal System-on-Chips (SoCs) enjoy price

advantages over systems manufactured using discrete components.

The increasing complexity of electronic systems, along with the growing need for

tighter quality control, has created significant challenges in testing these systems. A par

ticularly vexing problem is the finding or diagnosing the cause(s) of failure of circuits, as

low yields in manufacturing can lead to high cost of manufactured parts.The need for

diagnosis algorithms in the design and manufacture of analog and mixed-signal circuits is

explained in the next section.

1.1 Motivation

It is often necessary to find the cause of failures in mixed-signal systems for design

debug, repair, or to tune the manufacturing process for improving yield. The typical pro-

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cess in creating an electronic circuit is shown in Figure 1.1. An electronic circuit under

goes testing during the design-prototype phase and during manufacturing before being

shipped, where it is tested to determine whether the circuit meets its performance specifi

cations. Typical performance specifications for an analog or mixed-signal circuit are gain

and bandwidth of an amplifier, total harmonic distortion for an Analog to Digital Con

verter (ADC), etc. During the prototype phase, if the circuit fails to meet its performance

specifications, it is necessary to find the causes of failure in order to change the design or

the prototype, to ensure correct operation of the circuit. During manufacturing test, if the

causes of failure of a product can be easily found, the information can be used for repair,

or to tune the design or the manufacturing process in order to improve yield.

^>Design t

Change Design

Prototype Test

Diagnose

rManufacture

r

Tune Process

Tune Design

Figure 1.1 Applications of Diagnosis

Test

cd

a

Diagnose

The remainder of this chapter is organized as follows. The state-of-the-art in test and

diagnosis of analog and mixed-signal circuits is presented in Section 1.2. The limitations

of current approaches are explained in Section 1.3. A summary of the contributions of the

research described in this thesis is presented in Section 1.4. An overview of the remainder

of this thesis is presented in Section 1.5.

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1.2 State-of-the-Art in Test and Diagnosis of Mixed-Signal

Circuits

In this section, the state-of the art in analog and mixed-signal test and diagnosis is

described. In Section 1.2.1, the production testing of analog and mixed-signal circuits is

examined. In Section 1.2.2, the techniques used for diagnosis of analog and mixed-signal

circuits, proposed in the literature, are discussed. In Section 1.2.3, an important applica

tion of diagnosis, i.e. methodologies for diagnosing the cause of yield loss in semiconduc

tor Integrated Circuits (ICs), is described in detail.

1.2.1 Production Testing of Analog and Mixed-Signal CircuitsEvery analog/mixed-signal electronic system is defined by a set ofperformance param

eters, such as gain and bandwidth of an amplifier. These performance parameters are

defined by (i) customer requirements, (ii) product differentiation needs and/or (iii)

requirements for standard compliance. During production testing of these systems, these

performance parameters are measured (fully or partially) and tested against defined limits,

called specifications. This process is known as specification testing.

1.2.2 Faul t Isolation and Diagnos is in Ana log and Mixe d-S ignal Circuits

Fault isolation and diagnosis techniques are concerned with the problem of finding the

cause of failure of an electronic circuit. Fault isolation is defined as the process of finding

a failed part in an electronic circuit, while fault diagnosis is defined as the process of find

ing the values of failed parameters or the root cause(s) of failures. Failures in analog and

mixed-signal circuits can been classified into two: (i) catastrophic faults and (ii) paramet

ric faults. Catastrophic faults cause complete loss of functionality of the circuit. Cata-

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strophic faults are often described in terms of open-circuit or short-circuit failures.

Parametric faults cause a degradation in the performance of the circuit. The performance

of a circuit is controlled by a set of circuit parameters, such as values of resistors and

capacitors in a discrete circuit, or a set of process parameters for an IC. Parametric faults

are represented by the variations in these circuit parameters.

Fault isolation and diagnosis for analog circuits have been investigated extensively in

the past. Bandler and Salama [1-2] and R. W. Liu [3-4] have given a review of the early

work on fault isolation and diagnosis for analog circuits. Existing approaches to fault iso

lation and diagnosis can be divided into two classes- (i) Simulation Before Test (SBT) and

(ii) Simulation After Test (SAT). SBT [21-28] approaches are based on the principle of

building a fault dictionary'-i.e. a list of all possible faulty behaviors of the circuit. The

behavior of the Circuit-Under-Test (CUT) is compared against a catalog of faulty

responses of the CUT, stored in the fault dictionary. The fault condition whose response

matches most closely with the observed response is picked as the diagnosed fault. SBT

techniques classify discrete faults and usually perform fault isolation, i.e. they identify the

failed part of the circuit.

SAT techniques perform circuit simulations after obtaining measurements from the

CUT, for fault isolation and diagnosis. SAT techniques are further classified into Parame

ter Identification (PI) techniques and Fault Verification (FV) techniques. PI techniques [5-

16] explicitly solve for the values of internal parameters of the CUT from a set of mea

surements on the CUT using on-line circuit simulations. PI techniques are able to diagnose

faults caused by the variation in multiple circuit parameters, since they solve for all the

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parameters of the CUT. PI techniques identify all the parameter values of the CUT, i.e they

perform fault diagnosis. FV techniques [17-20] check constraints (Kirchoff's current and

voltage law, for example) that must be satisfied by the fault-free circuit to isolate faults.

FV techniques identify faulty parts ofthe CUT, i.e they perform fault isolation.

1.2.3 Yield Analysis and Yield Management for ICs

Semiconductor IC manufacturing is one of the most important areas in the electronics

industry. The increasing requirements of quality control and intense price pressures have

fuelled a large amount of research on the problem of achieving and maintaining high

yields in the manufacture ofICs. Yield is defined as the ratio of the number of functional

ICs to the total number of ICs manufactured. ICs are manufactured in semiconductor

wafers which contain hundreds or even thousands ofICs. These wafers contain special test

sites which are used to monitor the parameters of the manufacturing process (Electrical

Test or ET parameters). Yield analysis and management tools [34-46] try to improve yield

by relating the parameters measured on these test sites to the yield obtained on the wafer

using advanced statistical techniques.

1.3 Limitations of Current Diagnosis Methodologies

Currently, ICs are tested for their functionality by measuring their performance parame

ters, as described in Section 1.2.1. The chief limitations of current methodologies for test

and diagnosis of analog and mixed-signal circuits are:

1. Specification tests are expensive in terms of test time and test equipment. This has

caused the test costs of mixed-signal circuits to become increasingly large in proportion

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to the of the total manufacturing cost of these circuits. Also, specification testing does

not give information about the cause of failure of the circuit being tested.

2. There exist no techniques to automatically generate optimized tests to aid diagnosis.

Most fault isolation and diagnosis tools assume that a set of measurements to be made

on the CUT are known. Chakrabarti and Chatterjee [93-94] have presented a method to

automatically generate tests for distinguishing the effects of faults caused by the varia

tion in a single circuit parameter, but the problem of generating tests for fault diagnosis

for faults caused by multiple parameter variations remains unsolved.

3. There exist no systematic methodology to separate failures caused by faults in the ana

log and digital portions ofa mixed-signal IC. Most techniques available concentrate on

the problems of isolating faults in either analog or digital systems. The problem of

mixed-signal fault isolation is becoming increasingly important with increasing frac

tions of electronic systems having mixed-signal content.

4. Current yield management methodologies concentrate on correlating yield loss with ET

measurements. However, ET measurements do not give complete information about

the causes of yield loss. Often, yield loss is caused by the interaction between many

process parameters, resulting in the yield loss being uncorrected with any particular

ET measurement. Also, estimating correlations between yield loss and ET measure

ments requires data from a large number of wafers. This implies that a large number of

low-yield wafers have to be processed before the cause of failures can be diagnosed and

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1.4 Contributions of Dissertation

The contributions of the proposed research in the areas of test and diagnosis of analog

and mixed signal systems are summarized below:

1. A methodology has been developed to identify the values of parameters that control a

circuit performance, from measurements made on the circuit, in the presence of mea

surement noise. Conditions to be met by a set of measurements made on the CUT, for

the accurate computation of circuit parameters, are derived.

2. A technique to automatically optimize test stimuli for analog circuits, in order to facili

tate the diagnosis of parameter values, has been developed. The methodology uses sto

chastic optimization techniques to search large, multidimensional waveform spaces to

obtain optimal tests to aid fault diagnosis.

3. The diagnosis techniques developed in this thesis have been applied to the problem of

diagnosing causes of yield loss in analog and mixed-signal ICs. The application of

these methodologies will result in faster yield ramps for analog and mixed-signal ICs,

resulting in faster time-to-volume production. It can also be applied to improve manu

facturing yields in mixed-signal ICs currently in production.

4. The diagnosis methodology has been applied to the test time reduction for ADCs,

resulting in a reduction of one order of magnitude in test time. For example, the appli

cation of the technique to a commercial ADC from National Semiconductor Corpora

tion resulted in a test time reduction from 1.1 seconds to 130 milliseconds.

5. A technique for isolating the failed parts in analog and mixed-signal printed-wiring

boards (PWBs) has been developed. The method allows for arbitrary, multiple paramet-

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ric variations in parts of the circuit being tested and is robust under the tolerances of

analog components and measurement noise.

6. Methodologies for fault isolation in mixed-signal circuits have been developed, which

enable the extension of the diagnosis techniques to larger systems. These methodolo

gies can be used for rinding whether the analog or the digital part of the CUT is faulty,

prior to applying specialized techniques for fault isolation or diagnosis for the analog or

the digital part of the CUT.

1.5 Dissertation Overview

The primary objective of this research is to find comprehensive diagnosis methodolo

gies for analog and mixed-signal circuits. The methods presented in this dissertation are

focused on the problem of diagnosing faults caused by multiple parameter variations in

analog and mixed-signal circuits.

In Chapter II, the mathematical foundations of the proposed diagnosis methodology are

presented. Conditions for the diagnosability of an analog circuit, in the presence of mea

surement noise, are derived and the effects of measurement noise and modeling accuracy

on the accuracy values of diagnosed circuit parameters is computed. In many analog ICs

the set of performance specification tests area not sufficient to accurately diagnose the

parameters of the circuit. In Chapter III, the methodology for generation of optimized tests

to aid diagnosis is presented. Again, the technique presented emphasizes robust fault diag

nosis in the presence of measurement noise and other impairments that accompany analog

measurements.

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In Chapter IV, the diagnosis methodologies are applied to the problem of diagnosing

the causes of parametric yield loss in analog ICs. A method to compute the contributions

of each process parameter to the variation in performance parameters of analog ICs in the

presence of changes in process statistics, is presented. In Chapter V, the diagnosis method

ology is applied to the linearity testing of ADCs. The methodology is shown to be superior

to currently available techniques and has been verified using hardware measurements on a

commercially available IC.

Extension of the diagnosis methodology to analog and mixed-signal boards is presented

in Chapter VI. A method to isolate the faulty pars of a Printed-Wiring-Board (PWB) using

steady-state voltage measurements on the internal nodes of the CUT, is presented.

A fault isolation technique, that determines whether the digital or the analog portion of

a mixed-signal circuit is faulty, is discussed in Chapter VII. Finally, Chapter VIII presents

conclusions and recommends avenues for future research.

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CHAPTER II

PARAMETRIC FAULT DIAGNOSIS FOR ANALOG

CIRCUITS

In this chapter, the conditions for diagnosability of a circuit parameters from a set of

measurements made on the circuit are derived and a fault diagnosis algorithm for paramet

ric faults in analog circuits is described.

2.1 Previous Work

As noted in Section 1.2.2, diagnosis methodologies, proposed in the literature can be

classified into Simulation-Before-Test (SBT) and Simulation-After-Test (SAT) methodol

ogies. SBT techniques [21-27] use pattern matching algorithms to classify faults into one

of the fault classes stored in a. fault dictionary (a list of all classes of faulty behavior, cre

ated through simulation). These techniques have been applied mainly to discrete, cata

strophic faults. Chatterjee et. al [26-28] have developed an SBT approach for parametric

faults using a fault sampling approach, but the technique is limited to parametric failures

caused by single parameter variations. Parameter identification (PI) [5-16] techniques

have been used for the diagnosis of multiple parameter failures in analog circuits. How

ever, PI techniques simulate the Circuit-Under-Test CUT repeatedly, after obtaining mea-

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surements from it, for fault diagnosis. This computational complexity has limited the

application of PI techniques to linear circuits and small, non-linear circuits. Another

important limitation of the methods proposed in the literature is that the effect of measure

ment noise, which can lead to errors in the diagnosed circuit parameters, is not considered

in the diagnosis process.

2.2 Overview

As noted in Section 2.1, the major obstacle in the extension of PI techniques to large

analog circuits is the need to perform circuit simulations based on measurement data. It is

proposed to build a nonlinear regression model to approximate the functional relationship

between parameters of the CUT and measurements made on it, which is denoted by

fpm(P) -The regression model is given by

fPm(P) = m pemap me


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The proposed methodology can be seen as a 'Pi-like' technique in which time consum

ing circuit simulation has been replaced by a simple evaluation of the regression model.

This means that the proposed technique can be used to diagnose large analog circuits

where simulation complexity makes conventional PI methods difficult to apply. Since all

the circuit parameters are solved for, in the proposed methodology, faults caused by varia

tion in multiple circuit parameters can be diagnosed. Also, like PI techniques, The pro

posed methodology is immune to fault masking due to tolerances of analog parameters.

An overview of the proposed methodology is shown in Figure 2.1. Given (i) a netlist of

Off-line Computations Diagnosis Procedure

CUT Netlist,Accessible Nodes,

Specifications

Circuit-Under-Test

VSelect Nodes &

SpecificationsSelected

MakeMeasurements

Regression Modelsfor Selected

Measurements

Measurements

Regression

Iterative Soln of

ifpmiP) = c)

Models DiagnosedParameter Set

Figure 2.1 Overview of fault diagnosis methodology

the CUT (simulation model), (ii) a list of all accessible nodes and (iii) tests to be applied

on the CUT, algorithms are proposed to assess the accuracy of the diagnosed parameters

in the presence of measurement noise. Then, a set of measurements that minimizes the test

time and the number of internal nodes accessed, without compromising diagnostic accu

racy, is chosen from the given set of measurements. Then, regression models are built

relating the parameters of the CUT to the selected measurements. During test, the selected

i:?.


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measurements are made on the CUT and values of the parameters of the CUT are com

puted that satisfy (2.2), using iterative numerical techniques.

The remainder ofthis chapter is organized as follows. In Section 2.3, conditions for the

parameters of an analog circuit to be diagnosable (i.e. the circuit parameters can be com

puted accurately from the given set of measurements), in the presence of measurement

noise and other modeling impairments, are derived. In Section 2.4, the procedure for

selecting a minimal set of measurements while ensuring diagnosability, is presented. In

Section 2.5, the procedure for building the non-linear regression model, given in (2.2), is

described. The numerical methods used for diagnosis are discussed in detail in Section 2.6

and experimental results are presented in Section 2.7.

2.3 Robust Diagnosability Conditions for Analog Circuits

In the proposed methodology, sensitivity-based heuristics are used to check if the circuit

parameters can be accurately computed from the set of measurements for the given circuit.

In Section 2.3.1, the classical methods for diagnosability analysis, proposed in the litera

ture are discussed and their limitations are analyzed. In Section 2.3.2, the conditions for

the accurate computation of device parameters from measurements made on a circuit, in

the presence of measurement noise, are described.

2.3.1 Classical Diagnosability Analysis

Classical diagnosability analysis has relied on computing the rank of the sensitivity

matrix, that relates the parameters to the changes in measurement values. Visvanathan and

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Vincentelli [56] have shown that the number of parameters of a circuit that can be

uniquely solved for, from a set of measurements made on the circuit is given by

nd = rank(S)

where S is the sensitivity matrix given by

(2.3)

S =

dm ]

dp{

dm2

dpx

dm

P\

P\

P\

dm{

dp2

dm2

dp2

dm

Pi

Pi

dm^

Kp">

dm7

' dPn

dm,Pn,

(2.4)

dp{rx

dp22

' ' dpnp

The rank of a matrix is given by the number of its non-zero singular values. However,

the parameters cannot often be computed accurately even though the condition in (2.3) is

satisfied, due to the effects ofmeasurement noise and modeling inaccuracies. Each mea-

A

\ """" 7/

: A P I :r*= =*"!

>

(b)

Figure 2.2 Illustrating the Effect of Measurement Noise

surement made on an analog circuit can be seen as an equation in the multi-dimensional

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parameter space, which is an (np - 1) dimensional surface in the parameter space. The

rows of the sensitivity matrix represent the normals to these surfaces. A rank-deficient

sensitivity matrix would result in the normals to the surfaces being linearly dependent.

The effect of measurement noise on the accuracy of diagnosed parameters is illustrated for

a two dimensional parameter space with two measurements in Figure 2.2(a) and

Figure 2.2(b). The two lines represent two measurements made on the CUT and the gray

areas around the lines represent an uncertainty in the measurements due to noise. The

intervals marked Apj and Ap2 in the two figures represent the uncertainty in diagnosed

parameters due to measurement noise. The two sets of measurements illustrated in

Figure 2.2(a) and Figure 2.2(b) satisfy the condition of diagnosability given by (2.3), but

they show widely varying effects on the accuracy of the diagnosed parameters. It is seen

that the parameters are diagnosed accurately in the system of Figure 2.2(a), but there can

be a large error in the values of diagnosed parameters in Figure 2.2(b), depending on the

value of measurement noise. The effect of measurement noise on the accuracy of diag

nosed parameters is quantitatively analyzed in Section 2.3.2.

2.3.2 Diagnosability Analysis

The effect of measurement noise on the accuracy of diagnosed parameters is analyzed

below. The analysis technique relates the standard deviation in the diagnosed parameter

values to the standard deviation in measurement noise in each of the measurements. For

this purpose, it is found to be more convenient to use a different normalization for the sen

sitivity matrix than the one given in (2.4). The normalized sensitivity matrix is given by

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s =

dml

dm,

a.

dml

3/?2

dm2

dp2

3m,

ap2

aP2

o

3m,

5vmi-

^ .

3m,

3 P l " 3/>2 " 3/^V2 a,

(2.5)

;thwhere a represents the standard deviation of the variation in the i parameter/?/.

Pi

Let each ofthe measurements in in be affected by measurement noise em having a vari-

2

ance ofcm. If different measurements have different variances in measurement noise, the

measurements can be normalized, so that they all have the same variance in measurement

noise. In the presence of noise (2.1) becomes

^0 + Am + em=f(p0 + Ap) (2.6)

where m0 and p0 are the nominal values of measurements and parameters respectively.

Assuming that the measurement noise and the change in measurements from the nominal

are small, the function ftp) can be approximated by a linear function about p0 to get

~f(p0 + Ap) =f(p0) + S ^ . Using the fact that ~m0 =}(p0), (2.7) is obtained.

- Am + e. (2.7)a,

Here, Ap is the computed(or diagnosed) change in parameters which is different from

the true change in parameters, which is denoted by Apt. The effect of measurement noise

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on the accuracy of the diagnosed parameters can be analyzed using the Singular Value

Decomposition (SVD) [126] of S. SVD decomposes a matrix into the product of3 matri

ces as

S = U X VT (2.8)

T T

where U and V are orthonormal matrices (U U = I , V V = I where I is the

identity matrix) and X is a diagonal matrix with decreasing positive diagonal elements.

Using (2.8) and the orthonormal property of U and V, the following equation is obtained

for the diagnosed parameters.

& = V X l UT (Am + em) = V Sl

(Am} + e}m) (2.9)

P

T T

where Am' = U Am and e'm = U em. Since U is orthonormal, it can be shown

2

that the variance ofe}m is


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where V] and V2 are the first {np - nn) and the last nn columns of the matrix V, respec

tively, and Xj is the square, diagonal matrix consisting of the first {np - nn) diagonal ele

ments of the matrix Z. It can be seen from (2.10) that the error in the diagnosed parameters

is partly due to measurement noise (V1 Ej e'm) and partly due to taking an incomplete

T Aft

inverse of the sensitivity matrix (V2 V2 ^=r )

Ap Apt -The relative error in diagnosed parameters, , is denoted by ep. The expected

GP

squarederrorin the i device parameter is computed using

7=1 h j = np-n+\

where a is the expected squared error in the i parameter and V^ is t he / element of%

the zth row of V. The fact that E = I , i.e. the parameter variations are inde

pendent, has been used in order to derive (2.11). The number of circuit parameters that can

be accurately computed, is given by counting the number of parameter values that can be

computed with a minimum accuracy level. From (2.11) it can be seen that nw the number

of singular values chosen for diagnosing the parameter values should be such that

nn = max(i) s.t. Z. > aw (2.12)

The condition given in (2.12) is based on differential sensitivity, which is valid only for

small changes in parameters. Therefore, it has to be evaluated at every point in the device

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parameter space (the space spanned by the range of possible variations of parameters) for

ensuring diagnosability across the whole space. However, this may prove to be computa

tionally too expensive. Therefore the heuristic of evaluating (2.12) only for the nominal

values of parameters and at points at the extremes of the parameter space, has been used to

estimate diagnosability. Details of this approach are described in Section 2.4.2.

2.3.3 Ambiguity Groups and Diagnosability

In many cases of circuits with large number of parameters, complete diagnosis is not

possible with the set of given measurements. In these cases, it is important to identify the

parameters which cannot be diagnosed accurately. This can be done using (2.11), which

gives the expected squared error in the diagnosed parameters. It is also important to iden

tify groups of parameters whose values are sensitive to the output variables, but cannot be

diagnosed accurately because the sensitivities of the parameters are linearly dependent.

Groups of parameters that cannot be uniquely solved for from the given set of measure

ments, and whose values are dependent, are called ambiguity groups [116-118]. Sten-

bakken et. al. [116-117] have given the basic definitions of ambiguity groups and an

algorithm to compute ambiguity groups. Liu et. al [118] have given an efficient algorithm

to compute ambiguity groups, These two approaches have ignored the effects of measure

ment noise while computing ambiguity groups. The conditions used are: Two parameters

Pi andp; are part of the same ambiguity group iff

1. The errors in the diagnosed parameters are greater than a given fraction (e) of the stan

dard deviation of the parameter variations, i.e.

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Circuit Netlist,Accessible Nodes

Compute SensitivityMatrix at Nominal

i = Sensitivity MatrixChoose Nodes& Test Signals

Choose points wheremeasurement set is

likely to change

Check Measurements

at Critical Pointsee

Critical parameterValues

"^Measurements^^-No Augment

^ - ^ V a l i d ? ^ - " ^ Measurement set

if Yes

Set of Nodes, TestSignals

Set of Nodes, TestSignals

Figure 2.4 Measurement Selection Methodology

2.4.1 Node and Signal Selection

It was shown in Section 2.3.2 that the number of parameters that can be diagnosed,

from a set of measurements, can be derived from the sensitivity matrix (2.11). This num

ber is used as a measure ofthe diagnostic information contained in a set of measurements.

The aim of the measurement selection algorithm is to select a subset of measurements

which has the same diagnostic information as the whole set of measurements. Ifthe num

ber of parameters that can be diagnosed from a sub-set of measurements is the same the

number of parameters that can be diagnosed from the whole set of measurements, the sub

set is defined to have complete diagnostic information.

The primary aim is to minimize the number of nodes that have to be accessed during

testing. Therefore, it is initially assumed that all the test signals are applied on the CUT

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and try to find a minimum set of nodes with complete diagnostic information. The follow

ing greedy procedure has been used to search for the set ofnodes.

1. {Selected Nodes} = , {Selected Measurements, m} = (j).

2. Find node which, if added to the set of selected nodes, will cause a maximum increase

in diagnostic information. Let this node be k.

3. Add node kto Selected Nodes.

4. Add all measurements made on node kXom.

5. Ifm does not have complete diagnostic information, go to step 2, else end.

Once a set of nodes has been selected, the number of test signals that have to be applied

are minimized, to minimize test time. In order to achieve this, a greedy search similar to

the one used for node selection has been used. For each test signal applied, the list of mea

surements consists of all the measurement(s) of the test signal performed on the selected

nodes. Test signals are sequentially added to the set of selected test signals till the set of

selected measurements has complete diagnostic information. After signal selection, a min

imal set of nodes and test signals for the CUT is obtained. Since these nodes and test sig

nals are selected using the sensitivity matrix computed with the nominal values of the

CUT's parameters, these may not give complete diagnostic information at other points in

the parameter space. Therefore, the set of measurements must be checked at points of the

parameter space where the relationship between parameters and measurements is likely to

have changed.

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2.5 Regression Model Construction

Once the measurements to be made on the CUT are identified, a regression model is

built relating the parameters of the CUT to the selected measurements. The regression

model is built from a set of training data generated through simulation of the CUT.

Instances of the CUT are generated by randomly varying the parameters of the CUT

according to the fault statistics given. If no information is known about the specific kinds

of faults that can occur, uniform, independent distribution of the different parameters is

assumed.

The Cadence circuit simulator, Spectre, was used for circuit simulations. To extract

measurements from the simulation data the Cadence waveform processing tool, Artil, was

used. A nonlinear regression tool, MARS [128], has been used to generate the regression

model from the simulation data. MARS has been used to model the measurements made

on analog circuits with applications to statistical fault simulation [140], test generation

[139] and fault diagnosis [14]. The tool is able to model highly nonlinear functions of

large number of input variables. The regression tool is adaptive, in the sense that the order

of the regression model adapts to the non-linearity of the function being captured. The

regression model constructed consists of piece-wise polynomial functions of the form

M

y-= J^afifit) (2.18) = l

where Bm(x) are spline functions of a set of parameters x. The functions Bt(x) are of the

form

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where x^* is one of the input variables in x chosen for the basis function, tjj is the

break-point for the basis function, s^ takes values of 1 and [x]+= \ x x > .A morel 0 x < 0

detailed description of the tool can be found in the original paper by Friedman [128].

2.6 Diagnosis Procedure

The proposed methodology solves for the values of circuit parameters using a modified

Newton-Raphson (N-R) [130] method. For the system of nonlinear equations

fpm(p)=

tnc , an iteration step of the N-R algorithm is given by

Pk+1 ~Pk = J W * (fpm(Pk) ~ mc) (2.20)

where mc are the measurements obtained from the CUT and JQfy) is the Jacobian

matrix of ~fpm{p) at/?^. Here, the Jacobian is the sensitivity matrix given in (2.4). Instead

of the exact sensitivity matrix, an approximate sensitivity matrix is computed by varying

each parameter by a small amount 6 and computing the difference in ~fpm(p) . An over

view of the diagnosis procedure is given in Figure 2.5. There are several issues involved in

diagnosis using N-R iterations. They are

1. The set of measurements may not uniquely identify the parameters of the CUT

2. Convergence: N-R is only locally convergent- i.e. the iterations converge to a solution

only if the starting guess is close to the solution

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Measurements fromCUT m^

= - -s&=

Coarse Search for

Solution

Poy255)Regression models were built for the selected measurements. Prototypes of the circuits

Figure 2.8 Prototype of Leapfrog filter

were built to test the diagnosis algorithms. Prototypes of the three circuits were built to

test the fault diagnosis algorithms. A photograph ofthe prototype leapfrog filter is shown

in Figure 2.8. Faults were injected into the circuit by varying the circuit parameters. The

R-C time constants of the filters were varied by selecting different values for the respec

tive resistors and capacitors. For varying the gain-bandwidth (GBW), slew rate and phase

margin of the opamp, an LM346 programmable opamp [143] was used. The GBW and

slew rate of this opamp can be varied by varying an external bias resistor. The selected

measurements were made on the CUTs. Test signals were generated using an HP33120A

signal generator and measurements were made using an HP54645D digital storage oscillo

scope. HP54645D has an 8-bit quantizer. This implies an uncertainty of about 0.4% (1/

256) in the measurements. The diagnosis algorithms were run on the measured data.The

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rate can be improved by using a detailed (transistor-level) simulation model for the opamp

to construct the regression models.

2.7.1 On-line Computational Requirements

For the three circuits, the average CPU time for diagnosis was computed. Experiments

were run on a SUN Ultra-2 workstation. The average CPU time requirements ofthe three

circuits is given in Table 2. 5.The second column shows the CPU time required for diag-

Table 2. 5: CPU time Required for diagnosis

Circuit

Average CPU Time for

Diagnosis (sec) Average # of iterations

State Variable Filter ,0.0284 1.44

Leapfrog Filter 0.252 2.3

8-bit Ladder DAC 0.2186 3.1

nosis, and the third column gives the number of iterations required by the N-R algorithm

for convergence. This is the number of times that the inverse ofthe sensitivity matrix was

computed during the diagnosis process.

2.8 Summary

In this chapter the basic framework for diagnosis of analog parameters from measure

ments made of the circuit was described. The effect of measurement noise on the accuracy

of diagnosed parameters was analyzed. An efficient algorithm for diagnosis of multiple

parameter faults was described, that can be extended to large circuits with significant sim

ulation times. Measurement results to verify the accuracy and computational efficiency of

the algorithms were presented.

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for frequency selection using behavioral modeling and fast fault simulation. B. Kaminska

et. al. [91-92] have extended this test generation approach for catastrophic faults and pre

sented a sensitivity-based test generation tool called LIMSoft. Tsai [97] formulated test

generation as a quadratic programming problem, trying to maximize the difference

between faulty and fault-free responses. G. Devarayanadurg and M. Soma [98-99] have

formulated test generation as a min-max optimization problem where the difference

between fault-free and faulty circuit responses was maximized under worst-case variations

in manufacturing tolerances of analog parameters. The approach was used for the genera

tion ofDC, AC and transient test stimuli. These test generation approaches try to test for

the presence or absence of manufacturing defects, rather for the circuit performance spec

ifications.

In recent years, there have been approaches to generation of stimuli that test a circuit's

specifications using alternate tests. These tests are optimized for minimum test time, sim

pler test set-ups, etc. These approaches related the results of alternate tests to the results of

specification tests. Lindermeir et. al [110-112] have used this approach to generate tests

that are simpler in terms of test hardware, while P. N. Variyam et. al [106-108] have used

alternate test that are much shorter in test time than conventional specification tests. R.

Voorakaranam et. al. [109] have used a similar approach, including the effects of measure

ment noise in the test generation process. K-T Cheng et. al [113] have used simpler tests to

allow for the implementation of test hardware on-chip for Built-In-Self-Test (BIST).

S. Chakrabarty et. al. [93-94] have presented an approach to test generation that tries to

distinguish or diagnose die effect of different faults from the circuit response. The

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approach is applied to fault isolation for catastrophic faults, or single parametric faults in

analog circuits. The authors present an approach for reducing the number of faults to be

considered during test generation through a. fault sampling algorithm.

In this chapter, an approach to generate tests for analog circuits is presented that is tar

geted at multiple parametric failures [115]. The approach is based on genetic optimization

and the robust diagnosability conditions derived in Section 2.3.

3.2 Overview

An overview of the proposed methodology is shown in Figure 3.1. The process for diag-

DUT NetlistParameter Info.Performance Meas

DiagnosabilityAnalysis

DUT

PerformanceMeasurements

New Step

Apply Tests

Automatic lestGeneration

Optimized

Tests

Build MARSModels

Diagnose

DiagnosedParameters

Figure 3.1 Overview of Test Generation Methodology

nosis remains the same as what was described in Chapter II. The only new step is the auto

matic generation of test stimuli to aid diagnosis, if complete diagnosis is not possible from

the performance parameter measurements. The newly generated tests are such that, when

addedto the performance parameter measurements, they enable a greater degree ofdiag-

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3.3.1 Test Cost Descript ion

The tests needed are such that, when augmented with the performance measurements,

will enable the accurate computation of device parameters. Test cost is computed from the

augmented sensitivity matrix, given by

S = (3.3)

where S^ is the sensitivity matrix of the performance measurements and Sn is the sensi

tivity matrix of the newly generated test. An SVD is performed on S and the singular val

ues Z; are computed. Equation (3.2) can be used as a test cost for optimization, but it has

the following weakness when used as a cost function with genetic optimization:

Genetic optimization uses parts of sub-optimal solutions, randomly combined, to form

increasingly better solutions. However, (3.2) ignores all singular values less than an.

Therefore, the variation in the smaller singular values, which need to be optimized

(increased) are ignored by (3.2).

Therefore, a modified cost function has been used for test optimization. The test cost is

given by

nr

C= sati= 1

/ v 2 >

__Ly y 2

sat(x) == x x4)

1 x > l

where Emax is a constant related to the minimum accuracy in computed parameters, i.e.

Zmax = am- K, where Kis a constant.lt is noted that this cost function is maximized, for

optimizing tests. This cost function maximizes the singular values, which has the same

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generations to converge to an optimal solution. Therefore, the approach of Successive

Approximation has been used to reduce the search space. In this strategy, the first few

most significant bits (MSBs) of the waveform parameters are optimized in the first stage

of the optimization and the lower order bits are optimized in subsequent stages with the

MSBs set to the optimal settings found in the previous stages. The search space in the case

b n

of a successive approximation GA is reduced to 2 5 w b/bs, where bs is the number of

bits being optimized at a given stage. This results in a much smaller search space for the

GA and hence, faster convergence. Setting bs equal to one would result in the smallest

search space for the GA. However, this can lead to a sub-optimal solution due to the

coarse quantization of the search space. Piece-wise linear (PWL) transient waveforms

have been used as the test signals being optimized. PWL waveforms have shown great

promise in automatic test generation for replacing performance tests [102-114] and for

distinguishing failure modes [93-94]. PWL waveform optimization using successive

approximation GA is illustrated in Figure 3.3. The waveform is optimized two bits at a

time, which gives four possible values for every voltage point in the PWL waveform. This

optimization process is general and can also be applied to other types of waveforms such

as multi-frequency tests.

3.5 Results

In this section, the proposed methodology is applied to a CMOS opamp described in the

ITC mixed-signal test benchmarks [138], and a low-power audio power amplifier [148].

The diagnosability of device parameters for the circuits were analyzed and tests were gen

erated to aid the computation of device parameters as described in Section 2.3. Regression

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device parameter computation technique, random circuit instances were generated by

varying all the device parameters of the circuit. Measurement noise was simulated by add

ing Gaussian distributed random numbers to the simulated test responses. Device parame

ter computation was attempted from the simulated test responses. The comparison of the

simulated and computed parameters for the device parameters of the opamp is given in

Figure 3.7. The 'true' (simulated) value for each parameter is given by the straight line

while the computed values for the device parameters are marked by '+' signs. The device

parameter computation algorithm is able to compute all but 4 parameters (Re, ldp, ldn,

xwp) accurately. It is seen that the computed parameters track the simulated parameters,

proving the effectiveness of the generated test and the device parameter computation algo

rithm.

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3.5.2 Results for a Low-Voltage Power Amplifier

A simplified schematic of the bipolar, low-voltage, power amplifier is shown in

Figure 3.8. The list ofdevice parameters simulated for the power amplifier is shown in

Inputo - t -

I llX

o

In 1

CD

1 2 3 4 5 6 7 8 9

Figure 4.10 Cause Effect Analysis of Slew Rate for Opamp

parameters. It can be seen that the shift in slew rate is mainly due to the shifts in the

device parameters Vtn, yn and the interaction between toxn and yn. Similar inferences may

be made about the shift in supply current. The bar-graphs on the right of Figure 4.10-

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u

I

^m SimulatedI I Diagnosed

I I

SimulatedDiagnosed

11 2 3 4 5 6 7 8 9 1 0 1 1 1 2

Figure 4.11 Cause Effect Analysis of PSRR for Opamp

Si m u l a te dD i n g n o s e d

* ID 40.1 -g

Si m u l a te dO i a g n o so d

o '

uMI n1 2 3 4 5 6 7 8 9 1 0Figure 4.12 Cause Effect Analysis of Supply Current for OpampFigure 4.13 show the relative contributions of each device parameter variation to the vari

ance of each performance. For example, it can be seen that the major portion of the vari

ance in slew rate is caused by the variation in the compensating capacitor Cc, the oxide

thickness toxn, and the variation in width due to etching xwn. The portion of the bar-

graphs labelled 'Error' refers to the part ofthe variation that could not be explained by the

variation in any of the parameters considered. It is seen that the technique is able to diag

nose a major portion ofthe cause of shift and variance in circuit performance parameters.

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n H - H S i m u l a te d 11 1 Dia ano sed l_

0 . 6

-

"

0.4

0.2

o

0. 2

0. 4

0. 6

t 1r:-0.8 - -

Si m u l a te dD i a g n o se d

"fi

I IIIulii1 2 3 4 5 8 7 8 9 1 0Figure 4.16 Cause-Effect Analysis of High-Frequency Gain for LM386

0. 8 "I^H Simu la ted II I Dia gno sed |"

0 . 6

"

"

0 . 4 T"10.2

0

0. 2

i

i

i

J J L :

0 . 4 - -

0 . 6 - -

0 . 8 - -

5 6 7 8

Figure 4.17 Cause-Effect Analysis of Supply Current for LM386

4.7.3 L ow-Po wer CMO S Opamp

To study the scalability of the diagnosis methodology, it was applied to a low-power

CMOS operational amplifier obtained from industry. The opamp contained 80 CMOS

transistors belonging to 5 types and bipolar transistors (substrate pnp), as well as resistors

and capacitors. The device parameter variations for this device was modeled using the

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. AA^TA ^ A~I N PI N M A ^ / V . /V \/ "Y \/ \A A/W

kxAAXyA W "^VÔc^\^ vÂ\Y/vÂ{W

2 3T i m e ( m s e c )

Figure 4.22 Stimuli and Opamp Response for Combination of Common-Mode and Differential-Mode Stimuli

computation are shown in Figure 4.23. The figure shows the correlation coefficients

15 20P a r a m e t e r I n d e x3 5

Figure 4.23 Correlation Coefficients Between Simulated and DiagnosedParameters

between the simulated and diagnosed parameters, for the 33 parameters which had signifi

cant effect on the variation of specifications. In the case of perfect diagnosis, all correla

tion coefficients would be equal to one (diagnosed parameters equal to simulated

parameters). It is seen that only 3 of the 33 parameters are diagnosed accurately. The

remaining parameters form ambiguity groups, and cannot be computed uniquely. This

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occurs due to the large number of process parameters for the CMOS opamp, which makes

the unique identification of any single parameter difficult.

Process disturbances were introduced in the device parameters as described in

Section 4.7.1, and diagnosis was attempted. The normal and modified distribution of per-

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is presented. In Section 5.4, the proposed technique for obtaining accurate estimates of

linearity metrics, is described. The improvement in accuracy is based on accurately esti

mating the expected variance of errors in linearity metrics estimated from histograms of

ADC outputs, due to device noise and quantization effects. In Section 5.5, an analysis

technique to accurately estimate the variances of errors in linearity estimates, obtained

from histograms for both ramp and sine wave input waveforms, is presented. In

Section 5.6, some of the practical considerations in the implementation of the technique

are discussed. Experimental results to validate the performance of the algorithm are given

in Section 5.7.

5.2 Review of Techniques for Estimation INL and DNL

In this section, the techniques used to compute CTs, INL and DNL for ADCs [83, 85-

87] are reviewed. In Section 5.2.1, the servo-loop technique for measuring linearity met

rics is presented. In Section 5.2.2, the techniques to measure INL and DNL from a histo

gram obtained for a linear ramp or sine wave input signal are described. In Section 5.2.3,

the techniques that have been proposed to reduce linearity test time using linear models

are described.

INL and DNL are measures of how much the CTs of an ADC differ from a ideal linear

behavior. INL and DNL are defined as follows [125]. DNL is a measure of the deviation

from the ideal 1 Least Significant Bit (LSB) of the input voltage span that is associated

with each output code. INL is the deviation of an ADC transfer function from the line

between the measured end-points (zero and full scale) of the ADC. INL and DNL are usu

ally expressed in LSBs. INL and DNL can be expressed in terms of the CTs as

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described in Section 5.2.3. The average device noise variance for the ADC is also mea

sured from the training set. The proposed methodology works with the histogram method

for measuring INL and DNL because of the reduced test time in comparison to the servo-

loop method. As noted in Section 5.2, the histogram techniques estimate all the CTs in one

pass. Gapofreddi and Wooley [76-77] have shown that the accuracy of CT estimates can

be improved by using a linear model (5.6). It is shown that, if the variance in the errors in

y are known, more accurate estimates of the 0 can be made than is suggested by (5.6).

From these optimal estimates for 9, an improved estimate of yean be made.

An overview of the proposed approach is given in Figure 5.1. The steps within the

dashed box have been demonstrated in literature [76-82] while the remaining parts are the

contributions ofthis work. The proposed technique consists of an off-line model building

phase and a production test strategy. During the off-line model building phase, a minimal

test length is selected that will give the required accuracy in the CT estimates. Also the

parameters required to calculate the optimal estimates for y from the histogram estimates

of y (Ay, GQ and a^) are computed. During production test, a sine wave or ramp of the

computed test length is applied to the DUT and the CTs are estimated from the resulting

histogram. Then, using the parameters computed during the model building phase an opti

mal estimate for the CTs is made. The ADC linearity metrics are computed from these

optimal CT estimates and the device is classified and good or faulty by comparing the

metrics against specified limits.

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Model Building

ADCs TrainingSet

Production Test Strategy

Measure AllCTs Accuarately

Estimate Device

Noise

Linear Model

Construction

ATo eL _ _ _ 4 _ _ _ _ _ 4 - J

'en

Estimate Variance of Error in y,

Test Length Selection: N

Ay,


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2 2 2

where e is characterized by variance oeQ. It can be shown that cey = Ge9 and that the

elements ofeQ are uncorrected, since the columns of A y are orthonormal. Since the vari

ance of the variables 0 are known, (from (5.5)) a least squares linear estimate for 0 can be

computed as follows. For two random variables x and y with zero means, standard devia

tions ox and Oy and correlation coefficient r, it can be shown [127] that the least squares

linear estimate for x given y is given by

x = E(x\y) = r- -y (5.9)y

Substituting x=Qh the z"th element of 0 and y=Qj+eQi, r = - and

/ 2 2VC6i + GeQ

= - - are obtained. Therefore, an optimal estimate for 0, which is denoted byGv p2~t 2~

0, is given by

2 2

= 3d-' ^7/ ( ? - *fy) V/,1 < i (5.10)

where


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2 -

where Uy, y , are as defined in Section 5.3 and a - is the variance of the variables 6'

2

defined in Section 5.3. Using calculations similar to (5.15), a ~r can be shown to be

2

2i= 4^- (5i7>Ge, + 1

2

Once G ~ has been determined, a limit on the errors in linearity measurements can be

computed such that

P\\e~\


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Code Transition

Figure 5.4 Errors in Histogram

of giving a output code greater than7 due to ADC noise and vice-versa. Since the voltage

samples are spaces A Volts apart, the resolution of the CT measurement is A Volts, as can

be seen from Figure 5.4. To analyze the effect of noise and finite resolution of measure

ment on the estimation of the CT, following quantities are defined.

Vb = max(Vi\P[C(Vi + en)>j]~0 (5.19)

i.e. Vb is the largest sample value ofthe input signal that has (approximately) zero prob

ability of giving an output code greater than/ is a small constant (equal to 10"6 in the

calculations in this chapter), that is required because a Gaussian distribution has a finite

probability of being arbitrarily large. C(x) is the code at the output of the ADC when x is

the input value. A set Sis defined as

S = {Si\P[C(st) t P[C(Si) >j] > Q (5.20)

i.e. a set of samples that have non-zero probabilities of giving an output code greater

than or less than or equal toy depending on the value of noise on the samples. Let the true

value for the CT y is given by y- = Vb+mA+a, A and a are as indicated in Figure 5.4. It is

[01


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assumed that the CT can occur at any point between the two voltage samples with equal

probability, i.e. a can vary uniformly from 0 to A. Under these definitions, the measured

value of the CT y. is given by

7,. = Vb + kA + ^ (5.21)

where the A/2 term has been added to make the estimate ofy- unbiased. The symbol k

represents the number of elements the set S', defined as

S' = {*,!*, C(*,)/} (5.22)

i.e. S' is the subset ofSthat give output less than or equal to / The error in estimation of

y, e . = y. - y. is given by (m - k) A + a - . The mean square value ofe^ is given by

A A 2

E(ey) = A f E((m-kf\a = x)dx + 2- j E((m- k)\a = x)(a- -)dx + ^- (5.23)

^=0 ^=0

where (JC|J/) is the conditional expectation of x given the value of>>. (5.23) requires

2 I

the estimation of E((m-k) \a) and E((m~ k)\a). Since w is a constant it is only

required to estimate the mean and variance ofk. For a given value of a, the random vari

able kcan be modelled as

*= 5 > i (5-24)

ieS

where ^ = 1 iff C(st)


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l-v,

P[C(Si)


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where VFS is the full-scale voltage of the ADC and n is the number ofbits.

5.5.2 Computation of G^ for Sine Wave Input Signal

For a sine wave signal, the resolution of the measurement A depends on the CT. It is

assumed that the sine wave and the clock input to the ADC are synchronized, so that

( ^iztik i+ 81, 0


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Since e can be computed from the measured CTs (y), cey may be estimated from the

measured CTs.

To check for variations in process statistics the variance of the computed variables 0;

may be monitored. If a significant change in the process statistics is observed, a new linear

model must be built using a training set derived form the ICs with the new process statis

tics.

5.7 Results

The experimental results are given in three sections. First, it is verified the expressions

derived in Section 5.5 are verified using simulation in Section 5.7.1. In Section 5.7.2, the

effect of device noise and test length on the estimates of CTs is analyzed and a minimum

test length for a give accuracy requirement in CT estimates is chosen. In Section 5.7.3, the

experimental set-up used for making measurements is described. In Section 5.7.4, experi

mental results from a commercial ADC [146] for a ramp input are presented. In

Section 5.7.5, simulation results for a sine wave input are presented.

5.7.1 Verification of o ^ Estimates via Simulation

In this section, the formulae derived in Section 5.5 are validated using simulation. The

simulation model used for behavioral simulations is shown in Figure 5.5, which models

the DC (low-frequency) behavior of ADCs.The model consists of (i) an input noise

source, (ii) an ideal sample-and-hold and (iii) a set of CTs which represent the DC transfer

function of the ADC. The behavioral simulation tool was implemented in C. In this simu

lation model, the CTs for the ADC were varied with a standard deviation of0.1 LSB and

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Test Length (Samples/Code)

(b)

Figure 5.7 Comparison of Error in a^ for Proposed Approach vs. Earlier

Approaches [89]

The error in estimated


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5.7.2 Selection of Test Length

In this section, the computation of test length for a given required accuracy and variance

of device noise is presented. Test length is directly proportional to test time is the sam

pling frequency of the ADC is specified.

For experimentation, linearity metrics of 75 ADC0831 ADCs were measured at 512

samples/code . A linear model was built for the CTs of the 75 ICs using techniques

described in Section 5.2.3 [81]. The r.m.s device noise was found to be 0.1 LSBs. The

variation in r.m.s error in the CTs for the proposed technique is shown in Figure 5.10. The

w5

men

H J 0 0 4

i-^b.oa

O RMS Error (Proposed Technique)* R M S Err or (C ap of re dd i an d Wo ol ey )

R M S Error (No Linear Model Used)

10 10 lO lO

Samples/Code (N/2 f

Figure 5.10 Variation in o^ vs. Test Length for a Ramp Signal

values of a^y without the use of the linear model and for the use of a previous technique

[76-77] are also shown for reference. It is seen that the performance ofthe proposed tech

nique is similar to the one proposed by Capofreddi and Wooley for large values of test

1. It should be noted that to produce a true ramp signal at 512 samples/code a DAC of 17 bits (ADC 8 bits+9)resolution is required. Since the Data Acquisition DAC has only 16 bits, a ramp at 512 samples/code

will have adjacent output samples to be the same value. However, since the quantization level of the DAC

is much less than the input noise of the ADC, this ramp behaves as an ideal ramp with the 17 bit resolution required.

no


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