Fault-Tolerant Network-Interface for Spatial Division Multiplexing Based
Network-on-Chip
By
Anup Das
2
Content
1. NoC Overview
• TDM-Based
• SDM-Based
2. Existing NI Architecture
3. New Area Optimized Architecture
4. Need for Fault-Tolerance
5. Fault-Tolerant NI Architectures
• Centralized Approach
• Distributed Approach
6. Results
7. Conclusion
Network-on-Chip
• Increasing Number of IPs/PEs per die• Communication bottleneck with shared bus• Need for a scalable alternative
–Use of networking concepts–NoC proposed by Benini et al.
3
Switch
NI
IP
NI
IP
Switch
NI
IP
NI
IP
Switch
NI
IP
Switch
NI
IP
Switch
Switch
Network-on-Chip (contd.)
• Two techniques for communication–Time Division Multiplexing
–Spatial Division Multiplexing
4
NI
IP
NI
IP
A B C
TDM-based NoC
Switch
NI
IP
NI
IP
Switch
A
SDM-based NoC
B
C
SwitchSwitch
Network Interface Architecture• N to 1 bit serializers – one for each outgoing
wire
• Data Distributor to send data from output queues to one of the serializers
• Each distributor can send data to each of the serializers
• Not all the distributors are loaded all the time
• A single distributor can serve all the serializers
5
Network Interface Architecture
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n to 1
n to 1
n to 1
Distributor 1Queue 1
Queue 2
Queue 3
Distributor 2
Distributor 3
32
32
32
out[7]
out[1]
out[0]32
32
New Area Optimized NI
• Single distributor for all the serializers
• New component called “requester” added for interfacing with the queue
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sID qID
001 000, 001, 010
010 011, 100, 101
100 110, 111
• At connection setup time – each serializer assigned to a queue
• Serializer requests for data which is then forwarded to corresponding queue
• Data from queues travels back to the requesting serializer
• 2 IDs introduced – serializer ID (sID) and queue ID (qID)
New Area Optimized NI
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32 to 1
Distributor
out[0]
out[1]
out[7]
32 to 1
32 to 1
Requester
Queue 2
Queue 1
Queue 3
32
3232
32
32
32
32
32
32
32
Need for Fault-Tolerance
• Transistor density on the rise
• Shrinking feature size
• Increasing number of faults manifesting post fabrication
• Yield Loss
• Need for fault-tolerance–IP/PE level–Interconnect Level
• Idea is to provide graceful degradation of performance in event of faults
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NI Fault-Tolerance - Centralized• Controller introduced between distributor and IP
queues• Changes data mapping dynamically when fault
occurs with load balancing
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n to 1Distributor 1Queue 1
Queue 2
Queue 3
Distributor 2
Distributor 3
32
32
32
out[0]
n to 1 out[1]
n to 1 out[7]
32
32
32
32
32
32
Centralized NI Operation
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Controller
S1S2S3S4S5S6S7S8
D1
D2
D3
Queue 1
Queue 2
Controller
S1S2S3S4S5S6S7S8
D1
D2
D3
Controller
S1S2S3S4S5S6S7S8
D1
D2
D3
Queue 3
Queue 1
Queue 2
Queue 3
Queue 1
Queue 2
Queue 3
NI Fault-Tolerance - Distributed• Multiple Distributors and Requestors –each
capable of fault recovery
• Two other IDs included – dID (distributor ID) and rID (requester ID)
• When forwarding request to requester, distributor forwards dID, sID and qID
• qID – used by requester to forward request to a queue
• dID – used by requester to send back data from the queue to the requesting distributor
• sID – used by the distributor to send data to the requesting serializer
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Distributed NI Operation
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S1S2S3S4S5S6S7S8
D1
D2
S1S2S3S4S5S6S7S8
D1
D2
S1S2S3S4S5S6S7S8
D1
D2
R1
R2
R1
R2
R1
R2
Queue 1
Queue 2
Queue 3
Queue 1
Queue 2
Queue 3
Queue 1
Queue 2
Queue 3
Results
Experimental Setup
• NoC considered with 8 links per node
• Data packets of size 32 bits
• Centralized Design coded in VHDL
• Distributed Design in Verilog
• Synopsys Design Compiler for ASIC synthesis
• UMC 65nm Standard Cells
• Area and Power number from the synthesis tool
• Area number converted to gate count for comparison across technologies
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Area Breakup
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Centralized Design Distributed Design
Components Centralized Design Distributed Deign
Distributor 1.8K 2.2K
Requester - 0.5K
Controller 1.5K -
Serializer + Other 5K 4.5K
Total (2 Distributors) 10.1K 9.9K
Area and Power Comparison
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Increasing Fault-Tolerance
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Throughput
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Summary
• Distributed Design more area and power efficient but centralized design becomes more efficient with more distributors
• Single fault in the controller of centralized design will render it useless
• No single fault will affect distributed NI behavior
• Next Step – –Increase granularity of load balancing–Fault-tolerance of Serializer
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Thank you