Fermilab Silicon Strip Readout Chip for BTEV
Raymond Yarema, Jim Hoff, Abderrezak Mekkaoui
Fermi National Accelerator Laboratory
Massimo Manghisoni, Valerio Re
Universita di Bergamo and INFN, Pavia, Italy
Valentina Angeleri, Pier Francesco Manfredi, Lodovico Ratti, Valeria Speziali
Universita di Pavia and INFN, Pavia, Italy
October 19, 2004 2004 Nuclear Science Symposium 2
The Experiment
• BTEV - new experiment– Due to run in 2009– Designed pixel readout– Designed SSD readout (w/INFN)
• Silicon Strip Detector– 21 planes– Each plane is 30.6 x 31.6 cm– Total of 129,000 strips– FSSR (Fermilab Silicon Strip
Readout) chip wire bonded to SSD
• Full custom • Mixed signal device• TSMC 0.25 µ CMOS
October 19, 2004 2004 Nuclear Science Symposium 3
Major Requirements
• Data driven architecture – no trigger• Can operate at 132, 264, or 396 nsec beam crossing• Over 10 years FSSR can see 5 Megarads
– Designed for TID and SEU
• Equivalent Noise Charge (ENC) < 1000erms @ Cdet = 20 pF
• Threshold dispersion < 500 erms• Power < 4 mW/channel
October 19, 2004 2004 Nuclear Science Symposium 4
FSSR Block diagram• FSSR Core
– 128 analog channels– 16 sets of logic, each
handling 8 channels– Core logic with BCO counter
• Programming Interface (slow control)– Programmable registers– DACs
• Data Output Interface– Communicates with core
logic– Formats data output– Same as BTEV FPIX chip
• Allows common DAQ
128 cha nne ls of a na log c ircuits
16 se ts of logic e a chha ndling 8 a na log cha nne ls
Core Logic
To s ilicon s trip de te c tors
P rogra mming Inte rfa ce
DACs P rogra mma bleRe gis te rs
S te e ring LogicWord S e ria lize r
ClockControlLogic
Ne xtBlockWord
Co
reD
ata
Ou
tpu
tIn
terf
ace
BCO clock I/O Re a doutclock
High S pe e dO utput
BCO ctr
1 16
October 19, 2004 2004 Nuclear Science Symposium 5
Chip Layout• Chip has128 channels with all digital
blocks– 50 micron pitch– Double row of bond pads
• Chip features for testing– One block of 64 channels has 32 with
Baseline Restorer and 32 without – Different input transistor sizes were
used on a few of the channels– A few of the analog front ends were
removed to add multiple test points for adjacent channels
– Individual transistors were added to characterize and compare their performance to operation in the preamplifier.
• Size is 7.27 mm x 4.46 mm
October 19, 2004 2004 Nuclear Science Symposium 6
Analog Channels• Preamplifier
– Positive charge input– Gain of 5 mV/fC
• Integrator and shaper– CR-(RC)2
– Four programmable shaping times (65, 85, 105, 125 nsec)
• Base Line Restorer– Stabilizes base line– Blocks DC offset– Affects noise, threshold dispersion,
gain (more info later)• Discriminator
– Comparator– Programmable threshold (chip wide)
• 1 bit of 128 bit Serial shift register– Controls switch to provide
Test Input– Controls switch to Kill
discriminator output
Cdet
Bias
Cf
Gm
Preamplifier
CR-(RC)2 BLR
Programmableshaping
Discriminator
Convertto
Diff.
Vthreshold
Kill
Test Input
Cinj
Integrator&Shaper
October 19, 2004 2004 Nuclear Science Symposium 7
Digital Section• Programming Interface
– Receives 13 bit of serial data• 5 bits for chip ID• 5 bits for programmable
address– CapSel – set shaping time– Kill – disconnect
discriminator– Inject – control test pulse– AqBCO – store BCO value– Alines – select # of output
serial lines– SendData – enable core– RejectHits – reject new
hits– Three types of resets
• 3 bits for instructions
– Write – download 2, 8, or 128 bits to register
– Read – output bits in register
– Set – set all register bits = 1
– Reset – set all register bits =0
– Default – set register bits to default value
• Chip ID set by wire bonds
Programming Interface
DACs ProgrammableRegisters
BCO clock I/O
October 19, 2004 2004 Nuclear Science Symposium 8
Digital Section (cont.)• Data Output Interface
– Serial data output
– Number of output lines is programmable (1, 2, 4, 6)
– LVDS output
– No output buffering
– Interfaces to Core Logic
– Formats the data
– Max data rate = 840 Mb/sec (6 lines)
– Readout clock (70 MHz) independent of BCO clock
– Data output is not time ordered
• Two types of 24 bit readout words– Sync/Status
• 10 bits status• 13 bits for synchronization• 1 bit for word mark
– Data word• 4 bits for strip number (1 of
8)• 5 bits for logic set number• 8 bits for hit BCO number• 6 bits are currently unused• 1 bit for word mark
Steering LogicWord Serializer
ClockControlLogic
NextBlockWord
Readoutclock
High SpeedOutput
October 19, 2004 2004 Nuclear Science Symposium 9
Test Results• The analog and digital sections along with all test
structures functioned properly allowing extensive testing of the chip.
• Noise performance is close to predicted values.• Overall gain is about 80 mV/fC.• Wide dynamic range of about 12 fC• Power dissipation is 3 mW/channel• The chip has been operated operated with a 70 MHz
readout clock to provide 840 Mb output data rate. • Threshold dispersion = 440 erms (with BLR)• ENC (Cdet = 20 pF, shaping time = 125 nsec, with BLR) is
790 erms.• All specifications met.
October 19, 2004 2004 Nuclear Science Symposium 10
Averaged Waveforms at Shaper Output Showing Different Shaping Time Settings
• Shaping time can be programmed (65, 85, 105, 125 nsec)
• Adjustment allows for
– Foundry process variations
– Different beam interaction times.
• Has small tail lasting for several microseconds that might cause a problem.
-1000
-800
-600
-400
-200
0
200
0 100 200 300 400 500 600 700 800
Channel # 65Q
inj=10 fC
Sh
ap
er O
utp
ut
[mV
]
Time [ns]
65 ns
125 ns
85 ns
October 19, 2004 2004 Nuclear Science Symposium 11
Equivalent Noise Charge Measurement at Shaper Output
• Close to simulated value
• Noise depends on shaping time
0
500
1000
1500
2000
0 10 20 30 40
NMOS, W/L = 1500/0.45EN
C
[e r
ms]
CD [pF]
tP = 85 ns
ENC = 220 e + 26.5 e/pF
October 19, 2004 2004 Nuclear Science Symposium 12
Base Line Restorer Test Results• Shaper output has small overshoot.• Overshoot causes unwanted variable offset at discriminator input.• BLR removes variable offset.• BLR also improves threshold dispersion (AC coupling), but increases noise.
• BLR is needed to remove variable offset and improve threshold dispersion
0
20
40
60
80
100
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
Channel 2, tp=85 ns
without baseline shift1% occupancy2% occupancy
Co
mp
ara
tor
firi
ng
eff
icie
nc
y (%
)
Injected charge [fC]
0
20
40
60
80
100
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
Channel 1, tp=85 ns
without baseline shift1% occupancy2% occupancy
Co
mp
ara
tor
firi
ng
eff
icie
nc
y (%
)
Injected charge [fC]
Input signal discriminator scan without BLR
Input signal discriminator scan with BLR
October 19, 2004 2004 Nuclear Science Symposium 13
Future Changes
• Since the current chip has unnecessarily wide dynamic range, the gain will be increased by decreasing the size of the preamplifier feedback capacitor from 200 fF to 150/100 fF. This will cause a further reduction in threshold dispersion.
• It was recently decided that a simple discriminator output will not satisfy the need to calibrate the detector as radiation changes its characteristics.– A 3 bit ADC, similar to the one used in the BTEV FPIX chip, will
be added to each channel– considered low risk.– The 3 bits will be inserted into the data word to replace 3 of the 6
unused bits. Thus there is no impact on the data rate.
October 19, 2004 2004 Nuclear Science Symposium 14
Conclusion
• A full size prototype of the silicon strip readout chip for BTEV has been designed and tested.
• The device was found to be fully functional.• With the presence of the BLR all initial
requirements were met.• The final design will include a gain change and
addition of a three bit ADC.• Work is progressing toward a submission in
January 2005.
October 19, 2004 2004 Nuclear Science Symposium 15
Back up Slides
October 19, 2004 2004 Nuclear Science Symposium 16
Averaged Waveforms at the Shaper Output for Different Input Charges
• Output is well behaved
• Gain is about 80 mv/fC
• Gain becomes non-linear above 12 fC.
-1000
-800
-600
-400
-200
0
200
0 100 200 300 400 500 600
Channel # 65Q
inj start=2 fC, Q
inj stop=10 fC, step 2 fC
Nominal peaking time 85 ns
Sh
aper
Ou
tpu
t [m
V]
Time [ns]
October 19, 2004 2004 Nuclear Science Symposium 17
Output Data Formatb23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12
(a) One output pair
b5 b4 b3 b2 b1 b0
b11 b10 b9 b8 b7 b6
b17 b16 b15 b14 b13 b12
b23 b22 b21 b20 b19 b18
b3 b2 b1 b0
b7 b6 b5 b4
b11 b10 b9 b8
b15 b14 b13 b12
b19 b18 b17 b16
b23 b22 b21 b20
(b) Two output pairs
(c) Four output pairs
(d) Six output pairs
October 19, 2004 2004 Nuclear Science Symposium 18
Base Line Restorer Circuit
Ref
2I
IFroms haper
To dis crimina tor
October 19, 2004 2004 Nuclear Science Symposium 19
Detector Plane with FSSR Readout Chips
October 19, 2004 2004 Nuclear Science Symposium 20
0
500
1000
1500
2000
0 5 10 15 20 25 30 35 40
without BLRwith BLR
y = 221.07 + 26.387x R= 0.9995
y = 216.22 + 33.228x R= 0.99863
EN
C [
e r
ms]
CD [pF]
tp =85 ns
ENC with and without a BLR
October 19, 2004 2004 Nuclear Science Symposium 21
Typical threshold dispersion and equivalent noise charge with and without a Base Line Restorer circuit for a shaping time of 85 nsec.
Threshold Dispersion
ENC
W/O BLR
790 erms 760 erms
W BLR 440 erms 890 erms
Specification
500 erms 1000 erms