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FIELD EFFECT TRANSISTOR - FET
https //sites google com/site/amirunikl/lecture
FIELD EFFECT TRANSISTOR - FET
https://sites.google.com/site/amirunikl/lecture
ContentsFETTypes of FETTypes of FETBiasingCommon Source AmplifierMosfetEnhancement MosfetEnhancement MosfetDepletion Mosfet
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FET ( Field Effect Transistor)
1. Unipolar device i. e. operation depends on only one type of charge carriers (h or e)
2 Voltage controlled Device (gate voltage controls drain
Few important advantages of FET over conventional Transistors
2. Voltage controlled Device (gate voltage controls drain current)
3. Very high input impedance (≈109-1012 Ω)4. Source and drain are interchangeable in most Low-frequency
applications5. Low Voltage Low Current Operation is possible (Low-power
consumption)6. Less Noisy as Compared to BJT7 No minority carrier storage (Turn off is faster) 7. No minority carrier storage (Turn off is faster) 8. Self limiting device9. Very small in size, occupies very small space in ICs10. Low voltage low current operation is possible in MOSFETS 11. Zero temperature drift of out put is possiblek
Types of Field Effect Transistors (The Classification)
o JFET n-Channel JFETFET
MOSFET (IGFET)p-Channel JFET
Enhancement MOSFET
Depletion MOSFET
FET
n-Channel EMOSFET
p-Channel EMOSFET
MOSFET MOSFET
n-Channel DMOSFET
p-Channel DMOSFET
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The Junction Field Effect Transistor (JFET)
Figure: n-Channel JFET.
Drain
SYMBOLS
Drain Drain
Gate Gate Gate
Source
n-channel JFET
Source
n-channel JFETOffset-gate symbol
Source
p-channel JFET
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Biasing the JFET
Figure: n-Channel JFET and Biasing Circuit.
Operation of JFET at Various Gate Bias Potentials
Figure: The nonconductive depletion region becomes broader with increased reverse bias.(Note: The two gate regions of each FET are connected to each other.)
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-
Operation of a JFET
Drain
P P +-
+
-
N
N
Gate
+ N
Source
Output or Drain (VD-ID) Characteristics of n-JFET
Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.
Non-saturation (Ohmic) Region:
The drain current is given by ⎥⎥⎤
⎢⎢⎡
−⎟⎠⎞⎜
⎝⎛ −=
2
2 2
2DS
DSPGSDSS
DS
VVVV
II
⎟⎠⎞⎜
⎝⎛ −<
PGSDSVVV
g y⎥⎥⎦⎢
⎢⎣
⎠⎝ 22 DSPGSP
DS V
⎥⎥⎦
⎤
⎢⎢⎣
⎡⎟⎠⎞⎜
⎝⎛ −=
2
2 PGSP
DSSDS
VVV
II
2
1 and⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛−=
P
GSDSSDS V
VII
Where, IDSS is the short circuit drain current, VP is the pinch off voltage
Saturation (or Pinchoff) Region: ⎟⎠⎞⎜
⎝⎛ −≥
PGSDSVVV
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Simple Operation and Break down of n-Channel JFET
Figure: n-Channel FET for vGS = 0.
Break Down Region
N-Channel JFET Characteristics and Breakdown
Figure: If vDG exceeds the breakdown voltage VB, drain current increases rapidly.
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VD-ID Characteristics of EMOS FETLocus of pts where ( )PGSDS VVV −=
Saturation or Pinch off Reg.
Figure: Typical drain characteristics of an n-channel JFET.
2⎟⎞
⎜⎛ V IDSS
Transfer (Mutual) Characteristics of n-Channel JFET
1 ⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛−=
P
GSDSSDS V
VII
V V
Figure: Transfer (or Mutual) Characteristics of n-Channel JFET
VGS (off)=VP
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JFET Transfer CurveThis graph shows the value of ID for a given value of VGS
Biasing Circuits used for JFET
Fixed bias circuitFixed bias circuitSelf bias circuitPotential Divider bias circuit
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JFET (n-channel) Biasing Circuits
0, ===+= GGSGSGGGG IFixedVVRIV Q
For Fixed Bias CircuitApplying KVL to gate circuit we get
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1⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛−=
P
GSDSSDS V
VII
, GGSGSGGGG
DDSDDDS
P
GSDSSDS
RIVVVV
II
−=
⎟⎟⎠
⎞⎜⎜⎝
⎛−=
and
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For Self Bias Circuit
and
Where, Vp=VGS-off & IDSS is Short ckt. IDS
S
GSDS
SDSGS
RV
I
RIV
−=∴
=+ 0
JFET JFET BiasingBiasing Circuits Count…Circuits Count…
or Fixed Bias Ckt.
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JFET Self (or Source) Bias Circuit
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1 and⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛−=
P
GSDSSDS V
VII
S
GS
P
GSDSS R
V
V
VI −=
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛−∴
2
1
021
2
=+⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛+−
S
GS
P
GS
P
GSDSS R
V
V
V
V
VI
This quadratic equation can be solved for VGS & IDS
The Potential (Voltage) Divider Bias
01
2
=−
−⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛−∴
S
GSG
P
GSDSS R
VV
V
VI
DSGSI V gives equation quadratic this Solving and
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Circuit Configuration
Biasing CircuitR1 and R2 – voltage divider
VG = VR2 = VDD x VR2/(VR1 + VR2)( )
VGS VG –VRS
VRS should be more positive compared to VG
VDD = VRD + VDS + VRS
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Circuit Layout and Analysis
Components and FunctionsGate resistor(R2) : In JFET amplifier gate resistor is used to maintain gate terminal is nearly about 0 V d.c (i.e gate terminal current is approximately zero) Gate resistor is in several mega current is approximately zero).Gate resistor is in several mega ohms value which prevents loading of the a.c signal sourceCoupling capacitor(C1) : In JFET amplifier coupling capacitor used as coupling devices to one stage to next stage and in input gate terminal in order to pass only input a.c signal and blocked d.cbiasing signal Bypass capacitor(Cs) : In JFET amplifier it is used with source yp p ( ) J presistor in parallel as shown in above figure.Which provides easy path for a.c signal to grounded which prevent voltage drop in source resistor and increase voltage gain
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Output Characteristics
Common Source JFET Amplifier Characteristics Curves
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A Simple CS Amplifier and Variation in IDS with Vgs
FET Mid-frequency Analysis:
A common source (CS) amplifier is shown to the right.
Rs Ci RL
Co
vo
+
+
+
io
ii
D
S
G
VDD
VDD
R1
RD
The mid-frequency circuit is drawn as follows:• the coupling capacitors (Ci and Co) and the
bypass capacitor (CSS) are short circuits
g
s
rd gmvπ vi = vπ
ii io
vo
d
s
+ +
_ _
mid-frequency CE amplifier circuit
RD RL RTh vs
+
_
is
CSS vi
vs
_ _
_
RSS
R2
• short the DC supply voltage (superposition)• replace the FET with the hybrid-π modelThe resulting mid-frequency circuit is shown below.
q y p
' 'o o ivi m L L d D L vs vi
i s s i
ii Th Th 1 2
i
Analysis of the CS mid-frequency circuit above yields:
v v ZA = = -g R , where R = r R R A = = A v v R + Z
vZ = = R , where R = R R i
⎡ ⎤⎢ ⎥⎣ ⎦
L
o iI vi
i L
o oo d D P vi I
o iseen by R
i Z A = = Ai R
v pZ = = r R A = = A Ai p
⎡ ⎤⎢ ⎥⎣ ⎦
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FET Mid-frequency Analysis:
A common source (CS) amplifier is shown to the right.
Rs Ci RL
Co
vo
+
+
v
+
io
ii
D
S
G
VDD
VDD
R1
RD
R2
The mid-frequency circuit is drawn as follows:• the coupling capacitors (Ci and Co) and the
bypass capacitor (C ) are short circuits
g
s
rd gmvπ vi = vπ
ii io
vo
d
s
+ +
_ _
id f CE lifi i it
RD RL RTh vs
+
_
is
CSS vi
vs
_ _
_
RSS
R2
bypass capacitor (CSS) are short circuits
• short the DC supply voltage (superposition)• replace the FET with the hybrid-π modelThe resulting mid-frequency circuit is shown below.
s smid-frequency CE amplifier circuit
' 'o o ivi m L L d D L vs vi
i s s i
ii Th Th 1 2
i
Analysis of the CS mid-frequency circuit above yields:
v v ZA = = -g R , where R = r R R A = = A v v R + Z
vZ = = R , where R = R R i
⎡ ⎤⎢ ⎥⎣ ⎦
L
o iI vi
i L
o oo d D P vi I
o iseen by R
i Z A = = Ai R
v pZ = = r R A = = A Ai p
⎡ ⎤⎢ ⎥⎣ ⎦
Procedure: Analysis of an FET amplifier at mid-frequency:
1) Find the DC Q-point. This will insure that the FET is operating in the saturation region and these values are needed for the next step.
2) Find gm. If gm is not specified, calculate it using the DC values of VGS as follows:
( )DSSD 2II V V (f JFET' d DM MOSFET' )∂
3) Calculate the required values (typically Avi, Avs, AI, AP, Zi, and Zo. Use the formulas for the appropriate amplifier configuration (CS, CG, CD, etc).
( )
( )
DSSDm GS P2
GS P
Dm GS T
GS
GS
g = = V - V (for JFET's and DM MOSFET's) V VIg = = V - V (for EM MOSFET's)
V(Note: Uses DC value of V )
K
∂∂∂
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PE-Electrical Review Course - Class 4 (Transistors)
Example 7:
Find the mid-frequency values for Avi, Avs, AI, AP, Zi, and Zo for the amplifier shown below. Assume that Ci, Co, and CSS are large.Note that this is the same biasing circuit used in Ex. 2, so VGS = -0.178 V.
10 k Ci 8 k
Co
vi
vo
+
+
vs
+
io
ii
D
S
G
18 V 18 V
800 k
500
400 k
The JFET has the following specifications:ΙDSS = 4 mA, VP = -1.46 V, rd = 50 k
CSS vi
_ _
_
2 k
PE-Electrical Review Course - Class 4 (Transistors)
Example 7:
Find the mid-frequency values for Avi, Avs, AI, AP, Zi, and Zo for the amplifier shown below. Assume that Ci, Co, and CSS are large.Note that this is the same biasing circuit used in Ex. 2, so VGS = -0.178 V.
10 k Ci 8 k
Co
vi
vo
+
+
vs
+
io
ii
D
S
G
18 V 18 V
800 k
500
400 k
The JFET has the following specifications:ΙDSS = 4 mA, VP = -1.46 V, rd = 50 k
CSS vi
_ _
_
2 k
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FET Amplifier Configurations and Relationships:
'' ' m L
vi m L m L 'm L
'L d D L d D L SS L
CS CG CDg RA -g R g R
1 g RR r R R r R R R R
+Rs Ci
RL
Co
CSS vi
vo
+
+
vs
+
_ _
_
io
ii
D
S
G
VDD
VDD
R1
RSS
RD
R2
i Th SS Thm
o d D d D SSm
i i ivs vi vi vi
s i s i s i
i i i
1Z R R Rg
1Z r R r R Rg
Z Z ZA A A AR + Z R + Z R + Z
Z Z Z
⎡ ⎤ ⎡ ⎤ ⎡ ⎤⎢ ⎥ ⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦ ⎣ ⎦⎡ ⎤ ⎡ ⎤ ⎡ ⎤
VCC
RD
S
R2
RSS
Rs Ci
RL
Co
C2
vi vo
+
+
vs
+
_ _ _
io ii
Common Gate (CG) Amplifier
R1
D
G
Common Source (CS) Amplifier
i i iI vi vi vi
L L L
P vi I vi I
Z Z ZA A A AR R R
A A A A A
⎡ ⎤ ⎡ ⎤ ⎡ ⎤⎢ ⎥ ⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦ ⎣ ⎦
vi I
Th 1 2
A A
where R = R R
Note: The biasing circuit is the same for each amp.
Rs Ci
vi
+
vs
+
__
ii G
VDD VDD
R1
RSS
R2
Common Drain (CD) Amplifier (also called “source follower”)
RL
Co
vo
+
_
io
D
S
Figure: Circuit symbol for an enhancement-mode n-channel MOSFET.
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Figure: n-Channel Enhancement MOSFET showing channel length L and channel width W.
Figure: For vGS < Vto the pn junction between drain and body is reverse biased and iD=0.
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Figure: For vGS >Vto a channel of n-type material is induced in the region under the gate. As vGS increases, the channel becomes thicker. For small values of vDS ,iD is proportional to vDS.
The device behaves as a resistor whose value depends on vGS.
Figure: As vDS increases, the channel pinches down at the drain end and iD increases more slowly. Finally for vDS> vGS -Vto, iD becomes constant.
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Current-Voltage Relationship of n-EMOSFET
Locus of points where
Figure: Drain characteristics
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Figure: This circuit can be used to plot drain characteristics.
Figure: Diodes protect the oxide layer from destruction by static electric charge.
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Figure: Simple NMOS amplifier circuit and Characteristics with load line.
Figure: Drain characteristics and load line
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Figure vDS versus time for the circuit of Figure 5.13.
Figure Fixed- plus self-bias circuit.
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Figure Graphical solution of Equations (5.17) and (5.18).
Figure Fixed- plus self-biased circuit of Example 5.3.
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Figure The more nearly horizontal bias line results in less change in the Q-point.
Figure Small-signal equivalent circuit for FETs.
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Figure FET small-signal equivalent circuit that accounts for the dependence of iD on vDS.
Figure Determination of gm and rd. See Example 5.5.
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Figure Common-source amplifier.
For drawing an a c equivalent circuit of Amp.•Assume all Capacitors C1, C2, Cs as short circuit elements for ac signal•Short circuit the d c supply•Replace the FET by its small signal modelReplace the FET by its small signal model
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Analysis of CS Amplifier
A C Equivalent Circuit
gs
ov v
vA = gain, Voltage
Simplified A C Equivalent Circuit
LgsmLoo
gs
RvgRiv −==∴
dDLLmgs
ov
rRRRgv
vA =−==∴ ,
Dd
DdDdo Rr
RrRrZ
+== imp., put Out
21 imp., Input RRRZ
Gin==
Analysis of CS Amplifier with Potential Divider Bias
)R||(rgAv Ddm−=
This is a CS amplifier configuration therefore the input is on the gate and the output is on the drain. 21 R||RZi =
DR10r D,m
dRgAv ≥−≅ Q
)R||(rgAv Ddm−= Dd R||rZo =
DdD 10RrRZo ≥≅
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Figure vo(t) and vin(t) versus time for the common-source amplifier of Figure 5.28.
An Amplifier Circuit using MOSFET(CS Amp.)
Figure Common-source amplifier.
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A small signal equivalent circuit of CS Amp.
Figure Small-signal equivalent circuit for the common-source amplifier.
Figure vo(t) and vin(t) versus time for the common-source amplifier of Figure 5.28.
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Figure Gain magnitude versus frequency for the common-source amplifier of Figure 5.28.
Figure Source follower.
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Figure Small-signal ac equivalent circuit for the source follower.
Figure Equivalent circuit used to find the output resistance of the source follower.
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Figure Common-gate amplifier.
Figure See Exercise 5.12.
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Figure Drain current versus drain-to-source voltage for zero gate-to-source voltage.
Figure n-Channel depletion MOSFET.
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Figure Characteristic curves for an NMOS transistor.
Figure Drain current versus vGS in the saturation region for n-channel devices.
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Figure p-Channel FET circuit symbols. These are the same as the circuit symbols for n-channel devices,except for the directions of the arrowheads.
Figure Drain current versus vGS for several types of FETs. iD is referenced into the drain terminal for n-channel devices and out of the drain for p-channel devices.
