FFT MegaCore Function User Guide -...

A-UG-FFT-1.02

MegaCore Function

FFT

101 Innovation DriveSan Jose, CA 95134(408) 544-7000http://www.altera.com

March 2001User Guide

Version 1.02

http://www.altera.com

ii Altera Corporation

FFT MegaCore Function User Guide

Altera, ACEX, APEX, APEX 20K, FLEX, FLEX 10KE, MAX+PLUS II, MegaCore, MegaWizard, OpenCore, and Quartus aretrademarks and/or service marks of Altera Corporation in the United States and other countries. Altera Corporationacknowledges the trademarks of other organizations for their respective products or services mentioned in this document,including the following: Verilog is a registered trademark of Cadence Design Systems, Incorporated. Java is a trademark of SunMicrosystems Inc. ModelSim is a trademark of Model Technologies. MATLAB is a registered trademark of the MathWorks.Microsoft is a registered trademark and Windows is a trademark of Microsoft Corporation. Altera products are protected undernumerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance ofits semiconductor products to current specifications in accordance with Altera’s standard warranty, but reservesthe right to make changes to any products and services at any time without notice. Altera assumes noresponsibility or liability arising out of the application or use of any information, product, or service describedherein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain thelatest version of device specifications before relying on any published information and before placing orders forproducts or services.

Copyright 2001 Altera Corporation. All rights reserved.

User Guide

About this User Guide

This user guide provides comprehensive information about the Altera® FFT MegaCore® function.

Table 1 shows the user guide revision history.

How to Find Information

� The Adobe Acrobat Find feature allows you to search the contents of a PDF file. Click on the binoculars icon in the top toolbar to open the Find dialog box.

� Bookmarks serve as an additional table of contents.� Thumbnail icons, which provide miniature previews of each page,

provide a link to the pages.� Numerous links, shown in green text, allow you to jump to related

information.

Table 1. Revision History

Revision Date Description

1.0 Jan 19th 2001 First release.

1.01 Jan 24th 2001 MegaWizard screen shots updated.

1.02 Mar 23rd 2001 JRE Runtime Environment information removed.

Altera Corporation iii

About this User Guide FFT MegaCore Function User Guide

How to Contact Altera

For the most up-to-date information about Altera products, go to the Altera world-wide web site at http://www.altera.com.

For additional information about Altera products, consult the sources shown in Table 2.

Note:(1) You can also contact your local Altera sales office or sales representative.

Table 2. How to Contact Altera

Information Type Access USA & Canada All Other Locations

Altera Literature Services

Electronic mail [email protected] (1) [email protected] (1)

Non-technical customer service

Telephone hotline (800) SOS-EPLD (408) 544-7000 (7:30 a.m. to 5:30 p.m. Pacific Time)

Fax (408) 544-7606 (408) 544-7606

Technical support Telephone hotline (800) 800-EPLD(6:00 a.m. to 6:00 p.m. Pacific Time)

(408) 544-7000 (1)(7:30 a.m. to 5:30 p.m. Pacific Time)

Fax (408) 544-6401 (408) 544-6401 (1)

Electronic mail [email protected] [email protected]

FTP site ftp.altera.com ftp.altera.com

General product information

Telephone (408) 544-7104 (408) 544-7104 (1)

World-wide web site http://www.altera.com http://www.altera.com

iv Altera Corporation




mailto:[email protected]




ftp.altera.com

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FFT MegaCore Function User Guide About this User Guide

Typographic Conventions

The FFT MegaCore Function User Guide uses the typographic conventions shown in Table 3.

Table 3. Conventions

Visual Cue Meaning

Bold Type with Initial Capital Letters

Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.

bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \maxplus2 directory, d: drive, chiptrip.gdf file.

Bold italic type Book titles are shown in bold italic type with initial capital letters. Example: 1999 Device Data Book.

Italic Type with Initial Capital Letters

Document titles are shown in italic type with initial capital letters. Example: AN 75 (High-Speed Board Design).

Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu.

“Subheading Title” References to sections within a document and titles of Quartus and MAX+PLUS II Help topics are shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX 8000 Device with the BitBlaster™ Download Cable.”

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix _n, e.g., reset_n.

Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\max2work\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.

1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.

� Bullets are used in a list of items when the sequence of the items is not important.

� The checkmark indicates a procedure that consists of one step only.

� The hand points to information that requires special attention.

� The angled arrow indicates you should press the Enter key.

� The feet direct you to more information on a particular topic.

Altera Corporation v

Notes:

Contents

User Guide

About this User Guide ............................................................................................................................... iiiHow to Find Information .............................................................................................................. iiiHow to Contact Altera .................................................................................................................. ivTypographic Conventions ............................................................................................................. v

Specifications ................................................................................................................................................9Features .............................................................................................................................................9General Description .........................................................................................................................9Functional Description ..................................................................................................................11

Transforms ..............................................................................................................................14Reference Designs ..................................................................................................................14Timing Diagrams ...................................................................................................................16

MegaWizard Plug-In Manager ....................................................................................................18Performance ....................................................................................................................................18

Getting Started ............................................................................................................................................21Downloading & Installing the Function ....................................................................................21

Obtaining MegaCore Functions ...........................................................................................22Installing the MegaCore Files ...............................................................................................22

Generating a Custom FFT Function ............................................................................................22AHDL Reference Designs .............................................................................................................26Using the MATLAB Utilities ........................................................................................................26

FFTVECA Utility ....................................................................................................................27FFTTBLA Utility .....................................................................................................................29

Using the Command Line Utilities ..............................................................................................29FFTVECA Utility ....................................................................................................................29FFTTBLA Utility .....................................................................................................................31

Compiling & Simulating ...............................................................................................................31In the Quartus Software ........................................................................................................32In the MAX+PLUS II Software .............................................................................................32

Performing Synthesis, Compilation & Post-Routing Simulation ............................................32In the Quartus Software ........................................................................................................33In the MAX+PLUS II Software .............................................................................................34

Configuring a Device .....................................................................................................................34

Altera Corporation vii

Notes:

User Guide

1

SpecificationsSpecifications

Features � Uses radix 4 and mixed radix 4 and 2 implementations� Block floating-point techniques—maintain the maximum dynamic

range of the data during processing.� Interfaces to on-chip or off-chip memory� System clock frequency > 100 MHz� Easy-to-use MegaWizard® Plug-In� MATLAB and command line simulation utilities� Two reference designs� Optimized for the APEX™ 20K, ACEX™ 1K, and FLEX® 10KE device

architectures� Fast Fourier transform (FFT) and inverse FFT (IFFT) implementations

General Description

The Altera® FFT MegaCore® function is a parameterizeable core for high performance applications that implements complex input and output transforms for FFT and IFFT. The core uses an in-place mixed radix 4 and 2 decimation in frequency architecture, and implements any transform length that is a power of 2. Partitioning between radix 4 and radix 2 passes is implemented automatically by the core’s control unit. When the desired FFT length is not a power of 4, the processor automatically switches between radix 4 and radix 2 processing to achieve the required transform length.

The core can use a combination of on-chip (internal) or off-chip (external) memories, but it does not include memory for data, intermediate storage, twiddle ROM, or any interfaces required to load and unload data memory. When using off-chip memory, the core requires two banks of data RAM for storage of the input data, output data, and intermediate processing values. Two reference designs are provided as examples of how to implement both types of memory interfaces. The core takes advantage of the dual port memory on APEX 20K, ACEX 1K, and FLEX 10KE devices, when internal memory is selected. Other devices can be used (FLEX 10K, and FLEX 6000), but you must implement the core’s memory requirements externally.

The core automatically generates all addresses for the data RAM and twiddle ROM accesses, and implements a block floating point system for maximum accuracy.

Altera Corporation 9

Specifications FFT MegaCore Function User Guide

The core reads in data in normal sequence. After processing, the final result is in digit-reversed format for a pure radix 4 FFT, or both digit and bit reversed format for a mixed radix 4 and radix 2 FFT. The reference designs include code to return data in normal order.

You can specify the core’s block floating point exponent width, the transform length, and the precision—the data precision and the twiddle precision are set independently.

10 Altera Corporation

FFT MegaCore Function User Guide Specifications

1

Specifications

Functional Description

Table 1 shows the core’s parameters.

Notes:(1) Automatically selected by the MegaWizard Plug-In and is equal to log2(points).(2) The core expects access delay to the twiddle ROM. When using internal twiddle ROM, you must add another delay

stage to the input and the output of the twiddle ROM, which equalizes the overall access delay to the twiddle ROM. (3) The data RAM and twiddle ROM are synchronous. You can make external asynchronous ROM appear synchronous

by registering the address and the data as they go to and from the memory (in addition to any delays automatically added to the core by the interface parameter). For the data RAM, this is more difficult, as any write enable pulse generally requires a set-up and hold time for the data and address inputs to the RAM. However, there are several commercial synchronous RAMs available that can be used, e.g. Micron MT58L256L32D or Cypress CY7C1335.

Table 1. Parameters

Parameter Range Description

datawidth 8 to 24 bits The precision of the input data and output data. It is also the precision of the intermediate values during processing of the FFT.

twiddlewidth 8 to 24 bits The precision of the twiddle factors.

addresswidth (1) The address width.

floatwidth 3 to 8 To implement block floating point, the exponent is held in a floatwidth wide word. On each pass of a radix 4 FFT, the word length increases by 2 bits. floatwidth must be increased for an IFFT, to accomodate the division by points (in the IFFT the normalization is performed in the exponent, which avoids loss of numerical precision in the fixed point output).

points 24 to 220 The transform length.

interface ‘internal’ or ‘external’

When interface is set to ‘internal’ the core is set up to use internal memory for the data RAM banks and the twiddle ROM. When interface is set to ‘external’, the core is set up to use external memory for the data RAM banks and the twiddle ROM, and inserts additional pipelining stages on its interfaces, which can be placed in the I/O cells of the device, allowing higher device performance. (2), (3)

transform FFT or IFFT Selects an FFT or an IFFT core.



Table 2 shows the input signals.

Table 3 shows the output signals.

Table 2. Input Signals

Signal Name Description

sysclk The system clock. All memory accesses and processing are at the system clock rate.

reset reset is an asynchronous, active high signal and must be asserted before the first FFT operation.

go When high, go starts the FFT processing anew block of data. go must be kept high until done goes high, otherwise the current FFT operation is aborted.

realdatain[datawidth..1]

imagdatain[datawidth..1]

These buses are for the real and imaginary components of the data and intermediate values stored in the memory bank.

realtwid[twiddlewidth..1]

imagtwid[twiddlewidth..1]

These buses are for the real and imaginary components of the twiddle factors.

Table 3. Output Signals (Part 1 of 2)


realdataout[datawidth..1]

imagdataout[datawidth..1]

These buses are the real and imaginary components of the butterfly results that are written to the data memory.

readaddress[addresswidth..1] readaddress[] contains the read address for the data memory.

writeaddress[addresswidth..1] writeaddress[] contains the write address for the data memory.

twidaddress[addresswidth..1] twidaddress[] contains the read address for the twiddle memories.

exponent[(floatwidth+1)..1] exponent[] gives the final scaling factor of the FFT data in twos complement form, compared to a floating point transform. For example, if the exponent is –6, you must multiply the core output by 26 for the values to be correct. Alternately, you can use exponent[] to control an output multiplexer of a FFT system design, to perform the multiplication.

done When high, the core has completed processing the last FFT. You can now read out of the data memory.

writeenable (1) writeenable enables the synchronous memory. You can only write data to the synchronous RAM when writeenable is low. writeenable should be connected to the write enable of the data RAM.



1

Specifications

Notes:(1) Only used when interface is internal. (2) Only used when interface is external.

direction (2) You must derive the memory write enable from the direction signal such that the left bank is enabled when direction is high, and the write bank is enabled when it is low. The core does not stop at anytime during processing, so the direction signal is the only write enable control for the left and write memory banks, until done is asserted when you must stop writing to the memories.

Table 3. Output Signals (Part 2 of 2)




Transforms

The core computes the forward transform as given in equation 1, and inverse transforms as given in equation 2.

points – 1

F(k) = Σf(n)e–j2πnk/points (1)n = 0

where k = 0, ..., points – 1

points – 1

f(n) = (1/points) ΣF(k)ej2πnk/points (2)k = 0

where n = 0, ..., points – 1

Reference Designs

The core is provided with two reference designs, which show you how the variations produced by the MegaWizard Plug-In are connected in a design. Reference design A shows you how to connect the core to internal dual-ported RAM and twiddle ROM; reference design B shows you how to connect to external data RAM and twiddle ROM. Both reference designs contain logic that implements bit reversed and digit reversed addressing.

Reference design A (aukfft_fftchipa) shows you how to connect the example variation, example_ffta, which uses internal memory. Figure 1 shows reference design A. Most of the connection glue logic is implemented in subcomponents. The aukfft_twidrom subcomponent instantiates reduced ROMs, and logic to recover the full data set. The aukfft_ram_dp subcomponent implements the data RAM, and includes an interface for direct connection to the core’s user interface. The glue logic that is required to arbitrate between the user interface and the core is also implemented in this subcomponent.



1

Specifications

Figure 1. Reference Design A

Reference design B (aukfft_fftchipb) shows you how to connect the example variation, example_fftb, which uses external memory. Figure 2 shows reference design B. Most of the connection glue logic is implemented in subcomponents. aukfft_xlrbufferif, implements the control logic that decodes the RAM bank that the core is reading from and writing to. Also, the glue logic that is required to arbitrate between the user interface and the core is implemented in this subcomponent. All of the memories are in the top level and have been labeled as external, which allows the external design to be simulated. When you compile for use with external memory, the required input and output signals must be added to the design interface, and the memory instance removed from the design.

If you want to use a mixture of internal and external memory, e.g., external data RAM and internal twiddle ROM, use reference design B as a basis for your design and take the interface signals for the required external memory to the top-level interface. If reference design B is compiled without any modifications, all the memories are implemented as internal memories, but this is less efficient than using reference design A.

writeenable

readaddress

writeaddress

realdataout

imagdataout

realdatain

imagdatain

go

exponent

done

twidaddress

realtwid

imagtwid

address

twreal

twimag

fftwriteenable

fftreadaddress

fftwriteaddress

fftrealdataout

fftimagdataout

fftrealdatain

fftimagdatain

read

write

writeaddress

readaddress

writereal

writeimag

readreal

readimag

aukfft_ram_dp

User Interface

example_fftaaukfft_twidrom

User Interface



Figure 2. Reference Design B

Timing Diagrams

Figure 3 shows the FFT core signals. The resolution of the diagram is such that the inclusion of sysclk is not practical. This is also true of the address and data buses where activity is shown rather than explicit edges. It is assumed that the incoming data has been written to the left memory bank.

exponent varies as data is being processed, because the core is trying to maintain maximum dynamic range using block floating-point techniques.

aukfft_fftchipb

Left External RAM Data Bank aukfft_xlrbufferif Right External

RAM Data Bank

example_fftb

User Interface

aukfft_xtwidromif

External Twiddle ROM



1

Specifications

Figure 3. FFT Core Signals

The twiddle ROM is read from continuously while processing and the core is designed to work with synchronous memories.

The read address/control is registered as it enters the synchronous memory and the data is registered on its way out, which results in a two clock cycle delay (see Figure 4).

Figure 4. Read Data Delay (Internal Memory)

When using external memory, the read address/control is registered on its way out and the returning data is registered on its way in, this is performed by the interface logic. This is in addition to the synchronous external memory (see Figure 5).

Figure 5. Read Data Delay (External Memory)

reset

go

done

writeenable

readaddress

writeaddress

realdatain, imagdatain

realdataout, imagdataout

realtwid, imagtwid

twidaddress

exponent

sysclk

readaddress[10:0]

realdatain[7:0]

imagdatain[7:0]

addr 0 addr 1 addr 2 addr 3 addr 4 addr 5 addr 6 addr 7

data 0 data 1 data 2 data 3 data 4 data 5

data 0 data 1 data 2 data 3 data 4 data 5

sysclk

readaddress[10:0]

realdatain[7:0]

imagdatain[7:0]

addr 0 addr 1 addr 2 addr 3 addr 4 addr 5 addr 6 addr 7

data 0 data 1 data 2 data 3

data 0 data 1 data 2 data 3



MegaWizard Plug-In Manager

The FFT MegaCore function has an interactive wizard-driven interface that allows you to create custom FFT functions easily. You can launch the MegaWizard Plug-In Manager from within the Quartus or MAX+PLUS II software, or you can run it from the command line. The wizard allows you to input your choice of parameters, verifies that all choices are valid, and generates a custom MegaCore function in VHDL, AHDL, or Verilog HDL, which you can integrate into your system design.

When you finish going through the wizard it generates:

� One of the following files (depending on your selection), which are used to instantiate an instance of the function in your design:– An AHDL Text Design File (.tdf) – A VHDL Design File (.vhd) – Verilog Design File (.v)

� Symbol Files (.bsf for the Quartus software, .sym for the MAX+PLUS II software) used to instantiate the function into a schematic design

� Two memory initialization files (.hex), which contain the twiddle ROM values

Performance The datawidth and twiddlewidth parameters have the biggest impact on size and performance—the logic and memory resources required by the core are essentially linear to each precision. All other parameters have little effect on the required logic resources, however points has a linear effect on the required memory resources.

The number of LEs (approximately) used by the core is given by:

10 × datawidth × twiddlewidth

The amount of RAM (in bits) required is given by:

2 × datawidth × points

The amount of twiddle ROM (in bits) required is given by:

twiddlewidth × points/2

The performance of the core is dependent on:

� the clock rate of the system � the number of clocks cycles required to calculate the FFT

The number of clock cycles is given by:

‘number of passes’ × ‘number of clock cycles per pass’



1

Specifications

where:

‘number of passes’ = ceiling(log2points/2)

‘number of clock cycles per pass’ = 14 + points + ceiling(log2twiddlewidth)

For example, points = 1024, twiddlewidth = 16, ‘number of passes’ = 5, ‘clock cycles per pass’ = 1042, and ‘number of clock cycles’ = 5210.

With a 100 MHz system clock the core needs 52 µs to calculate the FFT.



Tables 4 and 5 shows examples of the performance and size of the core, for the reference design A, with different devices.

Notes:(1) The Quartus software (version 2000.09) compiler settings were: auto device select, any package, any pin count,

fastest speed grade, full compilation, smart compilation, advanced power fit fitter, optimize I/O timing, and optimize internal timing.

(2) LEs: logic elements(3) ESBs: embedded system blocks

Table 4. Performance and Size for APEX 20KE Devices Note (1)

FFT or IFFT

Device floatwidth

datawidth

twiddlewidth

points Size (2)

Memory(3)

fMAX(MHz)

Transform Time (µs)

FFT EP20K60E-1 5 8 8 64 1,232 2 126 2

IFFT EP20K60E-1 5 8 8 64 1,257 2 149 2

FFT EP20K60E-1 5 8 8 512 1,325 5 150 17

IFFT EP20K60E-1 5 8 8 512 1,330 5 139 19

FFT EP20K200E-1 5 8 8 4,096 1,390 40 112 220

IFFT EP20K200E-1 5 8 8 4,096 1,394 40 116 212

FFT EP20K1500E-1 5 8 8 16,384 1,518 160 69 1663

IFFT EP20K1500E-1 5 8 8 16,384 1,523 160 73 1572

FFT EP20K100E-1 5 16 16 64 3,022 4 98 1

IFFT EP20K100E-1 5 16 16 64 3,027 4 98 1

FFT EP20K100E-1 5 16 16 512 3,116 10 96 27

IFFT EP20K100E-1 5 16 16 512 3,121 10 101 26

FFT EP20K100E-1 5 16 16 1,024 3,126 20 100 52

IFFT EP20K100E-1 5 16 16 1,024 3,131 20 96 54

FFT EP20K400E-1 5 16 16 4,096 3,198 80 94 262

IFFT EP20K400E-1 5 16 16 4,096 3,202 80 86 287

FFT EP20K1500E-1 5 16 16 8,192 3,271 160 64 897

IFFT EP20K1500E-1 5 16 16 8,192 3,276 160 58 990

FFT EP20K160E-1 5 24 24 64 5,339 6 70 4

IFFT EP20K160E-1 5 24 24 64 5,344 6 75 3

FFT EP20K160E-1 5 24 24 512 5,433 15 75 35

IFFT EP20K160E-1 5 24 24 512 5,438 15 70 37

FFT EP20K600E-1 5 24 24 4,096 5,531 120 82 300

IFFT EP20K600E-1 5 24 24 4,096 5,535 120 76 324



1

Specifications

Notes:(1) The MAX+PLUS II software (version 9.6) settings were: Filter Settings (Processing menu) use Quartus fitter and

Advanced Try Harder; Global Project Timing Requirements (Assign menu) 150 MHz fMAX; Global Project Logic Synthesis (Assign menu) fast and optimize speed 10.

(2) LCs: logic cells(3) EABs: embedded array blocks

Table 5. Performance and Size for FLEX 10KE Devices Note (1)

FFT or IFFT

Device floatwidth

datawidth

twiddlewidth

points Size (2)

Memory(3)

fMAX(MHz)

Transform Time

FFT EPF10K30E-1 5 8 8 64 1,165 2 135 2

IFFT EPF10K30E-1 5 8 8 64 1,170 2 135 2

FFT EPF10K30E-1 5 8 8 512 1,231 3 120 22

IFFT EPF10K30E-1 5 8 8 512 1,237 3 129 20

FFT EPF10K200S-1 5 8 8 4,096 1,299 20

IFFT EPF10K200S-1 5 8 8 4,096 1,302 20 74 333

FFT EPF10K100E-1 5 16 16 64 2,984 4 94 1

IFFT EPF10K100E-1 5 16 16 64 2,989 4 87 1

FFT EPF10K100E-1 5 16 16 512 3,050 6 95 27

IFFT EPF10K100E-1 5 16 16 512 3,056 6 94 28

FFT EPF10K100E-1 5 16 16 1,024 3,050 10 90 57

IFFT EPF10K100E-1 5 16 16 1,024 3,061 10 89 58

FFT EPF10K200S-1 5 16 16 2,048 3,066 20 61 372

IFFT EPF10K200S-1 5 16 16 2,048 3,089 20 64 355

FFT EPF10K130E-1 5 24 24 64 5,757 6 62 4

IFFT EPF10K130E-1 5 24 24 64 5,762 6 64 4

FFT EPF10K130E-1 5 24 24 512 5,823 9 58 45

IFFT EPF10K130E-1 5 24 24 512 5,829 9 62 42

FFT EPF10K130E-1 5 24 24 1,024 5,833 15 58 89

IFFT EPF10K130E-1 5 24 24 1,024 5,838 15 58 89


Notes:

User Guide

2

Getting StartedGetting Started

This section describes how to obtain the FFT MegaCore® function, explains how to install it on your PC, and walks you through the process of implementing the function in a design. You can test-drive MegaCore functions using the Altera OpenCore™ feature to simulate the functions within your custom logic. When you are ready to generate programming or configuration files, you should license the function through the Altera web site or through your local Altera sales representative. This walk-through involves the following steps:

1. Downloading and installing the FFT MegaCore function.

2. Generating a custom MegaCore function.

3. Implementing your system using AHDL, VHDL, or Verilog HDL.

4. Compiling your design.

5. Simulating your design to confirm the operation of your system.

6. Licensing the FFT MegaCore function and configuring the devices.

The instructions assume that:

� You are using a PC.� You are familiar with either the Quartus™ or MAX+PLUS® II

software.� Quartus version 2000.09 (or higher) is installed in the default location

(c:\quartus), or MAX+PLUS II version 10 (or higher) is installed in the default location (c:\maxplus2).

� You are using the OpenCore feature to test-drive the FFT MegaCore function or you have licensed the function.

Downloading & Installing the Function

Before you can start using Altera MegaCore functions, you must obtain the MegaCore files and install them on your PC. The following instructions describe this process.


Getting Started FFT MegaCore Function User Guide

Obtaining MegaCore Functions

If you have Internet access, you can download the FFT MegaCore function from the Altera web site at http://www.altera.com. Follow the instructions below to obtain the FFT MegaCore function via the Internet. If you do not have Internet access, you can obtain the FFT MegaCore function from your local Altera representative.

1. Point your web browser at http://www.altera.com/IPmegastore.

2. In the IP MegaSearch keyword field type FFT.

3. Click the appropriate link for your desired MegaCore function.

4. Click the link for the download icon.

5. Follow the online instructions to download the function and save it to your hard disk.

Installing the MegaCore Files

For Windows, follow the instructions below:

1. Click Run (Start menu).

2. Type <path name>\<file name>, where <path name> is the location of the downloaded MegaCore function and <file name> is the filename of the function. Click OK.

3. The MegaCore Installer dialog box appears. Follow the online instructions to finish installation.

4. After you have finished installing the MegaCore files, you must specify the MegaCore function’s library folder (\FFT v1.0.2\lib) as a user library in the Quartus and MAX+PLUS II software. Search for ‘User Libraries’ in Quartus or MAX+PLUS II Help for instructions on how to add a library.

Generating a Custom FFT Function

This section describes the design flow using the Altera FFT MegaCore function and the Quartus or MAX+PLUS II development system. Altera provides a MegaWizard® Plug-In Manager with the FFT MegaCore function. The MegaWizard Plug-In Manager, which you can use within the Quartus or MAX+PLUS II software or as a stand-alone application, lets you create or modify design files to meet the needs of your application. You can then instantiate the custom megafunction in your design file.


http://www.altera.com/IPmegastore


FFT MegaCore Function User Guide GettingGetting Started

2

Getting Started

You can use the Altera OpenCore feature to compile and simulate the MegaCore functions in the Quartus or MAX+PLUS II software, allowing you to evaluate the functions before deciding to license them.

� If you are using the MAX+PLUS II software, use version 9.3 or higher when designing with this MegaCore function. The function relies on library files that exist only in these versions of software.

To create a custom version of the FFT MegaCore function, follow these steps:

1. Start the MegaWizard Plug-In Manager by choosing the MegaWizard Plug-In Manager command (Tools menu in the Quartus software, File menu in any MAX+PLUS II application), or by starting the stand-alone version of the MegaWizard Plug-In Manager by typing the command megawiz � at a command line. The MegaWizard Plug-In Manager dialog box is displayed.

� Refer to the Quartus or MAX+PLUS II Help for more information on how to use the MegaWizard Plug-In Manager.

2. Specify that you want to create a new custom megafunction and click Next.

3. Select FFT v1.0.2 in the DSP folder (see Figure 1).



Figure 1. Selecting the Megafunction

4. Choose the language for the output file(s)—either AHDL, VHDL, or Verilog HDL—and specify a name for the output file, <custom name>. Click Next.

5. Select the parameter values that you require. See Table 1 on page 11 for a description of the parameters. The MegaWizard Plug-In only allows you to select legal combinations of parameters, and warns you of any invalid configurations. Select either the internal or the external memory interface radio button (see Figure 2). Click Next.



2

Getting Started

Figure 2. Selecting the Parameters

6. The final screen lists the main design files that the wizard creates (see Figure 3). The wizard creates two additional files <custom name>_inst and <custom name>_bb. Click Finish.

Figure 3. Summary of Files Generated

When you have created your custom megafunction, you should connect it to memory and provide an interface for reading and writing data. The reference designs show you how to achieve this, for memories that are either internal or external.



AHDL Reference Designs

The FFT MegaCore function is supplied with two AHDL reference designs—A (aukfft_fftchipa.tdf), which shows you how to connect to internal dual-ported RAM and twiddle ROM; and B (aukfft_fftchipb.tdf), which shows you how to connect to external data RAM and twiddle ROM. You can use the reference designs to simulate the functionality of the core in your system. The reference designs are:

� Supplied as source code� Synthesizable� Intended to be used as a basis for your design

Both reference designs determine the final destination data bank at compile time, and attach the reference design’s read interface automatically.

To use the reference design with your MegaWizard generated files, perform the following steps:

1. Open the relevant reference design in a text editor.

2. Change the name of any components with the prefix example_ffta or example_fftb to <custom name>. Change example_ffta_twidsin.hex or example_fftb_twidsin.hex to <custom name>_twidsin.hex. Change example_ffta_twidcos.hex or example_fftb_twidcos.hex to <custom name>_twidcos.hex.

3. Change the reference design’s paramenters to match your wizard generated parameters.

4. Save the reference design in your project folder.

Using the MATLAB Utilities

Altera provides two MATLAB utilities to test the FFT MegaCore function. These utilities (FFTVECA.m and FFTTBLA.m) work with reference design A.

� For more information on MATLAB, refer to the Math Works website at http://www.mathworks.com.

Before you use the MATLAB utilities, you must generate twiddle ROM data for the reference design.


http://www.mathworks.com


2

Getting Started

� Altera recommends you create a working folder <project> into which you copy the reference design A from the fft\reference_design folder (aukfft_fftchipa.tdf, example_ffta.bsf, example_ffta.cmp, example_ffta.inc, example_ffta.tdf, example_ffta_twidsin.hex, example_ffta_twidcos.hex, aukfft_twidrom.tdf, and aukfft_ram_dp.tdf).

You are now ready to use the MATLAB utilities.

FFTVECA Utility

FFTVECA.m creates a vector simulation file (.vec) from a MATLAB input vector. To create the .vec file perform the following steps:

1. Open the MATLAB software. At the command prompt change the folder to \fft\matlab.

2. Create an input vector <vec> in MATLAB, with completely random data, by typing the following command:

>> maxvalue = 2^(datawidth) – 1;�>> rr = rand(1,points);� % create a random vector>> rr = rr - .5;�% make positive and negative

% vector components>> ss = rand(1,points);�>> ss = ss - .5;�>> vec = floor (rr*maxvalue + i*ss*maxvalue);�

% vector has real and imaginary components, % scale to maximum value.

where points and datawidth are the same values as in reference design A (default values: points = 512, datawidth = 8, floatwidth = 5).

3. Call the utility, which creates a file aukfft_fftchipa.vec in the \fft\matlab folder, by typing the parameters and values as shown:

FFTVECA (<vec>, points, datawidth, floatwidth)�

e.g.

FFTVECA (vec, 512, 8, 5)�



In the Quartus Software

1. Set-up a new project with the copy of reference design A as the design.

2. Click Start Compilation (Processing Menu) to compile your design.

3. Click Simulation Mode (Processing menu). Choose Simulator Settings (Processing menu) and select the Time/Vectors tab. In the Source of Vector Stimuli box, select aukfft_fftchipa.vec. Click OK.

4. Click Run Simulation (Processing menu) to begin simulation.

5. Close the Report window. Click Open (File menu). In the Files of Type box select waveform vector files, and open aukfft_fftchipa-sim.vwf (this is in the <project>\db folder). Change all signals to hexadecimal and save this file as a vector table output file, aukfft_fftchipa.tbl, in the \fft\matlab folder.

In the MAX+PLUS II Software

1. Click Open (File menu) and select reference design A, <project>\aukfft_fftchipa.tdf.

2. Click Project (File menu) and select Set Project to Current File.

3. Open the MAX+PLUS II compiler.

4. Click Start to compile your design.

5. Open the MAX+PLUS II Simulator.

6. In the MAX+PLUS II software select Inputs/Outputs (File menu) and select aukfft_fftchipa.vec.

7. Run the MAX+PLUS II Simulator, by clicking Start to begin the simulation.

8. Run the MAX+PLUS II Simulator, by clicking Start to begin the simulation. Select Create Table File (File menu). Save this file as aukfft_fftchipa.tbl, in the \fft\matlab folder.



2

Getting Started

FFTTBLA Utility

The FFTTBLA utility is used to extract the result of the FFT into a MATLAB vector. Call the FFTTBLA.m utility as shown:

Y = FFTTBLA (points, datawidth); �

You can now use MATLAB to analyze the results. For example, type in the following command:

Y(90)

Using the Command Line Utilities

If you do not have MATLAB, Altera provide command line utilities (for Windows only) (fftveca.exe and fftbla.exe) that work with reference design A. The command line utilities have the same functionality as the MATLAB utilities of the same name, and you can use them to generate waveforms for test cases.

� Reference design A’s default parameters are: points = 512, datawidth = 8, floatwidth = 5, and twiddlewidth = 8, which you can change.

� Altera recommends you create a working folder <project> into which copy the reference design A from the fft\reference_design folder.

You are now ready to use the command line utilities.

FFTVECA Utility

FFTVECA.exe creates a vector simulation file (.vec). To create the .vec file perform the following steps:

1. Open a command prompt window. Change the folder to fft\bin.

2. Call the utility, which creates a file aukfft_fftchipa.vec in the \fft\bin folder, by typing the parameters and values as shown:

fftveca points datawidth floatwidth waveform amplitude frequency phase

The first three parameters are the same as the core parameters and

� waveform = cosine, cisoid, rand, or impulse� amplitude is given by 0 < amplitude < 2 (datawidth – 1), as a float� frequency is given by – points/2 ≤ frequency ≤ points/2, as a float� phase can be – 0.5 ≤ phase ≤ 0.5, as a float



Cosine is generated from

round (amplitude × cos(2π(n × frequency/points + phase))),

where n = 0,..., points – 1.

Cisoid is generated from

round (amplitude × cos(2π(n × frequency/points + phase)) + √(–1) × sin(2π(n × frequency/points + phase)))),

where n = 0,..., points – 1.

Impulse is generated from

amplitude × (cos(2π × phase) + √(–1) × sin(2π × phase)) in array location zero. All other locations are set to zero.

Rand is generated from

amplitude × uniform(n),

where n = 0,..., points – 1, and uniform(n) is a uniform random number in the range {–1,..., +1}


1. Set-up a new project with the copy of reference design A as the design.


3. Click Simulation Mode (Processing menu). Choose Simulator Settings (Processing menu) and select the Time/Vectors tab. In the Source of Vector Stimuli box, select aukfft_fftchipa.vec. Click OK.


5. Close the Report window. Click Open (File menu). In the Files of Type box select waveform vector files, and open aukfft_fftchipa-sim.vwf (this is in the <project>\db folder). Change all signals to hexadecimal and save this file as a vector table output file, aukfft_fftchipa.tbl, in the \fft\bin folder.



2

Getting Started


1. Click Open (File menu) and select reference design A, <project>\aukfft_fftchipa.tdf.





6. In the MAX+PLUS II software select Inputs/Outputs (File menu) and select aukfft_fftchipa.vec.


8. Run the MAX+PLUS II Simulator, by clicking Start to begin the simulation. Select Create Table File (File menu). Save this file as aukfft_fftchipa.tbl, in the \fft\bin folder.

FFTTBLA Utility

The FFTTBLA utility is used to extract the FFT results from the file aukfft_fftchipa.tbl into the file aukfft_fftout.txt. Call the FFTTBLA.exe utility as shown:

FFTTBLA (points, datawidth); �

The file aukfft_fftout.txt contains the real and imaginary outputs of the FFT in the following format:

real[0] imag[0]real[1] imag[1]..real[points – 1] imag[points – 1]

The exponent is not extracted. This file can be read by the application of your choice for further analysis or visualization, e.g., Microsoft Excel to compute and chart the magnitude and phase.

Compiling & Simulating

The following steps explain how to compile and simulate your design in the Quartus and the MAX+PLUS II software.





2. Click Simulation Mode (Processing menu). Choose Simulator Settings (Processing menu) and select the Time/Vectors tab. In the Source of Vector Stimuli box, select <custom name>.vec, where <custom name> is the name you specified in the MegaWizard Plug-In.



1. Click Open (File menu) and select the MegaWizard generated file <custom name>.tdf, .v or, .vhd, where <custom name> is the name you specified in the MegaWizard Plug-In.





6. In the MAX+PLUS II software select Inputs/Outputs (File menu) and select <custom name>.vec.


8. Click the Open SCF button to view the design’s waveform.

After you have verified that your design is functionally correct, you are ready to perform system verification.

Performing Synthesis, Compilation & Post-Routing Simulation

The Quartus and MAX+PLUS II software work seamlessly with tools from all EDA vendors, including Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, and Viewlogic. After you have licensed the MegaCore function, you can generate EDIF, VHDL, Verilog HDL, and Standard Delay Output Files from the Quartus or MAX+PLUS II software and use them with your existing EDA tools to perform functional modeling and post-route simulation of your design.



2

Getting Started

The following sections describe the design flow to compile and simulate your custom MegaCore design with a third-party EDA tool. To synthesize your design in a third-party EDA tool and perform post-route simulation, perform the following steps:

1. Create your custom design instantiating a FFT MegaCore function.

2. Synthesize the design using your third-party EDA tool. Your EDA tool should treat the MegaCore instantiation as a black box by either setting attributes or ignoring the instantiation.

� For more information on setting compiler options in your third-party EDA tool, refer to the MAX+PLUS II ACCESS Interfaces Guidelines.

3. After compilation, generate a hierarchical netlist file in your third-party EDA tool.

4. Open your netlist file in the Quartus or MAX+PLUS II software.


1. Select Compile mode (Processing Menu).

2. Specify the compiler settings in the Compiler Settings dialog box (Processing menu) or use the Compiler Settings wizard.

3. Specify the user libraries for the project and the order in which the compiler searches the libraries.

4. Specify the input settings for the project. Choose EDA Tool Settings (Project menu). Select Custom EDIF in the Design entry/synthesis tool list. Click Settings. In the EDA Tool Input Settings dialog box, make sure that the relevant tool name or option is selected in the Design Entry/Synthesis Tool list.

5. Depending on the type of output file you want, specify Verilog HDL output settings or VHDL output settings in the General Settings dialog box (Project Menu). Use the 1993 VHDL language option.

6. Compile your design. The Quartus compiler synthesizes and performs place-and-route on your design, and generates output and programming files.

7. Import your Quartus-generated output files (.edo, .vho, .vo, or .sdo) into your third-party EDA tool for post-route, device-level, and system-level simulation.




1. Set your EDIF file as the current project.

2. Choose EDIF Netlist Reader Settings (Interfaces menu).

3. In the EDIF Netlist Reader Settings dialog box, select the vendor for your EDIF netlist file in the Vendor drop-down list box and click OK.

4. Make logic option and/or place-and-route assignments for your custom logic using the commands in the Assign menu.

5. In the MAX+PLUS II compiler, make sure Functional SNF Extractor (Processing menu) is turned off.

6. Turn on the Verilog Netlist Writer or VHDL Netlist Writer command (Interfaces menu), depending on the type of output file you want to use in your third-party simulator. Use the 1993 VHDL language option.

7. Compile your design. The MAX+PLUS II compiler synthesizes and performs place-and-route on your design, and generates output and programming files.

8. Import your MAX+PLUS II-generated output files (.edo, .vho, .vo, or .sdo) into your third-party EDA tool for post-route, device-level, and system-level simulation.

Configuring a Device

After you have compiled and analyzed your design, you are ready to configure your targeted Altera device. If you are evaluating the MegaCore function with the OpenCore feature, you must license the function before you can generate configuration files.


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