1.INTRODUCTION

FIFO is an acronym for First In, First Out, an abstraction in ways of organizing and

manipulation of data relative to time and prioritization. This expression describes the

principle of a queue processing technique or servicing conflicting demands by ordering

process by first-come, first-served (FCFS) behaviour : what comes in first is handled first,

what comes in next waits until the first is finished, etc.

Thus it is analogous to the behaviour of persons queueing (or "standing in line", in common American parlance), where the persons leave the queue in the order they arrive,

or waiting one's turn at a traffic control signal. FCFS is also the shorthand name for the FIFO operating system scheduling algorithm, which gives every process CPU time in the order they come. In the broader sense, the abstraction LIFO, or Last-In-First-Out is the opposite of the abstraction FIFO organization, the difference perhaps is clearest with considering the less commonly used synonym of LIFO, FILO—meaning First-In-Last-Out. In essence, both are specific cases of a more generalized list (which could be accessed anywhere). The difference is not in the list (data), but in the rules for accessing the content. One sub-type adds to one end, and takes off from the other, its opposite takes and puts things only on one end.

A priority queue is a variation on the queue which does not qualify for the name FIFO, because it is not accurately descriptive of that data structure's behavior. Queueing theory encompasses the more general concept of queue, as well as interactions between strict-FIFO queues.

1.1Data structure

In computer science this term refers to the way data stored in a queue is processed. Each item in the queue is stored in a queue (simpliciter) data structure. The first data to be added to the queue will be the first data to be removed, then processing proceeds sequentially in the same order. This is typical behavior for a queue, but see also the LIFO and stack algorithms.

Head or tail first

Authors and users of FIFO queue software should consider carefully the use of the terms "head" and "tail" to refer to the two ends of the queue. To many people, items should enter a queue at the tail, remain in the queue until they reach the head and leave the queue from there. This point of view is justified by analogy with queues of people waiting for some kind of service and parallels the use of "front" and "back" in the above example. Other people, however, believe that you enter a queue at the head and leave at the tail, in the manner of food passing through a snake. Queues written in that way appear in places that might be considered authoritative, such as the GNU/Linux operating system.

Pipes

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In computing environments that support the pipes and filters model for interprocess communication, a FIFO is another name for a named pipe.

Disk Scheduling

Disk controllers can use the FIFO as a disk scheduling algorithm to determine the order to service disk I/O requests.

Communications and networking

Communications bridges, switches and routers used in Computer networks use FIFOs to hold data packets in route to their next destination. Typically at least one FIFO structure is used per network connection. Some devices feature multiple FIFOs for simultaneously and independently queuing different types of information.

Electronics

FIFOs are used commonly in electronic circuits for buffering and flow control which is from hardware to software. In hardware form a FIFO primarily consists of a set of read and write pointers, storage and control logic. Storage may be SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of non-trivial size a dual-port SRAM is usually used where one port is used for writing and the other is used for reading.

A synchronous FIFO is a FIFO where the same clock is used for both reading and writing. An asynchronous FIFO uses different clocks for reading and writing. Asynchronous FIFOs introduce metastability issues. A common implementation of an asynchronous FIFO uses a Gray code (or any unit distance code) for the read and write pointers to ensure reliable flag generation. One further note concerning flag generation is that one must necessarily use pointer arithmetic to generate flags for asynchronous FIFO implementations. Conversely, one may use either a "leaky bucket" approach or pointer arithmetic to generate flags in synchronous FIFO implementations.

Examples of FIFO status flags include: full, empty, almost full, almost empty, etc...

The first known FIFO implemented in electronics was done by Peter Alfke in 1969 at Fairchild Semiconductors. Peter Alfke is now a Director at Xilinx.

FIFO full/empty

In hardware FIFO is used for synchronization purposes. It is often implemented as a circular queue, and thus has two pointers:

1. Read Pointer/Read Address Register 2. Write Pointer/Write Address Register

Read and write addresses are initially both at the first memory location and the FIFO queue is Empty.

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FIFO Empty

When read address register reaches to write address register, the FIFO triggers the Empty

signal.

FIFO Full

When write address register reaches to read address register, the FIFO triggers the FULL

signal.

1.2REAL TIME APPLICATIONS

Real-Time FIFO for Deterministic Data Transfer Between Vis

In LabVIEW Real-Time(RT) applications, you may need to transfer data to or from a VI set to time critical priority (time critical VI). This data can be transferred to or from a non-

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deterministic system, such as over the network to another computer, or to the hard drive. Typically, the data is first transferred to or from a VI set to normal priority, or a priority lower than time critical, which we will call the Communication Loop. Non-deterministic operations can then be performed in the Communication Loop without harming the real-time performance of the Time-critical Loop. The Communication Loop can then communicate with an external application over the network, or perform File I/O.

Figure 1.1 A common real-time application structure

Communicating Data Between VIs

There are three methods to communicate between VIs: global variables, functional globals (a VI that acts like a global variable), and a RT FIFO. FIFO stands for "First In, First Out". Global variables are a lossy form of communication since there can be many writes to the global variable before a read is ever performed, thus data can be lost. Since only one VI can access a global variable at a time, it can cause priority inversions, which in turn cause jitter, or increase execution time, in the time critical loop. Functional globals have a similar behavior. However, with the RT FIFO, a write and a read can be performed at the same time. Also, the RT FIFO acts like a fixed size queue, so that data elements that you write to an RT FIFO do not overwrite previous elements, unless the RT FIFO is full, in which case the oldest element is over written. The RT FIFO can be a lossy communication if the reader does not read elements from the FIFO before the FIFO fills up. The advantage of using the RT FIFO is that even if the reader pauses momentarily, and multiple writes to the RT FIFO occur during that time, data is not lost as long as the reader can catch up and read the elements out of the RT FIFO before it fills up. This document will focus on the third method of communication between VIs: the RT FIFO.

Using RT FIFO

The RT FIFO is simple to use. Its use involves creating the RT FIFO in one VI and either passing the RT FIFO reference to the other VI, or opening a reference to the RT FIFO in the another VI. Then writes to the RT FIFO are performed in one VI, and reads from the RT FIFO performed in another VI, and finally, the RT FIFO is deleted. Figure 2 shows an example of using the RT FIFO, although in this example data is transferred to and from the same VI.

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Figure 1.1B Very Simple RT FIFO Example

Creating an RT FIFO

An RT FIFO is created using the RTFIFOCreate VI. The type of elements that the RT FIFO will contain is determined by type of the data wired to the type input terminal (the RT FIFO VIs are polymorphic). All of the elements in an RT FIFO must be of the same type. RT FIFOs can be created of elements of the following types:

Numeric Waveform

Boolean (Element only)

Clusters of the above datatypes

RT FIFO elements can also be arrays of the same types as listed above. To specify the size of the arrays in each RT FIFO element, first wire an array to the type input terminal, then wire the size for the arrays to the elements in array input terminal. The reference output for the RT FIFO, rt fifo, is a cluster, and will be pink for RT FIFOs with array elements or booleans. In Figure 3, an RT FIFO called Data FIFO is created that contains array elements. In this case each array element has 5 elements.

Figure 1.2. Creating an RT FIFO of Array Elements

The RT FIFO is fixed length, and the memory for the RF FIFO is allocated when the RT FIFO is created. If the RT FIFO was of unlimited length, then it would have to dynamically allocate more memory as the number of elements in the RT FIFO increased.

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Determinism, or real-time behavior, of time critical VIs would be harmed if this dynamic memory allocation occurred inside of the time critical VI. To specify the size of the RT FIFO, wire the desired size to the size input terminal of the RT FIFO Create VI. In Figure 4, an RT FIFO of 20 elements is created.

Figure 1.3. Specifying the RT FIFO Size

Opening a reference to an existing RT FIFO

To open a reference to an existing RT FIFO, use the RTFIFOCreate VI with the name of the RT FIFO wired to the name terminal. If an RT FIFO with that name does not exist, wiring a TRUE wired to the create if not found terminal as shown in Figure 3, will create a new FIFO. Wiring a FALSE to this will create an error code if the RT FIFO is not found.

Figure 1.4. Opening a Reference to an Existing RT FIFO

Writing when full or reading when empty

If you perform a write when the RT FIFO is full and a slot does not become available before the TIMEOUT, the oldest element is overwritten and the timeout output will be TRUE. To avoid overwriting elements, you need to either make sure that the reader will always read elements from the RT FIFO faster than they are written, you need to ensure that the RT FIFO is large enough to contain the elements that are written to it while the reader is unable to read or you can wire a FALSE into the overwrite on timeout input. In the case that overwrite on timeout is FALSE, the data to be written will be disregarded.

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Figure 1.5. Overwrite Input.

If you perform a read when the RT FIFO is empty, then the empty output will be TRUE.

Figure 1.6. Empty OutputA real time data acquisition and signal processing unit for biomedical applications

A data acquisition and signal-processing system for real-time bioelectrical signal recording and analysis is described. The hardware is designed to accommodate a variety of bioelectric signals: EKG, EMG, EEG, action potentials, movement, and respiration. The flexibility of the unit is achieved by software control of amplifier gain, bandpass filter bandwidth, and sampling conditions. The user downloads a customized data-acquisition program, generated on the host microcomputer, by one of three available interfaces (serial, parallel, or DMA). The unit provides analog signal conditioning, digitization, and processing of the signal(s) according to user requirements. Acquisition and feature extraction strategies can be adjusted online by the investigator or can be programmed to respond automatically to changes in the input signals. An onboard digital signal-processing chip allows the use of various fast algorithms for real-time frequency-domain analysis. Only extracted data are uploaded to the host for future analysis and graphical display.

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2.0 VLSI

PROLOGUE:

Most of the students of Electronics Engineering are exposed to Integrated Circuits (IC's) at a very basic level, involving SSI (small scale integration) circuits like logic gates or MSI (medium scale integration) circuits like multiplexers, parity encoders etc. But there is a lot bigger world out there involving miniaturization at levels so great, that a micrometer and a microsecond are literally considered huge! This is the world of VLSI - Very Large Scale Integration. The article aims at trying to introduce Electronics Engineering students to the possibilities and the work involved in this field.

2.1 INTRODUCTION:

VLSI stands for "Very Large Scale Integration". It is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into the hundreds of millions of transistors. This is the field which involves packing more and more logic devices into smaller and smaller areas. Thanks to VLSI, circuits that would have taken boardfuls of space can now be put into a small space few millimeters across! This has opened up a big opportunity to do things that were not possible before. VLSI circuits are everywhere ... your computer, your car, your brand new state-of-the-art digital camera, the cell-phones, and what have you.

The first semiconductor chips held one transistor each. Subsequent advances added more and more transistors, and, as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as "small-scale integration" (SSI), improvements in technique led to devices with hundreds of logic gates, known as large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today's microprocessors have many millions of gates and hundreds of millions of individual transistors

VLSI has been around for a long time, there is nothing new about it ... but as a side effect of advances in the world of computers, there has been a dramatic proliferation of tools that can be used to design VLSI circuits. Alongside, obeying Moore's law, the capability of an IC has increased exponentially over the years, in terms of computation power, utilization of available area, yield. The combined effect of these two advances is that people can now put diverse functionality into the IC's, opening up new frontiers. Examples are embedded systems, where intelligent devices are put inside everyday objects, and ubiquitous computing where small computing devices proliferate to such an extent that even the shoes you wear may actually do something useful like monitoring your heartbeats! These two fields are kinda related, and getting into their description can easily lead to another article.

Digital VLSI circuits are predominantly CMOS based. The way normal blocks like latches and gates are implemented is different from what students have seen so far, but the behavior remains the same. All the miniaturization involves new things to consider. A lot of

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thought has to go into actual implementations as well as design. Let us look at some of the factors involved ...

1. Circuit Delays: Large complicated circuits running at very high frequencies have one big problem to tackle - the problem of delays in propagation of signals through gates and wires ... even for areas a few micrometers across! The operation speed is so large.

2. Power. Another effect of high operation frequencies is increased consumption of power. This has two-fold effect - devices consume batteries faster, and heat dissipation increases. Coupled with the fact that surface areas have decreased, heat poses a major threat to the stability of the circuit.

3. Layout. Laying out the circuit components is task common to all branches of electronics. What’s so special in our case is that there are many possible ways to do this; there can be multiple layers of different materials on the same silicon

The power dissipation and speed in a circuit present a trade-off; if we try to optimize on one, the other is affected. The choice between the two is determined by the way we chose the layout the circuit components. Layout can also affect the fabrication of VLSI chips, making it either easy or difficult to implement the components on the silicon.

CHALLENGES :

As microprocessors become more complex due to technology scaling, microprocessor designers have encountered several challenges which force them to think beyond the design plane, and look ahead to post-silicon

Power usage/Heat dissipation – As threshold voltages have ceased to scale with advancing process technology, dynamic power dissipation has not scaled proportionally. Maintaining logic complexity when scaling the design down only means that the power dissipation per area will go up. This has given rise to techniques such as dynamic voltage and frequency scaling (DVFS) to minimize overall power.

Process variation – As lithography techniques tend closer to the fundamental laws of optics, achieving high accuracy in doping concentrations and etched wires is becoming more difficult and prone to errors due to variation. Designers now have to simulate across multiple fabrication process corners before the chip is certified ready for production

Stricter design rules – Due to lithography and etch issues with scaling, design rules for layout have gotten much more stringent. Designers have to keep more of these rules in mind while laying out custom circuits. The overhead for custom design is now reaching a tipping point, with many design houses now opting to switch to electronic design automation (EDA) tools to automate their design process

Timing/design closure – As clock frequencies tend to scale up, designers are finding it more difficult to distribute and maintain low clock skew between these high frequency clocks across the entire chip. This has led to a rising interest in multicore and multiprocessor architectures, since an overall speedup can be obtained by lowering the clock frequency and distributing processing

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First-pass success – As die sizes shrink (due to scaling), and wafer sizes go up (to lower manufacturing costs), the number of dies per wafer increases, and the complexity of making suitable photomasks goes up rapidly. A mask set for a modern technology can cost several million dollars. This non-recurring expense deters the old iterative philosophy involving several "spin-cycles" to find errors in silicon, and encourages first-pass silicon success. Several design philosophies have been developed to aid this new design flow, including design for manufacturing (DFM), design for test (DFT), and many others.

Classification of VLSI design:

Analog :Small transistor count precision circuits such as Amplifiers, Data converters, filters, Phase Locked Loops, Sensors etc.

Digital ( ASICS) :

Progress in the fabrication of IC's has enabled us to create fast and powerful circuits in smaller and smaller devices. This also means that we can pack a lot more of functionality into the same area. The biggest application of this ability is found in the design of ASIC's. These are IC's that are created for specific purposes - each device is created to do a particular job, and do it well. The most common application area for this is DSP - signal filters, image compression, etc. To go to extremes, consider the fact that the digital wristwatch normally consists of a single IC doing all the time-keeping jobs as well as extra features like games, calendar, etc.

System on chip:

These are highly complex mixed signal circuits (digital and analog all on the same chip). A network processor chip or a wireless radio chip is an example of a SOC.

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2.2TYPICAL DESIGN FLOW FOR A DIGITAL CHIP

There are two types of designs :

( i ) Array based design.

Array means single dimensional or multi dimensional vectors of either single bit wide or N –bit wide .Array based design are used to design memory elements. They are mainly used for testing purpose by using FPGA ( Field Programmable Gate Array).FPGA ‘s are programmable .

Array based design can not decrease the size of the chip and consumes more power . software’s used for Array based design are XILINX and MODELSIM.

( ii ) Cell based design.

In this design there are predefined cells .Cell is a library which consists of all the information belongs to basic elements ( BJT & MOSFET) which are used in VLSI design .We can decrease the size of the chip ,hence power consumption is also less unlike in array based design . cell based design chips are not reprogrammable .These chips are only used for ASIC ( Application Specific Integrated Circuit ) purpose . Software’s used are CADENCE & SYNOPSIS.

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Cell based design are of two types :

(i) . Reprogrammable design . (ii) . Non Reprogrammable design

2.3 Levels of Design :

Device Level Design :

This the Lowest level of design where we use only one device . In this we concentrate on various parameters like voltage , current ,noise, temperature etc for a particular device

Circuit Level Design :

This the medium level of design more than one device can be used the circuit . In order to design at circuit level manual methods takes longer time Ex: Halfadder

System Level Design :

This one is the highest level of design , where we have more than one circuit present in a system Ex: Processor.

If we want to design system by manual methods are not at all possible so we use languages which describe the Hardware (HDL’s) .

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3.0 CADENCE TOOLS

The Cadence suite is a huge collection of programs for different CAD applications

from VLSI design to high-level DSP programming. The suite is divided into different

“packages,” and for VLSI design, the packages we will be using are the IC package and the

DSMSE package.

The Cadence toolset is a complete microchip EDA system, which is intended to

develop professional, full-scale, mixed-signal microchips and breadboards.  The modules

included in the toolset are for schematic entry, design simulation, data analysis, physical

layout, and final verification. The strength of the Cadence tools is in its analog

design/simulation/layout and mixed signal verification and is often used in tandem with other

tools for RF and/or digital design/simulation/layout, where complete top-level verification is

done in the Cadence tools. Another important concept is that the Cadence tools only provide

a framework for doing design.  Without a foundry-provided design kit, no design can be

done. 

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design

innovation, today said Global Unichip Corporation (GUC), a leading system-on-chip (SOC)

design foundry, is the first Taiwan-based design company to complete a successful tape out

of a 65-nanometer device. The success of this 65-nanometer tape out further strengthened

GUC's advanced technology capabilities to serve the top tier customers worldwide. GUC

used the Cadence(R) Low-Power Solution and SOC Encounter(TM) GXL RTL-to-GDSII

system to achieve the tape out.

3.1 ABOUT CADENCE COMPANY

Cadence enables global electronic-design innovation and plays an essential role in the

creation of today's integrated circuits and electronics. Customers use Cadence software and

hardware, methodologies, and services to design and verify advanced semiconductors,

consumer electronics, networking and telecommunications equipment, and computer

systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has

approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales

offices, design centers, and research facilities around the world to serve the global electronics

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Since ours is digital designing the tools used in our project are:

IUS - Incisive Unified Simulator.

RC-RTL Compiler.

SOC encounter-System On Chip encounter.

This tool work on 18 nanometer technology.

Now, we will study in detail about these tools and results of our project using these tools.

FIGURE 3.1 FLOW OF DESIGN USING CADENCE TOOLS

3.2 INCISIVE UNIFIED SIMULATOR

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Incisive Unified Simulator is a tool used to simulate digital

circuits. The designs are represented using many different languages such as Verilog or

VHDL. IUS supports those language as well additional languages used for specialized

verification functions, such as SystemC, a derivative of C++. The tool handles any design

that can be represented using a digital representation with the key languages. The Verilog

only environment is called NC-Verilog and the VHDL one is called NC-VHDL.

Designers depending on the complexity of their simulation tasks will create environments

that use multiple languages to perform advanced verification tasks.

Who needs IUS:–System architects who need to do analysis on various scenarios

to determine what the right grouping of components would be. This is typically done with

simple IP models to look at high level behavior.–Design engineers who are creating the

various parts of the circuit use IUS to test the behavior and make sure the requirements

are met–Verification Engineers are a specialized team that take the design once it is

completed and create test that exercise the complete design testing actual conditions as

best as possible. –IP vendors used IUS to create IP models and ensure that their models

behaves correctly with the tools that their customers will use.–Board designers will use

IUS as means

BENEFITS

• Speeds time-to-market with lower risk and higher predictability.

• Increases productivity by enabling verification to start months earlier, before test bench

development and simulation.

• Improves quality and reduces risk of re-spins by exposing corner-case functional bugs

that are difficult or impossible to find using conventional methods.

• Reduces block design effort and debug time, and shortens integration time.

• Provides design teams with an advanced debug environment with simulation synergies

for ease-of adoption.

• Offers the ultimate simulation-based speed and efficiency.

• Increases RTL performance by 100 times with native transaction-level simulation and

optional Acceleration-on-Demand.

• Reduces test bench development up to 50% with transaction-level support, unified test

generation, and verification component re-use.

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• Shortens verification time, finds bugs faster, and eliminates exhaustive simulation runs

with dynamic assertion checking.

• Decreases debug time up to 25% through unified transaction/signal viewing, HDL

analysis capability, and unified debug environment for all languages.

This program is a front-end to some of the other tools in this directory. Its job is to

compile, elaborate, and launch the simulation.

ncvlog

This is the Verilog compiler. Typing this command in with no arguments gives you a

listing of the possible options. Two arguments which are useful are -cdslib, which

specifies the location of your cds.lib file, and -work, which specifies the location of your

worklib file.

To compile a Verilog file named test.v, and its test bench named tb_test.v, using a cdslib

of cds.lib, and a work library of worklib, you can execute the following command:

ncvlog -cdslib cds.lib -work worklib test.v tb_test.v

ncelab

This is the elaborator. Again, typing this command with no arguments outputs a list of

options. The above -cdslib and -work arguments apply.

To elaborate an compiled test bench called tb_test.v, execute the following command:

ncelab -cdslib cds.lib -work worklib worklib.tb_test_v

ncsim

This is the actual simulator. To launch a compiled and elaborated test bench, execute the

following command: ncsim -gui -cdslib cds.lib -work worklib worklib.tb_test_v:module

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4.0 VERILOG

In the semiconductor and electronic design industry, Verilog is a hardware description

language (HDL) used to model electronic systems. Verilog HDL, not to be confused with

VHDL, is most commonly used in the design, verification, and implementation of digital

logic chips at the Register transfer level (RTL) level of abstraction. It is also used in the

verification of analog and mixed-signal circuits

4.1 ABOUT LANGUAGE

Hardware description languages, such as Verilog, differ from software programming

languages in several fundamental ways. HDLs add the concept of concurrency, which is

parallel execution of multiple statements in explicitly specified threads, propagation of

time, and signal dependency (sensitivity). There are two assignment operators, a blocking

assignment (=), and a non-blocking (<=) assignment. The non-blocking assignment

allows designers to describe a state-machine update without needing to declare and use

temporary storage variables. Since these concepts are part of the Verilog's language

semantics, designers could quickly write descriptions of large circuits, in a relatively

compact and concise form. At the time of Verilog's introduction (1984), Verilog

represented a tremendous productivity improvement for circuit designers who were

already using graphical schematic-capture, and specially-written software programs to

document and simulate electronic circuits.

The designers of Verilog wanted a language with syntax similar to the C programming

language, which was already widely used in engineering software development. Verilog

is case-sensitive, has a basic preprocessor (though less sophisticated than ANSI C/C++),

and equivalent control flow keywords (if/else, for, while, case, etc.), and compatible

language operators precedence. Syntactic differences include variable declaration

(Verilog requires bit-widths on net/reg types), demarcation of procedural-blocks

(begin/end instead of curly braces {}), though there are many other minor differences.

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A Verilog design consists of a hierarchy of modules. Modules encapsulate design

hierarchy, and communicate with other modules through a set of declared input, output,

and bidirectional ports. Internally, a module can contain any combination of the

following: net/variable declarations (wire, reg, integer, etc.), concurrent and sequential

statement blocks and instances of other modules (sub-hierarchies). Sequential statements

are placed inside a begin/end block and executed in sequential order within the block. But

the blocks themselves are executed concurrently, qualifying Verilog as a Dataflow

language.

Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating,

undefined"), and strengths (strong, weak, etc.) This system allows abstract modeling of

shared signal-lines, where multiple sources drive a common net. When a wire has

multiple drivers, the wire's (readable) value is resolved by a function of the source drivers

and their strengths.

A subset of statements in the Verilog language is synthesizable. Verilog modules that

conform to a synthsizeable coding-style, known as RTL (register transfer level), can be

physically realized by synthesis software. Synthesis-software algorithmically transforms

the (abstract) Verilog source into a netlist, a logically-equivalent description consisting

only of elementary logic primitives (AND, OR, NOT, flipflops, etc.) that are available in

a specific VLSI technology. Further manipulations to the netlist ultimately lead to a

circuit fabrication blueprint (such as a photo mask-set for an ASIC), or a bitstream-file

for an FPGA)

There are now two industry standard hardware description languages, VHDL and

Verilog. The complexity of ASIC and FPGA designs has meant an increase in the

number of specialist design consultants with specific tools and with their own libraries of

macro and mega cells written in either VHDL or Verilog. As a result, it is important that

designers know both VHDL and Verilog and that EDA tools vendors provide tools that

provide an environment allowing both languages to be used in unison. For example, a

designer might have a model of a PCI bus interface written in VHDL, but wants to use it

in a design with macros written in Verilog.

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VHDL (Very high speed integrated circuit Hardware Description Language) became

IEEE standard 1076 in 1987. It was updated in 1993 and is known today as "IEEE

standard 1076 1993". The Verilog hardware description language has been used far

longer than VHDL and has been used extensively since it was launched by Gateway in

1983. Cadence bought Gateway in 1989 and opened Verilog to the public domain in

1990. It became IEEE standard 1364 in December 1995.

There are two aspects to modeling hardware that any hardware description language

facilitates; true abstract behavior and hardware structure. This means modeled hardware

behavior is not prejudiced by structural or design aspects of hardware intent and that

hardware structure is capable of being modeled irrespective of the design's behavior.

4.2 VHDL/VERILOG COMPARED & CONTRASTED

This section compares and contrasts individual aspects of the two languages; they are

listed in alphabetical order.

Capability

Hardware structure can be modeled equally effectively in both VHDL and Verilog. When

modeling abstract hardware, the capability of VHDL can sometimes only be achieved in

Verilog when using the PLI. The choice of which to use is not therefore based solely on

technical capability but on.personal preferences

EDA tool availability

The modeling constructs of VHDL and Verilog cover a slightly different spectrum across

the levels of behavioral abstraction; see Figure 4.1.

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FIGURE 4.1 Comparison of VHDL and VERILOG.

HDL modeling capability

4.3 COMPILATION

VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system

file, may be separately compiled if so desired. However, it is good design practice to keep

each design unit in it's own system file in which case separate compilation should not be

an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode.

Compilation is a means of speeding up simulation, but has not changed the original

nature of the language. As a result care must be taken with both the compilation order of

code written in a single file and the compilation order of multiple files. Simulation results

can change by simply changing the order of compilation.

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DATA TYPES

VHDL. A multitude of language or user defined data types can be used. This may m ean

dedicated conversion functions are needed to convert objects from one type to another.

The choice of which data types to use should be considered wisely, especially

enumerated (abstract) data types. This will make models easier to write, clearer to read

and avoid unnecessary conversion functions that can clutter the code. VHDL may be

preferred because it allows a multitude of language or user defined data types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very

much geared towards modeling hardware structure as opposed to abstract hardware

modeling. Unlike VHDL, all data types used in a Verilog model are defined by the

Verilog language and not by the user. There are net data types, for example wire, and a

register data type called reg. A model with a signal whose type is one of the net data

types has a corresponding electrical wire in the implied modeled circuit. Objects, that is

signals, of type reg hold their value over simulation delta cycles and should not be

confused with the modeling of a hardware register. Verilog may be preferred because of

it's simplicity.

Design reusability

VHDL. Procedures and functions may be placed in a package so that they are avail able

to any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used

within a model must be defined in the module. To make functions and procedures

generally accessible from different module statements the functions and procedures must

be placed in a separate system file and included using the `include compiler directive.

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Easiest to Learn

Starting with zero knowledge of either language, Verilog is probably the easiest to grasp

and understand. This assumes the Verilog compiler directive language for simulation and

the PLI language is not included. If these languages are included they can be looked upon

as two additional languages that need to be learned. VHDL may seem less intuitive at

first for two primary reasons. First, it is very strongly typed; a feature that makes it robust

and powerful for the advanced user after a longer learning phase. Second, there are many

ways to model the same circuit, especially those with large hierarchical structures.

Forward and back annotation

A spin-off from Verilog is the Standard Delay Format (SDF). This is a general purpose

format used to define the timing delays in a circuit. The format provides a bidirectional

link between, chip layout tools, and either synthesis or simulation tools, in order to

provide more accurate timing representations. The SDF format is now an industry

standard in it's own right.

High level constructs

VHDL. There are more constructs and features for high-level modeling in VHDL than

there are in Verilog. Abstract data types can be used along with the following statements:

* package statements for model reuse,

* configuration statements for configuring design structure,

* generate statements for replicating structure,

* generic statements for generic models that can be individually characterized, for

example, bit width.

All these language statements are useful in synthesizable models.

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Verilog. Except for being able to parameterize models by overloading parameter

constants, there is no equivalent to the high-level VHDL modeling statements in Verilog.

LANGUAGE EXTENSIONS

The use of language extensions will make a model non standard and most likely not

portable across other design tools. However, sometimes they are necessary in order to

achieve the desired results.

VHDL. Has an attribute called 'foreign that allows architectures and subprograms to be

modeled in another language.

Verilog. The Programming Language Interface (PLI) is an interface mechanism between

Verilog models and Verilog software tools. For example, a designer, or more likely, a

Verilog tool vendor, can specify user defined tasks or functions in the C programming

language, and then call them from the Verilog source description. Use of such tasks or

functions make a Verilog model nonstandard and so may not be usable by other Verilog

tools. Their use is not recommended.

Libraries

VHDL. A library is a store for compiled entities, architectures, packages and

configurations. Useful for managing multiple design projects.

Verilog. There is no concept of a library in Verilog. This is due to it's origins as an

interpretive language.

Low Level Constructs

VHDL. Simple two input logical operators are built into the language, they are: NOT,

AND, OR, NAND, NOR, XOR and XNOR. Any timing must be separately specified

using the after clause. Separate constructs defined under the VITAL language must be

used to define the cell primitives of ASIC and FPGA libraries.

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Verilog. The Verilog language was originally developed with gate level modeling in

mind, and so has very good constructs for modeling at this level and for modeling the cell

primitives of ASIC and FPGA libraries. Examples include User Defined Primitive s

(UDP), truth tables and the specify block for specifying timing delays across a module.

Managing large designs

VHDL. Configuration, generate, generic and package statements all help manage large

design structures.

Verilog. There are no statements in Verilog that help manage large designs.

Operators

The majority of operators are the same between the two languages. Verilog does have

very useful unary reduction operators that are not in VHDL. A loop statement can be

used in VHDL to perform the same operation as a Verilog unary reduction operator.

VHDL has the mod operator that is not found in Verilog

Parameterizable models

VHDL. A specific bit width model can be instantiated from a generic n-bit model using

the generic statement. The generic model will not synthesize until it is instantiated and

the value of the generic given.

Verilog. A specific width model can be instantiated from a generic n-bit model using

overloaded parameter values. The generic model must have a default parameter value

defined. This means two things. In the absence of an overloaded value being specified, it

will still synthesize, but will use the specified default parameter value. Also, it does not

need to be instantiated with an overloaded parameter value specified, before it will

synthesize.

Procedures and tasks

24

VHDL allows concurrent procedure calls; Verilog does not allow concurrent task calls.

Readability

This is more a matter of coding style and experience than language feature. VHDL is a

concise and verbose language; its roots are based on Ada. Verilog is more like C because

it's constructs are based approximately 50% on C and 50% on Ada. For this reason an

existing C programmer may prefer Verilog over VHDL. Although an existing

programmer of both C and Ada may find the mix of constructs somewhat confusing at

first. Whatever HDL is used, when writing or reading an HDL model to be synthesized it

is important to think about hardware intent.

Structural replication

VHDL. The generate statement replicates a number of instances of the same design-unit

or some sub part of a design, and connects it appropriately.

Verilog. There is no equivalent to the generate statement in Verilog.

Test harnesses

Designers typically spend about 50% of their time writing synthesizable models and the

other 50% writing a test harness to verify the synthesizable models. Test harnesses are

not restricted to the synthesizable subset and so are free to use the full potential of the

language. VHDL has generic and configuration statements that are useful in test

harnesses, that are not found in Verilog.

Verboseness

VHDL. Because VHDL is a very strongly typed language models must be coded

precisely with defined and matching data types. This may be considered an advantage or

disadvantage. However, it does mean models are often more verbose, and the code often

longer, than it's Verilog equivalent.

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Verilog. Signals representing objects of different bits widths may be assigned to each

other. The signal representing the smaller number of bits is automatically padded out to

that of the larger number of bits, and is independent of whether it is the assigned signal or

not.

To launch a compiled and elaborated test bench, execute the following command: ncsim -

gui -cdslib cds.lib -work worklib worklib.tb_test_v:module

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5.0 VERILOG CODING

5.1 Synthesizable FIFO Model

This example describes a synthesizable implementation of a FIFO. The FIFOdepth and FIFO width in bits can be modified by simply changing the value of two parameters, ‘FWIDTH and ‘FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits

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28

29

30

31

32

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5.2 SUB MODULE BLOCK

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5.3 TEST BENCH

`resetall

`time scale 1 ns / 1 ns

`view

module FIFO_test();

reg CLK,RSTN;

reg [(`fcwidth – 1):0]DATA_IN;

reg FINN,FCLRN,FOUTN;

wire [(`fwidth – 1):0]f_data;

wire F_FULLN,F_EMPTYN,F_LASTN,F_SLASTN,F_FIRSTN;

FIFO F(CLK,RSTN,DATA_IN,FINN,FCLRN,FOUTN<F_DATA,F_FULLN,F_EMPTYN,F_LASTN, F_SLASTN ,F_FIRSTN);

Initial

Begin

#0

CLK = 1’b0;

RSTN = 1’b0;

DATA_IN = 32’d1;

FCLRN = 1’b0;

FINN = 1’b0;

FOUTN = 1’b1;

$monitor ($time,”CLK=%b,RSTN=%b,DATA_IN=%d,FINN=%b,FCLRN=%b,FOUTN=%b, F_DATA=%b,F_FULLN=%b,F_EMPTYN=%b,F_LASTN=%b, F_SLASTN=%b ,F_FIRSTN=%b”,CLK,RSTN,DATA_IN,FINN,FCLRN,FOUTN<F_DATA,F_FULLN,F_EMPTYN,F_LASTN, F_SLASTN ,F_FIRSTN);

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end

initial

begin

#10

CLK = 1’b1;

RSTN = 1’b0;

DATA_IN = 30’b111111111111111111111111111111;

FCLRN = 1’b0;

FINN = 1’b1;

FOUTN = 1’b0;

$monitor ($time,”CLK=%b,RSTN=%b,DATA_IN=%b,FINN=%b,FCLRN=%b,FOUTN=%b, F_DATA=%b,F_FULLN=%b,F_EMPTYN=%b,F_LASTN=%b, F_SLASTN=%b ,F_FIRSTN=%b”,CLK,RSTN,DATA_IN,FINN,FCLRN,FOUTN<F_DATA,F_FULLN,F_EMPTYN,F_LASTN, F_SLASTN ,F_FIRSTN);

end

initial

begin

#20

CLK = 1’b1;

RSTN = 1’b0;

DATA_IN = 32’d1;

FCLRN = 1’b0;

FINN = 1’b0;

FOUTN = 1’b1;

$monitor ($time,”CLK=%b,RSTN=%b,DATA_IN=%d,FINN=%b,FCLRN=%b,FOUTN=%b, F_DATA=%b,F_FULLN=%b,F_EMPTYN=%b,F_LASTN=%b,

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F_SLASTN=%b ,F_FIRSTN=%b”,CLK,RSTN,DATA_IN,FINN,FCLRN,FOUTN<F_DATA,F_FULLN,F_EMPTYN,F_LASTN, F_SLASTN ,F_FIRSTN);

end

initial

begin

#30

CLK = 1’b0;

RSTN = 1’b1;

DATA_IN = 32’d0;

FCLRN = 1’b0;

FINN = 1’b0;

FOUTN = 1’b1;

$monitor ($time,”CLK=%b,RSTN=%b,DATA_IN=%d,FINN=%b,FCLRN=%b,FOUTN=%b, F_DATA=%b,F_FULLN=%b,F_EMPTYN=%b,F_LASTN=%b, F_SLASTN=%b ,F_FIRSTN=%b”,CLK,RSTN,DATA_IN,FINN,FCLRN,FOUTN<F_DATA,F_FULLN,F_EMPTYN,F_LASTN, F_SLASTN ,F_FIRSTN);

end

initial

begin

#40

CLK = 1’b1;

RSTN = 1’b1;

DATA_IN = 32’d0;

FCLRN = 1’b0;

FINN = 1’b0;

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FOUTN = 1’b1;

$monitor ($time,”CLK=%b,RSTN=%b,DATA_IN=%d,FINN=%b,FCLRN=%b,FOUTN=%b, F_DATA=%b,F_FULLN=%b,F_EMPTYN=%b,F_LASTN=%b, F_SLASTN=%b ,F_FIRSTN=%b”,CLK,RSTN,DATA_IN,FINN,FCLRN,FOUTN<F_DATA,F_FULLN,F_EMPTYN,F_LASTN, F_SLASTN ,F_FIRSTN);

end

initial

begin

#50

CLK = 1’b1;

RSTN = 1’b1;

DATA_IN = 32’d1;

FCLRN = 1’b0;

FINN = 1’b0;

FOUTN = 1’b1;

$monitor ($time,”CLK=%b,RSTN=%b,DATA_IN=%d,FINN=%b,FCLRN=%b,FOUTN=%b, F_DATA=%b,F_FULLN=%b,F_EMPTYN=%b,F_LASTN=%b, F_SLASTN=%b ,F_FIRSTN=%b”,CLK,RSTN,DATA_IN,FINN,FCLRN,FOUTN<F_DATA,F_FULLN,F_EMPTYN,F_LASTN, F_SLASTN ,F_FIRSTN);

end

endmodule

`noview

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7.0 ADVANTAGES

FIFO’s are very simple because of single clock design property.

In FIFO’s accurate count of fullness can be kept.

They are simple in their design properties.

Construction of FIFO’s does not require much capital.

They are used in many real time applications. One such application is FIFO is

used as disk controller as disk scheduling algorithm to determine the order to

service disk I/O request.

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8.0 CONCLUSION

FIFO’s are having many many real time applications due to its simple nature where in it

has a single clock design property where accurate count of fullness can be kept.FIFO is

used in all the digital systems where the data is needed to be read sequentially.It has chip

select and can be used while embedding with any other digital system.

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9.0 BIBILIOGRAPHY

www.google.com

www.wikipedia.org

www.electronicsforyou.com

www.googlebooks.com

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