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Figs. Chap. 2 · J. Lienig, M. Thiele, Fundamentals of Electromigation-Aware Integrated Circuit...

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Interaction of electric field on metal ions Force on metal ions (Cu + ) resulting from momentum transfer from the conduction electrons Anode + Cathode - E - - - Cu + - F wind F field << © J. Lienig, M. Thiele, Fundamentals of Electromigation-Aware Integrated Circuit Design. Springer, ISBN 978-3-319-73557-3, 2018. Figures of Chapter 2: Fundamentals of Electromigration
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  • Interaction of electric field on metal ions

    Force on metal ions (Cu+) resulting from momentum transfer from the conduction electrons

    Anode+

    Cathode-

    E-

    -

    -

    Cu+-

    Fwind Ffield

  • Hillocks

    Voids

    Grain boundaries

    Whiskers

  • Metal2 Cu

    Metal1 Cu e

    Via Depletion

    Ta/TaNliner layer

    Low-kdielectric

    SiN, NSiCcap layer

    Void

    Metal2 CuTa/TaNliner layer

    Low-kdielectric

    SiN, NSiCcap layerMetal1 Cu

    e

    Line Depletion

    Void

  • Growth of voids

    Increase of local current density

    Increase of Joule heating

    Increase of temperature

  • Stress Migration

    due to mechanical stress

    Thermal Migration

    due to thermal gradient

    Electrolytic electromigration Solid state electromigration

    Migration in Solid-State Materials

    Electromigration

    due to electrical field

    Solid-state electromigration

    Chemical Diffusion

    due to concentration gradient

  • -(a) (b)

    (c)

  • 0,01

    0,1

    1

    10

    100

    -40 0 25 60 80 100 125 150 175

    Temperature T [Celsius]

    Consumer electronics

    Automotive electronics

    Jmax(T) / Jmax(T = 25°C Jmax(T) compared to Jmax(Tref = 25°C) acc. Eq. (2.1)

  • (c)(a) (b)

    Min. Max.

    Current density

  • Amorphous

    Polycrystalline

    Near-bamboo

    Bamboo

    Monocrystalline

    No crystal lattice or grain boundaries

    Grain boundaries dominate

    Featuring both crystal lattice and grain boundaries

    Crystall lattice dominates

    Crystall lattice and lattice defects define characteristics

  • Diffusion process Activation energy in eV

    Aluminum Copper

    Bulk diffusion 1.2 2.3

    Grain-boundary diffusion 0.7 1.2

    Surface diffusion 0.8 0.8

  • Triple pointBlocking

    grain

  • (a) Dielectric deposition (b) Trench etching

    (c) Metal deposition (d) Metal removal

    Silicon substrate

    Dielectric (e.g., SiO2)

  • Dielectric (e.g., SiO2)

    Metal(Cu)

    Surface coatingDielectric cap

    Diffusion barrierMetal liner

  • Example Frequency

    Controlling the background lighting for a computer screen 10 mHz

    Frame rate on a PC monitor 60 Hz

    Sampling frequency for audio signals 44 kHz

    Carrier frequency for radio frequency identification (RFID) 13.56 MHz

    Processor clock frequency 3 GHz

  • MTF (AC)MTF (DC)

    103

    102

    101

    10010

    -2

    10-1

    100

    101

    102

    103

    104

    105

    106

    107

    108

    Frequency in Hz

  • Structural widthSkin depth

    2016 2020 2024Year

    10-5

    10-6

    10-7

    Size

    in m

    10-8

    10-9

  • Cu

    Dielectric (e.g., SiO2)

  • T

    Vacancy

    Atom

  • σ

    Vacancy

    Atom

    Tensile stressCompressive stress

  • a

    b

    Vacancy

    Atom

    Tensile stress Compressive stress

  • a

    b

    Vacancy

    Atom

    Tensile stress Compressive stress

  • D

    ∆c

    c

    TM

    SM

    EM

    T

    σ

    j

  • − +EMTM

    SM

    T

    σ

    Vacancy

    Atom

  • − +EMTM

    SM

  • Current (e−)

    Via

    Void

  • Current (e−)Void

    a

    TSV

    VoidCurrent (e−)

    b

    Alternating CurrentVoid

    c

  • Die 2

    Die 1 TSV

    Mechanicalfailure

    Mobility changes

  • Φ1, j1 Φ3, j3

    Φ4, j4

    Φ2, j2

    Φ5, j5

    I1,2

    ModelLayout

    I2,4

    I4,5

    I2,3

  • ModelLayout

  • Clock frequencyProblem size

    Rel

    ativ

    e ch

    ange

    1

    10

    20

    30

    40

    2016 2018 2020 2022 2024 2026

    Year

  • Technology

    PatternLibrary

    Simulation(FEM)

    Schematic

    Placement,Routing, …

    Circuit Layout

    Physical Design

  • 0 3.31.1 2.2

    j / j0

  • 0 3.31.1 2.2

    j / j0

  • 0.97 1.031.0

    j / j0

  • Current density

    Atomic flux

    Flux divergence

    Mechanical stress

    Steady state Void nucleation

    Lifetime

    Void growth

    Check for limit

    Basic currentdensity simulation

    Void growthsimulation

    Atomic fluxsimulation

    Incorporation ofmechanical stress

  • -1.0 1.00

    ΔJ / ΔJmax

    e–

    Metal 1

    Via

    Metal 2

  • -1.0 1.00

    σ / σmax

    σ / σmax

    x in µm

    Metal

    Conductive Stripe

  • -1.0 1.00

    σ / σmax

    σ / σmax

    x in µm

    Metal

    Conductive Stripe

  • Foliennummer 1Foliennummer 2Foliennummer 3Foliennummer 4Foliennummer 5Foliennummer 6Foliennummer 7Foliennummer 8Foliennummer 9Foliennummer 10Foliennummer 11Foliennummer 12Foliennummer 13Foliennummer 14Foliennummer 15Foliennummer 16Foliennummer 17Foliennummer 18Foliennummer 19Foliennummer 20Foliennummer 21Foliennummer 22Foliennummer 23Foliennummer 24Foliennummer 25Foliennummer 26Foliennummer 27Foliennummer 28Foliennummer 29Foliennummer 30Foliennummer 31Foliennummer 32Foliennummer 33Foliennummer 34Foliennummer 35Foliennummer 36Foliennummer 37Foliennummer 38Foliennummer 39Foliennummer 40


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