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Semiconductor Manufacturing Processes

Design

Wafer Preparation

Front-end Processes

Photolithography

Etch

Cleaning

Thin Films

Ion Implantation

Planarization Test and Assembly

Thin Films

Photo-

lithography

Cleaning

Front-End

Processes

EtchIon

Implantation

Planarization

Test &

Assembly

DesignWafer

Preparation

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Design

Thin Films

Photo-

lithography

Cleaning

Front-End

Processes

EtchIon

Implantation

Planarization

Test &

Assembly

DesignWafer

Preparation

Establish Design Rules

Circuit Element Design

Interconnect Routing

Device Simulation

Pattern Preparation

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Wafer Preparation

Thin Films

Photo-

lithography

Cleaning

Front-End

Processes

EtchIon

Implantation

Planarization

Test &

Assembly

DesignWafer

Preparation

Polysilicon Refining

Crystal Pulling Wafer Slicing & Polishing

Epitaxial Silicon Deposition

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Polysilicon Refining

Chemical Reactions

Silicon Refining: SiO2+ 2 CSi + 2 CO

Silicon Purification: Si + 3 HClHSiCl3+ H2

Silicon Deposition: HSiCl3+ H2Si + 3 HCl

Reactants

H2

Silicon Intermediates

H2SiCl2

HSiCl3

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Crystal Pulling

Quartz Tube

Rotating Chuck

Seed Crystal

Growing Crystal

(boule)

RF or Resistance

Heating Coils

Molten Silicon

(Melt)

Crucible

Materials

Polysilicon Nodules *

Ar *H2

*High proportion of the total product use

Process Conditions

Flow Rate: 20 to 50 liters/min

Time: 18 to 24 hours

Temperature: >1,300 degrees C

Pressure: 20 Torr

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Epitaxial Silicon Deposition

Gas

Input Lamp

Module

Quartz

Lamps

Wafers

Susceptor

Exhaust

*High proportion of the total product use

Chemical Reactions

Silicon Deposition: HSiCl3+ H2Si + 3 HClProcess Conditions

Flow Rates: 5 to 50 liters/min

Temperature: 900 to 1,100 degrees C.

Pressure: 100 Torr to Atmospheric

silicon wafer

p- silicon epi layer

p+ silicon substrate

DopantsAsH3

B2H6

PH3

EtchantHCl

Carriers

Ar

H2*

N2

Silicon SourcesSiH4

H2SiCl2

HSiCl3*

SiCl4*

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Thin Films

Photo-

lithography

Cleaning

Front-End

Processes

EtchIon

Implantation

Planarization

Test &

Assembly

DesignWafer

Preparation Thermal Oxidation

Silicon Nitride Deposition

- Low Pressure Chemical Vapor

Deposition (LPCVD) Polysilicon Deposition

- Low Pressure Chemical Vapor

Deposition (LPCVD)

Annealing

Front-End Processes

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Front-End Processes

*High proportion of the total product use

Polysilicon

H2N2

SiH4*AsH3

B2H6

PH3

Exhaust ViaVacuum Pumps

and Scrubber

3 Zone

Temperature

Control

Gas Inlet

Vertical LPCVD Furnace

Quartz TubeChemical Reactions

Thermal Oxidation: Si + O2SiO2

Nitride Deposition: 3 SiH4+ 4 NH

3Si

3N

4+ 12 H

2

Polysilicon Deposition: SiH4Si + 2 H2Process Conditions (Silicon Nitride LPCVD)

Flow Rates: 10 - 300 sccm

Temperature: 600 degrees C.

Pressure: 100 mTorr

silicon dioxide (oxide)

p- silicon epi layer

p+ silicon substrate

Nitride

NH3*H2SiCl2*

N2

SiH4*

SiCl4

Oxidation

ArN2H2O

Cl2

H2

HCl *

O2*Dichloroethene*

Annealing

ArHe

H2N2

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Photolithography

Thin Films

Photo-

lithography

Cleaning

Front-End

Processes

EtchIon

Implantation

Planarization

Test &

Assembly

DesignWafer

Preparation

Photoresist Coating Processes

Exposure Processes

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Photoresist Coating Processes

p- epi

p+ substrate

field oxide

photoresist

PhotoresistsNegative Photoresist*

Positive Photoresist*

Other Ancillary Materials (Liquids)Edge Bead Removers*

Anti-Reflective Coatings*

Adhesion Promoters/Primers (HMDS)*

Rinsers/Thinners/Corrosion Inhibitors*

Contrast Enhancement Materials*

DevelopersTMAH*

Specialty Developers*

Inert GasesAr

N2

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Exposure Processes

p- epi

p+ substrate

field oxide

photoresist

ExposeKr + F2(gas)*

Inert GasesN2

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Ion Implantation

Thin Films

Photo-

lithography

Cleaning

Front-End

Processes

EtchIon

Implantation

Planarization

Test &

Assembly

DesignWafer

Preparation

Well Implants

Channel Implants

Source/Drain Implants

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Ion Implantation

180 kV

Resolving

Aperture

Ion Source

Equipment Ground

Acceleration Tube

90 Analyzing Magnet

Terminal Ground

20 kV

Focus Neutral beam and

beam path gated

Beam trap and

gate plate

Wafer in wafer

process chamber

X - axis

scanner

Y - axis

scanner

Neutral beam trap

and beam gate

GasesAr

AsH3

B11

F3*He

N2

PH3

SiH4

SiF4GeH4

SolidsGa

In

SbLiquids

Al(CH3)3

*High proportion of the total product use

junction

depthp- epi

p+ substrate

field oxide

photoresist mask

n-w ell

p-channel transistor

phosphorus

(-) ions

Process Conditions

Flow Rate: 5 sccm

Pressure: 10-5Torr

Accelerating Voltage: 5 to 200 keV

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Etch

Thin Films

Photo-

lithography

Cleaning

Front-End

Processes

EtchIon

Implantation

Planarization

Test &

Assembly

DesignWafer

Preparation

Conductor Etch

- Poly Etch and Silicon Trench

Etch

- Metal Etch

Dielectric Etch

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Conductor Etch

*High proportion of the total product use

EtchChambers

Cluster ToolConfiguration

Transfer

Chamber

Loadlock

Wafers

RIE Chamber

Transfer

Chamber

Gas Inlet

Exhaust

RF Power

Wafer

p+ substrate

p-well

n-channel transistor

n-w ell

p-channel transistor

source-drain areas

gate linew idthgate oxide

Polysilicon EtchesHBr *

C2F6

SF6*

NF3*

O2

Aluminum EtchesBCl3 *

Cl2

DiluentsAr

He

N2

Chemical Reactions

Silicon Etch: Si + 4 HBrSiBr4

+ 2 H2

Aluminum Etch: Al + 2 Cl2AlCl4Process Conditions

Flow Rates: 100 to 300 sccm

Pressure: 10 to 500 mTorr

RF Power: 50 to 100 Watts

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Dielectric Etch

*High proportion of the total product use

EtchChambers

Cluster ToolConfiguration

Transfer

Chamber

Loadlock

Wafers

RIE Chamber

Transfer

Chamber

Gas Inlet

Exhaust

RF Power

Wafer

Contact locations

n-w ell

p-channel transistor

p-well

n-channel transistorp+ substrate

Chemical Reactions

Oxide Etch: SiO2+ C2F6SiF4+ CO2+ CF4+ 2 CO

Process Conditions

Flow Rates: 10 to 300 sccm

Pressure: 5 to 10 mTorr

RF Power: 100 to 200 Watts

Plasma Dielectric EtchesCHF3*

CF4

C2F6

C3F8

CO *

DiluentsAr

He

N2

CO2

O2SF6

SiF4

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Cleaning

Thin Films

Photo-

lithography

Cleaning

Front-End

Processes

EtchIon

Implantation

Planarization

Test &

Assembly

DesignWafer

Preparation

Critical Cleaning

Photoresist Strips

Pre-Deposition Cleans

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Critical Cleaning

11 22 33 44 55

1 Organics 2 Oxides 3 Particles 4 Metals 5 Dry

H2SO4+ HF + NH4OH + HCl + H2O or IPA +

H2O2 H2O H2O2+ H2O H2O2+ H2O N2

H2O Rinse H2O Rinse H2O Rinse H2O Rinse

Contact locations

n-w ell

p-channel transistor

p-well

n-channel transistorp+ substrate

RCA CleanSC1 Clean (H2O + NH4OH + H2O2)*

* SC2 Clean (H2O + HCl + H2O2)*

Piranha Strip* H2SO4+ H2O2*

Nitride StripH3PO4*

Oxide StripHF + H2O*

Solvent CleansNMP

Proprietary Amines (liquid)

Dry CleansHF

O2Plasma

Alcohol + O3

Dry StripN2O

O2

CF4+ O2

O3

Process Conditions

Temperature: Piranha Strip is 180 degrees C.

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Thin Films

Thin Films

Photo-

lithography

Cleaning

Front-End

Processes

EtchIon

Implantation

Planarization

Test &

Assembly

DesignWafer

Preparation Chemical Vapor Deposition

(CVD) Dielectric

CVD Tungsten

Physical Vapor Deposition(PVD)

Chamber Cleaning

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Chemical Vapor Deposition (CVD) Dielectric

*High proportion of the total product use

CVD DielectricO2

O3TEOS *

TMP *

TEOS

Source

LPCVD

Chamber

Transfer

Chamber

Gas Inlet

Exhaust

RF Power

Wafer

Metering

Pump

Inert Mixing

Gas

Process Gas

Vaporizer

Direct

Liquid

Injection

n-well

p-channel transistor

p-well

n-channel transistorp+ substrate

Metal 1insulator layer 2

Chemical Reactions

Si(OC2H5)4+ 9 O3SiO2+ 5 CO + 3 CO2+ 10 H2O

Process Conditions (ILD)

Flow Rate: 100 to 300 sccm

Pressure: 50 Torr to Atmospheric

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Chemical Vapor Deposition (CVD) Tungsten

*High proportion of the total product use

CVD DielectricWF

6*

Ar

H2

N2

Output

Cassette

InputCassette

Wafer

HanderWafers

Water-cooled

Showerheads

Multistation Sequential

Deposition Chamber

Resistively

Heated Pedestal

n-w ell

p-channel transistor

p-well

n-channel transistorp+ substrate

titanium tungsten

Chemical Reactions

WF6+ 3 H2W + 6 HFProcess Conditions

Flow Rate: 100 to 300 sccm

Pressure: 100 mTorr

Temperature: 400 degrees C.

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Physical Vapor Deposition (PVD)

Barrier MetalsSiH

4

Ar

N2

N2Ti PVD Targets *

Physical

VaporDeposition

Chambers

Cluster ToolConfiguration

Transfer

Chamber

Loadlock

Wafers

PVD Chamber

Transfer

Chamber

Cryo Pump

Wafer

N S N

+

e -

Backside

He Cooling

Argon &

Nitrogen

Reactive

Gases

DC Power

Supply (+)

*High proportion of the total product use

n-w ell

p-channel transistor

p-w ell

n-channel transistorp+ substrate

Process Conditions

Pressure: < 5 mTorrTemperature: 200 degrees C.

RF Power:

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Chamber Cleaning

*High proportion of the total product use

Chamber CleaningC2F6*

NF3ClF3

Water-cooled

Showerheads

Multistation Sequential

Deposition Chamber

Resistively

Heated Pedestal

Chemical Reactions

Oxide Etch: SiO2+ C2F6SiF4+ CO2+ CF4+ 2 CO

Process ConditionsFlow Rates: 10 to 300 sccm

Pressure: 10 to 100 mTorr

RF Power: 100 to 200 Watts

Aluminum

Surface Coating

Process Material Residue

Chamber Wall Cross-Section

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Planarization

Thin Films

Photo-

lithography

Cleaning

Front-End

Processes

EtchIon

Implantation

Planarization

Test &

Assembly

DesignWafer

Preparation

Oxide Planarization

Metal Planarization

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Test and Assembly

Thin Films

Photo-

lithography

Cleaning

Front-End

Processes

EtchIon

Implantation

Planarization

Test &

Assembly

DesignWafer

Preparation

Electrical Test Probe

Die Cut and Assembly

Die Attach and Wire Bonding

Final Test

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Electrical Test Probe

Defective IC

Individual integrated circuits

are tested to distinguish good

die from bad ones.

n-well

p-channel transistor

p-well

n-channel transistorp+ substrate

bonding pad

nitrideMetal 2

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Die Cut and Assembly

Good chips are attached

to a lead frame package.

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Die Attach and Wire Bonding

lead frame gold wire

bonding pad

connecting pin

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Final Test

Chips are electrically

tested under varying

environmental conditions.

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References

1. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT,

Austin Community College, January 2, 1997.

2. Semiconductor Processing with MKS Instruments, Inc.

3. Worthington, Eric. New CMP architecture addresses key process issues, Solid State

Technology, January 1996.

4. Leskonic, Sharon. Overview of CMP Processing, SEMATECH Presentation, 1996.5. Gwozdz, Peter. Semiconductor Processing Technology SEMI, 1997.

6. CVD Tungsten, Novellus Sales Brochure, 7/96.

7. Fullman Company website. Fullman Company - The Semiconductor Manufacturing

Process, http://www.fullman.com/semiconductors/index.html, 1997.

8. Barrett, Craig R. From Sand to Silicon: Manufacturing an Integrated Circuit,Scientific

American Special Issue: The Solid State Century, January 22, 1998.