Finger Print Based Access System

8/2/2019 Finger Print Based Access System

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FINGER PRINT BASED VOTING MACHINE


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Abstract

Personal Safes are revolutionary locking storage cases that open with just the

touch of your finger. These products are designed as secure storage for

medications, jewelry, weapons, documents, and other valuable or potentially

harmful items. These utilize fingerprint recognition technology to allow access to

only those whose fingerprints you choose. It contains all the necessary

electronics to allow you to store, delete, and verify fingerprints with just the touch

of a button. Stored fingerprints are retained even in the event of complete power

failure or battery drain. These eliminates the need for keeping track of keys or

remembering a combination password, or PIN. It can only be opened when an

authorized user is present, since there are no keys or combinations to be copied

or stolen, or locks that can be picked.

In this project the fingerprint module from Miaxis Biometrics is used. It can store

up to 750 finger prints on its own memory. It can be controlled through its serial

port. The microcontroller AT89S52 interact with the module. You can Add a

fingerprint, Delete a fingerprint and Identify the fingerprint. To add a fingerprint,

just show the finger on the module and press the ADD key. Now themicrocontroller will send the ADD command to the module and the module will

add it into the memory. To delete the finger follow the same as above.

To identify the finger, press the Identify button and if the finger matches then the

Relay is complemented. Also the fingerprint ID is displayed over the LCD display.


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Block diagram:


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MICRO CONTROLLER 89S51


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MICROCONTROLLER 89S51

3.1 INTRODUCTION:

The 8051 family of microcontrollers is based on architecture which is highly

optimized for embedded control systems. It is used in a wide variety of applications from

military equipment to automobiles to the keyboard on PC. The basic architecture consists

of the following features:

One 8051 processor cycle consists of twelve oscillator periods. Each of the twelve

oscillator periods is used for a special function by the 8051 core such as op code fetches

and samples of the interrupt daisy chain for pending interrupts. The time required for any

8051 instruction can be computed by dividing the clock frequency by 12, inverting that

result and multiplying it by the number of processor cycles required by the instruction in

question. Therefore, if you have a system which is using an 11.059MHz clock, you can

compute the number of instructions per second .inverting this will provide the amount of

time taken by each instruction cycle. Features of a microcontroller is given as follows:

An eight bit ALU

32 discrete I/O pins (4 groups of 8) which can be individually accessed

Two 16 bit timer /counters

Full duplex UART

6 interrupt sources with 2 priority levels

28 bytes of on board RAM

Separate 64K byte address spaces for DATA and CODE memory


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3.2 MEMORY ORGANIZATION:

The 8051 architecture provides the user with three physically distinct memory

spaces which can be seen in figure 3.1.Each memory space consists of contiguous

addresses from 0 to maximum size, in bytes, of the memory space .Address overlaps are

resolved by utilizing theseinstructions which refer specifically to a given address space.

The three memory spaces function as described below.

3.2.1 THE CODE SPACE:

The first memory space is the CODE segment in which the executable program

resides. This segment can be upto 64K (since it is addressed by 16 address lines). The

processor treats this segment as read only and will generate signals appropriate to access a

memory device such as an EPROM. However, this does not mean that the CODE segment

must be implemented using an EPROM. Many embedded systems these days are using

EEPROM which allows the memory to be overwritten either by the 8051 itself or by an

external device. This makes upgrade to the product easy to do since new software can be

downloaded into the EEPROM rather than having to disassemble it and install a new

EPROM.

FIG-3.1 Memory organization


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3.2.2 THE DATA SPACE:

The second memory space is the 128 bytes of internal RAM on the 8051, or the

first 128 bytes of internal RAM on the 8052. This segment is typically referred to as the

DATA segment. The RAM locations in this segment are accessed in one or two cycles

depending on the instruction. This access time is much quicker than access to the XDATA

segment because memory is directly rather than via a memory pointer such as DPTR which

must first be initialized. Therefore, frequently used variables and temporary scratch

variables are usually assigned to the DATA segment.

Variables stored in the DATA segment can also be accessed indirectly via R0 or

R1.The register being used as the memory pointer must contain the address of the byte to

be retrieved or altered. These instructions can take one or two processor cycles depending

on the source/destination data byte.

3.3 PROCESSOR STATUS:

Processor status is kept in a bit addressable SFR called PSW(Processor Status

Word).This register contains the carry bit, an auxiliary bit which is used with BCD

operations, the Accumulator parity flag and overflow flag, two general purpose flags, and

two bits which select the register bank to use as the default. As mentioned before, the

register bank selection bits make a two bit number from 0 to 3 which indicate the bank to

be used. Bank 0 begins at the base of the DATA segment (address 00H), bank 1 begins at

08H, bank 2 begins at address 10H and bank 3 at address 18H.Any of these memory

locations are always available for direct and indirect memory accesses via their addresses

regardless of the register bank selection.


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3.3.1 POWER CONTROL:

The CHMOS versions of the 8051 feature two power saving modes that can be

activated by software: idle mode and power down mode. These modes are accessed via the

PCON (Power Control). The idle mode is activated by setting the IDLE bit high. The idle

mode causes all program execution to stop. Internal RAM contents are preserved and the

oscillator continues to run but is blocked from the CPU. The timers and the UART

continue to function as normal. Idle mode is terminated by the activation of any interrupt.

Upon completion of the interrupt service routine, execution will continue from the

instruction following the instruction which set the IDLE bit.

3.3.2 INTERRUPTS OF 8051:

The basic 8051 supports six interrupt sources: two external interrupts, two

timer/counter interrupts, and a serial byte in/out interrupt. These interrupt sources force the

processor to vector to one of five locations in the lowest part of the CODE address space

(serial input and serial output interrupts share the same vector ). The interrupt service

routine must either reside there or be branched from there.

3.3.3 ON-BOARD TIMER/COUNTERS:

The standard 8051 has two timer/counters (other 8051 family members have

varying amounts), each of which case they count processor cycles or can be used to count

falling edges on the signal applied to their respective I/O pin (either T0 or T1). When used

as a counter, the input signal must have a frequency equal to or lower than the instruction

cycle frequency divided by 2 i.e: the oscillator frequency /24 ,since the incoming signal is

sampled every instruction cycle, and the counter is incremented only when a 1 to 0

transition is detected which will require two samples . If desired, the timer/counters can

force a software interrupt when they overflow. The TCON (Timer Control ) SFR is used tostart or stop the timers as well as hold the overflow flags of the timers. The timer/counters

are started or stopped by changing the timer run bits (TR0 and TR1) in the TCON.

3.4 FEATURES:


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Endurance:1000 write/erase cycles

4.0 V to 5.5V operating range

Fully static operation:0 to 33 MHz

Three-level program memory lock

128x x 8 bit Internal RAM

32 programmable I/O lines

Two 16-bit timer/counters

Six interrupt sources

Full duplex UART serial channel

Low-power idle and power-down modes

Interrupt Recovery from Power-down mode

Watchdog Timer

Dual Data Pointer

Power-off Flag

Fast Programming Time

Flexible ISP Programming (Byte and Page Mode)

3.5 DESCRIPTION:

The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with

4K bytes of In-System Programmable Flash memory. The device is manufactured using

Atmel high-density nonvolatile memory technology and is compatible with the industry-

standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory

to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By

combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip,

the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and

cost-effective solution to many embedded control applications.The AT89S51 provides the following standard features: 4K bytes of Flash, 128

bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters,

a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,

and clock circuitry. In addition, the AT89S51 is designed with static logic for operation

down to zero frequency and supports two software selectable power saving modes. The


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Supply voltage (all packages except 42-PDIP).

GND:

Ground (all packages except 42-PDIP; for 42-PDIP GND connects only the logic core and

the embedded program memory).

VDD:

Supply voltage for the 42-PDIP which connects only the logic core and the embedded

program memory.

PWR/GND:

Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWR/GND and GND

are weakly

connected through the common silicon substrate, but not through any metal link. The

application board must connect both GND and PWRGND to the board ground.

PORT 0:

Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can

sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-

impedance inputs. Port 0 can also be configured to be the multiplexed low-order

address/data bus during accesses to external program and data memory. In this mode, P0

has internal pull-ups. Port 0 also receives the code bytes during Flash programming and

outputs the code bytes during program verification. External pull-ups are required

during program verification.

PORT 1:

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output

buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled


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high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are

externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1

also receives the low-order address bytes during Flash programming and verification.

PORT2:




externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2

emits the high-order address byte during fetches from external program memory and during

accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this

application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to

external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of

the P2 Special Function Register. Port 2 also receives the high-order address bits and some

control signals during Flash programming and verification.

PORT 3:




externally being pulled low will source current (IIL) because of the pull-ups. Port 3

receives some control signals for Flash programming and verification. Port 3 also serves

the functions of various special features of the AT89S51, as shown in the following table.

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0 (external interrupt 0)


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P3.3 INT1 (external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR (external data memory write strobe)

P3.7 RD (external data memory read strobe)

RST:

Reset input. A high on this pin for two machine cycles while the oscillator is

running resets the device. This pin drives High for 98 oscillator periods after the Watchdog

times out. The DIS-RTO bit in SFR AUXR (address 8EH) can be used to disable this

feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG:

Address Latch Enable (ALE) is an output pulse for latching the low byte of the

address during accesses to external memory. This pin is also the program pulse input

(PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate

of 1/6 the oscillator frequency and may be used for external timing or clocking purposes.

Note, however, that one ALE pulse is skipped dur-ing each access to external data

memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH.

With the bit set, ALE is active only during a MOVX or MOVC instruction.

Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the

microcontroller is in external execution mode.

PSEN:

Program Store Enable (PSEN) is the read strobe to external program memory.

When the AT89S51 is executing code from external program memory, PSEN is activated

twice each machine cycle, except that two PSEN activations are skipped during each access

to exter-nal data memory.


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EA/VPP:

External Access Enable. EA must be strapped to GND in order to enable the device

to fetch code from external program memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA

should be strapped to VCC for internal program executions. This pin also receives the 12-

volt programming enable voltage (VPP) during Flash programming.

XTAL1:

Input to the inverting oscillator amplifier and input to the internal clock operating

circuit.

XTAL2:

Output from the inverting oscillator amplifier.

INTERRUPT REGISTERS:

The individual interrupt enable bits are in the IE register. Two priorities can be set

for each of the five interrupt sources in the IP register.

DUAL DATA POINTER REGISTERS:

To facilitate accessing both internal and external data memory, two banks of 16-bit

Data Pointer Registers are provided: DP0 at SFR address locations 82H- 83H and DP1 at

84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user

should alwaysinitialize the

DPS bit to the appropriate value before accessing the respective Data Pointer Register.

POWER OFF FLAG:


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The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is

set to 1 during power up. It can be set and rest under software control and is not affected

by reset.

PROGRAM MEMORY:

If the EA pin is connected to GND, all program fetches are directed to external

memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses

0000H through FFFH are directed to internal memory and fetches to addresses 1000H

through FFFFH are directed to external memory.

DATA MEMORY:

The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are

accessible via direct and indirect addressing modes. Stack operations are examples of

indirect addressing, so the 128 bytes of data RAM are available as stack space.

3.5.2 OSCILLATOR CHARACTERISTICS:

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier

that can be configured for use as an on-chip oscillator.Either a quartz crystal or ceramic

resonator may be used. To drive the device from an external clock source, XTAL2 should

be left unconnected while XTAL1 is driven, as shown in Figure 3.3. There are no

requirements on the duty cycle of the external clock signal, since the input to the internal

clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage

high and low -time specifications must be observed.


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FIG-3.3 Oscillator connection

3.5.3 IDLE MODE:

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain

active. The mode is invoked by software. The content of the on-chip RAM and all the

special function registers remain unchanged during this mode. The idle mode can be

terminated by any enabled interrupt or by a hardware reset.

When idle mode is terminated by a hardware reset, the device normally resumes

program execution from where it left off, up to two machine cycles before the internal reset

algorithm takes control. On-chip hardware inhibits access to internal RAM in this event,

but access to the port pins is not inhibited.

To eliminate the possibility of an unexpected write to a port pin when idle mode is

terminated by a reset, the instruction following the one that invokes idle mode should not

write to a port pin or to external memory.

3.5.4 POWER-DOWN MODE:


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In the Power-down mode, the oscillator is stopped, and the instruction that invokes

Power-down is the last instruction executed. The on-chip RAM and Special Function

Registers retain their values until the Power-down mode is terminated. Exit from Power-

down mode can be initiated either by a hardware reset or by activation of an enabled

external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-

chip RAM. The reset should not be activated before VCC is restored to its normal

operating level and must be held active long enough to allow the oscillator to restart and

stabilize.

3.6 TIMER 0 AND TIMER 1 OPERATION:

The 8051 comes equipped with two timers, both of which may be controlled, set,

read, and configured individually.

The 8051 timers have three general functions:

1) Keeping time and/or calculating the amount of time between events,

2) Counting the events themselves, or

3) Generating baud rates for the serial port.

TIMER 0:

Timer 0 functions as either a timer or event counter in four modes of operation.

Timer 0 is controlled by the four lower bits of the TMOD register (see Table 2-5) and bits

0, 1, 4 and 5 of the TCON register TMOD register selects the method of timer gating

(GATE0), timer or counter operation (T/C0#) and mode of operation (M10and M00). The

TCON register provides timer 0 control functions: overflow flag (TF0), run control bit

(TR0), interrupt flag (IE0) and interrupt type control bit (IT0).

For normal timer operation (GATE0= 0), setting TR0 allows TL0 to be

incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to

control timer operation.Timer0 overflow (count rolls over from all 1s to all 0s) sets TF0

flag, generating an interrupt request. It is important to stop timer/counter before changing

mode.


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3.6.1 T0 MODE 0:

Mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (TH0

register)with a modulo 32 pre scalar implemented with the lower five bits of the TL0

register. The upper three bits of TL0 register are indeterminate and should be ignored. Pre

scalar overflow increments the TH0 register. As the count rolls over from all 1s to all 0s,

it sets the timer interrupt flag TF0. The counted input is enabled to the Timer when TR0 =

1 and either GATE = 0 or INT0 = 1.(Setting GATE = 1 allows the Timer to be controlled

by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the

Special Function register TCON GATE is in TMOD. The 13-bit register consists of all 8

bits of TH0 and the lower 5 bits of TL0. The upper 3bits of TL0 are indeterminate and

should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 0 operation

is the same for Timer 0 as for Timer 1. There are two different GATE bits, one for Timer 1

(TMOD.7) and one for Timer 0 (TMOD.3).

FIG -3.4 Timer 0 in mode 0

3.6.2 T0 MODE 1:


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Mode 1 is the same as Mode 0, except that the Timer register is being run with all

16bits.Mode 1 configures timer 0 as a 16-bit timer with the TH0 and TL0 registers

connected in cascade. The selected input increments the TL0 register.

FIG- 3.5 Timer 0 in mode 1

3.6.3 T0 MODE 2:

Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that

automatically reloads from the TH0 register TL0 overflow sets TF0 flag in the TCON

register and reloads TL0 with the contents of TH0, which is preset by software. When the

interrupt request is serviced, hardware clears TF0. The reload leaves TH0unchanged. The

next reload value may be changed at any time by writing it to the TH0register.Mode 2

operation is the same for Timer/Counter 1.


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FIG-Timer 0 in mode 2

3.6.4 T0 MODE 3:

Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bittimers. This mode is provided for applications requiring an additional 8-bittimer or counter.

TL0 use the timer 0 control bits C/T0# and GATE0 in the TMOD register,and TR0 and

TF0 in the TCONregister

in the normal manner. TH0 is locked into a timer function (counting FPER /6) and takes

over use of the timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of timer

1 is restricted when timer 0 is in mode 3.

FIG-3.7 Timer 0 in mode3


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TIMER 1 :

Timer 1 is identical to timer 0, except for mode 3, which is a hold-count mode. The

following comments help to understand the differences:

Timer 1 functions as either a timer or event counter in three modes of operation.

Timer1s mode 3 is a hold-count mode.

Timer 1 is controlled by the four high-order bits of the TMOD register and bits 2, 3, 6 and

7 of the TCON register The TMOD register selects the method of timer gating (GATE1),

timer or counter operation (C/T1#) and mode of operation (M11 and M01). The TCON

register provides timer 1 control functions: overflow flag (TF1), run control bit (TR1),

interrupt flag (IE1) and interrupt type control bit (IT1).

Timer 1 can serve as the baud rate generator for the serial port. Mode 2 is best suited for

this purpose.

For normal timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by

the selected input. Setting GATE1 and TR1 allows external pin INT1# to control timer

operation.

Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an

interrupt request.

When timer 0 is in mode 3, it uses timer 1s overflow flag (TF1) and run control bit(TR1). For this situation, use timer 1 only for applications that do not require an interrupt

(such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3 to

turn it off and on.

It is important to stop timer/counter before changing modes.

3.6.5 T1 MODE 0:

Mode 0 configures Timer 1 as a 13-bit timer, which is set up as an 8-bit timer (TH1

register) with a modulo-32 pre scaler implemented with the lower 5 bits of the TL1

register. The upper 3 bits of the TL1 register are ignored. Pre scaler overflow increments

the TH1 register.


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FIG-3.8 Timer1 in mode0

3.6.6 T1 MODE 1:

Mode 1 configures Timer 1 as a 16-bit timer with the TH1 and TL1 registers

connected in cascade. The selected input increments the TL1 register.

3.6.7 T1 MODE 2:

Mode 2 configures Timer 1 as an 8-bit timer (TL1 register) with automatic reload

from the TH1 register on overflow. TL1 overflow sets the TF1 flag in the TCON register

and reloads TL1 with the contents of TH1, which is preset by software. The reload leavesTH1 unchanged.

FIG-3.9 Timer 1 in mode2


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3.6.8 T1 MODE 3:

Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to

halt Timer 1 when TR1 run control bit is not available i.e., when Timer 0 is in mode 3.

3.6.9 INTERRUPT:

Each timer handles one interrupt source; that is the timer overflow flag TF0 or TF1.

This flag is set every time an overflow occurs. Flags are cleared when vectoring to the

timer interrupt routine. Interrupts are enabled by setting ETx bit in IE0 register. This

assumes interrupts are globally enabled by setting EA bit in the IE0 register.

FIG- 3.10 Timer interrupt system


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TABLE 3.1 TCON register


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TABLE 3.2 TMOD register

TABLE- 3.3 TH0 register


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TABLE 3.4 TL0 register

TABLE 3.5 TH1 register

TABLE-3.6 TL1 register


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LIQUID CRYSTAL DISPLAY


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LIQUID CRYSTAL DISPLAY

INTRODUCTION:

The most commonly used Character based LCDs are based on Hitachi's HD44780

controller or other which are compatible with HD44580. Liquid crystal displays are created

by sandwiching a thin (10-12 micro mm ) layer of a liquid crystal fluid between two glass

plates. A transparent, electrically conductive film or back plane is put up on the rear glass

sheet. The transparent sections of the conductive film in the shape of the desired characters

are coated on the front glass plate. When a voltage is applied between a segment and the

back plane, an electric field is created in the region under the segment. This electric field

changes the transmission of light through the region under the segment film.

PIN DESCRIPTION:

The most commonly used LCDs found in the market today are 1 Line, 2 Line or 4

Line LCDs which have only 1 controller and support at most of 80 charachers, whereas

LCDs supporting morethan80charactersmadeuseof2HD44780controllers.Most LCDs with

1 controller has 14 Pins and LCDs with 2 controller has 16 Pins (two pins are extra in both

for back-light LED connections).Pin description is shown in the table below:

FIG-10.1 Character LCD type HD44708 Pin diagram


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TABLE-10.1 Character LCD pins with 1 controller

INSTRUCTION REGISTER AND DATA REGISTER :

There are two 8-bit registers in HD44780 controller Instruction and Data register.

Instruction register corresponds to the register where you send commands to LCD e.g LCD

shift command, LCD clear, LCD address etc. and Data register is used for storing data

which is to be displayed on LCD. when send the enable signal of the LCD is asserted, the

data on the pins is latched in to the data register and data is then moved automatically to the

DDRAM and hence is displayedontheLCD. Data Register is not only used for sending data

to DDRAM but also for CGRAM, the address where you want to send the data, is decided

by the instruction you send to LCD.


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TABLE-10.2 Character LCD pins with 2 controller

COMMANDS AND INSTRUCTION SET:

Only the instruction register (IR) and the data register (DR) of the LCD can be

controlled by the MCU. Before starting the internal operation of the LCD, control

information is temporarily stored into these registers to allow interfacing with various

MCUs, which operate at different speeds, or various peripheral control devices. The

internal operation of the LCD is determined by signals sent from the MCU. These signals,which include register selection signal (RS), read/write signal (R/W), and the data bus

(DB0 to DB7), make up the LCD instructions (Table-10.3). There are four categories of

instructions that:

Designate LCD functions, such as display format, data length, etc.


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Set internal RAM addresses

Perform data transfer with internal RAM

Perform miscellaneous functions

Below is a brief list of useful commands which are used frequently while working on the

LCD.

S.No Instruction Hex Decimal

1 Function Set: 8-bit, 1 Line, 5x7 Dots 0x30 48




5 Entry Mode 0x06 6

6Display off Cursor off(clearing display without clearing DDRAM

content)

0x08 8

7 Display on Cursor on 0x0E 14

8 Display on Cursor off 0x0C 12

9 Display on Cursor blinking 0x0F 15

10 Shift entire display left 0x18 24

12 Shift entire display right 0x1C 30

13 Move cursor left by one character 0x10 16

14 Move cursor right by one character 0x14 20

15 Clear Display (also clear DDRAM content) 0x01 1

16Set DDRAM address or cursor position ondisplay

0x80+add 128+add

17Set CGRAM address or set pointer to CGRAM

location0x40+add 64+add

TABLE-10.3 Frequently used commands and instructions for LCD

BUSY FLAG:

Busy Flag is an status indicator flag for LCD. When we send a command or data to

the LCD for processing, this flag is set (i.e BF =1) and as soon as the instruction is

executed successfully this flag is cleared (BF = 0).

To read Busy Flag, the condition RS = 0 and R/W = 1 must be met and The MSB

of the LCD data bus (D7) act as busy flag. When BF = 1 means LCD is busy and will not


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accept next command or data and BF = 0 means LCD is ready for the next command or

data to process.

READING THE BUSY FLAG:

There must be some delay which is needed to be there for LCD to successfully process

the command or data. So this delay can be made either with a delay loop of specified time

more than that of LCD process time or we can read the busy flag, which is recommended.

The reason to use busy flag is that delay produced is almost for the exact amount of time

for which LCD need to process.

STEPS TO READ BUSY FLAG:

When we send the command, the BF or D7th bit of the LCD becomes 1 and as soon as

the command is processed the BF = 0. Following are the steps while reading the Busy flag.

Select command register

Select read operation

Send enable signal

Read the flag

SENDING COMMANDS TO LCD:

To send commands we simply need to select the command register. Everything is same

done in the initialization routine. Summarizing the common steps and put them in a single

subroutine.

Move data to LCD port

select command register

select write operation

send enable signal

wait for LCD to process the command

HD44708 LCD:


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DESCRIPTION:

The HD44780U dot-matrix liquid crystal display controller and driver LSI displays

alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-

matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the

functions such as display RAM, character generator, and liquid crystal driver, required for

driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal

system can be interfaced with this controller/driver.

A single HD44780U can display up to one 8-character line or two 8-character lines.

The HD44780U has pin function compatibility with the HD44780S which allows the user

to easily replace an LCD-II with an HD44780U. The HD44780U character generator ROM

is extended to generate 208 5X8 dot character fonts and 32 5X10 dot character fonts for a

total of 240 different character fonts. The low power supply (2.7V to 5.5V) of the

HD44780U is suitable for any portable battery-driven product requiring low power

dissipation.

LCD FEATURES:

5 X8 and 5 X10 dot matrix possible

Low power operation support: 2.7 to 5.5V

Wide range of liquid crystal display driver power 3.0 to 11V

Liquid crystal drive waveform

A (One line frequency AC waveform)

Correspond to high speed MPU bus interface

2 MHz (when VCC = 5V)

4-bit or 8-bit MPU interface enabled

80X8-bit display RAM (80 characters max.)

9,920-bit character generator ROM for a total of 240 character fonts

208 character fonts (5 X8 dot)

32 character fonts (5 X10 dot)

HD44780U FEATURES:


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64 X 8-bit character generator RAM

8 character fonts (5 X 8 dot)

4 character fonts (5 X 10 dot)

16-common 40-segment liquid crystal display driver

Programmable duty cycles

1/8 for one line of 5 X 8 dots with cursor

1/11 for one line of 5 X 10 dots with cursor

1/16 for two lines of 5 X 8 dots with cursor

Wide range of instruction functions:

Display clear, cursor home, display on/off, cursor on/off, display character blink,

cursor shift, display shift

Pin function compatibility with HD44780S

Automatic reset circuit that initializes the controller/driver after power on

Internal oscillator with external resistors

Low power consumption

FUNCTION DESCRIPTION:

REGISTERS:

The HD44780U has two 8-bit registers, an instruction register (IR) and a data

register (DR).The IR stores instruction codes, such as display clear and cursor shift, and

address information for display data RAM (DDRAM) and character generator RAM

(CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to

be written into DDRAM or CGRAM and temporarily stores data to be read from DDRAM

or CGRAM. Data written into the DR from the MPU is automatically written into DDRAM

or CGRAM by an internal operation. The DR is also used for data storage when reading

data from DDRAM or CGRAM. When address information is written into the IR, data is

read and then stored into the DR from DDRAM or CGRAM by an internal operation.

Data transfer between the MPU is then completed when the MPU reads the DR. After the

read, data in DDRAM or CGRAM at the next address is sent to the DR for the next read

from the MPU. By the register selector (RS) signal, these two registers can be selected.


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ADDRESS COUNTER (AC):

The address counter (AC) assigns addresses to both DDRAM and CGRAM. When

an address of an instruction is written into the IR, the address information is sent from the

IR to the AC. Selection of either DDRAM or CGRAM is also determined concurrently by

the instruction.

After writing into (reading from) DDRAM or CGRAM, the AC is automatically

incremented by 1 (decremented by 1). The AC contents are then output to DB0 to DB6

when RS = 0 and R/W = 1

REGISTER SELECTION:

RS R/W Operation

0 0 IR write as an internal operation (display clear, etc.)

0 1 Read busy flag (DB7) and address counter (DB0 to DB6)

1 0 DR write as an internal operation (DR to DDRAM or CGRAM)

1 1 DR read as an internal operation (DDRAM or CGRAM to DR)

DISPLAY DATA RAM (DDRAM):

Display data RAM (DDRAM) stores display data represented in 8-bit character

codes. Its extended capacity is 80 8 bits, or 80 characters. The area in display data RAM

(DDRAM) that is not used for display can be used as general data RAM. FIG-10.2 for the

relationships between DDRAM addresses and positions on the liquid crystal display.The

DDRAM address (ADD) is set in the address counter (AC) as hexadecimal.

1-line display (N = 0) (FIG-10.3 )

When there are fewer than 80 display characters, the display begins at the head position.

For example, if using only the HD44780, 8 characters are displayed. See FIG-10.4. When

the display shift operation is performed, the DDRAM address shifts as shown in FIG-10.4


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FIG-10.2 DRAM address

FIG-10.3 1-Line display

FIG-10.4 1-Line by 8-Character display

2-line display (N = 1) (FIG-10.5)

Case 1: When the number of display characters is less than 40X2 lines, the two lines are

displayed from the head. Note that the first line end address and the second line start

address are not consecutive. For example, when just the HD44780 is used, 8 characters 2

lines are displayed. When display shift operation is performed, the DDRAM address shifts.

FIG-10.5 2-Line display


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Case 2: For a 16-character 2-line display, the HD44780 can be extended using one 40-

output extension driver. When display shift operation is performed, the DDRAM address

shifts as shown in FIG-10.7.



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HD44708 BLOCK DIAGRAM:


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FIG-10.8 Block diagram of HD44708 LCD

72

PIN ARRANGEMENT:


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FIG-10.9 Pin arrangement of HD44708 LCD

73

PIN FUNCTIONS:


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TABLE-10.4 Pin description of HD44708 LCD


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Fingerprint Recognition Sensor

The sensor is a solid-state fingerprint sensor that reliably captures fingerprint information.It is designed to integrate into devices for improved security and convenience. The sensor

provides a reliable, quick and user-friendly alternative to passwords, PIN's and other forms

of user authentication. This fingerprint scanner is capable of gathering and storing uniquefinger prints. Simply hold your finger on the optical scanner, query the device over serial,

and you will be issued a unique ID. Use that ID within your embedded system to determine

access levels, time clocks, door locks, etc. Unit includes 4 pin connector cable to connectand read to controller. The outputs is TTL level serial data. A biometric sensor, fingerprint

sensor to be specific, also known as the fingerprint reader, is a fingerprint image capture

device, the very front end of the biometric fingerprint identification/verification module.

The fingerprint sensor captures the fingerprint images, matches the uniqueness of eachprint read by the sensor and compares it to the one stored in its module or local system

database. It consists of optical fingerprint sensor, high performance DSP processor and

Flash. It boasts of

functions such as fingerprint enrollment, fingerprint deletion, fingerprint verification,fingerprint upload, fingerprint download, etc.

Features

Rugged, solid-state optical fingerprint sensor

High resolution 500 DPI imager Adapts to wet/dry fingers

Simple Interfacing protocol

Specifications:

Module is connected to HOST via 4 PIN cable(provided with module).


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1 +Ve Positive power pin(+), Apply proper filtered DC regulated power (Typical 5V)

2 TXD Module Serial Transmit Output, Open-drain output, need to use pull-up

Resistance to supply in application (Typical value: 10K)

3 RXD Module Serial Receive Input, Wide voltage input up to 7V (TTL level)

4 GND Power supply ground

Applications

Computer peripherals improves security and convenience

Transportation systems validation of operators, drivers and inspectors Medical equipment authorization of operator or technician

Physical access systems approval for entry

Kiosks and vending machines confirmation of person receiving the selection

Point of Sale terminals authentication of tellers and cashiers

Power supply design


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Voltage Regulator:Voltage Regulator is used to provide a constant voltage. The input to a

Voltage Regulator is +2 volts more than the output voltage. Many types of Voltage

Regulator are used. 7805 provides an output of 5 volts, when the input is greater then 7

volts, 7809 provides an output of 9 volts when the input is greater Than 11 volts similarly

7812 provides an output of 12 volts when the input is greater than 14 volts. When the

current in the regulator gets heated up so a heat sink is used which reduces the heat and

saves the regulator from damage.

Central Tapped transformer:

In this type of transformer there are two ends in their primary

winding and three in their secondary winding. The middle end of these three ends iscommon end, w. r. t. This end voltage on both remaining ends is same.Generally, common

end is of black wire and the remaining two wire red, green or yellow.

These transformers are purchase according to the supply, which is to be obtained

from them. Suppose we want to obtain 6v supply from double winding transformer than we

have to buy 6-0-6volt transformer. Double winding transformer is of following voltage

capacities are available in the market:

3-0-3v, 4.5-04.5v, 6-0-6v, 9-0-v, 12-0-12v, 24-0-24v

Full rectification using two diodes:

In this rectifier circuit, two diodes are used and each one is connected on the two

ends of secondary winding of double winding transformer (center taped transformer) as

shown in the fig.

According to the circuit, positive end of both the diodes is connected with each

other. Diode D1 conducts only when positive half cycle comes on its negative end.

Similarly, diode D2 conducts only when positive half cycle of AC comes on its negative

end. On both of these diodes positive half cycle comes alternately, means when positive

half cycle of AC comes on diode D1 then diode D2 gets half cycle and when diode D2 gets

positive half cycle. In this way diode D1, D2 conducts alternately using every half cycle of

AC. As a result of this, DC is obtained at the output end in which no gaps remain left


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between the two continuous pulses. If in this circuits, connecting of both the diodes are

reversed then continuous negative pulses will be obtained from the common negative ends

of the diode.

In this way, full wave rectification is obtained by connecting same

polarity diodes on both ends of the secondary of the double winding transformer. The

frequency of the pulses found at the output is just double of the frequency of the input

(50c/s) means it is 100c/s

- ++

780

200MICROFARAD

5402

5402

Step Down Transformer

PRIMARY220V

SECONDARY12-0-


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BIBLOGRAPHY

Reference Books:

The 8051 Microcontroller and Embedded Systems - Muhammad Ali Mazidi

The 8051 Micro-controller - Ayala

Programming and customizing the 8051 - Myke Predko

Websites:

www.atmel.com

www.analogicgroup.com

www.philips.com

www.google.com

www.gsmworld.com
http://www.atmel.com/http://www.analogicgroup.com/http://www.philips.com/http://www.google.com/http://www.gsmworld.com/http://www.atmel.com/http://www.analogicgroup.com/http://www.philips.com/http://www.google.com/http://www.gsmworld.com/

Date post:	06-Apr-2018
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Finger Print Based Access System

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