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Finite State MachinesFinite State Machines
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Finite State Machines (FSMs)Finite State Machines (FSMs)
Any Circuit with Memory Is a Finite StateAny Circuit with Memory Is a Finite StateMachineMachine
Even computers can be viewed as huge FSMsEven computers can be viewed as huge FSMs
Design of FSMs InvolvesDesign of FSMs Involves Defining statesDefining states Defining transitions between statesDefining transitions between states
Optimization / minimizationOptimization / minimization
Above Approach Is Practical for SmallAbove Approach Is Practical for SmallFSMs OnlyFSMs Only
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Moore FSMMoore FSM
Output Is a Function ofOutput Is a Function of aa Present State OnlyPresent State Only
Present State
Register
Next State
function
Output
function
Inputs
Present StateNext State
Outputs
clock
reset
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Mealy FSMMealy FSM Output Is a Function of a Present State andOutput Is a Function of a Present State and
InputsInputs
Next State
function
Output
function
Inputs
Present StateNext State
Outputs
Present State
Register
clock
reset
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Moore MachineMoore Machine
state 1/
output 1
state 2/
output 2
transition
condition 1
transition
condition 2
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Mealy MachineMealy Machine
state 1 state 2
transition condition 1/
output 1
transition condition 2/
output 2
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FSMs in VHDLFSMs in VHDL
Finite State Machines Can Be EasilyFinite State Machines Can Be EasilyDescribed With ProcessesDescribed With Processes
Synthesis Tools Understand FSMSynthesis Tools Understand FSM
Description If Certain Rules Are FollowedDescription If Certain Rules Are Followed State transitions should be described in aState transitions should be described in a
process sensitive toprocess sensitive to clockclock andand asynchronousasynchronousresetreset signals onlysignals only
Outputs described as concurrent statementsOutputs described as concurrent statementsoutside the processoutside the process
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Moore FSMMoore FSMProcess (clock, reset)Process (clock, reset)
Present State
Register
Next State
function
Output
function
Inputs
Present State
Next State
Outputs
clock
reset
concurrent
statements
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Mealy FSMMealy FSMProcess (clock, reset)Process (clock, reset)
Next State
function
Output
function
Inputs
Present StateNext State
Outputs
Present State
Register
clock
reset
concurrent
statements
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Moore FSMMoore FSM -- Example 1Example 1
Moore FSM that Recognizes Sequence 10Moore FSM that Recognizes Sequence 10
S0 / 0 S1 / 0 S2 / 1
0 0
0
1
11S0 / 0 S1 / 0 S2 / 1
0 0
0
1
11
reset
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Moore FSM in VHDLMoore FSM in VHDL
TYPE state IS (S0, S1, S2);TYPE state IS (S0, S1, S2);SIGNAL Moore_state: state;SIGNAL Moore_state: state;
U_Moore: PROCESS (clock, reset)U_Moore: PROCESS (clock, reset)
BE
GINBE
GINIF(reset = 1) THENIF(reset = 1) THENMoore_state IF input = 1 THENIF input = 1 THEN
Moor
e_state
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WHEN S1 =>WHEN S1 =>IF input = 0 THENIF input = 0 THEN
Moore_state
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Mealy FSM in VHDLMealy FSM in VHDLTYPE state IS (S0, S1);TYPE state IS (S0, S1);SIGNAL Mealy_state: state;SIGNAL Mealy_state: state;
U_Mealy: PROCESS(clock, reset)U_Mealy: PROCESS(clock, reset)BEGINBEGIN
IF(reset = 1) THENIF(reset = 1) THENMealy_state IF input = 1 THENIF input = 1 THEN
Mealy_state
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WHEN S1 =>WHEN S1 =>
IF input = 0 THENIF input = 0 THENMealy_state