First Quarter 2003 Newsletter for Altera...

NV-2003-Q1

First Quarter 2003

Newsletter for Altera Customers

Inside This Issue:

� Nios Processor Version 3.0Delivers the FeaturesCustomers Want MostPage 4

� Using the Nios EmbeddedProcessor, ProgrammableLogic, IP & SOPC BuilderTools to Construct CustomMicrocontrollersPage 7

First Quarter 2003 News & Views Altera Corporation2

With 20 years of innovation behind us, we at Altera find ourselves at a very exciting point intime, in full view of new territories we are set to conquer. Today’s FPGAs, far from theiroriginal versions, have reinvented themselves into powerful chips that are the heart of ourcustomers’ systems. Driven by our steadfast objective of giving our customers what theyneed, we have reached the crossroads where the benefits and cost structure of our FPGAsnow meet the strict demands of customers who want to slash system costs, without sacrific-ing features or performance.

Consequently, a paradigm shift is occurring, not just for Altera, but for the semiconductorindustry as a whole. System architects and designers are increasingly using programmable

logic devices (PLDs) to replace other technologies. Our markets have expanded far beyond ouroriginal comfort zone communications as other markets clamor louder than ever for flexibilitywith no price penalty. StratixTM devices have presented themselves as a viable alternative to digitalsignal processors (DSPs) for imaging applications, for example. Replacing microcontrollers with aNios® processor embedded into a CycloneTM device is creating quite a storm as a highly flexible, low-cost processor solution. (To date, Nios embedded processors have been sold to over 10,000 users andthat community continues to grow at an exponential rate.) Stratix GX devices, with embeddedserializer/deserializer (SERDES), are facing-off with ASSPs in the digital broadcast space, whereapplications such as high-definition TV require faster data rates and faster logic to process theburgeoning amount of information. HardCopyTM devices are now finding their way into storagesystems, as the cost and performance equation is far too tempting to resist. These are not your father’sPLDs.

So hang on to your hat, FPGAs are the next big thing. As George Gilder wrote in the December 2002edition of his newsletter, “the innovative digital architecture of the coming era will be realized indynamically programmable logic devices, which jettison the cumbersome complications of CPUarchitectures while reaping all their flexibility.”

This issue of News & Views, the first to celebrate our twentieth anniversary, highlights customerapplications of Altera FPGAs. Now sitting at the heart of systems that are part of our daily lives, FPGAproducts from Altera will continue to be a result of our on-going dialog with you, our customers.

Not Your Father’s PLDs

2

ViewpointExecutive

Hugh Durdan,Vice President, Computer, Consumer& Industrial Business Group

3First Quarter 2003 News & Views Altera Corporation

FeaturesNios Processor Version 3.0 Delivers the

Features Customers Want Most ........................... 4Using the Nios Embedded Processor,

Programmable Logic, IP & SOPCBuilder Tools to Construct CustomMicrocontrollers .................................................... 7

Nios in the News ..................................................... 10Test Drive the Nios Processor for Free! ................. 10Stratix Devices Enable EoS for MAN

Applications (with up to a 10-GbpsData Rate) ........................................................... 11

The Dini Group Announces Stratix FPGA-BasedLogic Emulation Product Ideal forMemory-Intensive or DSP-FocusedApplications ........................................................ 12

Stratix FPGAs Enable Real-TimeMicroprocessor Development ............................. 14

Plexus Develops a DSP Development &Evaluation Platform Using AlteraExcalibur Devices ................................................ 16

Devices & ToolsCyclone: The Lowest-Cost FPGAs Ever are

Shipping in Volume Today .................................. 18Cyclone FPGA Features ........................................... 18What Customers are Saying about Cyclone

FPGAs .................................................................. 18All Stratix Devices Now Shipping in

Production .......................................................... 19Stratix Devices Offered in Two New Packages ....... 19Stratix GX: The High-Speed System Solution ......... 19Characterization ..................................................... 19Implementing SA-1110-Like Designs in

Excalibur Devices ................................................ 20EPXA10D Development Kit ...................................... 20

Printed on recycled paper.

Altera, ACAP, ACCESS, ACEX, ACEX 1K, AMPP, APEX, APEX 20K, APEX 20KC, APEX 20KE, APEX II, Atlantic, Avalon, BitBlaster, ByteBlaster, ByteBlaster II,ByteBlasterMV, Classic, ClockBoost, ClockLock, ClockShift, CoreSyn, Cyclone, DirectDrive, E+MAX, Excalibur, FastLUT, FastTrack, FineLine BGA, FLEX, FLEX 10K,FLEX 10KE, FLEX 10KA, FLEX 8000, FLEX 6000, FLEX 6000A, Flexible-LVDS, HardCopy, IP MegaStore, Jam, LogicLock, MasterBlaster, MAX, MAX 9000, MAX 9000A,MAX 7000, MAX 7000E, MAX 7000S, MAX 7000A, MAX 7000AE, MAX 7000B, MAX 3000, MAX 3000A, MAX+PLUS, MAX+PLUS II, MegaCore, MegaLAB,MegaWizard, Mercury, MultiCore, MultiVolt, MultiTrack, NativeLink, Nios, nSTEP, OpenCore, OptiFLEX, PowerFit, PowerGauge, Quartus, Quartus II, RapidLAB,SignalCore, SignalProbe, SignalTap, SignalTap Plus, SignalTap II, SoftMode, Stratix, Stratix GX, Terminator, The Programmable Solutions Company, TriMatrix,True-LVDS, and specific device designations are trademarks and/or service marks of Altera Corporation in the United States and other countries. Altera acknowledges thetrademarks of other organizations for their respective products or services mentioned in this document, specifically: Adobe and Acrobat are registered trademarks of AdobeSystems Incorporated. ARM and Multi-ICE are registered trademarks and ARM922T and ETM9 are trademarks of ARM limited. HP-UX is a trademark of Hewlett-Packard Company. HyperTransport is a trademark of HyperTransport Consortium. Intel and StrongARM are registered trademarks of Intel. Mentor Graphics is aregistered trademark and Exemplar, LeonardoSpectrum, and ModelSim are trademarks of Mentor Graphics Corporation. Microsoft, Windows, Windows 98, andWindows NT are registered trademarks of Microsoft Corporation. PALACE is a trademark of Aplus Design Technologies, Inc. RapidIO is a trademark of RapidIO TradeAssociation. Rochester Electronics is a registered trademark of Rochester Electronics, Inc. Sun is a registered trademark and Solaris is a trademark of Sun Microsystems,Inc. Synplicity, Synplify, Synplify Pro are registered trademarks of Synplicity, Inc. Altera products are protected under numerous U.S. and foreign patents and pendingapplications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standardwarranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Alteracustomers are advised to obtain the latest version of device specifications before relying on any published information and before placing ordersfor products or services. The actual availability of Altera’s products and features could differ from those projected in this publication and areprovided solely as an estimate to the reader.

Copyright © 2003 Altera Corporation. All rights reserved.

Nios Embedded Processor Version 3.0Now Shipping ...................................................... 21

Nios Development Kit, Stratix EditionNow Shipping ...................................................... 21

APEX II Device Availability ...................................... 21APEX II Industrial Offerings ..................................... 22Mercury Devices Available in Production Mode .... 22APEX 20KC Devices Available in Production

Mode ................................................................... 22Industrial-Grade APEX Device Offerings ................. 23ACEX 1K Device Availability .................................... 23MAX Power Calculator ............................................. 24Free ByteBlasterMV Cable ....................................... 24New Serial Configuration Devices .......................... 24Enhanced Configuration Devices ............................ 24Quartus II Software Version 2.2 Service Pack 1

Adds Full Support for Cyclone Devices .............. 24New Device Support ............................................... 25Customer Release Notes ........................................ 25Quartus II Web Edition Software Adds Full

Support for Cyclone Devices .............................. 25New Design Software Starter Suite CD is

Now Available ..................................................... 25ByteBlaster II Cable Now Shipping ........................ 25

Contributed ArticlesThe Development of an Altera-Based

10 Gigabit Ethernet Tester ................................. 26

Altera NewsAltera is Listening ................................................... 28Altera Presents Good Design Practices at

Third-Party Conferences ..................................... 28

In Every IssueDiscontinued Devices Update ................................ 29How to Contact Altera ............................................ 30

John Panattoni,Publisher

Justin Bennett,Technical Editor

Pete Santana, Cover Layout101 Innovation DriveSan Jose, CA 95134Tel: (408) 544-7000Fax: (408) [email protected]

ContentsTable of


Features

Nios Processor Version 3.0 Delivers the Features Customers Want Most

Since its introduction in the fall of 2000, Altera’sNios® embedded processor has become the softcore processor solution of choice for developersworldwide, with over 10,000 hardware kitsshipped. The design community has chosen theNios processor as their standard FPGA processorbecause it is easy to use and provides solid, reli-able performance.

Created with the Nios Developer in Mind

The community of Nios developers has provideda wealth of feedback over the past year, helpingour design team focus on the most useful featuresand enhancements. With the Nios processor ver-sion 3.0, Altera delivers the latest collection ofproduct enhancements based on developer feed-back. This feedback ensures the Nios processorwill be even easier to use and addresses a widerrange of embedded applications.

Altera gathered feedback that clearly indicatedthat developers want even faster memory accessto low-cost SDRAM memory, better software de-velopment and debugging tools, faster access toproduct updates, new intellectual property (IP)cores, enhanced timer functions, and faster float-ing-point mathematical operation. Altera listened,incorporating many of these features inversion 3.0, and providing an Internet-based de-livery method for rapid deployment of the re-maining and future enhancements.

Choosing the Right Memory

Developers will always get the best system perfor-mance when executing code from FPGA internalmemory blocks. Altera’s Stratix devices, with over7 Mbits of on-chip memory, make it possible torun an entire real-time operating system (RTOS)and application code from internal memory.While this strategy provides performance bene-fits, using internal memory for program and datastorage is usually not economically practical. Typ-ically, system designers choose external SDRAMfor its low cost and high capacity advantages,even though they pay the price of additional la-tency that is inherent in SDRAM devices.

New Optimized SDRAM Controller

The new SDRAM controller included inthe Nios processor version 3.0 is optimized todeliver efficient access to single data rate (SDR)SDRAM devices while maintaining a small FPGAresources footprint. Enhancements to the Ava-lonTM switch fabric that connects the Nios pro-cessor and associated peripherals providepipelined data transfers, allowing posted read andposted write operations to minimize the latencyeffects. Coupled with the new, configurable on-chip cache, designers can achieve single-cycle ac-cess to SDRAM at speeds in excess of 100 MHz,dramatically boosting system performance.

New On-Chip Instruction & Data Cache

Version 3.0 of the Nios processor enables fast,sustained access to SDRAM with the new in-struction and data caches included. Among avail-able FPGA processor solutions, on-chip cache isan Altera® advantage provided by the availabilityof large dual-port RAM blocks on Stratix andCycloneTM devices. Designers can configure thecache buffers from 1 to 16 KB in depth, allowingthem to adjust the size to fit application require-ments.

The direct-mapped instruction cache and write-through data cache provide an effective perfor-mance boost with minimal impact on logicelement (LE) usage. The usefulness of the SDRAMcontroller and on-chip cache span a wide array ofapplications, from high-speed networking equip-ment to cost-sensitive consumer products. Forexample, an automotive electronics developer re-lies on the new SDRAM controller to store graph-ical data. A high-speed image processing enginewithin the FPGA fabric then processes this data.This example is typical of many applications inwhich designers use custom logic within the FPGAto provide high-speed data processing in hard-ware. The combination of the new SDRAM con-troller and on-chip cache delivers the data transferspeeds needed to achieve aggressive system per-formance goals.

Altera’s StratixTM devic-es, with over 7 Mbits ofon-chip memory, makeit possible to run an en-tire real-time operatingsystem (RTOS) and ap-plication code from in-ternal memory.


Features

continued on page 6

Tools to Accelerate Software Development

The Nios development kits include a compilerand debugger based on the industry-standardGNUPro Toolkit. The GNU debugger (GDB) andthe Insight graphical user interface (GUI) pro-vide a powerful set of software debugging toolsthat rely on a piece of software (the debugging“stub”) running on the target system. While thismethod is useful for debugging most applica-tions, it is not an effective solution for debuggingreal-time code due to the intrusive nature of thedebugging stub at run time.

The Nios processor version 3.0 provides real-time code debugging capabilities with the newJTAG-based, on-chip instrumentation (OCI)module from FS2. This on-chip debugging tooleliminates the need to run debugging software onthe target system. Instead, it monitors and con-trols processor activity directly in hardware basedon commands received through the FPGA’s JTAGport. The OCI core is supported by the AlteraByteBlasterMVTM download cable, providing themost essential debugging facilities, including soft-ware download, run control, memory examina-tion, modification, and software breakpoints.

For more advanced debugging requirements suchas hardware breakpoints and processor trace, twodevelopment kits are available separately fromthe Accelerated Technology, the embedded sys-tems division of Mentor Graphics® Corporationand FS2. These products extend the baseline Niosprocessors debugging capabilities and add a ro-bust software development environment. Figure1 highlights the different levels of debugging sup-port available in the Nios development kits.

The following products are available for purchasefrom Mentor Graphics and FS2:

■ ISA-NIOS ($7,000): Includes AcceleratedTechnology’s code|lab EDE debug softwareand FS2’s debugging hardware. This hard-ware/software kit combines support for hard-ware breakpoints and on-chip program tracewith a powerful development environmentand source-level debugger.

■ ISA-NIOS/T ($9,000): Same features as ISA-NIOS plus an external trace buffer in the FS2debugger hardware for deep trace capture.

Fast Product Updates

Nios developers will always demand the latestperipherals, interfaces, custom instructions, hard-ware acceleration units, software, documentation,and reference designs. In the past, these new fea-tures were delivered a few times a year in Niosprocessor updates. The SOPC Builder develop-ment tool version 2.8, included with Nios proces-sor version 3.0, now checks the Altera updateserver and notifies developers when new compo-nents, custom instructions, hardware accelera-tors, documentation, and software are availablefor download.

Notes to Figure 1:(1) Command-line interface included in the Nios devel-

opment kits.(2) Evaluation version included in the Nios develop-

ment kits.(3) FS2 ISA sold separately. The ByteBlaster cable does

not support trace or hardware breakpoints.(4) Probe interface and on-chip trace memory are op-

tional and are only supported with the FS2’s ISAproduct for use with the Nios processor.

Figure 1. FS2’s ISA & OCI Core

NiosProcessor

Core

Probe InterfaceBlock

JTAGController

Trace Memory

Windows Dynamically Linked Library

Command-Line Interface (1) code|lab Debug Software (2)

The FS2 In-Target System Analyzer orthe Altera ByteBlasterTM Cable (3)

FPGA

(4)

OCI Core

Trace Port JTAG

(4)

The Nios processor ver-sion 3.0 provides real-time code debuggingcapabilities with the newJTAG-based, on-chipinstrumentation (OCI)module from FS2.


Features

Several new components will be available inQ2 2003, including:

■ Streaming Parallel Output: This configurableoutput port provides continuous, cycle-ac-curate output of digital data with minimalintervention required by the CPU. It oper-ates in periodic, event-driven, and “time-scripted” modes.

■ Pulse Width Modulator: This modulator canbe connected directly to the Nios CPU, or tothe output of the streaming parallel outputperipheral to generate continuous, cycle-ac-curate pulse-width modulated signals.

■ One-Bit Digital-to-Analog Converter (DAC):This 1-bit DAC can be connected directly tothe Nios CPU, or to the output of the stream-ing parallel output peripheral to generate con-tinuous, cycle-accurate DAC signals.

■ Input Capture/Event Counter: This config-urable input port provides continuous, cy-cle-accurate time stamping of logic eventswith minimal CPU intervention.

■ Floating Point Custom Instruction: This smallfootprint custom instruction provides float-ing point multiply, add, and subtract opera-tions to accelerate math-intensive softwareroutines.

■ Nucleus PLUS RTOS Software Component:This software component automatically gen-erates an ATI Nucleus PLUS RTOS kernelspecific to a designer’s system configurationduring system generation.

New Stratix Development Kit

The Nios processor version 3.0 is available in theNios Development Kit, Stratix Edition. Availablefrom Altera and authorized distributors for $995,this kit comes with everything a designer needs toimmediately begin development of Nios-baseddesigns on the new Stratix EP1S10 developmentboard, which is included. Support for the 10/100Ethernet port on the EP1S10 board is includedwith the addition of Altera’s network protocolsoftware library providing support for ICMP,TCP, UDP, IP, ARP, and raw Ethernet protocols.

Also included in the Stratix development kit areevaluation versions of several tools, including:

■ code|lab Debug: A 30-day evaluation versionof the code|lab debug software fromAccelerated Technology allows software en-gineers to debug their software, connectingto their target system via an AlteraByteBlaster download cable or optional FS2In-System Analyzer.

■ Nucleus Plus LV: An evaluation version ofthis royalty free, source-available RTOS letssoftware developers create embedded appli-cations and run them for a limited time onthe Stratix development board.

■ IAR visualSTATE: An evaluation version ofthis powerful software design tool allows Niosdevelopers to automatically generate C/C++code from state machine modelscreated within a graphical user interface.

Future-Proof Your Next Design with the NiosProcessor

One of the most compelling reasons why devel-opers choose the Nios processor is avoiding prod-uct obsolescence. In the past, many designers raninto problems when their processor suddenly be-came obsolete. Not only did this require a hard-ware redesign, but it also put their softwareinvestment at risk, potentially requiring a com-plete re-write.

The Nios processor and associated peripheralscome with a royalty-free, perpetual license, giv-ing developers the right to create and deploy Niosdesigns indefinitely in any Altera device. Becausethe Nios processor is a soft core processor, it canbe compiled to target a wide range of AlteraFPGAs, from the high-performance Stratix de-vices, to the low-cost Cyclone devices.

More to Come

As the Nios processor continues to grow in popu-larity, Altera continues to create tools, IP, andsoftware to maintain the Nios processor’s leader-ship in FPGA-based processor technology. TheNios processor version 3.0 is here today, deliver-ing the most desired enhancements to the Niosdesign community.

Nios Processor Version 3.0 Delivers the FeaturesCustomers Want Most, continued from page 5

One of the most com-pelling reasons why de-velopers choose the Niosprocessor is avoidingproduct obsolescence.


Microcontrollers are the original system-on-chip(SOC) devices. In the last few years, programma-ble logic manufacturers have proffered the termsystem-on-a-programmable-chip (SOPC), whichcaptures the idea of using programmable logic tocreate system-level custom hardware includingmicrocontrollers. The elements required for thisinclude: full-featured, 32-bit RISC microproces-sors, available peripherals and options for build-ing custom peripherals, intellectual property (IP),and complete development tools. These elementsare now available, and in combination with low-cost CycloneTM FPGAs, designers have attractivealternatives to off-the-shelf microcontrollers.

With microprocessor systems in FPGAs, the de-signer can code specific software blocks as hard-ware that can be called as “single custominstructions” from the microprocessor. From thesoftware engineer’s perspective, this is simply afunction call in C or assembly language, but rath-er than a set of instructions being called, hard-ware is used to execute the algorithm. Similarly, a

Features

Using the Nios Embedded Processor, Programmable Logic, IP & SOPCBuilder Tools to Construct Custom Microcontrollers

designer can change the system architecture tomatch the problem, including adding multiplearbitrated slave-peripherals on a multi-masterbus, custom peripherals, or direct memory ac-cess (DMA) controllers. This article gives a de-tailed example and performance numbers of anMP3 player optimized using custom instructions.

Detailed Example: MP3 Player

Custom instructions can increase system perfor-mance by adding custom logic to the arithmeticlogic unit (ALU) of the Nios® embedded proces-sor. An MP3 player design was created to showthe potential performance enhancements of us-ing a custom instruction in a real-world, com-pute-intensive application. By adding two custominstructions, this design was able to increase sys-tem performance by approximately three times.Figure 1 shows a block diagram of the MP3 sys-tem design.

continued on page 8

Figure 1. MP3 System Design Diagram

ParallelIO (PIO)

1k × 32Boot

MonitorROM

DebuggingTimer

Timer

PulseWidth

Modulator(PWM)

UART

Speaker RS232

IDE/Compact

Flash

256k × 32SRAM

Dual 7-Segment

Display

32-Bit Nios CPU

APEX EP20K200E Device

DCT32 fmul

Custom Instructions

Avalon Bus

Tri-State Bridge


Features

MP3 Decoder

In many MP3 players, the processor is used forcontrol functions and moving data. A specializedMP3 decoder ASIC is used to perform the com-pute-intensive decode and send data to the sounddevice1. In Altera’s design example, the Nios pro-cessor handles control signals, transferring data,and MP3 decoding.

In general, Altera’s MP3 decoder:

■ Reads the MP3 data from CompactFlash con-troller through an IDE interface

■ Buffers the MP3 data in SRAM■ Decodes the MP3 data■ Synthesizes the MP3 subbands into pulse

code modulation (PCM) data■ Sends the PCM data to the PWM

The player uses MPEG Audio Decoder (MAD)for MP3 decoding because of the following spe-cial features:

■ 100% fixed-point (integer) computation■ Available as source-code on the web■ Distributed under the terms of the GNU Gen-

eral Public License (GPL)

References to functions found in the source-codewill be used throughout this article.

Custom Instructions

The majority of the execution time for MP3 de-coding takes place in the synthesis of the sub-bands. Therefore, the Altera MP3 design focuseson a function called mad_synth_frame, whichcontains two functions that could be optimizedusing the custom instructions f_mul and DCT32.

Using the Nios Embedded Processor, Programma-ble Logic, IP & SOPC Builder Tools to ConstructCustom Microcontrollers, continued from page 7

f_mul

f_mul and mad_f_mul are macros used byMAD to emulate floating-point multiplicationusing integer multiplication. These macros aredefined as:

#define mad_f_mul(x, y)

((((x) + 0x00002000L)>> 14) ×(((y) + 0x00002000L)>> 14))

#define f_mul(x,y)(((x)| 0x0001FFFFL) ×((y)| 0x0001FFFFL))

These functions are a set of shifts, adds, multi-plies, and logical OR operations, which are easy toimplement in hardware. The Altera MP3 designuses a hardware custom instruction called f_mulwhich performs the software macro previouslymentioned. By using the prefix option, this de-sign was able to incorporate both macros into asingle custom instruction. Below is the code usedto define f_mul and mad_f_mul using Altera’scustom instruction:

#define f_mul(x,y) nm_fmul((x),(y))

#define mad_f_mul(x,y) nm_fmul_pfx

(1,(x),(y))

DCT32

DCT32 performs the discrete cosine transform(DCT) in the MP3 decode. The MAD softwareuses an optimized DCT to increase performance.From a software perspective, this optimized algo-rithm provides a significant performance im-provement over the general DCT, using only80 multiplies, while the standard DCT equationrequires 1,024 multiplies.

The hardware used for the DCT32 custom in-struction was provided by Celoxica2, a providerof reconfigurable computing solutions with theirHandel-C-based design tools. Altera’s DCT32 cus-tom instruction was designed with the followingfeatures:

■ Stores 32 inputs and 32 outputs■ Works independently of the CPU during

DCT calculation■ Uses the prefix instruction to receive com-

mands:- Load/unload- Start DCT calculation- Poll if complete


Features

Because the custom instruction can be polled,other code can run in parallel until the DCToutput is needed. At that time, the custom in-struction is polled to see if the calculation is com-plete. If complete, the Nios processor unloads theoutput data while loading the next group of in-puts. Figure 2 shows a flow diagram illustratinghow a designer can use the DCT32 custom in-struction.

MP3 Example: Performance Versus Size3

Altera measured the number of cycles needed tocomplete a single mad_synth_frame func-tion using a hardware multiply instruction aswell as the custom instructions f_mul andDCT32. Performance improvement comes with

a cost; custom instructions generally require ad-ditional hardware resources (e.g., logic elements(LEs) and memory). Table 1 shows the hardwarerequirements and results for the three exampledesigns using the mad_synth_frame function.

continued on page 10

Figure 2. DCT32 & mad_synth_frame Software Flow Diagram

Startmad_synth_frame

Done Loading?

Done Loading/Unloading?

End of Frame?

Complete?

Finishmad_synth_frame

Load the first setof 32 data inputs

one at a time into DCT32

Read the 32outputs while loading

the next 32 inputsinto DCT32

Tell DCT32 to begincomputing DCT

Run other softwareroutines in parallel

Poll DCT32 to seeif complete

No

No

No

No

Yes

Yes

Yes

Yes

The initial data isloaded one input at a time

while the output is disregarded

Table 1. Number of Cycles to Compute a MP3 Frame

Hardware Used

Number of Cycles

Logic Elements

Memory (Bits)

Hardware

multiply only

1,279,000 3,542 26,624

f_mul 293,000 3,642 26,624

f_mul and

DCT32 parallel

231,600 4,331 30,528


Features

f_mul was the most efficient custom instruc-tion, reducing the number of cycles needed by77% with an increase in system size of 3%. Thissmall increase was due to removing the dedicatedhardware multiplier in favor of the f_mul cus-tom instruction.

The DCT32 instruction runs in parallel modeand reduces the number of cycles needed by 21%compared to f_mul, using 18.9% of LE resourc-es from the f_mul design.

For a reduction of over 80% in the number ofcycles needed to perform mad_synth_frame,the system size only increased by 22.3%. Thisexample executes on a Nios development boardat 33 MHz, and all performance gains are achievedwithout increasing clock frequency. If higher per-formance is required, the designer still has otheroptions available, such as increasing clock fre-

Using the Nios Embedded Processor, Programma-ble Logic, IP & SOPC Builder Tools to ConstructCustom Microcontrollers, continued from page 9

quency, using faster memory, or adding instruc-tion or data cache.

Conclusion

The use of FPGA microcontrollers extends the setof tools that a designer has available to improvesystem performance. As with all tools, it is theskilled application of these tools that determinethe speed with which performance targets can bemet. The beauty of using FPGAs for microcon-trollers is experimenting with new designs in aniterative approach, further blurring the lines be-tween software and hardware development.

References

1 The Beginner’s Guide to Making a HardwareMP3 Player Version 2.0

2 Celoxica, Ltd., 20 Park Gate, Milton Park,Abingdon Oxfordshire, OX14 4SH UnitedKingdom

3 AN 188: Custom Instructions for the Nios Em-bedded Processor

Test Drive the Nios Processor for Free!

Altera’s low cost-solution is now available on CD-ROM. Take the Nios processor out for a spin atabsolutely no cost to you and see what over 10,000 developers are raving about. The Low-CostSolution CD contains the Nios embedded processor (evaluation version), a complete Nios develop-ment kit, Quartus® II Web Edition, SOPC Builder, and accompanying documentation.Order Altera’s Low-Cost Solution CD now at www.altera.com/niostestdrive.

Nios in the News

The Nios® part has excelled beyond the company’s expectations, with more than 10,000licenses sold to date. Cary Snyder, senior analyst with Forward Concepts, estimates thenumber of embedded applications using the soft-core processor is much greater. “I don’tthink that Altera even knows how much people are using it. In other words, how manytimes in a given chip it might be used. In some cases it is simple enough to use it inmultiple substantiations in a chip. If you want flexibility in your design which is whypeople would go to FPGAs in general they can get it by popping in a Nios core.”

Altera’s Trojan HorseExerpted from Electronic News, 2/17/03


Features

by Bamdad AfraSenior Engineer/GEOS Chief ArchitectNuvation Engineering

There is an increasing demand for Ethernet traf-fic over metropolitan area networks (MANs).Since their infrastructures are not geared towardspacket-switched traffic (e.g., Ethernet), carriersare now struggling to provide this service capabil-ity. In recent years, these carriers have invested alarge amount of capital in creating the time-do-main multiplexing (TDM) infrastructure (e.g.,circuit-switched oriented SONET) to providevoice and private-line connections.

The most cost-effective solution for providingEthernet services is to transport it over the exist-ing infrastructure to make use of the capital al-ready invested transport Ethernet traffic(packet-switched) over SONET (circuit-switched)equipment.

For instance, consider a special case ofEthernet-over-SONET (EoS) equipment. In thiscase, the EoS equipment is required to transportup to 10 ports of Gigabit Ethernet traffic by con-necting to a SONET ring. An optimal solution isto aggregate the traffic from all gigabit Ethernetports into a single 10-gigabit per second (Gbps)SONET pipe (e.g., OC-192). The traffic aggrega-tion requires all EoS equipment to adopt a stan-dard protocol, such as generic framing procedure(GFP), to de-multiplex the traffic at the destina-tion.

To design such equipment, one would have tochoose a number of system components. Themajor system components are listed below:

■ Serializer/deserializer (SERDES) devices forgigabit Ethernet ports

■ MAC/PHY devices for handling Ethernettraffic

■ A device for aggregation and GFP protocolimplementation

■ SONET framer■ SONET optical module

Stratix Devices Enable EoS for MAN Applications(with up to a 10-Gbps Data Rate)

SERDES, MAC/PHY, SONET framer, andSONET optical modules are available from a num-ber of well-known companies such as Intel andPMC Sierra. Designers can implement a GFPprotocol in an FPGA (a GFP protocol is requiredto interface the MAC and SONET framer). Al-tera® StratixTM FPGAs handle traffic aggregationand GFP protocol implementation, as shown inFigure 1.

The Stratix device interfaces to the MAC/PHYand SONET framer devices using the SPI4.2 in-terface specification from the Optical Internet-working Forum (OIF). This interface uses a 16-bitdouble data rate (DDR) with a clock rate of up to400 MHz, making it capable of handling over10-Gbps data rates.

The internal components of the Stratix device arereadily accessible through easy-to-use Alteramegafunctions. You can implement Stratix de-vices using two types of intellectual property (IP)cores: POS-PHY Level 4 and GEOS. The POS-PHY Level 4 IP core facilitates interfacing to theSPI4.2 bus for application-specific implementa-tions in the Stratix device. The GEOS IP coreimplements the GFP protocol in addition to traf-fic aggregation. Additionally, GEOS implementsfeatures such as full-duplex pause flow controland Ethernet jumbo frame transport overSONET.

The POS-PHY Level 4 IP core is available throughAltera, and the GEOS IP core is available throughNuvation.

For more information on Nuvation, go towww.nuvation.com.

Figure 1. Stratix Implementation Block Diagram

EthernetMAC/PHY

SONETFramer

Stratix Device

POS-PHY

POS-PHY

POS-PHY

POS-PHY

GEOS SPI4-2SPI4-2To/From

GE SERDESDevices

To/FromSONETOpticalModule

Company:

Nuvation

Engineering

Industry:

Electronic Design

Services

End Product:

FPGA Design

Firmware

Altera Product:

Stratix Devices


Features

Figure 1. DN5000k10 Logic Emulation Board

The Dini Group Announces Stratix FPGA-Based Logic Emulation ProductIdeal for Memory-Intensive or DSP-Focused Applications

by Mike DiniPresidentThe Dini Group

With ASIC mask costs nearing and sometimesexceeding $1 million, designers need to pay moreattention than ever to the verification of logicdesign. Prototyping the logic in an FPGA beforethe masks are cut is a good way to assure first-time success. Prototyping a design can also helpto catch oversights and errors in a simulation testfixture. Additionally, since hardware prototypescan be clocked at frequencies in the MHz range,billions (even trillions) of test vectors are possi-ble. With these issues in mind, The Dini Grouphas developed a line of off-the-shelf productsbased on StratixTM FPGAs that can be used forlogic emulation, algorithm acceleration, and re-configurable computing.

The DN5000k10 emulation board can beequipped with two to five Stratix EP1S80 FPGAs(see Figure 1). The block diagram is shown inFigure 2. The EP1S80 device is one of the largestFPGAs available today, providing 79,040 flipflops,7.4 Mbits of embedded RAM, and 22 digital sig-nal processing (DSP) blocks. The embeddedStratix DSP blocks allow designers to implementmultiplier-based logic such as finite impulse re-sponse (FIR) filters, modulators, correlators, andcoder/encoders.

Four external 512k × 36 pipelined/flowthrough/zero bus turnaround (ZBT) SSRAM devices anda 128 Mbytes × 72 SDRAM device are available tobolster the large amount of embedded memoryalready available in each Stratix device. The boarduses high I/O count, 1,508-pin FineLine BGA®packages to support a rich, fixed interconnectscheme between the FPGAs. A flexible clockingscheme, based on two external phase-locked loop(PLL) devices, works in concert with the 12 PLLsavailable in each Stratix FPGA to enable a widevariety of board clocking options.

The DN5000k10 board can be hosted in a32-/64-bit PCI/PCI-X slot, or can be used as astand-alone board. The board includes a 32-bittarget PCI interface (in Verilog HDL and VHDL).It also includes drivers for a number of operatingsystems at no additional cost, as well as sourcecode for the PCI target and the drivers.

Because it is necessary to interface logic emula-tion boards to custom circuitry, the DN5000k10board has three high-speed 200-pin connectorson the top of the circuit board. A total of488 signals are available to handle the complexinterfaces to custom circuitry.

FPGA configuration is performed using aSmartMedia card. The user copies configurationfiles for the FPGAs to the SmartMedia card via aFlashPath floppy adapter, and a microprocessoron the DN5000k10 board controls the configura-tion process. It configures in parallel at 48 MHz.The microprocessor performs sanity checks onthe configuration files in an attempt to take asmuch mystery as possible out of an occasionallydifficult process. An RS232 port is available todetermine the status of the configuration pro-cess, and to manually select the configurationfiles. A single SmartMedia card can store severalconfiguration files. It takes less than five secondsto configure a fully equipped DN5000k10 boardwith five EP1S80 devices.

Company:

The Dini Group

Industry:

Consulting Design

Services

End Product:

Logic Emulation

Algorithm

Acceleration

Reconfigurable

Computing

Altera Products:

Stratix Devices

APEX II Devices


Features

The DN5000k10 board is built to order, and cantypically be assembled, tested, and shipped inabout one week. A version of the DN5000k10board with a single Stratix EP1S80 device is alsoavailable. The Dini Group also has a series ofemulation products based on Altera’s APEXTM IIdevices.

About The Dini Group

The Dini Group is headquartered in La Jolla,California. In addition to its logic emulation prod-

Figure 2. DN5000k10 Block Diagram

ucts, The Dini Group is a hardware andsoftware consulting firm specializing in high-per-formance digital circuit design using ASICs andFPGAs. More information is available atwww.dinigroup.com.

Mike Dini has been in the industry for 20 yearsand is a regular contributor to various conferenc-es on the subject of FPGAs and their applications.He has been using FPGAs since 1984 and hasdone hundreds of designs.

32-/64-Bit PCI/PCI-X

ECLK

ECLK

ECLK

256

AF 143144

BE

153

AE

ED

153AD BD

190AB

69

110

69

256

158

69

69

FE

FBAD

AB

DE

Top

of P

WB

(tes

t co

nnec

tors

)

+5.0 V

-12.0 V

+12.0 V

+3.3 V

+1.5 V

ResetControl

21

AF

164AB

150

AD15

clocks

150

FB

RS232

EPM3256ACPLD

2

20

32k × 8 SRAM

ACLK

BCLK

CCLK

DCLK

ECLK

Configuration

PLL 1

PLL 2

OSCX1

OSCX2

ClockSelectionJumpers

orExternalCable

+5.0 V+3.3 V (10 A)

+1.5 V (10 A)

FPGAConfiguration

SwitchingPowerSupply

Flow Through/Pipelined SSRAM

512k × 36

StratixEP1S80Device

StratixEP1S80Device

StratixEP1S80Device

StratixEP1S80Device

StratixEP1S80Device


512k × 36

FB

ECLKFlow Through/

Pipelined SSRAM512k × 36

158

Configuration


512k × 36

SDRAM(168-Pin DIMM)

Up to 1 Gbyte × 64

92

Flash-Based µPFPGA Configuration

Controller

SmartMediaCard 16/32/64 Mbyte

(FPGA Configuration Storage)


Features

Company:

Logic Product

Development

Industry:

Embedded Systems

End Product:

SuperH (SH4-202)

Processor Develop-

ment Platform

Altera Products:

Stratix Devices

Configuration Devices

MAX 3000A Devices

Stratix FPGAs Enable Real-Time Microprocessor Development

by Nick KleinLogic Product Development

With the availability of contract silicon manufac-turing from companies such as UMC, TSMC,and a wide variety of licensed peripheral intellec-tual property (IP), microprocessor manufactur-ers are now offering their cores as part of acustomizable system-on-a-chip (SOC) solution.

One of the issues facing SOC developers is theability to prototype their SOC solution and pro-vide a software development platform prior tosilicon availability. Logic Product Developmentworks with SuperH, Inc. (a leading supplier ofmultimedia RISC CPU cores) to produce a mod-ular development and prototyping platform. Thesolution is a stackable three-board configuration,including a CPU board, a system board, and anFPGA board. Both the CPU board and FPGAboard are equipped with StratixTM FPGAs.

System Board

The system board is located at the bottom of thethree-board configuration. It has an array of pe-ripherals and interfaces that would be found on atypical PC motherboard:

■ 3.3-V peripheral component interconnect(PCI) slot

■ Three 5.0-V PCI slots■ PC card connection■ Super I/O controller that provides 1× paral-

lel, 2× PS2, 2× serial, and 2× IDE ports■ On-board video controller■ Ethernet pass-through from CPU board■ Micro ATX form factor that uses standard

ATX power supply■ Two universal serial bus (USB) 1.1 ports

(host side)

Logic Product Development used a MAX® 3000A(EPM3256A) CPLD to handle PCI arbitrationand to manage access to the SRAM buffer that isshared between the microprocessor and the PCIbridge. Another MAX 3000A CPLD provides I2Sto microprocessor local bus conversion (operat-ing as a transceiver), allowing a connection to alow-cost I2S stereo coder/decoder.

CPU Board

The first CPU board developed contains theSH4-202 evaluation device from SuperH, a serialport, Ethernet, SDRAM, flash memory, a StratixEP1S10 FPGA, and an EPC4 configuration de-vice (used to configure the EP1S10 device). Theseperipherals enable the board to be operated as astand-alone evaluation board. A designer can alsoconnect the CPU board to the system board al-lowing additional peripheral availability. TheSH4-202 is a 32-bit RISC CPU core with a128b-vector floating point unit, and 16K I and32K D caches running at speeds of up to266 MHz. This core is implemented in a deviceproduced through UMC’s 0.13-µm CMOS tech-nology. This device includes the SuperHyway Buson-chip interconnect that provides a high-band-width, low-latency bus to connect the CPU coreto the peripherals.

The Stratix EP1S10 FPGA on the CPU board tiesthe entire system together. It handles multipleselectable address maps for the entire system,provides a programmable interrupt controller for32 interrupt sources, and an interface for pro-gramming the FPGA board from the SH4-202,and connects to the SuperHyway via an off-chipport and FlashEMI SH4-202 interface. “This al-lows complete flexibility for interfacing the restof the system with the SuperH evaluation de-vice,” says Jason Sheard, Program Manager atLogic Product Development.

FPGA Board

The FPGA board is designed for customer IPdevelopment of SOC custom peripherals. A de-signer can stack up to eight FPGA boards ontothe CPU board for additional logic and I/O re-sources. This number is limited only by the pow-er supply and the connector’s current capability.These boards connect to the CPU board for pow-er and access to the SuperHyway Bus off-chipSH4-202 interface.


Features

The FPGA board contains a Stratix EP1S40 FPGA,the core and I/O power supplies, an EPC16 con-figuration device, and a number of I/O connec-tors. The I/O connectors on the board supportboth differential and single-ended signals to ac-commodate a wide variety of I/O standards atselectable voltage levels. The Stratix FPGA can beprogrammed using the EPC16 configuration de-vice, Joint Test Action Group (JTAG), or passiveserial from the CPU board. A designer can selectbank I/O voltage and programming options byusing jumpers on each FPGA board.

Stratix Devices

EP1S10 and EP1S40 devices provide the largenumber of logic elements (LEs), I/O pins, speed,and advanced logic capabilities that are requiredfor this design. “SuperH and SuperH core usersneed the IP Emulation FPGAs to run complexlogic at speeds of up to 150 MHz and Stratixdevices offer the best solution available today formeeting this need. As an Altera® Certified DesignCenter (CDC), Logic has the tools and experienceto implement this design,” says Matt Tilstra, FPGADesign Engineer at Logic Product Development.

While the FPGA board currently uses a StratixEP1S40 device, the board is compatible with anymember of the Stratix family in a 1,020-pin ball-grid array (BGA) package. This range includesStratix EP1S25 to EP1S60 devices, providing anadditional level of flexibility in offering differentcost and FPGA resource options.

About Logic Product Development

Logic Product Development is the largest fullyintegrated product development consulting firmin the American midwest, and has helped trans-form product concepts to market success for over40 years. By balancing goals and end-user re-quirements, Logic’s comprehensive array of ca-pabilities propels the development process,allowing a product to move rapidly from conceptto full production. Logic’s integrated approachenables multiple disciplines to work concurrent-ly on the development of a product, greatly re-ducing development time and accelerating marketlaunch.

For more information, visit www.logicpd.com orcall (612) 672-9495.

While the FPGA boardcurrently uses a StratixEP1S40 device, theboard is compatible withany member of theStratix family in a1,020-pin ball-grid ar-ray (BGA) package.


Features

Plexus Develops a DSP Development & Evaluation PlatformUsing Altera Excalibur Devices

Company:

Plexus

Industry:

Electronic

Manufacturing

Services

End Product:

Product Realization

Services

Altera Product:

Excalibur Devices

by Michael Tendick & Tim MurphyPlexus

In the highly competitive digital signal processing(DSP) market, time to market is critical. Plexuswas given 6 months to develop a platform thatwas designed for end customers to verify theirDSP applications. Given the wide variety of DSPinterfaces, the system must be flexible enough tohandle different communications protocols andinterfaces such as UTOPIA, HDLC, and periph-eral component interconnect (PCI). With all thesesystem requirements, the selection of a systemarchitecture would be the key to the project’ssuccess. The risk of “show-stopping” problemshad to be minimized while the speed of imple-mentation must be maximized. After looking atpotential architectures for their development andoperational platform, Plexus chose Altera®ExcaliburTM devices.

The combination of programmable logic, anARM® processor, memory controllers, and on-board SRAM resulted in reduced printed circuitboard (PCB) space and development time. Thedual-port RAM was an ideal interface betweenthe processor and programmable logic sections.The tools accelerated development by allowingparallel hardware and software design.

Custom Kernel Design

The Excalibur ARM922TM processor was used toadjust the platform’s operating conditions andprovide an interface between a PC and the coresembedded in the Excalibur device’s programma-ble logic array. Plexus created a custom kernel torun on the ARM processor which was set up in atiered command structure, allowing the designerto add new commands, or groups of commands,at any time without affecting the existing com-mands.

The first group of commands adjusts operatingconditions, including several on-board clockspeeds and voltages, and monitors on-board tem-

peratures. The second group of commands pro-vide an abstract interface to the FPGA communi-cation cores. These commands allow load transmitbuffers to be loaded with data, to transmit thatdata over any desired interface, to receive dataover any interface, to place that data in receivebuffers, and to output the data to a PC. The PCinterface to the development platform is a stan-dard RS232 interface. This arrangement allowsany standard PC to interface with the develop-ment platform using standard software such asHyperTerminal. With this well-defined commandstructure, Plexus created a graphical user inter-face (GUI) that could be installed on a PC. TheGUI allows users unfamiliar with the commandstructure to control the platform.

The development platform contains flash memo-ry dedicated to holding scripts and DSP boot-code, allowing the DSP technology to be verifiedwithout user intervention. This automated test-ing is made possible by kernel commands thatcompare transmit and receive signals.

Communication Subsystem Design

The rest of the Excalibur system consists of sever-al communication blocks used to test the variouscommunications interfaces. These interface blocksinclude UTOPIA Level 2, multi-channel bufferedserial port (McBSP), universal host port interface(UHPI), HDLC, and PCI. The UTOPIA, HDLC,and PCI blocks are third-party purchased cores.Plexus developed the UHPI and McBSP cores.The ARM processor controls the data flowingthrough the cores through both the AMBATM busand the dual-port RAM. AMBA, the ARM sys-tem-level processor bus, allows peripheral coresdesigned for the AMBA bus to be quickly andeasily connected to the system. The dual-portRAM acts as a mailbox between the ARM coreand the FPGA’s logic. The ARM processor hasaccess to one side of the dual-port RAM and theFPGA design has access to the other side.


Features

Unfortunately, the cores did not have AMBA in-terfaces, so the main task for Plexus was to cus-tomize the cores’ back-end interface to allow themto talk to the ARM processor. The register blockwas designed to be AMBA-compliant, which al-lowed access to each core’s configuration regis-ters. The dual-port RAM was used to pass databetween the ARM processor and the cores. TheARM processor uses the register block to set upaccesses and the dual-port RAM to send and re-ceive data. Direct memory access (DMA) engineswere designed on the FPGA side to control theflow of data without additional ARM overhead.

At one time, there were five digital design engi-neers working on the design in two locations. Toenable the design engineers to work asautonomously as possible, the Quartus® IIsoftware’s LogicLockTM feature was used.LogicLock regions allow multiple blocks to beindependently implemented and then merged.

Simulation

Multiple engineers on the team were responsiblefor block-level simulations, while system-levelsimulations were performed by a dedicated veri-fication engineer. The verification engineer caughtspecification misinterpretations made by the de-sign engineers, whereas the design engineers test-ed implementation-specific corner cases notapparent by reading the specification. Using the

Excalibur device required cooperation betweenthe HDL and software design teams throughoutthe project. This tight working relationship wasbeneficial as it allowed for cross-functional de-sign. The full ARM model was used for system-level simulations. Kernel software was written,compiled, and used in simulation months beforethe hardware was complete. This method workedwell in that actual application code could be runand debugged before hardware was available. Withsimulation proving basic functionality of the ker-nel and the HDL, the entire engineering team wasable to focus on hardware, saving valuable timein the six-month development schedule.

Conclusion

The development and evaluation platform allowsdesigners to see “signs of life” from the silicon inonly five minutes. Within a month, the customerbegan requesting additional prototypes to allowtheir customers to accelerate the time to marketof their silicon-based applications. This success-ful project helped to create a close partnershipbetween Plexus and their customer. AdditionalIP cores and kernel functionality are being addedcontinuously to allow more rigorous and thor-ough testing of the new silicon.

To enable the design en-gineers to work asautonomously as possi-ble, the Quartus IIsoftware’s LogicLockfeature was used.


&ToolsDevices

Cyclone

Cyclone: The Lowest-Cost FGPAs Ever areShipping in Volume Today

Altera is now shipping production devices of thefirst two family members from its low-costCycloneTM FPGA family. Based on an industry-leading 1.5-V, 0.13-µm, all-layer-copper process,EP1C20 FPGAs in the 324- and 400-pinFineLine BGA® packages and EP1C6 FPGAs inthe 144-pin thin quad flat pack (TQFP), 240-pinplastic quad flat pack (PQFP), and 256-pinFineLine BGA packages are now available.

At less than $1.50 per 1,000 logic elements (LEs)for volume applications, engineers can begin de-signing for Cyclone devices using the Altera®Quartus® II design software, the Nios® embed-ded processor, and Altera’s intellectual property(IP) cores.

Only 15 months from conception to shipment,Altera developed the Cyclone FPGA family fasterthan any other device family in company history.Altera rolled out Cyclone devices in record time,having shipped multiple device densities sinceDecember 2002. For a true low-cost solution forhigh-volume applications, designers can have im-mediate access to Cyclone devices throughAltera’s distributors. The Quartus II design soft-ware supports all Cyclone FPGAs.

Table 1 shows Cyclone device availability.

Cyclone FPGA Features

Cyclone FPGAs provide:

■ Up to 20,060 LEs■ Up to 294,912 bits of embedded RAM■ Dedicated external memory interface circuit-

ry for integration with double data rate(DDR) SDRAM and FCRAM devices as wellas single data rate (SDR) SDRAM memorydevices

■ Up to two phase-locked loops (PLLs) for on-and off-chip system timing management

■ LVDS support of up to 129 channels capableof 311 megabits per second (Mbps)

■ Nios embedded processor support■ Free software support with the Quartus II

Web Edition software

What Customers are Saying about CycloneFPGAs

“Our company had not used programmable logicbefore, but the Cyclone FPGA family convincedus that we could achieve a high degree of designflexibility at the lowest possible cost. Even thoughit is a new product family, Altera’s successfultrack record of shipping StratixTM devices dem-onstrated to us that they could deliver Cyclonedevices in a short amount of time, and the factthat we now have them in-hand proves that wemade the right decision.”

Gary PacePrincipal EngineerOilfield Electric Marine

Table 1. Cyclone Device Availability

Device Production Availability

EP1C3 April 2003

EP1C4 September 2003

EP1C6 Now

EP1C12 March 2003

EP1C20 Now


Devices & Tools

Stratix

Stratix GX

All Stratix Devices Now Shipping in Produc-tion

All Stratix devices are now shipping in produc-tion volume. EP1S10, EP1S20, EP1S25, EP1S30,EP1S40, EP1S60, and EP1S80 production devic-es are now shipping. See Table 2.

Note to Table 2: (1) Since production devices are available, engineering

samples will no longer be offered for these devices.

Stratix Devices Offered in Two New Packages

Stratix devices are now available in two new pack-ages. The EP1S40 device will be offered in the780-pin Fineline BGA package, and the EP1S80device will be available in the 1,020-pinFineline BGA package. The 780-pin FineLine BGApackage supports vertical migration between theEP1S10 device up to and including the EP1S40device. The 1,020-pin FineLine BGA package alsosupports vertical migration between the EP1S30device up to and including the EP1S80 device.

The EP1S40 device in the 780-pin FineLine BGApackage and the EP1S80 device in the 1,020-pinFineLine BGA package will be available inQ2 2003. These packages are supported in theQuartus II software version 2.2 and higher.

Stratix GX: The High-Speed System Solution

Altera is now shipping Stratix GX EP1SGX25C,EP1SGX25D, and EP1SGX25F devices; these de-vices were released in both a 672-pin and

Figure 1. Transceiver Eye Diagram (3.125 Gbps)


1,020-pin ball-grid array (BGA) package. The firstEP1SGX25 devices have been released to valida-tion partners, but will not generally be availableto customers until June 2003. This schedule al-lows time for the completion of characterization,and will ensure that a full design pack is available.See Table 3 for Stratix GX device availability.

Characterization

The characterization process is proceeding toschedule. Initial results have been extremely en-couraging, with better than expected performance.Figure 1 shows an eye diagram measurement tak-en from the transmitter Stratix GX high-speedtransceiver.

Stratix GX has been characterized to operate suc-cessfully at 3.125 gigabits per second (Gbps) across40 inches of FR-4 fabric. Characterization hasalso been ongoing on the source-synchronousdynamic phase alignment (DPA) circuitry.Source-synchronous operation has been shownto be successful above 1 Gbps.

Table 2. Stratix Device Availability Note (1)

Device Availability

EP1S10 Now

EP1S20 Now

EP1S25 Now

EP1S30 Now

EP1S40 Now

EP1S60 Now

EP1S80 Now

Table 3. Stratix GX Device Availability

Device General ES Availability

EP1SGX10C Q3 2003

EP1SGX10D Q3 2003

EP1SGX25C Q2 2003

EP1SGX25D Q2 2003

EP1SGX25F Q2 2003

EP1SGX40D Q3 2003

EP1SGX40G Q3 2003


Excalibur

Implementing SA-1110-Like Designs inExcalibur Devices

Many embedded processor solutions are avail-able on the market today. In many cases, theytarget application-specific or application-orient-ed devices. Although they have generic appeal,peripheral availability may not be optimal forparticular applications.

One example of such a device is the Intel®SA-1110 StrongARM® processor. Based on a corecompliant with the ARM V4 instruction set, thisdevice targets higher-end personal digital assis-tant (PDA) and consumer device applications. Ifa designer is using an Intel SA-1110 device in anapplication space other than the consumer mar-ket, it may not be the best solution. The designmay not require all three on-board UARTs, theLCD controller, or the infrared data association(IrDA) peripheral, or you might want a similarperipheral, or another complete functional blockin its place.

Altera’s solution is to implement StrongARM-like designs in ExcaliburTM devices using SOPCBuilder. Because it uses an Excalibur device, theinstruction set architecture (ISA) remains con-sistent between the two devices and the customperipheral set of the Intel SA-1110 device can bemapped into the Excalibur device.

A designer can use an Excalibur EPXA1 device tointegrate the Intel SA-1110 functionality as astand-alone processor. In many cases, an IntelSA-1110 device will be used in conjunction withan FPGA to provide a PCI interface. A design thatuses an Excalibur EPXA4 device can implementboth of these functions.

EPXA10D Development Kit

Using an Excalibur EPXA10 device, the EPXA10DDevelopment Kit is an ideal platform for devel-oping system-on-a-programmable-chip (SOPC)designs for a wide variety of applications requir-ing high-density logic with a high-performanceprocessor (e.g., wireless base stations and net-work switches).

The board provides an Ethernet physical inter-face (PHY), magnetics, and a connector, whichare supported by an OpenCore® Plus version ofan Ethernet media access control (MAC) inter-face provided as part of the kit. The board alsoincludes two UART port connectors, one con-nected directly to the UART pins on the embed-ded processor subsystem, and one to thegeneral-purpose I/O pins in the programmablelogic. A UART OpenCore Plus IP core is alsoprovided.

The EPXA10D development board features in-clude:

■ Excalibur EPXA10 device in a 1,020-pinFineline BGA package

■ 10/100 Ethernet PHY, supporting full andhalf duplex modes

■ Two off RS232 UART connectors■ 16-Mbyte flash memory (boot from flash

supported)■ 64-Mbyte double data rate (DDR) SDRAM

on board■ Five on-/off-board clock sources for system

design■ ByteBlasterMVTM download cable■ IEEE Std. 1149.1 Joint Test Action Group

(JTAG) connector■ Multi-ICE® connector for ARM® debug tools■ Two Altera expansion headers for daughter

cards (one standard and one long)■ One user-definable 8-bit dual in-line parallel

(DIP) switch block■ Four user-defined, push-button switches

The EPXA10D Development Kit includes:

■ Excalibur EPXA10 development board■ Power supply■ Documentation■ Software, drivers, and application examples

on CD-ROM■ Connection cables■ Quartus II software with one-year time lim-

ited license■ SOPC Builder and GNUPro tools

The ordering code for the development kit isEPXA-DEVKIT-XA10D, and the retail price is$7,995.

Devices & Tools, continued from page 19

Devices & Tools


APEX II

APEX II Device Availability

All members of the APEXTM II device family areshipping. APEX II devices range in density from16,640 to 67,200 LEs and are memory-rich; theyoffer 4 Kbits of memory per embedded systemblock (ESB), with total device memory rangingfrom 416 Kbits to 1.1 Mbits. The APEX II devicefamily supports high-speed data transfers througha wide range of high-speed I/O standards suchas LVDS, PCML, LVPECL, HSTL, SSTL,and HyperTransportTM technology. WithTrue-LVDSTM circuitry, APEX II devices canachieve data transfer rates of up to 1 Gbps perchannel. Designers can take advantage of theseI/O features by using APEX devices in the follow-ing applications:

■ PHY-link layer interface applications(POS-PHY, Flexbus, and UTOPIA)

■ Host-processor interface applications(HyperTransport technology, PCI, andPCI-X)

■ Switch fabric interfaces (CSIX and LCS)■ External memory interfaces (DDR, zero bus

turnaround (ZBT), and quad data rate (QDR)memory devices)

For new designs requiring high performance, useStratix and Stratix GX FPGAs. These FPGAs de-liver top performance and are feature rich.

See Table 4 for APEX II device availability.

Nios Processor

Nios Embedded Processor Version 3.0 NowShipping

The Nios embedded processor version 3.0 furtherenhances the industry’s most popular configurableembedded processor. Version 3.0 builds on thesuccessful version 2.x CPU architecture, and givesdesigners the following enhancements:

■ JTAG-Based Software Debugger Interface: TheNios on-chip instrumentation debuggingmodule supports processor run control, hard-ware breakpoints, and real-time trace via astandard JTAG connection.

■ Instruction and Data Cache: The cache mem-ory improves CPU performance when ac-cessing off-chip memory devices.

■ Enhanced SDRAM Controller: Offers higherfMAX performance with low-cost SDRAMdevices, and achieves approximately onememory access per clock cycle in conjunc-tion with the new cache memory feature.

The Nios embedded processor version 3.0 shipswith SOPC Builder version 2.8, offering the sameeasy-to-use graphical interface for defining andintegrating Nios processor systems.

Nios Development Kit, Stratix Edition NowShipping

The Nios Development Kit, Stratix Edition pro-vides all the hardware and software developmenttools required for a designer to begin developingcustom embedded systems based on the Niosprocessor. The kit includes the Nios processorversion 3.0 and a development board featuring aStratix EP1S10 device, in addition to 8-Mbyteflash memory, 1-Mbyte SRAM, 16-MbyteSDRAM, a CompactFlash connector, 10/100Ethernet MAC/PHY device, and switches, LEDsand prototype connectors. The Nios Develop-ment Kit, Stratix Edition is priced at $995, and isavailable today.

For the most recent news on the Nios processorversion 3.0 and the Nios Development Kit, StratixEdition, visit www.altera.com/nios or see “NiosProcessor Version 3.0 Delivers the Features Cus-tomers Want Most” on page 4.


Devices & Tools

Table 4. APEX II Device Availability

Device Package Availability

EP2A15 672-pin FineLine BGA

724-pin BGA

Now


724-pin BGA

Now


724-pin BGA

1,020-pin FineLine BGA

Now

EP2A70 724-pin BGA


Now


Devices & Tools


Mercury

APEX

APEX 20KC Devices Available in ProductionMode

All APEX 20KC devices and packages are avail-able. Table 7 shows the availability of APEX 20KCdevices.

For new designs requiring high performance, useStratix and Stratix GX FPGAs. These FPGAs de-liver top performance and are feature rich.

Mercury Devices Available in ProductionMode

All devices and all speed grades of the MercuryTM

device family are shipping in production mode,including industrial-grade offerings in both prod-uct lines (see Table 6). High-speed 1.25-Gbpsserial links featuring clock data recovery (CDR)circuitry and an embedded serializer/deserializ-er (SERDES) make these devices ideal for serialbackplane applications.

APEX II Industrial Offerings

All the industrial-grade devices for the APEX IIdevice family are now available. Industrial-gradeproduction versions of the device offerings areavailable in a -8 speed grade. Table 5 shows theavailability for industrial-grade offerings.

Table 5. APEX II Industrial Device Offering


EP2A15 672-pin FineLine BGA Now


724-pin BGA

Now

Now

EP2A40 724-pin BGA


Now

Now

Table 6. Mercury Device Availability

Device Package Temperature Grade

Availability

EP1M120 484-pin

FineLine BGA

Commercial in

-5, -6, -7 speed

grade

Now

Industrial in

-6 speed grade

Now

EP1M350 780-pin

FineLine BGA

Commercial in

-5, -6, -7 speed

grade

Now

Industrial in

-6 speed grade

Now

Table 7. APEX 20KC Device Availability


EP20K200C 208-pin PQFP

240-pin PQFP

356-pin BGA

484-pin FineLine BGA

Now

Now

Now

Now

EP20K400C 652-pin BGA


Now

Now




Now

Now

Now




Now

Now

Now


ACEX

ACEX 1K Device Availability

ACEX® 1K devices are available in quad flat pack(QFP) and FineLine BGA packages in 576-,1,728-, 2,880-, and 4,992-LE densities. These cost-optimized devices are specially suited for low-cost, high-volume applications. For mid- andhigh-density designs, see Altera’s newest and low-est-cost Cyclone FPGA family on page 18.

Free software support for all ACEX 1K devices isavailable in the Quartus II Web Edition softwareversion 2.2, which is available for download atwww.altera.com.

Note to Table 9:(1) The “X” denotes phase-locked loop (PLL) and LVDS

support.

Industrial-Grade APEX Device Offerings

Industrial-grade APEX devices are now availablein a wide variety of package offerings. Refer toTables 8, 9, and 10.

Table 8. APEX 20KC Device Industrial Offering

Device Package Speed Grade

EP20K200C 484-pin FineLine BGA -8

EP20K400C 672-pin FineLine BGA -8



-8

EP20K1000C 1,020-pin FineLine BGA -8

Table 9. APEX 20KE Device Industrial Offering


EP20K30E 144-pin FineLine BGA -2X (1)

EP20K60E 144-pin FineLine BGA

208-pin PQFP


-2X (1)

EP20K100E 144-pin FineLine BGA

240-pin PQFP


356-pin BGA

-2X (1)

EP20K160E 484-pin FineLine BGA -2X (1)

EP20K200E 240-pin PQFP

356-pin BGA



-2X (1)

EP20K300E 240-pin PQFP

652-pin BGA


-2X (1)

EP20K400E 652-pin BGA


-2X (1)



-2X (1)



-2X (1)

Note to Table 10:(1) The “V” denotes 5.0-V tolerant I/O interfaces. The

“X” denotes PLL support.

Table 10. APEX 20K Device Industrial Offering


EP20K100 208-pin PQFP

240-pin PQFP


-2V (1)

-2V (1)

-2XV (1)

EP20K200 240-pin PQFP


-2V (1)

EP20K400 652-pin BGA


-2V (1)

Devices & Tools



Devices & Tools

Design Software

Quartus II Software Version 2.2 ServicePack 1 Adds Full Support for Cyclone Devices

Service pack 1 for the Quartus II softwareversion 2.2 is now available from the Altera website. This release adds programming file genera-tion for the first Cyclone devices, adds pin-outsupport for Cyclone EP1C6 and EP1C12 devicesin the 256-pin FineLine BGA package, and addsadvanced support for two new Stratix packages.


MAX

MAX Power Calculator

The MAX® Power Calculator spreadsheet is nowavailable for download on the Altera® web site onthe MAX Design Utilities page. This spreadsheetallows for easy and seamless power estimationfor MAX 3000 and all MAX 7000 device families.It automatically calculates the power accordingto the equations and constants within each MAXdevice family data sheet. Choose the family andtarget device, and enter the number of macrocellsused (with turbo on or off) with frequency ofoperation and toggle rate. The number of macro-cells used and number of macrocells with turboare in the MAX+PLUS® II or Quartus II softwarereport (.rpt) files.

If you enter the ambient temperature and thedevice package, the spreadsheet can combine datawith the power result to verify that the designmeets thermal requirements. The spreadsheet alsoautomatically lists available packages accordingto the device family and density selected, provid-ing a simple and complete power analysis tool forany MAX design.

Free ByteBlasterMV Cable

Altera values customer feedback to better under-stand how our products are used and what wecan do to improve them in future. To gatherinput from the broadest range of customers, thenew MAX web pages include an on-line survey.The survey is accessible from the promotion but-ton at the right side of the page and the first50 survey responses will receive a freeByteBlasterMVTM cable.

Configuration

New Serial Configuration Devices

Altera’s new serial configuration devices are thelowest-cost configuration devices in the industryand provide the ideal complement to CycloneFPGAs in addressing high-volume, price-sensi-tive applications. Engineered for maximum effi-ciency, serial configuration devices deliver featuressuch as in-system programmability (ISP) and re-programming capabilities at a cost even lowerthan one-time programmable (OTP) solutions.

Enhanced Configuration Devices

Enhanced configuration devices provide a com-plete single-device solution for a wide range ofdensity requirements. Vertical migration capa-bility allows designers to easily migrate from theEPC4 to the EPC8 to the EPC16 device in thesame package without having to change the boardlayout. Commercial and industrial grade EPC4,EPC8, and EPC16 devices are all now available.

Enhanced configuration devices offer ISP througha built-in IEEE standard for boundary-scan-based, in-system configuration standard of pro-grammable devices (IEEE 1532). The inclusion ofISP and re-programmability provides a signifi-cant advantage over OTP solutions by introduc-ing flexibility and reusability to the configurationprocess.


New Device Support

Service pack 1 for the Quartus II softwareversion 2.2 adds support for the devices listed inTable 11.

Devices & Tools

Note to Table 11:(1) Advanced compilation and simulation only.

Table 11. New Quartus II Software Device Support

Family Device Package

EP1C6 144-pin TQFP

240-pin QFP

Cyclone

EP1C20 324-pin FineLine BGA


EP1S40 780-pin FineLine BGA (1)

956-pin BGA



Stratix

EP1S80 1,020-pin FineLine BGA (1)

Customer Release Notes

Information regarding all of the major enhance-ments in Quartus II software releases is con-tained in the Quartus II Software Release Notesdocument. This document is available from theLiterature section of the Altera web site atwww.altera.com within one week of each release.

Quartus II Web Edition Software Adds FullSupport for Cyclone Devices

The Quartus II Web Edition software is an entry-level version of the Quartus II design softwaresupporting all devices in the new Cyclonefamily the lowest cost FPGAs ever. TheQuartus II Web Edition software version 2.2service pack 1 is now available on the Altera website including programming file generation forthe first available members of the new Cyclonefamily listed in Table 11. The Quartus II WebEdition software also supports selected Stratix,APEX II, APEX 20KE, Excalibur, MAX 7000,MAX 3000, FLEX® 10KE, ACEX 1K, andFLEX 6000 devices.

New Design Software Starter Suite CD is NowAvailable

The Altera Design Software Starter SuiteCD-ROM includes all of the software necessaryto start designing with Altera devices. TheCD-ROM includes a complete environment forsystem-level design, FPGA and CPLD design, andembedded software development, including thefollowing software:

■ Quartus II Web Edition FPGA and CPLDdesign software

■ SOPC Builder automated system develop-ment software

■ GNUPro toolkit embedded processor devel-opment software

■ Nios OpenCore Plus hardware evaluation■ DSP Builder interface to The MathWorks

Simulink and MATLAB software evaluation■ MAX+PLUS II BASELINE CPLD design soft-

ware

This CD-ROM can be requested as an optionfrom the Quartus II Web Edition download pageor by emailing [email protected].

ByteBlaster II Cable Now Shipping

The ByteBlasterTM II programming cable is a di-rect replacement for the ByteBlasterMVTM pro-gramming cable. The ByteBlaster II cable supportsall the same features as the ByteBlasterMV cableand adds the following new features:

■ Support for active serial configuration modeto support the new low-cost EPCS1 andEPCS4 configuration devices

■ Support for 1.8-V programming and config-uration

The ByteBlaster II is now shipping and is sup-ported in the Quartus II software version 2.2 andhigher. An updated ByteBlaster II software driveris included in the Quartus II software version 2.2service pack 1 to support the new EPCS1 andEPCS4 configuration devices.


ArticlesContributed

The Development of an Altera-Based 10 Gigabit Ethernet Testerby Guylain Barlow ([email protected])Innocor Ltd.Altera Megafunction Partners Program (AMPPSM)

The growing presence of the Internet protocol(IP) at the heart of telecom networks puts pres-sure on service providers and vendors to opti-mize management of user traffic. One changethat has resulted from this is extending long-established local area network (LAN)-based Eth-ernet protocols into network cores. This changespawned the creation of Gigabit Ethernet and,more recently, 10 Gigabit Ethernet as defined bythe IEEE in its 802.3ae specification. Vendors andservice providers now seek independent sourcesto verify their 10 Gigabit Ethernet products. Themain challenge for test equipment manufactur-ers consists of determining which specific featureset meets the needs of the 10 Gigabit Ethernetuser. The starting point is to understand how10 Gigabit Ethernet is used.

Innocor’s 10 Gigabit test products use Altera’sprogrammable logic exclusively. The high-speedSFI-4, PL4/SPI-4.2, and 8b10b I/O capabilitiescombined with the high logic element (LE) den-sity and embedded RAM of the StratixTM andAPEXTM II devices make them ideal for such de-manding broadband applications.

Test feature needs vary largely between10 Gigabit Ethernet applications. Three main ar-eas of testing are transport with a focus on fram-ing and error conditions; routing/switching/storage where latency, loss, and upper layers areof high interest; and the component level thatconcentrates on the physical layer. Test equip-ment that can provide testing for 10 GigabitEthernet LAN and wide area network (WAN) onthe same hardware provides savings to the userand protects the product investment. Require-ments for core routing, switching, and even stor-age are very different. 10 Gigabit Ethernet is anew PHY interface that supports test needs relat-ed to POS and lower speed Ethernet. In this envi-ronment, test applications focus more on upperlayer applications and network simulations whencompared to transport-based users.

The 802.3ae standard is the starting point to de-termine the specific elements of 10 GigabitEthernet that require testing. Target users andapplications must then be identified to refine therequirements and derive the test equipment’soverall architecture. Innocor designed itsTestpoint SM-9953EX 10 Gigabit Ethernet offer-ing in collaboration with customers involved inproviding and developing transport technology.As a result, Innocor initially focused on definingstrong Layer 2 features to test aspects that impactframing devices. Additional features were pro-vided to test the system level and flow control.The following were found to be the key elementsto ensure flexibility and investment protectionfor the user:

■ Support for 10 Gigabit Ethernet WAN(9.953 Gbps) and 10 Gigabit Ethernet LAN(10.3 Gbps) on a single hardware platform.

■ Simple field upgrades to support incremen-tal features via programmable logic technol-ogy.

■ Support for multiple laser types at differentwavelengths and power level via multi-sourceagreement (MSA) technology.

■ Ability to support long-haul applications us-ing forward error correction (FEC) withITU-T G.709 for 10 Gigabit Ethernet WAN(10.7 gigabits per second (Gbps)) and10 Gigabit Ethernet LAN (11.1 Gbps).

Key feature areas were identified to test10 Gigabit Ethernet interfaces on transport equip-ment:

■ Frame Sizes: Support to inject and identifyshort, in-range, and long frames. The testequipment must also test MAC frame lengthmismatches. Virtual local area network(VLAN) support is also required.

■ Payload Test Patterns: Data test equipmentsometimes validates payload via proprietarycyclic redundancy code (CRC) schemes.Transport equipment testing requires themore robust pseudo-random bit sequence(PRBS) approach to test down to the bitlevel. Tests based on PRBS31 is supported atthe media access control (MAC) and physi-cal coding sub-layers (PCSs).


Contributed Articles

■ Bandwidth Control: Refers to varying theinter-frame gap length including invalid con-dition tests where the inter-frame gaps is lessthan the smallest allowable value.

■ Flow Control Features: Ensures matching traf-fic rates between the LAN (10.3 Gbps) andWAN (9.953 Gbps) interfaces via either MACpause frames or ifsStretch capabilities to reg-ulate the inter-frame gap size.

■ PCS Layer: PCS encodes the informationfrom the MAC layer. The test equipmentmust detect and inject discrete errors andblock rates. In addition, tests must be pro-vided to detect remote and local faults.

■ MAC Layer Errors: Capabilities to provideCRC error injection in the form of packeterror rates.

■ Disruption Time Measurement: The responseof the transport equipment to protectionswitching should be measured for 10 GigabitEthernet WAN or LAN.

■ Synchronization: Options to provide clock-ing, including internal clock, loop timing,and clock rate variations.

To meet the requirements listed above, the tester’shardware architecture must include flexible fram-ing technology and field-upgradable program-mable logic. Bidirectional line rate technology isimportant to push the limits of systems under testup to the 10 Gigabit Ethernet LAN rate of10.3 Gbps. A different set of requirements is driv-en by the applications supported by routing,switching, and storage devices that demand moreat the upper layers. These additional needs resultin either higher costs to address all requirementsor a more tailored hardware architecture. Thebest approach for any test equipment manufac-turer is to use programmable logic within theconfines of logic element usage and input-outputarchitectures. An example of design choice for IPtesting is how to perform Internet traffic simula-tions that integrate multiple complex protocolsand traffic flows. This requirement, especially inthe case of 10-Gbps rates, can imply a large num-ber of dedicated hardware resources raising equip-ment cost. Alternatively, traffic patterns can beconstructed via software and played from high-speed memory devices resulting in repeatable traf-fic sequences. 10 Gigabit Ethernet testers mustconsider the following high-level requirements:

■ Provisions for multiple protocol support in-cluding 802.2 LLC/SNAP, IPv4, IPv6, TCP,

and UDP. Header field edition must be pro-vided.

■ Generation and analysis of multiple trafficstreams. Simulation of a multitude of MAC,IP addresses to emulate traffic from multiplesources, and destinations. Each stream musthave its own bandwidth, packet length, andprotocol definitions.

■ Testing for quality of service parameters in-cluding the evaluation of delays and latencythrough a system under test and identifyingout-of-sequence, lost, and discarded pack-ets.

■ Packet filtering for statistics and to enablebuffer captures along with protocol decodes.

■ Routing protocol conformance and perfor-mance testing, which is similar to simulatinga network on the control plane for protocolssuch as MPLS, OSPF, and BGP-4.

On the 10 Gigabit Ethernet component testingfront, dedicated hardware is required in a test set.The requirements for that market segment in-clude:

■ Evaluation of optical signal to noise ratio(OSNR)

■ Stressed-eye testing■ Jitter tolerance generation and measurements■ Receiver sensitivity■ XAUI interface testing

In many cases, these requirements overlap, whichposes not only technical but also cost-controlchallenges. The development of 10 Gigabit Ether-net test equipment therefore depends on the tar-get market and applications. The key is to providea balance and give the user the most flexibility forthe price.

Innocor has developed its SM-9953EX to addressthe needs of manufacturing and research anddevelopment facilities for the emerging transportmarket based on 10 Gigabit Ethernet. In addi-tion, a set of complementary features such as IPstreaming, time-stamping, packet sequencing, andfiltering addresses the requirements of routing,switching, and storage device testing for manu-facturing. Besides testing 10 Gigabit Ethernet LANand WAN, Innocor’s SM-9953EX can also testSONET, SDH, ATM, and POS at rates of 10 Gbps.

For more information about Innocor’s testsolutions, visit the Innocor web site atwww.innocor.com or email [email protected].


NewsAltera

Design practices have an enormous impact on adesign’s timing performance, logic utilization, andsystem reliability. Using good design practicesallows successful design migration between ASICand FPGA implementations for prototyping andproduction. Poor design practices can lead to lowperformance, high logic or resource utilization,and unstable or unreliable designs associated withincreased verification time.

Altera Contributes to Third-Party Conferences

To help you with good design practices, Alterawill be presenting at the Synopsys Users Group

Customers who have recently contacted Altera®Applications were asked to evaluate their techni-cal support experience through Altera’s continu-ing customer applications survey program.

Nearly 1,000 customers in 2002 were asked howthey felt about Altera Technical Support. Respon-dents were asked questions such as the quality ofour answers, and the timeliness of our reply.They were also asked to indicate the types ofservices they might like to see from us in thefuture. From increased employee training to en-hanced web site organization, these surveys helpedus plan a number of improvements in the way wedo business.

To thank those who took the time to give feed-back, Altera has rewarded some survey takerswith Amazon.com gift certificates or Palm hand-helds. Pictured in Figure 1 is Ray Schouten,

Altera is Listening

Altera Presents Good Design Practices at Third-Party Conferences

Altera Field Applications Engineer congratulat-ing Scott Gygi of L3 Communications on win-ning a new Palm m515 handheld.

(SNUG) Conference (March 17 to 19) and theInternational Mentor Users Group (MUG) Con-ference (April 28 to 30). Altera speakers will dis-cuss how designers can obtain optimal results forFPGA designs by:

■ Understanding the impact of synchronousdesign practices

■ Following recommended design techniques■ Targeting the advanced FPGA architectural

features

For more details, go to www.snug-universal.orgor www.mentorug.org.

Figure 1. Palm m515 Winner


Discontinued Devices Update

Altera will be obsoleting select devices from prod-uct-term and FPGA families (see Table 1). Mostof the devices will have longer-than-usual last-time buy (18 months) and last-time ship dates(an additional 6 months) to allow customers togradually transition to using alternative orderingcodes.

Select ordering codes from mature families suchas MAX® 7000S are being obsoleted to increasethe operational efficiency in the manufacturingflow. On mainstream product families such asthe MAX 7000A, FLEX® 10KE, APEXTM 20K and

newer product families, such as the MAX 7000B,ACEX® 1K, and APEX 20KE, ordering codes havebeen consolidated to offer a limited set of codesthat will cover the various package and speedgrade options.

Continued support for devices beyond the phase-out period may be available through RochesterElectronics, an extended after-market supplier.For more information, contact Rochester Elec-tronics at (508) 462-9332 or your local Alterasales office.

In Every Issue

Continued support fordevices beyond the phaseout period may be avail-able through RochesterElectronics, an extend-ed after-market suppli-er.

Product Family

Device Last Order Date

Last Shipment

Date

Reference

MAX 7000S Selected devices with fixed-pulse width programming

option

10/31/03 04/30/04 PDN 0203

MAX 7000A Selected devices in micro ball-grid array (BGA),

FineLine BGATM, and TQFP packages

10/31/03 04/30/04 PDN 0203

MAX 7000B Selected devices 10/31/03 04/30/04 PDN 0203

Selected FLEX 8000 pin-grid array (PGA) packages 02/28/02 08/31/02 PDN 0107 FLEX 8000

Selected devices 02/28/03 08/31/03 PDN 0107

Selected FLEX 10K PGA packages 02/28/02 08/31/02 PDN 0107 FLEX 10K

Selected FLEX 10K PGA & BGA packages 02/28/03 08/31/03 PDN 0107

FLEX 10KA Selected PGA packages 02/28/03 08/31/03 PDN 0107

Selected PGA packages 02/28/03 08/31/03 PDN 0107 FLEX 10KE


Selected PGA packages 02/28/03 08/31/03 PDN 0107 APEX 20K


APEX 20KE Selected devices 10/31/03 04/30/04 PDN 0204

ACEX 1K Selected devices 10/31/03 04/30/04 PDN 0204


In Every Issue

Notes:(1) The Quartus Installation and Licensing and MAX+PLUS II Getting Started manuals are available from the Altera® web site. To obtain other

MAX+PLUS® II software manuals, contact your local distributor.(2) You can also contact your local Altera sales office or sales representative. See the Altera web site for the latest listing.

It is now easier than ever to get information and services from Altera. The table below lists some of the ways you can reach Altera.

How to Contact Altera

Information Type U.S. & Canada All Other Locations

Product Literature http://www.altera.com http://www.altera.com

Altera Literature Services (1) [email protected] [email protected]

News & Views Information http://www.altera.com/literature/nview.html

[email protected]

http://www.altera.com/literature/nview.html

[email protected]

Non-Technical Customer Service (800) 767-3753 (408) 544-7000

Technical Support http://www.altera.com/mysupport http://www.altera.com/mysupport

(408) 544-6401 (408) 544-6401 (2)

FTP Site ftp.altera.com ftp.altera.com

General Product Information (408) 544-7104 (408) 544-7104 (2)

http://www.altera.com http://www.altera.com

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