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Flash & EEPROM Module

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Flash & EEPROM Module. NVM. System Memory. SCI 1. SCI 1. ATD 1. ATD 0. 12K SRAM. 256K FLASH EEPROM. Internal Bus. SPI 2 or PWM CH 4-7. SPI 1 or PWM CH 0-3. SPI 0. BKP INT MMI. PWM 8 CHAN. HCS12 CPU. SIM. CM BDM MEBI. - PowerPoint PPT Presentation
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HCS12 Technical Training Module 14-NVM, Slide 1 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001. NVM Flash & EEPROM Module
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Page 1: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 1

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

NVM

Flash & EEPROMModule

Page 2: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 2

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

System Memory

Internal Bus

SCI1

256K FLASH EEPROM

12K SRAM

ATD 1

HCS12 CPU

BKP INT MMI

CM BDM MEBI

4K BYTESEEPROM

SIM

msCAN3

msCAN2

msCAN1

SCI1

SPI 2or

PWMCH4-7

BDLCor

msCAN0

msCAN4or

IIC

SPI 1or

PWMCH 0-3

SPI 0

ATD 0

PLL PIT

ECT 8CHAN

PWM 8CHAN

Page 3: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 3

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

FLASH EEPROM

• 256K bytes of Flash made of four 64K byte blocks• Single supply program and erase.• Automated program and erase algorithm.• Interrupt on command completion.• All four flash blocks can be programmed and erased in parallel.• Read-While-Write into different block.• Fast sector erase and word program operation.• Flexible protection scheme against accidental program or erase.• Security feature to prevent intrusive access.

Page 4: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 4

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Memory Map & Flash Control

Vectors

4K EEPROM

Registers

12K RAM

16K Flash(Fixed)

16Kx16 Flash Pages(Windowed)

16K Flash(Fixed)

$0000

$0400

$1000

$4000

$8000

$C000

$FF00

$FFFF

Page $30

Page $31

Page $3F

Page $3E

Page $3F

Flash ControlRegisters

$0100

$010F

Flash Protect Low Area.5K, 1K, 2K, 4K

Flash Protect High Area 2K, 4K, 8K, 16K

Page $3E

$30 - $3F Denotes contents of PPAGE Register

Flash Protect High Area

Address Description$FF00 -$FFF7 Backdoor comparison key

$FF08-$FF09 Reserved

$FF0A Flash block 3 protection

$FF0B Flash block 2 protection

$FF0C Flash block 1 protection

$FF0D Flash block 0 protection

$FF0E Reserved

$FF0F Security Byte

Flash 0 Protection/Security Fields

Page 5: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 5

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Flash Control Registers

• All four Flash Blocks Occupy 16 Bytes In The I/O Register Area.• Registers Are Divided Into Banked and Unbanked• Banked Registers Are Selected With BLKSEL1: BLKSEL0 In FCNFG• Unbanked Registers Control State Machine Clock, Security, Interrupts• Banked Registers Control Erasure, Programming, Protection• Banked Registers Allow Erasure and Programming All Four Blocks in Parallel

FDIV5PRDIV8FDIVLD $x100FDIV4 FDIV3 FDIV2 FDIV1 FDIV0

FSEC

Reserved

FCNFG

KEYEN NV6 NV5 NV4 NV3 NV2 SEC01 SEC00 $x101

$x102

$x103

0 0 0 0 0 0 0 0

CBEIE CCIE KEYACC 0 0 0 BKSEL1 BKSEL0

Bit 7 Bit 06 5 4 3 2 1

FCLKDIV

0 0 0 0 0 0 0 0

FPROT

FSTAT

FCMD

$x104

$x105

$x106

FPOPEN F FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0

CBEIF CCIF ACCERRPVIOL 0 BLANK 0 0

0 ERASE PROG ERVER MASS000

Reserved $x107 - x10F

Unbanked

Banked

Page 6: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 6

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Flash Clock Divider RegisterFLCKDIV - Flash Clock Divider Register

Address Offset $0000

FDIVLD — Flash Clock Divider LoadedThis bit is set when the FCLKDIV register is written to. An attemptto program or erase the flash without having written to this registerpreviously will result in an access error and the command will not be executed.

1 = Register has been written to since the last reset.0 = Register has not been written to.

PRDIV8 — Enable Prescaler by 81 = Enables a prescaler by 8 before feeding into the FCLKDIV divider.0 = OSCCLK is directly fed into the FCLKDIV divider

FDIV[5:0] — Flash Clock DividerThe combination of FDIV8 and FDIV[5:0] is used to divide the oscillator clock down to a frequency of 150KHz - 200KHz. This resulting clock, FCLK, is used to drive the program and erase state machines for the flash. For frequencies of OSCCLK > 12.8MHz the Prescaler bit PRDIV8 must be set on.

FCLKDIV Settings

if (OSCCLK > 12.8 MHz) PRDIV8 = 1else PRDIV8 = 0

if (PRDIV8 == 1) CLK = OSCCLK / 8else CLK = OSCCLK

FCLKDIV[5:0] = INT((CLK / 1000) / 200)

FCLK = CLK / (FCLKDIV[5:0] + 1)

Page 7: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 7

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Flash Security

• Memory Security Mechanism Prevents Unauthorized Access To Flash and

EEPROM.• Prevents Access via BDM or Expanded Bus Unless Flash and EEPROM

Are Erased.• Security Is Controlled By The Two LSBs of The FSEC Register.

• These Bits Are Loaded From Flash Location $FF0F.• Two Bits of Opposite Polarity Are Used To Prevent Security Mechanism

From Being ‘Tricked’.• Security Mechanism Can Be Temporarily Disabled, But It Requires

Firmware Support In The Target Application.• 64-bit Access Key Ensures That Security Mechanism Can Not Be

Easily Disabled By A Hacker.

Page 8: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 8

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Flash Security Control

FSEC - Flash Security RegisterAddress Offset $x001

This register is loaded from flash address $FF0F during thereset sequence, indicated by “F” in the reset row of the register description.KEYEN — Enable backdoor key to security1 = Backdoor to flash read via BDM or external bus interface is enabled0 = Backdoor to flash read via BDM or external bus interface is disabled.

When KEYEN is set, the user can then bypass the security by:1. Setting the KEYACC bit in the configuration (FCNFG) register.

2. Writing the correct four 16 bit words to the flash using the backdoor comparison keys addresses.

3. Clear the KEYACC bit.

4. If all four 16bit words match the flash content, the MCU is unsecured by forcing the bits SEC[1:0] to the unsecured state.

5. If any of the four 16bit words does not match the flash content the MCU remains secured and a security violation signal is sent to the CPU.

NV[6:2] = Non-Volatile FlagsThese Non-Volatile Flags are available to the user

SEC[1:0] Security State

0:0

0:1

1:0

1:1

Secured

Secured

Unsecured

Secured

Page 9: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 9

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Flash ConfigurationFCNFG - Flash Configuration Register

Address Offset $0003

This unbanked register enables the interrupts, gates the securitybackdoor writes and selects the register bank to be operated on.

CBEIE — Command Buffers Empty Interrupt EnableThis bit enables the interrupts in case of empty address, data and command buffers.1 = An interrupt will be requested whenever the CBEIF flag is set0 = Command Buffers Empty Interrupts disabled

CCIE — Command Complete Interrupt EnableThis bit enables the interrupts in case of all commands being completed.1 = An interrupt will be requested whenever the CCIF flag is set0 = Command Complete Interrupts disabled

KEYACC — Enable Security Key Writing1 = Writes to flash module are interpreted as keys to open the backdoor.0 = Flash writes are interpreted as the start of a program or erase sequence.

BKSEL[1:0]— Register bank selectThese two bits are used to select which of the four register banks areaddressed. The register bank associated with Flash 0 is the defaultout of reset.00 = Bank 001 = Bank 110 = Bank 211 = Bank 3

Page 10: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 10

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Flash ProtectionFPROT - Flash Protection Register

Address Offset $0004

This register determines whether a whole block or subsections of a block are protected against accidental programor erase. Each flash block can have two protected areas, one starting from relative address $8000 (called lower) towards higher addresses and the other growing downwards from $FFFF (called higher).

FPOPEN — Opens the flash block or subsections of it for program or erase.1 = The flash block or subsections are enabled to program or erase.0 = The whole flash block is protected.

FPHDIS — Flash Protection Higher address range disableThis bit determines whether there is a protected area at the higher end of the flash block address map.1 = Protection disabled0 = Protection enabled

FPHS[1:0] — Flash Protection Higher address size.These bits determine the size of the protected area.

FPLDIS — Flash Protection Lower address range disableThis bit determines whether there is a protected area at the lower end of the flash block address map.1 = Protection disabled0 = Protection enabled

FPLS[1:0] — Flash Protection Lower Address sizeThese 2 bits determine the size of the protected area.

Note: “F” indicates that registers are loaded from Flash control area as follows:. $FF0D --> Block 0, $FF0C --> Block 1, $FF0B --> Block 2, $FF0A --> Block 3

Page 11: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 11

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Higher AddressRange Protection

Page 12: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 12

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Lower AddressProtection Range

Page 13: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 13

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Memory Protection

$0000Flash Control RegistersRegister Base + $100

$3E

$3F

16K PagedMemory

$4000

$8000

$C000

$FFFF

$30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $3F

Block 3 Block 2 Block 1 Block 0

Protected Low Area0.5K, 1K, 2K, 4K

Protected High Area2K, 4K, 8K, 16K

$FF00 - $FF0F, Access Key, Protection, Security

Page 14: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 14

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Flash Status

Address Offset $0005

FSTAT - Flash Status Register

*CBEIF — Command Buffers Empty Interrupt FlagIndicates that the address, data and command buffers are empty sothat a new command sequence can be started. The flag is cleared bywriting a “1”. By clearing the flag the command sequence is launched.Writing a “0” aborts a command sequence that has not yet beenlaunched and sets the ACCERR flag.1 = Buffers are ready to accept a new command.0 = Buffers are full.

*CCIF — Command Complete Interrupt FlagIndicates that there are no more commands pending. 1 = All commands are completed0 = Command in progress

*PVIOL — Protection violationIndicates an attempt was made to program or erase an address in aprotected memory area. A subsequent program or erase commandcannot be executed while this flag is set. The flag is also cleared by writing anew, valid command after CBEIF is cleared or when CCIF is clear.1 = A protection violation has occurred.0 = no failure

*BLANK — Blank Verify FlagIndicates that the flash block is fully erased in response to an Erase-Verify command. 1 = Flash block fully erased.0 = Flash block not fully erased.

*These flags are cleared by writing “1” to them.

Page 15: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 15

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Access Errors

1. Writing to the flash address space before initializing FCLKDIV.

2. Writing to the flash address space in the range $8000–$BFFF when PPAGE does not select a 16K block in the flash selected by BKSEL[1:0].

3. Writing to the flash address space $4000–$7FFF or $C000–$FFFF with BKSEL[1:0] not selecting Flash 0.

4. Writing a misaligned word or a byte to the flash address space.

5. Writing to the flash address space while CBEIF is not set.

6. Writing a second aligned word to the flash address space before executing a program or erase command on the previously written word.

7. Writing to any Flash register other than FCMD after writing an aligned word to the flash address space.

8. Writing a second command to the FCMD register before executing the previously written command.

9. Writing a MASS erase command to FCMD while any protection is enabled. See FPROT register description.

10. Writing a SECTOR erase command to FCMD while protection is enabled for that sector. See FPROT register description.

11. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the command register.

12. The part enters STOP mode and a program or erase command is in progress. The command is aborted. The flag is cleared by writing a “1”.1 = Access error has occurred.0 = Command sequence or command execution successfully completed.

Page 16: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 16

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Flash Command

Address Offset $0006

FCMD - Flash Command Buffer Register

ERASE — Erase flashErases a flash sector (512 bytes) or the whole flash depending on the MASS bit. Trying to erase a sector located in a protected area will result in a protection violation indicated by the PVIOL bit in the FSTAT register being set.1 = Perform a sector erase if MASS=0 or a mass erase if MASS=1.

PROG — Word programmingTrying to program a word located in a protected area will result in a protection error indicated by PVIOL set.

ERVER - Enable Erase VerifyVerifies the flash block is fully erased. A successful verification will set the BLANK bit in the FSTAT register. 1 = Perform an erase verify after mass erase.

MASS - Enables Mass ErasePerform a mass erase of the selected 64K byte block. This bit worksin conjunction with the ERASE bit. If any protection is active on theselected block, mass erase has no effect and the PVIOL bit in theFSTAT register is set. Write at anytime.1 = Perform a mass erase of the whole block.0 = Perform sector erase.

Command Operation

$20

$40

$41

$05

Memory Program

Sector Erase

Mass Erase

Erase Verify

other Illegal

Description

Program 1 aligned Word (2 bytes)

Erase a 512 byte sector

Erase a 64K byte block

Verify Erasure of a 64K byte block

Generate an access error

Page 17: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 17

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Erase Flowchart

Write BKSEL[1:0]Bits

CBEIFFlagSet?

Yes

No

Write PPAGERegister Flash Array

Protectedor

Bad Command

Write AlignedData Word

Write Commandto FCMD Reg.

Clear CBEIFFlag

ACCERRor PVIOL

FlagSet?

No

CCIFFlagSet?

No YesCommandCompleted

Delay 5 BusCycles

Page 18: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 18

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Programming Flowchart

Write BKSEL[1:0]Bits

CBEIFFlagSet?

Yes

No

Write PPAGERegister Flash Array

Protectedor

Bad Command

Write AlignedData Word

Write Commandto FCMD Reg.

Clear CBEIFFlag

ACCERRor PVIOL

FlagSet?

No

DoneWith Data

Block?

No

Yes Block ProgramCompleted

Delay 5 BusCycles

Page 19: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 19

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

EEPROM

4K BYTE

Page 20: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 20

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

EEPROM Features

• 4K Non-Volatile Electrically Erasable programmable memory located @$0000 - $0FFF.

• Relocateable to any 4K Boundary

• Organized as 2048 by 16-bit Words to allow for word size Read/Write and Programming

• Erase Sector 4 bytes (2 words)

• Three-step MCU instructions sequence to program or erase the EEPROM.

• Single supply program and erase.

• Automated program and erase algorithm.

• Interrupt on command completion.

• Fast sector erase and word program operation.

• Flexible protection scheme against accidental program or erase.

• Programming voltage derived from VDD with internal charge pump

• Hardware Interlocks

Page 21: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 21

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

4K EEPROM MODULE

CommandInterface

EEPROM ARRAY2K x 16 Bits

Command Pipeline

comm2addr2data2

ClockDivider

Registers

comm1addr1data1

word2word3

word2047OscillatorClock

CommandCompleteInterrupt

CommandBufferEmptyInterrupt

word0word1

word2046

word2044word2045

Write & Eraseperformed here

Data Readsfrom here

Module Clock generated here

Page 22: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 22

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

High Speed Programming (EECLK = 200KHz) :• Very fast EEPROM Program (word) 46s

• EEPROM Sector Erase (2 words) 20ms

• EEPROM Mass Erase (4Kbytes) 100ms

Erase Cycling•100,000 Erase cycles

(should always check individual data sheets)

Further Reading:

• AN2204/D: “Fast NVM Programming for the MC9S12DP256”.

MC9S12 0.25u EEPROM Info

Page 23: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 23

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

EEPROM Register Summary

Three Configuration registers• Clock Divider Register (ECLKDIV)

– Prescaler value for the EEPROM sub-system clock. – MUST be configured to generate a module clock between

150KHz and 200KHz for program & erase.• Configuration Register (ECNFG)

– Enables EEPROM interrupts• Protection Register (EPROT)

– Controls whether the EEPROM is protected against program & erase.

– Configures the size of the protected block – all 4K OR 64 to 512 bytes.

– Loaded from the non-volatile EEPROM Protection Field on Reset.

Three Configuration registers• Clock Divider Register (ECLKDIV)

– Prescaler value for the EEPROM sub-system clock. – MUST be configured to generate a module clock between

150KHz and 200KHz for program & erase.• Configuration Register (ECNFG)

– Enables EEPROM interrupts• Protection Register (EPROT)

– Controls whether the EEPROM is protected against program & erase.

– Configures the size of the protected block – all 4K OR 64 to 512 bytes.

– Loaded from the non-volatile EEPROM Protection Field on Reset.

Two ‘working’ registers• Command Buffer Register (ECMD)

– Determines what operation is to be performed on the EEPROM block.• Status Register (ESTAT) -

– Contains EEPROM state machine Control, Status and Interrupt flags

Page 24: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 24

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

EEPROM Module Clock Prescaler

ECLKDIV - EEPROM Clock Divider Register

EDIVLD — Flash Clock Divider LoadedThis bit is set when the ECLKDIV register is written to. An attempt to program or erase the EEPROM without having written to this register previously will result in an access error and the command will not be executed.

PRDIV8 — Enable Prescaler by 8A pre-prescaler! Set this bit if oscillator frequency is >12.8MHz.

EDIV[5:0] — Flash Clock DividerThe combination of PRDIV8 and EDIV[5:0] is used to divide the oscillator clock down to a frequency of 150KHz - 200KHz. This resulting clock, EECLK, is used to drive the program and erase state machines for the EEPROM.Follow the flow chart in the specification to calculate the correct value for each application.

FOR CORRECT PROGRAM AND ERASE OPERATION EECLK MUST BE WITHIN SPEC REGARDLESS OF THE SYSTEM FREQUENCY.

EDIVLD — Flash Clock Divider LoadedThis bit is set when the ECLKDIV register is written to. An attempt to program or erase the EEPROM without having written to this register previously will result in an access error and the command will not be executed.

PRDIV8 — Enable Prescaler by 8A pre-prescaler! Set this bit if oscillator frequency is >12.8MHz.

EDIV[5:0] — Flash Clock DividerThe combination of PRDIV8 and EDIV[5:0] is used to divide the oscillator clock down to a frequency of 150KHz - 200KHz. This resulting clock, EECLK, is used to drive the program and erase state machines for the EEPROM.Follow the flow chart in the specification to calculate the correct value for each application.

FOR CORRECT PROGRAM AND ERASE OPERATION EECLK MUST BE WITHIN SPEC REGARDLESS OF THE SYSTEM FREQUENCY.

EDIVLD PRDIV8 EDIV[5:0]

Bit 7 6 5 4 3 2 1 0

Page 25: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 25

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

EEPROM Command Summary

** NOTE: locations must only be programmed once following each erase.

The operation executed by the EEPROM state machine is determined by the value written to the Command Buffer Register (ECMD)

CommandValue

Operation Comments

$20Word

ProgramProgram a word. **(2 bytes, word aligned)

$40SectorErase

Erase an EEPROM sector.(4 bytes, double word aligned)

$41MassErase

Erase the whole EEPROM. (Only possible when EPDIS and EOPEN bits are set)

$05EraseVerify

Verify the EEPROM block is fully erased. A successful verification will set the BLANK bit in the ESTAT register.

$60SectorModify

Erase the EEPROM sector containing the word and then program one word with the new data.By launching a sector modify command and then pipelining a Program command it’s possible to completely update a Sector.

other illegal Any other value will generate an Access Error.

Page 26: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 26

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

EEPROM Configuration

ECNFG - EEPROM Configuration Register Address Offset $0003

CBEIE - Command Buffers Empty Interrupt EnableThis bit enables the interrupts in case of an empty address, data andcommand buffers.1 = An interrupt will be requested whenever the CBEIF flag is set0 = Command Buffers Empty Interrupts disabled

CCIE - Command Complete Interrupt EnableThis bit enables the interrupts in case of all commands beingcompleted.1 = An interrupt will be requested whenever the CCIF flag is set0 = Command Complete Interrupts disabled

Page 27: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 27

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

EEPROM ProtectionEPROT - EEPROM Configuration Register

Address Offset $0004

EPOPEN — Opens the EEPROM block or a subsection of it for program or erase.1 = The EEPROM block or subsections are enabled to program or erase.0 = The whole EEPROM block is protected. In this case the other bits within the protect register are don’t care.

EPDIS — EEPROM Protection disableThis bit determines whether there is a protected area at the higher endof the EEPROM block address map.1 = Protection disabled0 = Protection enabled EEPROM Protection address size

Page 28: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 28

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

EEPROM Command

Address Offset $0006

ECMD - EEPROM Command Buffer Register

ERASE — Erase EEPROMErases a EEPROM sector (4 bytes) or the whole EEPROM depending on the MASS bit. Trying to erase a sector located in a protected area will result in a protection violation indicated by the PVIOL bit in the FSTAT register being set.1 = Perform a sector erase if MASS=0 or a mass erase if MASS=1.

PROG — Word programmingTrying to program a word located in a protected area will result in a protection error indicated by PVIOL set.

ERVER - Enable Erase VerifyVerifies the EEPROM block is fully erased. A successful verification will set the BLANK bit in the FSTAT register.1 = Perform an erase verify after mass erase.

MASS - Enables Mass ErasePerform a mass erase of the selected 64K byte block. This bit worksin conjunction with the ERASE bit. If any protection is active on theselected block, mass erase has no effect and the PVIOL bit in theFSTAT register is set. Write at anytime.1 = Perform a mass erase of the whole block.0 = Perform sector erase.

Command Operation

$20

$40

$41

$05

Memory Program

Sector Erase

Mass Erase

Erase Verify

other Illegal

Description

Program 1 aligned Word (2 bytes)

Erase a 512 byte sector

Erase a 64K byte block

Verify Erasure of a 64K byte block

Generate an access error

Page 29: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 29

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Address Offset $0005

ESTAT - EEPROM Status Register

*CBEIF — Command Buffers Empty Interrupt FlagIndicates that the address, data and command buffers are empty sothat a new command sequence can be started. The flag is cleared bywriting a “1”. By clearing the flag the command sequence is launched.Writing a “0” aborts a command sequence that has not yet beenlaunched and sets the ACCERR flag.1 = Buffers are ready to accept a new command.0 = Buffers are full.

*CCIF — Command Complete Interrupt FlagIndicates that there are no more commands pending. 1 = All commands are completed0 = Command in progress

*PVIOL — Protection violationIndicates an attempt was made to program or erase an address in aprotected memory area. A subsequent program or erase commandcannot be executed while this flag is set. The flag is also cleared by writing anew, valid command after CBEIF is cleared or when CCIF is clear.1 = A protection violation has occurred.0 = no failure

*BLANK — Blank Verify FlagIndicates that the EEPROM block is fully erased in response to an Erase-Verify command. 1 = EEPROM block fully erased.0 = EEPROM block not fully erased.

*These flags are cleared by writing “1” to them.

EEPROM Status

Page 30: Flash & EEPROM Module

HCS12 Technical Training Module 14-NVM, Slide 30

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Access Errors

1. Writing to the EEPROM address space before initializing ECLKDIV.

2. Writing a misaligned word or a byte to the EEPROM address space.

3. Writing to the EEPROM address space while CBEIF is not set.

4. Writing a second aligned word to the EEPROM address space before executing a program or erase command on the previously written word.

5. Writing to any EEPROM register other than ECMD after writing an aligned word to the EEPROM address space.

6. Writing a second command to the ECMD register before executing the previously written command.

7. Writing a MASS erase command to ECMD while any protection is enabled. See EPROT register description.

8. Writing a sector erase command to ECMD while protection is enabled for that sector. See EPROT register description.

9. Writing to any EEPROM register other than ESTAT (to clear CBEIF) after writing to the command register.

BLANK — Blank Verify FlagIndicates that the EEPROM block is fully erased in response to an Erase- Verify command. The flag is cleared by writing a “1”. 1 = EEPROM block fully erased.0 = EEPROM block not fully erased.


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