Flash-Memory Storage Systems: Design Issues and Challenges

Flash-Memory Storage Systems: Design Issues and Challenges

Department of Computer Science & Information Engineering

National Taiwan University

Tei-Wei Kuo

2008/7/14 Embedded Systems and Wireless Networking Lab. 2

Agenda

IntroductionManagement IssuesBehavior AnalysisReliability – Wear LevelingOther Challenging IssuesConclusion


Introduction – Why Flash MemoryDiversified Application Domains

Portable Storage DevicesConsumer ElectronicsIndustrial ApplicationsCritical System Components


Trends in VLSI Technology

Source: www.icknowledge.com

* This slide was from the ASP-DAC’06 talk delivered by Prof. SangLyul. Min from the Seoul National University.

Flash Makers – NAND Flash Memory


http://hugoleijtens.spaces.live.com/blog/cns!4B94B7453D4BFD9E!988.entry

Source: iSuppli Corp (Unit: Million Dollars)

[EE Times,11/30/2007]For years, NAND priceshave dropped by anaverage of 40 percentor more per year.


Trends – Storage Media

Source: Using multilevel cell NAND flash technology in consumer applications, Electronic Engineering Times, July ,2005

Samsung 2GB USB 2.0 Flash DrivePrice: $49.99Less Rebate: - $25.00 Final Price: $24.99*

T-One 2GB Microdrive/3600RPM$144.99

September 2006



Source: Using multilevel cell NAND flash technology in consumer applications, Electronic Engineering Times, July ,2005. Amazon.com

Transcend 8GBCompactFlash CardPrice: $84.85

Microdrive 4GBCompact Flash Type II

Price: $116

SanDisk 4GBCompactFlash CardPrice: $55.99

March 2007

http://www.amazon.com/gp/product/images/B000E40RB4/ref=dp_image_0/002-4709339-6086423?ie=UTF8&n=172282&s=electronics

http://www.amazon.com/gp/product/images/B000243DOE/ref=dp_image_0/002-4709339-6086423?ie=UTF8&n=172282&s=electronics



Source: Using multilevel cell NAND flash technology in consumer applications, Electronic Engineering Times, July ,2005Component Times, Nov 2007.; March/July 2008, www. amazon.com

20Gb IBM HDD

Transcend 8GB SDHC SD CARD (USD23.77)

HITACHI 6GB Microdrive MD6GBBP (USD169.95, Feb 2008No Longer Carried in July)

July 2008

Seagate FreeAgent Desktop 500 GB 3.5" USB 2.0 External Hard Drive (USD104.99)

Transcend 32GB SSD, 2.5- Inch, SATA, MLC (USD343.30 (2008/03) USD202.79 (2008/07))

Flash Stories – Solid-State Disks< 50% Heat, Ultra Silence, Light Weight, MTTF – 200M hours (HDD – 30M hours), Energy Efficiency

2008/7/14 Embedded Systems and Wireless Networking Lab. 9IDC, SanDisk - Component Times, Nov 2007

Flash Stories – Flash WarsFab

300mm Wafer Fab by Toshiba and SanDisk at Yokkaichi, Japan

80,000 Wafers per Month (2008)210,000 Wafers per Month

300mm Wafer Fab by IM Flash

Technologies (Intel & Micron) at UtahJoint Venture: Sony and Qimonda, Hynix and Sandisk

Technology32nm (Samsung, Intel), 43nm (Toshiba), 50nm (IM)


Introduction – The Characteristics of Storage Media

*Flash Erase Time: NOR(10ms), NAND (1.5ms)[Reference] DRAM: DDR-400. NOR FLASH: Intel 28F128J3A-150. NAND FLASH: Samsung K9K8G08U0M. Disk: Segate Barracuda ATA II.11. Jian-Hong Lin, Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, and Cheng-Chih Yang, "A NOR Emulation Strategy over NAND Flash Memory," the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Daegu, Korea , August 21-24, 2007.

MediaAccess time

Read Write Erase

DRAM 5ns (1B)2.56us (512B)

5ns (1B)2.56us (512B)

-

NOR FLASH 150ns (1B)14.4us (512B)

211us (1B)3.52ms (512B)

1.2s (16KB)

NAND FLASH 20us (1B)32.8us (512B)

200us (1B)212us (512B)

1.5ms (128KB)

DISK 12.4ms (512B)(average)

12.4 ms(512B)(average)

-

13X 83X

400X 50X


Introduction – Single-Level Cell (SLC)

Selected cellIDS

Control GateDrain

Source

Each Word Line is connected to control gates.Each Bit Line is connected to the drain.

Cell


Introduction – Multi-Level Cell (MLC) vs SLC

NU

MB

ER

OF

CE

LLS


Introduction – Consumer Applications

Electronic Engineering Times, July 2005


Bandwidth Requirements – Video

ˇ

ˇ



Bandwidth Requirements – Audio

ˇ

ˇ



Introduction – Challenges in Flash-Memory Storage Designs

Requirements in Good PerformanceLimited Cost per Unit Increasing in Access FrequenciesStrong Demands in ReliabilityTight Coupling with Other ComponentsLow Compatibility among Vendors


Agenda



Management Issues – System Architectures

AP

File-System Layer

AP AP

Block Device Layer (FTL emulation)

Flash Memory

MTD drivers

AP


Management Issues – Flash-Memory Characteristics

……

Block 0Block 1

Block 2Block 3

Erase one block

1 Page = 512B1 Block = 32 pages(16KB)

……

Write one page



Write-OnceNo writing on the same page unless its residing block is erased!Pages are classified into valid, invalid, and free pages.

Bulk-Erasing Pages are erased in a block unit to recycle used but invalid pages.

Wear-LevelingEach block has a limited lifetime in erasing counts.



Example 1: Out-place Update

Live pages Free pages

A B C D

Suppose that we want to update data A and B…


Dead pages

A B C D A B


Example 1: Out-place Update


A live pageA dead pageA free page

This block is to be recycled. (3 live pages and 5 dead pages)

L D D L D D L D

L L D L L L F D

L F L L L L D F

F L L F L L F D


Example 2: Garbage Collection


L L D L L L D

L F L L L L D

L L F L L F D

L

L

D D D D


Live data are copied to somewhere else.

L

D DDD





The block is then erased.

Overheads: •live data copying •block erasing.

L L D L L L D

L F L L L L D

L L F L L F D

L

L

F F F F F F F F

L





Example 3: Wear-Leveling

L D D L D D L D

L L D L L L F D

L F L L L L D F

F L L F L L F D

100

10

20

15

Erase cycle counts

Wear-leveling might interfere with the decisions of the block-recycling policy.


A

B

C

D


Management Issues – Challenges

The write throughput drops significantly after garbage collection starts!The capacity of flash-memory storage systems increases very quickly such that memory space requirements grows quickly.Reliability becomes more and more critical when the manufacturing capacity increases!The significant increment of flash-memory access rates seriously exaggerates the Read/Program Disturb Problems!


Agenda

IntroductionManagement IssuesBehavior Analysis

Performance vs Overheads – FTL vs NFTLTrace Study

Reliability – Wear LevelingOther Challenging IssuesConclusion


System Architecture

GarbageCollection

AddressTranslation

FTL/NFTLLayer

File system (FAT, EXT2, NTFS......)

Device Driver

fwrite(file,data)

Block write(LBA,size)

Flash I/O Requests

Controlsignals

File Systems

process processprocess Applications

Flash-MemoryStorage System

Physical Devices(Flash Memory Banks)

process

31

31

System Architecture

*FTL: Flash Translation Layer, MTD: Memory Technology Device

SD, xD,MemoryStick,SmartMedia

CompactFlash

2008/1/30 Embedded Systems and Wireless Networking Lab. 312008/7/14

2008/7/14Embedded Systems and Wireless Networking Lab. 32

Policies – FTLFTL adopts a page-level address translation mechanism.

The main problem of FTL is on large memory space requirements for storing the address translation information.


Policies – NFTL (Type 1)

.

.

.

(9)

Write data to LBA=1011

.

.

.

NFTLAddress Translation Table

(in main-memory)

FreeFreeFreeUsedFreeFreeFreeFree

FreeFreeFreeFreeFreeFreeFreeFree

A Chain Block

Address = 9

A Chain Block

Address = 23

VBA=126

Block Offset=3

If the page has been used

Write to the page with block

offset=3

A logical address under NFTL is divided into a virtual block address and a block offset.

e.g., LBA=1011 => virtual block address (VBA) = 1011 / 8 = 126 and block offset = 1011 % 8 = 3

FreeFreeFreeFreeFreeFreeFreeFree

A Chain Block

Address = 50

Used

Write to the page with block

offset=3


Policies – NFTL (Type 2)A logical address under NFTL is divided into a virtual block address and a block offset.

e.g., LBA=1011 => virtual block address (VBA) = 1011 / 8 = 126 and block offset = 1011 % 8 = 3

.

.

.

(9,23)

Write data to LBA=1011

.

.

.

NFTLAddress Translation Table

(in main-memory)

FreeFreeFreeUsedFreeFreeFreeFree

UsedUsedUsedFreeFreeFreeFreeFree

A Primary Block

Address = 9

A Replacement Block

Address = 23

VBA=126

Block Offset=3

If the page has been usedWrite to the

first free page


Policies – NFTL

NFTL is proposed for the large-scale NAND flash storage systems because NFTL adopts a block-level address translation.

However, the address translation performance of read and write requests might deteriorate, due to linear searches of address translation information in primary and replacement blocks.


Policies – FTL or NFTLFTL NFTL

Memory Space Requirements Large SmallAddress Translation Time Short Long

Garbage Collection Overhead Less MoreSpace Utilization High Low

The Memory Space Requirements for one 1GB NAND (512B/Page, 4B/Table Entry, 32 Pages/Block)

FTL: 8,192KB (= 4*(1024*1024*1024)/512)NFTL: 256KB (= 4*(1024*1024*1024)/(512*32))

Remark: Each page of small-block(/large-block) SLC NAND can store 512B(/2KB) data, and there are 32(/64) pages per block. Each page of MLCx2 NAND can store 2KB, and there are 128 pages per block.


Address Translation Time - NFTLThe address translation performance of read and write requests can be deteriorated, due to linear searches of physical addresses.

1. Assume that each block contains 8 pages.

2. Let LBA A, B, C, D, and E be written for 5, 5, 1, 1, and 1 times, respectively. Their data distribution could be like to what in the left figure.

3. For example, it might need to scan 9 spare areas for LBA B.


Garbage Collection Overhead - NFTL

3. Overhead is 2 block erases and 5 page writes.

1. Copy the most-recent content to the new primary block.2. Erase the old primary block and the replacement block.


Space Utilization - NFTL

3 free pages are wasted.


Agenda

IntroductionManagement IssuesBehavior Analysis

Performance vs Overheads – FTL vs NFTLTrace Study

Reliability – Wear LevelingOther Challenging IssuesConclusionP.-C. Huang, Y.-H. Chang, J.-W. Hsieh, and M. Lin, “The Behavior Analysis of Flash-Memory Storage Systems, IEEE ISORC’08.

Flash Storage System Architecture


Peak Read/Write Throughput

The sequential access pattern usually yields the best-case throughput of a flash-memory storage system

It is due to the address mapping and garbage collection overheads

ith access

LBA

Largest request packet length


Worst-Case Write Response TimeAccess patterns with small accesses to trigger garbage collection activities

The first pass fills the whole flash memory to force out-place updatesThe second pass actually triggers the updates and garbage collection

LBA

ith access

Pass1 Pass2


Reliability - First-Failure Time

Access patterns that repetitively write to some specific LBA’s to see whether the management facilities can evenly distribute the writes to PBA’s.

Random accesses are inserted to avoid the caching effects

LBA

ith access



Agenda


Y.-H. Chang, J.-W. Hseuh, and T.-W. Kuo,, “Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design,” ACM/IEEE 44-th Design Automation Conference (DAC), San Diego, USA, June 2007. [Best Paper Nomination]


Wear Leveling versus Product LifetimeSettings

File system: FAT16 file system with 8KB cluster sizeFlash memory: 256MB small-block flash memory with 100K erase cycles

Updating of a 16MB file repeatedly with the throughput: 0.1MBs

The file requires 2K clusters = 16MB ÷ 8KB(cluster size)The FAT size of this file is 4KB (2K(clusters) x 2 bytes)The 20% of blocks in flash memory joins the dynamic wear leveling Data of a 16MB file is stored in 1K blocks (16MB ÷ 16KB(block size))Suppose flash memory is managed in the block level

File systems update the FAT in each cluster writing so that FAT is updated 2Ktimes for a 16MB fileWriting of a 16MB incurs 1K block erases because of the reclaiming of invalid space.


Wear Leveling versus Product Lifetime

Ways in Data UpdatesIn-Place-Updates: Rewriting on the Same PageDynamic Wear Leveling: Rewriting over Another Free Page with Erasing over Blocks with Dead PagesStatic Wear Leveling: Rewriting over Another Free Page with Erasing over Any Blocks

Expected Lifetime of

)days(5.987606024)12(

1000%01(blocks)16ond)0.1(MB/sec

16(MB) Leveling Wear Static

)days(5.197606024)12(

10020%(blocks)16ond)0.1(MB/sec

16(MB) Leveling Wear Dynamic

)days(09.06060242

100ond)0.1(MB/sec

16(MB) update) place-(in Leveling Wear NO

≈×××+××

×=

≈×××+

×××=

≈×××

×=

KKKK

KKKK

KK


Use a counter for each blockThe garbage collector always finds the block with the least erase count.

Some heuristic approach erases a block to maintain 2 free blocks when the garbage collector finds the erase count of the block is over a given threshold.

Problems:High extra block erases and live-page copyingsHigh main-memory consumptionHigh computation cost

Wear Leveling versus Product Lifetime Static Wear Leveling – Block-Level Mapping

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15FlashMemory

Counter

: free block : dead block

: block contains (some) valid data

: index in the selection of a victim block

: index to the selected free block 5 5 4 55 4 45 45 5 44 55 4

Update data in block 3Write new data to block 4GC starts find a victim block

5

Update block 15GC starts

5 5 5 5

49

Comparison of Different Technologies

Physical Block Addresses (PBA)

Eras

eC

ycle

s

0 20 40 60 80 1000

1000

2000

3000

4000

5000Perfect SWL

Physical Block Addresses (PBA)0 20 40 60 80 100

0

1000

2000

3000

4000

5000Intuitive SWL

Eras

eC

ycle

s

0 20 40 60 80 1000

1000

2000

3000

4000

5000

No Wear Leveling

0 20 40 60 80 1000

1000

2000

3000

4000

5000

Dynamic Wear Leveling

2008/7/14 Embedded Systems and Wireless Networking Lab.

50

An Efficient Static Wear Leveling Mechanism

A modular design for compatibility considerations A SWL mechanism

Block Erasing Table (BET)

bit flags

SW LevelerSWL-ProcedureSWL-Update


51

The Block Erasing Table (BET)A bit-array: Each bit is for 2k consecutive blocks.

Small k – in favor of hot-cold data separationLarge k – in favor of small RAM space

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15Flash

BET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

1 1 1 1

k=0 k=2

ecnt=0fcnt =0

ecnt=0fcnt =0

ecnt=1fcnt =1ecnt=2fcnt =2ecnt=3fcnt =2

ecnt=1fcnt =1ecnt=2fcnt =2ecnt=3fcnt =2ecnt=4fcnt =2

: a block that has been erased in the current resetting interval: an index to a block that the Cleaner wants to erase

fcnt: the number of 1’s in the BET ecnt: the total number of block erases done since the BET is reset

2008/7/14Embedded Systems and Wireless Networking Lab.

52

Endurance Improvement - The First Failure Time

When k=3 and T=100, the endurance is improved by

100.2%.

When k=0 and T=100, the endurance is improved by

87.5%.


53

SummaryAn Efficient Static Wear Leveling Mechanism

Small Memory Space RequirementLess than 1KB for 8GB flash memory

Efficient ImplementationAn adjustable house-keeping data structureAn cyclic queue scanning algorithm

Performance EvaluationImprovement Ratio of the Endurance:

The ratio is more than 50%

Extra Overhead: It is less than 3% of extra block eraseThere is limited overhead in live-page copyings



Agenda



Challenging Issues – Reliability

Selected cellIDS

Control GateDrain

Source

Each Word Line is connected to control gates.Each Bit Line is connected to the drain.

Cell


Challenging Issues – ReliabilityRead Operation

When the floating gate is not charged with electrons, there is current ID (100uA)if a reading voltage is applied. (“1” state)

5V

1V

Program OperationElectrons are moved into the floating gate, and the threshold voltage is thus raised.


Challenging Issues – ReliabilityOver-Erasing Problems

Fast Erasing Bits All of the cells connected to the same bit line of a depleted cell would be read as “1”, regardless of their values.

Read/Program Disturb ProblemsDC erasing of a programmed cell, DC programming of a non-programmed cell, drain disturb, etc.Flash memory that has thin gate oxide makes disturb problems more serious!

Data Retention ProblemsElectrons stored in a floating gate might be lost such that the lost of electrons will sooner or later affects the charging status of the gate!


Challenging Issues – ObservationsThe write throughput drops significantly after garbage collection starts!The capacity of flash-memory storage systems increases very quickly such that memory space requirements grows quickly.Reliability becomes more and more critical when the manufacturing capacity increases!The significant increment of flash-memory access rates seriously exaggerates the Read/Program Disturb Problems!Wear-leveling technology is even more critical when flash memory is adopted in many system components or might survive in products for a long life time!


ConclusionWhat Is Happening?

Solid-State Storage DevicesNew Designs in the Memory HierarchyMore Applications in System Components and Products

Challenging Issues: Performance, Cost, and Reliability

Scalability TechnologyReliability TechnologyInterdisciplinary Work


Contact Information

• Professor Tei-Wei [email protected]: http://csie.ntu.edu.tw/~ktwFlash Research: http://newslab.csie.ntu.edu.tw/~flash/Office: +886-2-23625336-257Fax: +886-2-23628167Address: Dept. of Computer Science & Information Engr.National Taiwan University, Taipei, Taiwan 106

http://csie.ntu.edu.tw/~ktw

http://newslab.csie.ntu.edu.tw/~flash/

Q & A


1-bit/Cell SLC NAND Flash100,000 Program/Erase cycles (with ECC)[1]10 years Data Retention[1]

2-bits/Cell MLC NAND Flash10,000 Program/Erase cycles (with ECC) [2]10 years Data Retention[2]

4-bits/Cell MLC NAND FLASH Developers (2006)

M-systems, Intel, Samsung, and Toshiba[1] ST Micro-electronics NAND SLC large page datasheet (NAND08GW3B2A)[2] ST Micro-electronics NAND MLC large page datasheet (NAND04GW3C2A)•USD34.65 per GB for NOR, •USD7.10 (SLC) and USD2.48 (MLCx2) per GB for NAND in 2008 Q1

Comparison of SLC and MLC

Introduction – Price and Read/Write Performance

NOR NAND SLC NAND MLCx2

Price $34.55/GB $6.79/GB $2.48/GB

Read 23.84 MB/sec 15.33 MB/sec 13.5 MB/sec

Write 0.07 MB/sec 4.57 MB/sec 2.34 MB/sec

Erase 0.22 MB/sec 85.33 MB/sec 170.66 MB/sec

*NOR: Silicon Storage Technology (SST). NAND SLC: Samsung Electronics. K9F1G08Q0M. NAND MLCx2: ST STMicroelectronics[1,2]

1. Jian-Hong Lin, Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, and Cheng-Chih Yang, "A NOR Emulation Strategy over NAND Flash Memory," the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Daegu, Korea , August 21-24, 2007.2. Yuan-Hao Chang and Tei-Wei Kuo, “A Log-based Management Scheme for Low-cost Flash-memory Storage Systems of Embedded Systems”

Non-Volatile Memory


Macronix International Co., Component Times, Nov. 2007

Performance Comparison(Still Under Development)

RAM Type R/W Speed Lifetime / Endurance Density Cost

MRAM 25~100ns/1B3, 2ns/1B in experiment5

Highly reliable, 20 yr data retention

1~4MB1GB TBA2 4USD/1MB

PRAM 50ns/1B Highly reliable, 1013 W/E cycles 4~64MB N/A

Racetrack Memory 20~32ns/1B4 Highly reliable1 Higher than

MRAM1Lower than

MRAM1

References1. http://www.digitimes.com.tw/EDM/EDM_DTF970122END/H11.pdf2. http://www.engadget.com/2008/06/02/toshiba-says-its-1gb-mram-chips-are-almost-ready-were-ready/3. http://203.66.161.5/document/mic_digi/Topology/report_topology/IA/2003/030806MRAM.pdf4. http://en.wikipedia.org/wiki/Racetrack_memory5. http://en.wikipedia.org/wiki/Magnetoresistive_Random_Access_Memory

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Flash-Memory Storage Systems: Design Issues and Challenges

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