The International Journal of Microcircuits and Electronic Packaging, Volume 21, Number 2, Second Quarter 1998 (ISSN 1063-1674) 8 International Microelectronics And Packaging Society Flip Chip MPU Module Using High Performance Printed Circuit Board “ALIVH” Flip Chip MPU Module Using High Performance Printed Circuit Board “ALIVH” Tsukasa Shiraishi, Kazuyoshi Amami, Yoshiriro Bessho, Kazunori Sakamaoto, Kazuo Eda, and Toru Ishida National / Panasonic Matsushita Electric Industrial Co., Ltd. 1006, Kadoma, Osaka, 571-8501 JAPAN Phone: +81-6-900-9628 Fax: +81-6-906-4587 e-mail: [email protected]Kazuyoshi Fukuoka Matsushita Electronic Components Co.,Ltd. 1006, Kadoma, Osaka, 571-8501 JAPAN Phone: +81-6-906-4739 Fax: +81-6-906-1387 Abstract The authors have developed a Flip Chip MPU module on a high performance printed circuit board “ALIVH”(Any Layer Inner Via Hole Structure) for sub-note PCs using modified stud-bump bonding (SBB) technology. Many MPU modules for sub-note PCs have been mass- produced since 1995 in Matsushita Electric, using the SBB technology. However, all of these modules employ ceramic substrates. There are great demands to reduce the cost and weight of sub-note PCs. Though the cost and weight of an organic substrate are much cheaper and lighter than those of a ceramic substrate, however, almost no Flip Chip technology and organic substrate can satisfy the high performance MPU operation. The newly developed high performance ALIVH substrate and the modified SBB technology can satisfy the performance MPU operation. The weight of the ALIVH substrate is lighter than conventional glass-epoxy type, and also high density of wiring can be obtained. The modified SBB technology can achieve fine pitch interconnection, nevertheless the substrate was organic. The authors have successfully fabricated high performance Flip Chip MPU module for sub-note PCs using the MCM-ALIVH. In this MPU module, 4 LSI bare chips were mounted onto an 8 layered ALIVH substrate. The CPU had 359 I/O pins and the minimum pad pith was 85microns. The clock frequency was 160 MHz. The weight of the MPU module was reduced to 40% of the conventional one. The obtained electrical characteristics were good enough for sub-note PCs. The SBB-ALIVH technology is very promising for MCMs to satisfy both high performance and low cost. Key words: SBB TM technology, ALIVH TM , MCM (Multichip Module), and MPU (Micro Processor Unit). 1. Introduction Recently, there is a great demand for an LSI packaging technol- ogy with high density and high performance. Therefore, the amount of MCMs is increasing radically. A Flip Chip bonding technology is effective for the high density MCMs. A sub-note PC is one of the electric appliances that need a Flip Chip bonding technology. An MPU module in the sub-note PC is constituted of the LSI chips with high performance, fine pad pitch and high speed processing. The researchers have already developed an advanced Flip Chip bonding technology, called Stud-Bump-Bonding (SBB TM ) technol- 205
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The International Journal of Microcircuits and Electronic Packaging, Volume 21, Number 2, Second Quarter 1998 (ISSN 1063-1674)
8 International Microelectronics And Packaging Society
Flip Chip MPU Module Using High Performance Printed Circuit Board “ALIVH”
Flip Chip MPU Module Using High PerformancePrinted Circuit Board “ALIVH”Tsukasa Shiraishi, Kazuyoshi Amami, Yoshiriro Bessho,Kazunori Sakamaoto, Kazuo Eda, and Toru IshidaNational / PanasonicMatsushita Electric Industrial Co., Ltd.1006, Kadoma, Osaka, 571-8501 JAPANPhone: +81-6-900-9628Fax: +81-6-906-4587e-mail: [email protected]
The authors have developed a Flip Chip MPU module on a high performance printed circuit board “ALIVH”(Any Layer Inner Via HoleStructure) for sub-note PCs using modified stud-bump bonding (SBB) technology. Many MPU modules for sub-note PCs have been mass-produced since 1995 in Matsushita Electric, using the SBB technology. However, all of these modules employ ceramic substrates. There aregreat demands to reduce the cost and weight of sub-note PCs. Though the cost and weight of an organic substrate are much cheaper andlighter than those of a ceramic substrate, however, almost no Flip Chip technology and organic substrate can satisfy the high performanceMPU operation. The newly developed high performance ALIVH substrate and the modified SBB technology can satisfy the performanceMPU operation. The weight of the ALIVH substrate is lighter than conventional glass-epoxy type, and also high density of wiring can beobtained. The modified SBB technology can achieve fine pitch interconnection, nevertheless the substrate was organic.The authors have successfully fabricated high performance Flip Chip MPU module for sub-note PCs using the MCM-ALIVH. In this MPUmodule, 4 LSI bare chips were mounted onto an 8 layered ALIVH substrate. The CPU had 359 I/O pins and the minimum pad pith was85microns. The clock frequency was 160 MHz. The weight of the MPU module was reduced to 40% of the conventional one. The obtainedelectrical characteristics were good enough for sub-note PCs. The SBB-ALIVH technology is very promising for MCMs to satisfy both highperformance and low cost.
Key words:
SBBTM technology, ALIVHTM, MCM (Multichip Module), and MPU(Micro Processor Unit).
1. Introduction
Recently, there is a great demand for an LSI packaging technol-ogy with high density and high performance. Therefore, the amountof MCMs is increasing radically. A Flip Chip bonding technology iseffective for the high density MCMs. A sub-note PC is one of theelectric appliances that need a Flip Chip bonding technology. AnMPU module in the sub-note PC is constituted of the LSI chips withhigh performance, fine pad pitch and high speed processing.
The researchers have already developed an advanced Flip Chipbonding technology, called Stud-Bump-Bonding (SBBTM) technol-
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ogy, by which bare LSI chips directly can be mounted onto ceram-ics (MCM-C)1. In the MCM-C, the MPU modules have been mass-produced using the SBB technology in Matsushita Electric Indus-trial Co., Ltd. since 1995. The SBB technology is explained in thenext section. However, there are great demands to reduce the costand weight of sub-note PCs. Though the cost and weight of organicsubstrate are much cheaper and lighter than those of a ceramic sub-strate, however, almost no Flip Chip technology and organic sub-strate can satisfy the performance MPU operation. The researchershave been studying that the LSI chips are mounted directly onto the“ALIVH TM”(Any Layer Inner Via Hole) substrate using the SBBtechnology2. The ALIVH substrate is one of organic substrates andit is a high density, high performance multilayered printed wiringboard. The MCM-ALIVH is fabricated using this SBB technologyand ALIVH substrate.
This time, the researchers have developed the SBB technologywith finer pitch inter-connections and newly developed ALIVH sub-strate has capability of forming a fine pattern and reliability for MCMsubstrates. As a result, the researchers successfully fabricated a highperformance Flip Chip MPU module for sub-note PCs using thisMCM-ALIVH, and the obtained electrical characteristics were goodenough for sub-note PCs.
2. SBB Technology
2.1. SBB Structure
Figure 1 shows the structure of the bonded portion by the SBBtechnology using Au bumps and the conductive adhesive. Au bumpsare formed by a newly developed technology which uses thewirebonding method. The Au bumps, called stud-bump, has two-stepped construction, so this conductive adhesive can be transferredcollectively only to the top of the Au bump. This restricts spread ofthe conductive adhesive when LSI chips are mounted on the elec-trode formed on substrates. The structure of the bonded portion iscomposed of the LSI pad, the Au bump, and the conductive adhe-sive. The LSI pad consists of Al and the terminal electrode of thesubstrate consists of Au plated Cu. Under the condition of imposedthermal stress, the conductive adhesive is deformed so that the ther-mal stress is relaxed, as a result the bonded portion is kept stable.
( LSI Chip )
Under-fill Resin Au Bump Al Pad
Conductive Adhesive
Electrode Terminal( Substrate )
Figure 1. The structure of the bonded portion by the SBBtechnology.
The epoxy under-fill resin is inserted to fill a gap between eachLSI chip and the substrate, to enhance structural stability and weatherresistance of the bonded portion. In addition, after curing the under-fill resin, not only a great adhesion is obtained, but also the connect-ing resistance is lowered by contacts of more conductive fillers pro-moted by contraction of the under-fill resin.
2.2. SBB Process
Figure 2 shows a schematic flow chart of the SBB mountingprocess. Au bumps having two-stepped construction formed ontoAl terminal pads on the LSI chip are pressed to have a uniform heightof 45µm±1µm. The pushing load for the levering is about 50 g/bump. After the conductive adhesive is transferred onto the top ofeach bump, the LSI chip is mounted onto the substrate. The mount-ing load for LSI chips is about 1 g/bump, causing no damage to thechips. After curing the conductive adhesive, if defective LSI chipsare found in the electrical inspection, they are repaired with the con-ductive adhesive in the curing state. The defective LSI chips can beeasily removed at room temperature, and can be replaced with newLSI chips without cleaning the electrode terminal of the substrate.The inspection and repairing techniques permit a remarkable increasein the yield of LSI chip mounting for the MCM with several LSIchips. Then, the gap between each LSI chip and the substrate isfilled with the epoxy under-fill resin, in order to complete the SBBprocess.
The features of the SBB technology are the following,· Advantageous to fine pitch interconnections.· High reliability.· Easy to manufacture.· Lead free.
ConductiveAdhesive
Re-placement
Bump Formation
Leveling Height
Transfer
Mounting
Inspection
Sealing
Curing
Final Inspection
Curing
LSI Chip Au Wire
Substrate
Figure 2. Flow chart of the SBB mounting.
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Flip Chip MPU Module Using High Performance Printed Circuit Board “ALIVH”
3. ALIVH 3,4
3.1. Structure
Figure 3 shows the structure comparison of the ALIVH substrateand the build-up substrate. For the ALIVH substrate, the base mate-rial made of epoxy impregnated non-woven aramid has a low di-electric constant, a smooth surface, a low CTE in plane and a lowerweight. Inner Via Hole (IVH) interconnection, that employs con-ductive pastes, is able to sit under the solder pad and between arbi-trary two layers. Therefore, packing density and wiring capabilityare greatly improved so that automatic design is made much easierand the design process takes less time to be completed. IVH formedby CO
2 laser processing has a cost advantage compared with con-
ventional drilled and electroplated through holes. Moreover, the pro-cess gives careful consideration to the environment, due to of plat-ing less technologies.
The ALIVH substrate has Any Layer Inner Via Hole structure,but on the other hand, for the build-up substrate, the IVH structurecannot be formed in the core and a through hole structure is formedin it. Therefore, wiring length of the circuit must be longer and thefast wiring design cannot be realized.
ALIVH Build-up
Structure
ir:insulation resin
Core
Figure 3. Structure comparison of the ALIVH substrateand the build-up substrate.
3.2. Comparison of ALIVH and Other Substrates
The properties of the ALIVH substrate and other substrates areshown in Table 1. Compared with build-up substrates, the lowerCTE and higher T
g lead to advantageous Flip Chip mounting. Com-
pared with ceramic substrates, the lower density leads to lightweightand the lower dielectric is suitable for high-speed signals.
Table 1. Properties of the ALIVH substrate and othersubstrates.
Substrate ALIVHBuild-Up
Ceramic
Dielectric constant(at1MHz)
C.T.E (ppm/ Å)
Tg (Å)
Density (g/cc)
(Core) (i/r)
4.1
8180
1.45
4.8
/
16 60
130 130-160
1.63
//
7.4
6565
3.98
Therefore, the ALIVH substrate is suitable for a module withhigh-speed processing and high density circuitry. Due to these rea-sons, the ALIVH substrate is highly satisfactory for the MPU mod-ule substrate in a sub-note PC.
4. MCM-ALIVH
4.1. Fine ALIVH
Figure 4 shows a combination structure of MCM-ALIVH andconventional ALIVH for a motherboard. Table 2 shows a designstandard for a conventional ALIVH for a motherboard and a fineALIVH for a module substrate. A fine ALIVH has capability offorming a finer pattern. Figure 5 shows photographs of printed wir-ing onto an MPU module substrate. The outer-layer line width isforty microns and the spacing width is forty-five microns.
Motherboard(ALIVH)
LSI Chips
Fine-ALIVH(for Module)
MCM-ALIVH
SBB Technology
Figure 4. Combination structure of MCM-ALIVH andconventional ALIVH for a motherboard .
Table 2. Design standard a conventional ALIVH for amotherboard and a fine ALIVH for a module substrate.
Laminates Non-Woven Aramid-Epoxy
Via Hole Size (µm) min.120
Via Land Size min. 250
Line / Space min. 50/50
ALIVH(for Mother-board)
Fine-ALIVH(for Module )
(µm)
(µm)
min.200
min. 400
min. 100/100
Figure 5. Photographs of printed wiring onto an MPUmodule substrate.
Top : (Ave.)38• mBottom : (Ave.)48• m
L/S=4
0/45•
m
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4.2. SBB Technology for Fine PitchInterconnection
The researchers have developed the modified SBB technologyin order to make fine pitch interconnections to fabricate the MCM-ALIVH.(1) Bump Formation
The forming small diameter of the Au stud bump is needed forfine pitch interconnections. Figure 6 shows a method of a Au studbump formation. An initial ball at the top of a Au wire is formedusing spark energy. The formation of a small initial ball is one of thekey technologies to form a Au stud bump for fine pitch interconnec-tions. To form a small initial ball, a fine Au wire is used and thespark energy level is regulated to low as much as possible. The ul-trasonic wave energy level is regulated in order to secure the neces-sary adhesion strength between a bump and a terminal pad withoutbreaking the shape of a bump. The pressure force of the bondingtool against the Au stud bump is regulated in order to secure thenecessary base height of a bump. The hole diameter of a bondingtool changes according to that of a Au wire. Figure 7 shows SEMphotographs of developed Au stud bumps. The pad pitch is 80 mi-crons.
Au Wire
Initial Ball
Hole Diameter
Au Stud Bump
Figure 6. Method of a Au stud bump formation.
Before leveling After leveling
Figure 7. SEM photographs of developed Au stud bumps.
(2) Conductive AdhesiveThe requirements for a conductive adhesive for fine pitch inter-
connections are as follows,
· Even if the bonding portion is deformed, the connecting resis-tance is kept stable.
· The height of the conductive adhesive on each Au stud bump iseven and sufficient.
It is difficult for a conventional conductive adhesive to satisfyboth requirements for fine-pitch interconnections, since the diam-eter of a Au stud bump becomes smaller.
The transformation is easy to occur in the organic substrates likeALIVH compared with the ceramic substrates. When this transfor-mation occurs around the electrode terminal connected to the Austud bump, it deforms the conductive adhesive too large and thecontacts of conductive fillers in it are obstructed. Especially, as com-pared with conductive fillers of a small size and large size, usingconductive fillers of a small size, the contact rate of conductive fill-ers is low and it is difficult to secure conductive passes as shown inFigure 8. Therefore, the connecting resistance becomes high. Onthe other hand, using conductive fillers of large size, the surface of aconductive adhesive becomes rough as shown in Figure 9. There-fore, the height of the conductive adhesive on each gold stud bumpis uneven. As a general consideration, the cohesive force is in pro-portion to a reciprocal of a filler diameter. Therefore, using conduc-tive fillers of small size, the height is higher.
Connectingresistance
No good (High connecting resistance )
Filler size Small Large
Good (Low connecting resistance )
Figure 8. Comparison of filler size in the conductiveadhesive (1).
Filler size Small Large
Height ofconductiveadhesive :h
Good(Even)
No good(Uneven)
h
Figure 9. Comparison of filler size in the conductiveadhesive (2).
The researchers carried out experiments using three types of con-ductive adhesive. Figure 10 shows the results. A developed conduc-tive adhesive satisfies both of the necessary connecting resistanceand the needed height.
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The authors measured the connecting resistance of the SBBbonded portions of each vehicle. The connecting resistance of thebonded portion making pairs of bumps at four corners and at thecenter of the LSI, in total 32 bumps making 16 pairs, was measuredby using the four probes method. In addition, the authors have mea-sured the insulation resistance between adjacent bumps.
As examples of the progress in these tests, Figure 13 shows thechange of the connecting resistance in the liquid to liquid thermalshock and Figure 14 shows the results of a temperature humiditystorage test. The researchers are continuing their evaluation usingadditional reliability tests.
1000 2000
100
200
Co
nnec
ting
Re
sist
anc
e /B
um
p(m
•)
Number of Cycles
Numbers of Measure points=16 Chips×32 points
(Measured by 4 probes method)
Condition: -55 to +125!
(Continued)
Figure 13. Liquid to liquid thermal shock test.
1000 2000
100
200
Time (hours)
Numbers of Measure points=16 Chips×32 points
(Measured by 4 probes method)
Condition: 85· ·85%Rh
(Continued)
Figure 14. Temperature humidity storage test.
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5.0 10.0
20
40
Con
nect
ing
Res
ista
nce/
Bum
p(m
•)
Average diameter of fillers (• ÿ )
5.0 10
7.5
10.0
Average diameter of fillers (• ÿ )
Height of conductive adhesiveConnecting resistance
measured by4 probes method
5.0
Hei
ght
(•
ÿ)
Developed
ConventionalDeveloped
Conventional
Figure 10. Results of experiments for conductive filler size.
(3) Under-fill ResinThe requirements for the under-fill resin for fine pitch intercon-
nection are as follows,· At the injection of the under-fill resin between the LSI chip and
the substrate, the under-fill resin flows into the narrow gap in a shorttime. After curing, the globular silicon dioxide fillers disperse ev-erywhere uniformly and air bubbles are not entrapped in the resin.
· Using the globular silicon dioxide fillers of smaller diameterthan that of a conventional one, it is easy to flow in a narrow gap ina short time and the fillers disperse everywhere uniformly as shownin Figure 11(a). On the other hand, in a conventional one, the fillerssink at the bottom as shown in Figure 11(b).
Figure 11. SEM photographs of cross-section views aroundthe bonding portion.
4.3. Results of Reliability Tests
The researchers are carrying out several reliability tests for 100microns pitch. In these tests, the test conditions are given in Table 3and the exterior view of a test vehicle is shown in Figure 12. Thepanel size of the substrate with 9 Flip Chip sites for a test vehicle is100 mm × 100 mm and the thickness is 0.8 mm. The size of one siteis 30 mm × 30 mm. The terminal electrode of the substrate consistsof Au plated Cu. The LSI chip for this test vehicle has 360 pads andcontinuity test pattern. The chip size is 10 mm × 10 mm and thethickness is 0.4 mm.
Table 3. Reliability test conditions.
Test Items Conditions
High temperature storage test 125 ·2,000 hours
Low temperature storage test -55 ·2,000hours
Temperature humidity storage test 85· ·85%Rh0 2,000 hours
Unsaturated pressurizedvapor bias applying
110· ·85%RhDC 5.5V
0 500hours
Liquid to liquid thermal shock test -55 to +125· 2,000cycles
m m
m
m m
m
°C
°C
°C
°C
85°C, 85% Rh
110°C, 85% Rh
Condition: 85°C 85% RH
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4.4. Fabrication of MPU module
Figure 15 shows an exterior view of a fabricated MPU modulefor sub-note PCs using MCM-ALIVH. In this MPU module, 4 LSIbare chips were mounted onto 8 layered ALIVH substrate. The prin-cipal specifications of the ALIVH substrate are shown in Table 4.The clock frequency is 160 MHz and the weight of this MPU mod-ule was reduced to 40% of the conventional one using the MCM-Ctechnology. The obtained electrical characteristics were good enoughfor sub-note PCs.
Figure 15. Exterior view of a fabricated MPU module forsub-note PCs.
Table 4. Principal specifications of the ALIVH substrate forMPU module.
MCM-ALIVH for CPU Module
Module Size ÿ 27×27mm
Number of layers ÿ 8
Line / Space ÿ 40/45• m
Via Land ÿ 350• m
5. Conclusion
The researchers have developed the SBB technology with finerpitch interconnections and newly developed ALIVH substrate thathas capability of forming a fine pattern and reliability for MCMsubstrates. As a result, they successfully fabricated a high perfor-mance Flip Chip MPU module for sub-note PCs using the MCM-
ALIVH and the obtained electrical characteristics were good enoughfor sub-note PCs. Therefore, the MCM-ALIVH is very promisingfor modules to satisfy both high performance and low cost. The re-searchers have confirmed the MCM-ALIVH will be one solutionfor the next generation MPU modules.
Many kinds of CPU chips will become the form of the area-arrayLSI chip in the near future and it is very difficult to fabricate a FlipChip module that is constituted of such an area-array LSI chip. Sincethe Al pads are formed on the active area in it, the electronic devicesin the active area are added damage by some forces at the Flip Chipmounting process and their characteristics are changed. The authorsbelieve the forces adding damage can be classified in the followingthree forces,
· The load force at the bump formation process.· The load force at the mounting LSI chip process.· The contraction force of the under-fill resin after curing. It the SBB mounting process, the load force at the mounting LSI
chip process is about 1g/bump and the contraction force is relievedby the flexibility of the conductive adhesive. These forces add nodamage to the electronic devices. However, according to the latestreport5, the load force at the bump formation process adds damageto them and changes their characteristics.
Therefore, the authors have developed “Cofired bump substrate”6.In this constitution, no damage occurs, since the bumps are formedonto the electrodes on the glass-ceramic substrate and the formingbumps onto Al pads is not needed. However, the MCM-ALIVH canrealize a high-performance, low-weight, and low-cost MCM parton a high level. Therefore, the researchers are studying how thechange of the characteristic of electronic devices occurs and theirobjectives to develop the MCM-ALIVH that can be applied to thearea-array LSI chips.
Acknowledgment
The authors would like to thank personnel computer divisionand Matsushita Techno Research Inc., and all other researchers whoparticipated in this study.
References
1. Y. Bessho, Y. Tomura, Y Hakotani and M. Tsukamoto, “Ad-vanced Stud-Bump-Bonding Technique for High DensityMCM”, Proceedings of 1993 Japanese IEMT Symposium, pp.362-365, June 1993.
2. T. Shiraishi, K. Amami, S. Yuhaku, Y. Bessho, K. Eda and T.Ishida, “Stud-Bump Bonding Technique Onto an AdvancedOrganic Substrate for MCM-Ls”, Proceedings of the 6th In-ternational Conference and Exhibition on Multichip Module,MCM ‘97, Denver, Colorado, pp. 109-114, April 1997.
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: 27mmx27mm
: 8
: 40µm/45µm
: 350µm
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Flip Chip MPU Module Using High Performance Printed Circuit Board “ALIVH”
3. T. Nishii, S. Nakamura, T. Takenaka and S. Nakatani, “Perfor-mance of Any Layer IVH structure Multi-layered Printed Wir-ing Board”, Proceedings of IEMT Symposium, Ohmiya, Ja-pan, pp. 93-96, December 1995.
4. Y. Hirano, K. Tsunio and S. Baba, “MCM for Portable Sub-note PCs”, Proceedings of the 11th JIPC Annual Meeting,Tokyo, Japan, pp. 27-28, March 1997.
5. N. Shimoyama, K. Machida, M. Shimaya and H. Akitani, “De-vice Degradation Induced by Stud Bumping Above the MOS-FETs” The 58th Japan Society of Applied Physics, ExtendedAbstracts, No. 2, Akita, Japan, pg. 745, October 1997.
6. M. Itagaki, N. Hase, S. Yuhaku, Y. Bessho and K. Eda, “ACofired Bump Bonding Technique for Chip-Scale-PackageFabrication Using Zero X-Y Shrinkage Low TemperatureCofired Ceramic Substrate”, Proceedings of the 1997 Interna-tional Symposium on Microelectronics, ISHM ‘97, Philadel-phia, Pennsylvania, pp. 685-690, October 1997.
About the authors
Mr. Shiraishi was born in Kagoshima,Japan, in 1961. He received the B.S.Degree in Electronics from KagoshimaUniversity, Japan and he joinedMatsushita Electronics Industrial Co.,Ltd. He developed the contact type lin-ear image sensor for a facsimile machinein Matsushita Electronic ComponentCo., Ltd. Since 1995, he has been en-gaged in the research and developmentof the Flip Chip mounting technologyfor Multichip Module (MCM) in thecurrent section.
Mr. Amami was born in Osaka, Ja-pan, in 1966. He received the B.S. De-gree in Applied Chemistry from WsaedaUniversity, Japan. Since joiningMatsushita Electric Industrial Co., Ltd.,he has been engaged in development ofmagnetic materials and currently he isdeveloping Flip Chip mounting technol-ogy for Multichip Module (MCM).
Mr. Fukuoka received the B.S. degree in control engineereingfrom Kyusyu Institute of Technology, Japan in 1978 and he joinedMatsushita Electric Industrial Co., Ltd. He had been developing theprinted circuit boards since 1978. He has been engaged in a man-ager for the expansion of fine ALIVH business in the current sec-tion.
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Mr. Bessho was born in Okayama,Japan, in 1960. He received the B.S. De-gree in Electrical Engineering fromOkayama University, Japan. Since join-ing Matsushita Electric Industrial Co.,Ltd., he has been engaged in develop-ment of Flip Chip mounting technologyfor Multichip Module (MCM).
Mr. Sakamoto was born inHiroshima, Japan, in 1958. He receivedthe M.S. Degree in Chemical Engineer-ing from Hiroshima University, Japan,in 1983 and he joined Matsushita Elec-tric Industrial Co., Ltd. He had been de-veloping the Magnetic Recording me-dia since 1983, he has been engaged inthe development of ALIVH substrate inthe current section.
Mr. Eda was born in Mie, Japan, in1946. He received the B.S. and M.S.Degrees in Electronics from NagoyaUniversity, Nagoya, Japan, in 1969 and1971, respectively. He received the Ph.D. Degree in Electronics from KyotoUniversity, Kyoto, Japan, in 1980. Hejoined the Wireless Research Laboratoryof the Matsushita Electric IndustrialCompany, Ltd., Kadoma, Osaka, Japan,in 1971, where he did research and de-velopment work on electronic ceramic
devices. From 1983 to 1984, he was a visiting scholar with the Uni-versity of California, Santa Barbara. Since 1985, he has been en-gaged in the research and development of high frequency devices,ceramic devices and packaging technologies.
Mr. Ishida was born in Ishikawa, Ja-pan, in 1944. He received the M.S. de-gree in chemical engineering fromTohoku University, Japan. Since joingMatsushita Electric Industrail Co., Ltd.,he did research and development workon LED devices of II-IV compoundsemiconductor, metal silicide resistors,capacitor type pressure sensors and theCu wiring multi-layered ceramic sub-strates. Presently he leads Devices En-gineering Development Center includ-
ing devices for telecommunication, sensor devices, packaging tech-nology and ceramic materials and process. He is a member of theAmerican Ceramic Society.
