Presentation on circuit design Presentation on circuit design flip flopflip flop

CONTENTSCONTENTS

INTRODUCTION CIRCUIT DIAGRAM CONVENTIONAL CMOS FLIP-FLOPS RESETTABLE FLIP-FLOPS ENABLED FLIP-FLOPS DIFFERENTIAL FLIP-FLOPS TRUE SINGLE PHASE CLK FLIP-FLOPS (TSPC) ADVANTAGES DISADVANTAGES

INTRODUCTIONINTRODUCTION

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described assequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.

CONVENTIONAL CMOS FLIP-FLOPSCONVENTIONAL CMOS FLIP-FLOPS

Flip flops usually take a single clock signal Q and logically generate its complement Q. If the clock rise/fall time is very slow; it is possible that both the clock and its complement will simultaneously be at intermediate period voltage making both transparent and increasing the flip flop hold time. In ASIC stander cell libraries, the clock is both complemented and buffered in the flip flop cell to sharpen up the edge rates at the expense of more inverters and clock loading.

Recall that the flip flop also has a potential internal race condition between the two latches.

The turni9ng on the clock PMOS transistors in both transmission gates. If the skew is too large, the data can sneak through both latches on the falling clock edge.

CMOS technology allows a very different approach to flip-flop design and construction. Instead of using logic gates to connect the clock signal to the master and slave sections of the flip-flop, a CMOS flip-flop uses transmission gates to control the data connections. (See the CMOS gate electronics page for a closer look at the transmission gate itself.)

The result is that a controllable flip-flop can be built with only inverters and transmission gates — a very small and simple structure for an IC.

CIRCUIT DIAGRAM OF CONVENTIONAL CMOS FLIP-CIRCUIT DIAGRAM OF CONVENTIONAL CMOS FLIP-FLOPSFLOPS

Resetteble flip flopsResetteble flip flops

Most practicle sequencing elements require a reset signal to enter a known initial state on startup flip flop with resert inputs.

There are two types of reset synchronous and asynchronous. Asynchronous reset forces low immediately, while synchronous reset waits for the

clock. Synchronous resett signals must be stable for setup and the clock edge while a

synchronous reset is characterized by a propagation delay from the reset output.. Synchronous reset simply requires ANDing the input and reset Asynchronous require getting both the data and the feedback to force the reset

independent of the clock. The trstate NAND gate can be constructed from an NAND gate in series with

clocked transmission gate.

Circuit diagram of Resetteble flip flopsCircuit diagram of Resetteble flip flops

ENABLED FLIP-FLOPSENABLED FLIP-FLOPS

Sequencing element also often except an enable input.

When enable is low, the element retain its state independently of the clock.

The input multiplexer feeds back to the old stage then the element is disabled.

Clock getting does not affect delay from the data and the and gate can be shared among multiple clocked elements

Circuit Diagram of ENABLED FLIP-FLOPSCircuit Diagram of ENABLED FLIP-FLOPS

DIFFERENTIAL FLIP-FLOPSDIFFERENTIAL FLIP-FLOPS

Differential flip flops true and complementary inputs and produce true and complementary outputs.

They are built from a clocked sense amplifier so they can rapidly respond to small differential input voltages, while they are larger then an ordinary single ended flip flops having an extra inverter to produce the complementary output.

They work well with low swing inputs such as register file bit lines and low swings busses.

Differential sense amplifier flip flop receiving differential inputs and producing a differential output.

CIRCUIT DESIGN OF DIFFERENTIAL FLIP-FLOPSCIRCUIT DESIGN OF DIFFERENTIAL FLIP-FLOPS

TRUE SINGLE PHASE CLOCK FLIP-FLOPS (TSPC)TRUE SINGLE PHASE CLOCK FLIP-FLOPS (TSPC)

ADVANTAGES OF CIRCUIT DESIGN FLIP FLOPSADVANTAGES OF CIRCUIT DESIGN FLIP FLOPS

The main advantage of flip flop is that it have a circuit inside it contain gates and can generate specific output, it make a complex circuit much simpler.

It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states.

DISADVANTAGES OF FLIP FLOPSDISADVANTAGES OF FLIP FLOPS

The primary disadvantages of flip flop is their reacting time between the input signal and resultant Output if the signal changes between this reaction time the flip flops.

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