Flow DW

Encounter Design Flow Guide and Tutorial

Product Version 3.2September 2003

2003 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.

Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA

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discontinued immediately upon written notice from Cadence.

Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadences customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information.

Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

August 29, 2003

Encounter Design Flow Guide and TutorialAbout This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Online Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

BuildGates/Physically Knowledgeable Synthesis Commands . . . . . . . . . . . . . . . . . . . 7Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Conventions Used in This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Design Flow Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Flow Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Tcl Script Examples and Linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2Logical Synthesis and Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . 19Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3

ContentsSeptember 2003 3 Product Version 3.2

Silicon Virtual Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Encounter Design Flow Guide and TutorialOutputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4Hierarchical Floorplan Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36


Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5Block Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44


Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Timing Closure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6Top-Level Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53September 2003 4 Product Version 3.2

Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Encounter Design Flow Guide and TutorialAdditional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Timing Closure Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7Chip Assembly and Sign-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60


Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8Chip Finishing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66


Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

9Sub Flows: PKS Physical Optimization, Timing/SI Closure . 71Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72PKS Physical Optimization Sub Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Steps: PKS Physical Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Timing/SI Closure Sub Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Steps: Timing Analysis/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76September 2003 5 Product Version 3.2

Encounter Design Flow Guide and TutorialATerminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

BList of Tcl Script Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

CTcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Logical Synthesis and Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Silicon Virtual Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Hierarchical Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Block Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Top-Level Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Chip Assembly / Sign-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168Chip Finishing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176Miscellaneous Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

CTS File Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

DTiming Closure Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184Preplacement Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184Floorplanning/Initial Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Routability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187Useful Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189Critical Path Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193Example Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197September 2003 6 Product Version 3.2

Encounter Design Flow Guide and TutorialAbout This Manual

This manual can be used in two ways:

Basic Flow GuideShows a design flow that highlights the capabilities of the Encounter product. It describes the tasks needed to complete a hierarchical design, starting from a gate-level netlist and ending with a file in GDSII stream mask data format using hierarchy and manual budgeting.

TutorialAnnotated Tcl scripts link directly from the flow steps, providing a tutorial-like resource for learning the Encounter tool.

Online UseThis manual is designed to be used online (HTML). Text and graphic hyperlinks provide direct access to relevant information in the Encounter User Guide and Encounter Text Command Reference. Links to the user guide are from the flow steps; links to the command reference are from the Tcl scripts.

BuildGates/Physically Knowledgeable Synthesis Commands

In addition to the Encounter commands, Appendix D, Timing Closure Strategies, contains BuildGates and Cadence Physically Knowledgeable Synthesis (BG/PKS) commands. These commands can usually be distinguished from Encounter commands by the use of the underscore character (for example, do_optimize). These commands are hyperlinked to the Command Reference for BuildGates Synthesis and Cadence PKS.

AudienceThis manual is written for experienced designers of digital integrated circuits. Such designers must be familiar with design planning, placement and routing, block implementation, chip assembly, and design verification. Designers must also have a solid understanding of UNIX and Tcl/Tk programming.September 2003 7 Product Version 3.2


About This Manual

Chapter SummaryThis manual is organized into the following chapters and appendixes:

Chapter 1, Introduction

Introduction to the document.

Chapter 2, Logical Synthesis and Scan Insertion

Synthesize the design and insert scan chains. Can be performed with BuildGates/PKS or Design Compiler.

Chapter 3, Silicon Virtual Prototyping

Determine the feasibility of the netlist, floorplan, and constraints.

Chapter 4, Hierarchical Floorplan Generation

Defines the top-level floorplan and blocks within that floorplan that you implement separately.

Chapter 5, Block Implementation

Creates physical implementations of the blocks you defined when you generated the hierarchical floorplan.

Chapter 6, Top-Level Implementation

Run placement and in-place optimization, and route the design at the top-level you defined in hierarchical floorplanning.

Chapter 7, Chip Assembly and Sign-Off

Flatten the design and perform final analysis.

Chapter 8, Chip Finishing

Create physical layouts of the data you have created, perform final verification, and prepare the design for tapeout.

Chapter 9, Sub Flows: PKS Physical Optimization, Timing/SI Closure

Description of sub flows.

Appendix A, Terminology

Terms used in the Encounter flow.September 2003 8 Product Version 3.2

Appendix B, List of Tcl Script Examples


About This Manual

List of all Tcl script examples.

Appendix C, Tcl Scripts

Tcl script examples relating to flow procedures.

Appendix D, Timing Closure Strategies

Possible solutions for timing closure issues.

Conventions Used in This ManualThis section describes the typographic and syntax conventions used in this manual.

text Indicates text that you must type exactly as shown. For example:analyze_connectivity -analyze all

text Indicates information for which you must substitute a name or value. In the following example, you must substitute the name of a specific file for configfile:wroute filename configfile

text Indicates the following:

Text found in the graphical user interface (GUI), including form names, button labels, and field names

Terms that are new to the manual, are the subject of discussion, or need special emphasis

Titles of manuals[ ] Indicates optional arguments.

In the following example, you can specify none, one, or both of the bracketed arguments:command [-arg1] [arg2 value]September 2003 9 Product Version 3.2


About This Manual

[ | ] Indicates an optional choice from a mutually exclusive list.In the following example, you can specify any of the arguments or none of the arguments, but you cannot specify more than one:command [arg1 | arg2 | arg3 | arg4]

{ | } Indicates a required choice from a mutually exclusive list. In the following example, you must specify one, and only one, of the arguments:command {arg1 | arg2 | arg3}

{ } Indicates curly braces that must be entered with the command syntax.In the following example, you must type the curly braces:command arg1 {x y}

... Indicates that you can repeat the previous argument.

.

.

.

Indicates an omission in an example of computer output or input.

Command Subcommand Indicates a command sequence, which shows the order in which you choose commands and subcommands from the GUI menu.In the following example, you choose Floorplan from the menu, then Power Planning from the submenu, and then Add Rings from the displayed list: Floorplan Power Planning Add RingsThis sequence opens the Add Rings form.September 2003 10 Product Version 3.2


About This Manual

Related DocumentsFor more information about the Encounter family and other related products and tools, consult the following Cadence documents. You can access these and other documents with the CDSDoc online documentation system.

Encounter User Guide

Encounter Text Command Reference

Encounter Known Problems and Solutions

Whats New in Encounter

NanoRoute Ultra Reference

PKS User Guide

Command Reference for BuildGates Synthesis and Cadence PKS

The following books are helpful references.

IEEE 1364 Verilog HDL LRM

TCL Reference, Tcl and the Tk Toolkit, John K. Ousterhout, Addison-Wesley Publishing Company

For a complete list of documents provided with this release, see the CDSDoc library.

TrainingIn addition to this documentation, courses on the Encounter family of products are available from Education Services at Cadence.September 2003 11 Product Version 3.2


About This ManualSeptember 2003 12 Product Version 3.2

Encounter Design Flow Guide and Tutorial1Introduction

This chapter provides an overview of the main flow procedures and also lists the assumptions you should be aware of before you start this flow.

Overview on page 14

Design Flow Procedures on page 15

Flow Assumptions on page 17

Tcl Script Examples and Linking on page 18September 2003 13 Product Version 3.2


Introduction

OverviewThe Encounter platform is a hierarchical physical implementation environment leveraging the capabilities of First Encounter for floorplanning, feasibility analysis, placement, and clock tree insertion along with the power of NanoRoute for SI aware routing; CeltIC for SI analysis; VoltageStorm for IR drop analysis; PKS for logic restructuring and complex optimizations; and Fire & Ice QX for sign-ff quality extraction.

The Encounter product is comprised of the following tools:

First EncounterVirtual prototyping, feasibility analysis, placement, clock tree insertion, GDSII generation

NanoRouteFast, high-capacity, signal integrity (SI) and timing-aware routing CeltICSign-off quality SI analysis

PKSComplex optimizations which require logic restructuring

The following tools interface with Encounter. They require separate licenses.

Fire & Ice QXSign-off quality parasitic extraction VoltageStormIR drop analysis

Design Entry

Logic Synthesis andScan Insertion(BuildGates)

Hierarchical Virtual Prototyping and Physical Implementation

Environment(Encounter)

Chip Finishing(VCE)

RTL Design DataInitial Constraints

Optimized NetlistMapped Constraints

Final NetlistRouted DatabaseSeptember 2003 14 Product Version 3.2


Introduction

Design Flow ProceduresThe Encounter design flow from RTL to GDSII consists of the following procedures. Each procedure contains a series of flow steps.

Logical Synthesis and Scan InsertionSynthesize the design and insert scan chains. Can be performed with Cadence BuildGates/PKS or Synopsys Design Compiler.

For more information, see Chapter 2, Logical Synthesis and Scan Insertion.

Virtual PrototypingDetermine the feasibility of the netlist, floorplan, and constraints.

For more information, see Chapter 3, Silicon Virtual Prototyping.

Hierarchical Floorplan GenerationDefine the top-level floorplan and blocks within that floorplan that you implement separately.

Hierarchical Floorplan Generation

Silicon Virtual Prototyping

Top-Level Implementation

Chip Assembly and Sign-Off

Chip Finishing

Logical Synthesis and Scan Insertion

Detailed Block Implementation

Design EntrySeptember 2003 15 Product Version 3.2

For more information, see Chapter 4, Hierarchical Floorplan Generation.


Introduction

Block ImplementationCreates physical implementations of the blocks you defined when you generated the hierarchical floorplan.

For more information, see Chapter 5, Block Implementation.

Top-Level ImplementationRun placement and in-place optimization, and route the design at the top-level you defined in hierarchical floorplanning.

For more information, see Chapter 6, Top-Level Implementation.

Chip Assembly and Sign-OffFlatten the design and perform final analysis.

For more information, see Chapter 7, Chip Assembly and Sign-Off

Chip FinishingCreate physical layouts of the data you have created, perform final verification, and prepare the design for tapeout.

For more information, see Chapter 8, Chip Finishing.

TerminologyAppendix of terms used in the flow.

For more information, see Appendix A, Terminology.

Tcl ScriptsTcl scripts relating to flow procedures.

For more information, see Appendix C, Tcl Scripts.

List of Tcl Script ExamplesList of all Tcl script examples.

For more information, see Appendix B, List of Tcl Script Examples.

Timing Closure StrategiesSolutions for timing issues related to the flow.

For more information, see Appendix D, Timing Closure Strategies.September 2003 16 Product Version 3.2


Introduction

Flow Assumptions1. The following library formats are used:

Timing LibrariesTLF

Timing ConstraintsSDC (Synopsys Design Constraints) Standard Cell and Macro Library DescriptionsLEF 5.5 unless otherwise indicated

(for example, the Fire & Ice QX interface in Tcl scripts). The cdump format is no longer required and has been replaced by an all LEF-based flow.

Design Floorplan descriptionsFloorplan file and DEF 5.5 unless otherwise indicated (for example, the Fire & Ice QX interface in Tcl scripts).

2. The flow assumes that both Fire & Ice QX and VoltageStorm are available for sign-off quality extraction and IR/EM analysis.

3. The flow as depicted uses channel-based routing only. No over-the-block routing is shown although the tool can support both abutted-block and feedthrough-based methodologies.

4. The clocking methodology is based on clock trees. Other methodologies can be supported with slight modifications to the flow.September 2003 17 Product Version 3.2


Introduction

Tcl Script Examples and LinkingThe Tcl script examples in this guide are designed to be used as a tutorial-like resource for learning the Encounter tool (see Appendix C, Tcl Scripts). The scripts map (link) directly from the flow steps and are annotated with information and links to the commands in the Encounter Text Command Reference.

ImportantThe Tcl scripts are for instructional purposes only. They contain links to the Encounter Text Command Reference, where more information on using the Encounter tool is available. These scripts are for reference only and are not meant to be run standalone.September 2003 18 Product Version 3.2

Encounter Design Flow Guide and Tutorial2Logical Synthesis and Scan Insertion

This chapter describes the logical synthesis and scan insertion flow.

Overview on page 20

Flow on page 21

Steps on page 22

Additional Information on page 23September 2003 19 Product Version 3.2



OverviewThis flow can be performed with Cadence BuildGates/PKS or Synopsys Design Compiler. The BG/PKS flow is documented here.

This flow begins with Cadence RTL Compiler (RC) to optimize and map the netlist. Subsequent passes through this flow can make use of custom wireload models or even floorplan data if PKS is used for preplacement optimization.

Inputs RTL design data

Timing constraints

Outputs Optimized netlist

Mapped constraintsSeptember 2003 20 Product Version 3.2



Flow

JTAG/ BIST Generation on page 22JTAG/BIST Generation

BG/PKS

Third Party

Hierarchical Physical Implementation

Go to Silicon Virtual Prototyping on page 25

RTL Constraints

Netlist MappedConstraints

FloorplanCustom WLM

Design-For-Test Configuration

Scan Insertion

Preplacement Optimization

Scan DEF Generation*

Netlist Generation

Constraint Generation

1

3

4

5

6

8

7

2

Virtual PrototypingHierarchical Floorplanning

Block ImplementationTop-Level ImplementationChip Assembly / Sign-Off

Chip Finishing

Logic Synthesis

Optimize and Map Netlist

RC

* Scan DEF Note

Optmize/Map NetlistSeptember 2003 21 Product Version 3.2



Steps

ImportantThese steps require the use of the BuildGates/Physically Knowledgeable Synthesis (BG/PKS) synthesis tool. The detailed flow for logical synthesis and scan insertion is described in the BG/PKS documentation (see the PKS User Guide).

1. Optimize and Map Netlist

Use RTL Compiler (RC) to optimize and map the netlist. RTL Compiler is a next-generation synthesis solution for multi-million gate chip design.

2. DFT Configuration

Test synthesis is performed prior to and during optimization. All flip-flops that pass the DFT rule checks are mapped to their scan-equivalent flops for creation of the scan chain configuration during optimization.

3. Scan Insertion

When the top-level scan chains are created by scan insertion, the tool will generate a scan order file (SOF). This file lists the top-level scan chains and depicts how the scan flops are connected along each of the chains.

4. Preplacement Optimization

Preplacement optimization runs and controls various optimization processes before place-and-route to produce a desired netlist. Subsequent passes can make use of custom wireload models or floorplan data if PKS is used for preplacement optimization.

5. Scan DEF Generation

The Scan DEF file (scanDEF) is a sub-section of the Cadence-developed DEF file format (text based) used to describe the scan chain configuration (architecture) and the set of reorderable scan chains present in the scan-mapped netlist.

6. JTAG/ BIST Generation

JTAG/BIST generation is performed with third party tools.

7. Netlist Generation

A Verilog netlist is generated.

8. Constraint GenerationSeptember 2003 22 Product Version 3.2

The synthesis constraints are applied to the resulting netlist.



Additional Information

Tcl Scripts

See Logical Synthesis and Scan Insertion on page 87.September 2003 23 Product Version 3.2


Logical Synthesis and Scan InsertionSeptember 2003 24 Product Version 3.2

Encounter Design Flow Guide and Tutorial3Silicon Virtual Prototyping

This chapter describes the Silicon Virtual Prototyping flow.

Overview on page 26

Flow on page 27

Steps on page 28




OverviewSilicon Virtual Protyping is used to determine the feasibility of the netlist, floorplan, and constraints. The design is placed, buffered, routed, extracted, and timed. Clock trees can be optionally inserted and scan chains can be reordered. Candidate floorplans with fences along with the timing and clock constraints are carried forward to the Hierarchical Floorplanning Generation Flow procedure.

Inputs Netlist

Timing and clock constraints

Additional inputs such as the scan DEF, pad placement information, and vendor floorplan information are design, flow and vendor specific.

Outputs Prototype floorplan with fences

Timing and clock constraintsSeptember 2003 26 Product Version 3.2



Flow

VP:

JTAG Placement

I/O, P/G Placement | Flip Chip

CTE Timing Analysis*(no net loading)

Amoeba Placement***

Scan Chain Reordering

Power Planning(rings and stripes)

IPO

Generate Floorplan File

T-Route / Extract / TA

Power Analysis

From Logical Synthesis and Scan Insertion on page 19

Timing/Clk Constraints

Floorplan w/Fences

VendorFloorplan

I/O Placement

Netlist*

1

2

3

5

7

9

10

11

8

12

13

14

15

Specify/Refine Floorplan- Module guides- Fences (shaping/sizing)- Blockages (place/routing)- Assign block locations- Power plan

Clock Tree Synthesis

6

Timing Issues

Power Issues

Timing Issues

Routability or Timing Issues

Timing/Clk Constraints

* Empty modules treated as blackboxes

** Place top-level modules and blackboxes (used in all-block designs)

Clock Issues

VP:

VP:

VP

VP:

VP:

VP:

VP:

Tcl

Tcl

Tcl

Tcl

Tcl

Tcl

Tcl

Tcl

VP:

VP:

VP:

VP:

Tcl

Tcl

Tcl

VP:

VP:

Tcl

Tcl

Tcl

VPVPVP

TclTclTcl

VPTcl



Chip Finishing

Logic Synthesis



*** Depending on design size, may use FP mode or clusteringPlace for increased capacity

Block Placement**(top modules and blackboxes)

4September 2003 27 Product Version 3.2

To Hierarchical Floorplan Generation on page 35



StepsTo create a virtual prototype, complete the following steps:

1. Run timing analysis.

Analyze timing with the CTE (Common Timing Engine) using no net loading to determine whether the initial design meets timing requirements.

User Guide: See Timing: Timing Analysis.

Tcl Script: VP: CTE Timing Analysis (no net loading) on page 88.2. Place I/O pads, and power and ground pads.

During this step you have the option of reading a file that contains preplaced pad coordinates or ordering information. With a fixed die size, absolute coordinates can be used to determine the design size. Power and ground pads must be included in the I/O file. They are a prerequisite for creating the power plan and determining the amount of power available to the design.

User Guide: See Place.

Tcl Script: VP: Load Floorplan (Place I/Os) on page 89.Note: To use the flip chip methodology for placing bumps, see the Flip Chip chapter in the Encounter User Guide. Flip chip and area I/O are used synonymously in the Encounter documentation.

3. Place JTAG cells.

Specify and place JTAG cells to be near the I/O cells. These structures stay in place when you run automatic tools.


Tcl Script: VP: JTAG Placement on page 89.

4. Place blocks.

Place top-level modules and blackboxes.

Note: This step is used in an all-block designs.

5. Specify and refine the floorplan.

Tcl Script: VP: Critical Block Placement on page 90.September 2003 28 Product Version 3.2

Add, delete, or modify the following:



Module guides

Define the initial placement guides for key modules. Guides tell the placer to place a specific modules cells near the guides location. Alternatively, fences can be used.

User Guide: See Floorplan: Basic Floorplanning.

Tcl Script: VP: Generate Floorplan Guides on page 94.

Fences (shaping/sizing)Refine the shape and size of fences to align the fences manually, using relative placement to preserve relationships between fences and keep fenced areas in specific locations. Correct the aspect ratio and size of the fenced areas.

Alternatively, you can run the automatic block placer.

The goal of this step is to make sure that when blocks are committed later in the process, you can successfully implement the blocks individually, and the design as a whole.

User Guide: See Partition.

Tcl Script: VP: Floorplan Refinement with Fences on page 97.

Blockages (place/routing)Add placement or routing blockages to clear routing channels in congested areas. For example, if there is heavy congestion around the corner of a block, add a placement blockage or density screen to relieve the congestion in that area.

Tcl Script: VP: Add Blockages if Necessary on page 95.

Assign block locations

Adjust block placement either manually or via block refinement. You can use the automatic floorplanning capability to adjust the core size and generate module or hard macro locations.

Tcl Script: VP: Critical Block Placement on page 90.

Power plan

Define the power rings and power stripes. The power plan can be saved to a file once a satisfactory initial structure has been obtained. Typically, you do this step only if you use a predefined power structure in the design. If necessary for the design, define multiple supply voltage domains (MSV).September 2003 29 Product Version 3.2

User Guide: See Floorplan: Power Planning.



Tcl Scripts:

VP: MSV Definition on page 90

VP: Initial Power Planning on page 91

6. Run Amoeba placement.

Use the Amoeba placer to place cells in the flat design. The placer places cells according to module guide and fence constraints. Depending on the design size, use floorplan mode or clustering for increased capacity.


Tcl Script: VP: Amoeba Placement on page 93.

7. Reorder scan chains.

Refine the initial scan chain order based on Amoeba placement results. Although changes made at this step are not used after you finish the initial floorplan, this step is still recommended in order to reduce wire length so that a more accurate analysis of congestion can be done.


Tcl Script: VP: Scan Reorder on page 93.

8. Do power planning.

Comment: Where did the scan chian reorder come from? Defining the power plan doesn't necessitate a re-placement. Let's review Kevin's scripts to see if they match the flow as specified. We may have to adjust one or the other.

Define the power rings and power stripes. Refine the initial scan chain order based on the most recent Amoeba placement results.

Tcl Script: VP: Generate Floorplan Guides on page 94.

9. Run trial routing, extract parasitics, and analyze timing.

Comment: Trial Route

Route the design using the trial router. If the congestion is acceptable, extract parasitics. If congestion is unacceptable, adjust module guides, re-place critical blocks and cells, or refine I/O and power and ground pads, as necessary. Examine the congestion map and congestion report to identify congested areas. After examining the congestion map, either create a placement blockage or a placement September 2003 30 Product Version 3.2

density screen.



User Guide: See Route: Trial Route.

Tcl Scripts:

VP: TrialRoute on page 95

VP: Add Blockages if Necessary on page 95

Extract parasitic resistance and capacitance (RC) values to calculate delays based on the wire lengths determined by trial routing.

User Guide: See Timing: RC Extraction.

Tcl Script: VP: Extract Parasitics on page 96.

Analyze timing to find timing violations. At this stage, timing might have violations however, useful information can still be obtained, such as the magnitude of errors or which net paths are failing. If the floorplan seems reasonable, run in-place optimization(IPO). Analyze timing again after IPO to determine how to alter the floorplan.


Tcl Script: VP: Timing Analysis on page 96.

10. Define clock tree constraints and synthesize the clock tree.

Define clock tree constraints such as insertion delay and slew limits.

User Guide: See Clock.

Synthesize the clock tree. Analyze the clock tree reports to determine if constraints have been met. As before, netlist changes are not passed forward. The clock tree is generated to determine area and timing issues with the current floorplan.

Tcl Scripts:

VP: Clock Tree Synthesis on page 98

MI: CTS File on page 177


Route the design using the trial router.


Tcl Script: VP: Trial Route/Extract on page 99.September 2003 31 Product Version 3.2

Perform parasitic extraction to determine net RCs.




Tcl Script: VP: Trial Route/Extract on page 99.

Analyze timing to determine whether the initial design meets timing requirements. If it does not, then re-place the module guides.


Tcl Script: VP: Timing Analysis on page 99.

12. Run in-place optimization (IPO).Run IPO, which adds buffer cells, resizes gates and fixes design rule violations. Although netlist changes made at this stage are not kept, IPO is necessary to assess potential timing issues with the current floorplan.

User Guide: See Timing: Optimization.

Tcl Script: VP: IPO on page 99.


Route the design using the trial router.


Perform parasitic extraction to determine net RCs.


Tcl Script: VP: Extract/Timing Analysis on page 100.

Analyze timing to determine whether the initial design meets timing requirements.


Tcl Script: VP: Extract/Timing Analysis on page 100.

If timing issues remain after several floorplan iterations, you might need to change the logical netlist. If no satisfactory floorplans can be found, it may be necessary to alter the RTL of the design.

14. Analyze power.

Do the complete flat power analysis using native mode. Note that the power plan will be refined in the next procedure.

User Guide: See Route: SRoute and Power.September 2003 32 Product Version 3.2

Tcl Script: VP: Power Analysis on page 100.



15. Generate floorplan.

Generate and save the floorplan file to pass to Hierarchical Floorplan Generation on page 35.

User Guide: See Floorplan; Basic Floorplanning.

Tcl Script: VP: Save Floorplan on page 101.September 2003 33 Product Version 3.2




Tcl Scripts

See Silicon Virtual Prototyping on page 88.September 2003 34 Product Version 3.2

Encounter Design Flow Guide and Tutorial4Hierarchical Floorplan Generation

This chapter describes how to create a hierarchical floorplan.

Overview on page 36

Flow on page 37

Steps on page 38




OverviewThis chapter describes how to create a hierarchical floorplan from a flat floorplan based on the fenced modules. Blocks are generated that are implemented separately, and a top-level floorplan is created that contains physical and timing block abstractions.

Inputs Initial netlist

Clock and timing constraints

Fenced floorplan

Outputs


Block abstracts

Block timing models

Top-level netlist

Top-level block placement

Timing constraints for the top level

Block Implementation

Block netlist

Block floorplan and placement information

Block budgeted constraints

Boundary voltagesSeptember 2003 36 Product Version 3.2



Flow

1

2

3

4

5

6

8

9

7


IPO

Generate LEF Abstracts

GenerateTLF/STAMP

Optimize Pins

Timing Budget Save Partitions

Commit Partitions

Push Down

Top-Level Netlist

Floorplan/ Placement

Block LEF(s) Block TLFsor Stamps

Block Netlist Budgeted Constraints



Amoeba Placement

Power Routing

Power AnalysisPower

Problems

TimingProblems

TimingProblems

Congestionor

Floorplan/Placement

BoundaryVoltages

Silicon Virtual Protyping

To Block Implementation on page 43

From Silicon Virtual Prototyping on page 25

Initial Netlist

Clk/TimingConstraints

Floorplan w/Fences

Define Physical Partition HF:

HF:

HF:

HF:

HF:

HF:

HF:

HF:

Tcl

Tcl

Tcl

Tcl

Tcl

Tcl

Tcl

Tcl

HF: Tcl

FR: Tcl



Chip Finishing

Logic Synthesis

T-Route* / Extract / TA*Use honorPartitions optionSeptember 2003 37 Product Version 3.2

To Top-Level Implementation on page 51



StepsTo create a hierarchical floorplan, complete the following steps:

1. Define the physical partitions.

Change fences to partitions and cut partitions for rectilinear partitions. Place the JTAG cells.


Tcl Scripts:

HF: Specifify Physical Partitions on page 103

HF: Place JTAG on page 103


Run timing-driven Amoeba placement based on the partitions you defined.


Tcl Script: HF: Amoeba Place on page 103.


Route signals based on partitions and examine the congestion map.

If congestion is acceptable, extract parasitics.

If congestion is unacceptable, refine the floorplan.


Tcl Script: HF: Trial Route/Extract/Timing Analysis on page 104.

Extract parasitic RC values to calculate delays based on the wire lengths determined by trial routing. Do extraction in detailed mode for budgeting.



Analyze timing to determine whether the floorplan based on the partitions you chose meets timing constraints.

If timing constraints are not met, go back and refine the floorplan.September 2003 38 Product Version 3.2

If timing constraints are met and congestion is acceptable, commit the partitions.





4. Run in-place optimization (IPO).In order to create the best budgets for the blocks, the design is run through IPO to optimize the timing. The -neverAddPort IPO option should be used to avoid changes to the block port lists (no new module ports).User Guide: See Timing: IPO.

Tcl Script: HF: IPO (no new module ports) on page 104.5. Run trial routing, extract parasitics, and analyze timing.

The design is routed using the -honorPartitions option, then extracted and timed again.

User Guide: See Route: Trial Route, Timing: RC Extraction, and Timing: Timing Analysis.

Tcl Script: FR: Trial Route/Extract/Timing Analysis on page 105.

6. Route power.

Route the power then do a power analysis (next step).User Guide: See SRoute.

Tcl Script: HF: Power Route on page 105.

7. Analyze power.

Power analysis must be done prior to partitioning so that power budgets can be created for the partitions.

User Guide: See Power.

Tcl Script: HF: Power Analysis on page 106.

8. Commit partitions.

Make a final decision on the partitions to implement as separate blocks. The tool automatically does the following:

Optimizes pins

For each block, the pin optimization places pins along the edges of the block. The September 2003 39 Product Version 3.2

pin optimizer uses trial routing to determine pin placement.



Creates the timing budget

The tool distributes timing delays, assigning arrival and departure times to each partition port based on an analysis of the logic inside the partition, the logic it connects to externally, and the top-level timing constraints for the design.

Pushes power into blocks

The tool pushes stripes and rings down into the blocks. The blocks inherit the power structure from the top-level floorplan.


Tcl Script: HF: Commit Partitions on page 107.

9. Save partitions.

When the partitions are saved, a directory for each block is created and its netlist, floorplan, and budgeted constraints are saved in the directory. The cell placements within the partitions can optionally be saved as well.

A directory is also created for the partitioned top level and the top-level netlist, floorplan, and updated constraints are saved into it. In addition, a simple timing model and physical abstract to represent each block is stored in the top-level directory.


Tcl Script: HF: Save Partitions on page 107.September 2003 40 Product Version 3.2




Tcl Scripts

See Hierarchical Floorplanning on page 102.September 2003 41 Product Version 3.2


Hierarchical Floorplan GenerationSeptember 2003 42 Product Version 3.2

Encounter Design Flow Guide and Tutorial5Block Implementation

This chapter describes block implementation.

Overview on page 44

Flow on page 45

Steps on page 46




OverviewThis chapter describes the creation of the physical implementations of the blocks defined when the hierarchical floorplan was generated.

Inputs Block netlist

Budgeted constraints

Floorplan and placement information

Outputs Verilog netlist

DEF file

LEF File

GDSII file

TLF model

OpenAccess (OA) Database Power model

Noise modelSeptember 2003 44 Product Version 3.2



Flow

BI:

BI:

BI:

BI: Tcl

BI:

BI:

Tcl

BI:

Tcl

Tcl

BI: Amoeba Placement (TD)12

3

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Reorder Scan Chains


IPO (High Effort)Congestion Optimization6



IPO (High Effort)


Extraction (FE)1

Power Grid Analysis4

Clock Slew (post CTS)5

Noise Model Creation2

LEF, DEF, GDS, OA, Netlist, SPEF

Timing Model Creation

From Hierarchical Floorplan Generation on page 35

GDSII

Timing Model

OA DB

BlockNetlist

BudgetedConstraint

FloorplanPlacement

Slew Balancing6

IPO (pre CTS)5

Equivalence Check

19

20

Power Model

LEF Abstract

Noise Model

SPEF

DEF Netlist

6 SI Prevention

1 QX*2 CeltIC3 NanoRoute4 VoltageStorm*

7 SI Analysis/Repair

5 Optional Steps

Timing/SI Closure Sub Flow2,7

BI:

BI:

BI:

BI: Tcl

Tcl

Tcl

Tcl

Tcl



Chip Finishing

Logic Synthesis

TD Routing w/SI Prevention3,6

11

Difficult Timing

Tcl

BI: Tcl

BI: Tcl

Tcl

Tcl

BI: Tcl

BI: Tcl

BI: Tcl

BI: Tcl

*License required

PKS Physical Optimization Sub Flow5September 2003 45 Product Version 3.2

To Chip Assembly and Sign-Off on page 59To Top-Level Implementation on page 51



StepsTo implement the blocks you defined when you created a hierarchical floorplan, complete the following steps:

1. Run Amoeba placement.Read in the blocks netlist, floorplan, and constraints. Check the timing then place the block using timing-driven Amoeba placement.

Tcl Scripts:

BI: Load Data on page 108

BI: Check Timing on page 109

BI: Detailed Placement on page 110

2. Reorder scan chains.

Reorder the scan chains to relieve routing congestion.


Tcl Script: BI: Reorder Scan Chains on page 110.

3. Run trial routing, extract parasitics, and do timing analysis.

The block is routed, extracted with an extended capacitance table, and timing is analyzed. For blocks with very difficult timing, it may be necessary to run PKS (physical synthesis) to optimize and restructure the netlist. See the PKS Physical Optimization Sub Flow on page 73 for more information.


Tcl Script: BI: Trial Route/Extract/Timing Analysis on page 110.

For additional information on timing closure, see Appendix D, Timing Closure Strategies.

4. Run in-place optimization.

Run a high-effort IPO.

User Guide: See Timing: Optimization

Tcl Script: BI: Timing Optimization (IPO) on page 111.September 2003 46 Product Version 3.2

5. Run congestion optimization.



Run crosstalk prevention with congestion optimization.

Tcl Script: BI: Timing Optimization (IPO) on page 111.6. Balance slews.

Run crosstalk prevention with slew balancing.

Tcl Script: BI: Timing Optimization (IPO) on page 111.7. Run high-effort in-place optimization (IPO).



Tcl Script: BI: Timing Optimization (IPO) on page 111.8. Synthesize clock trees.

After the logic is optimized, clock trees are created using CTS.

User Guide: See Clock

Tcl Script: BI: Clock Tree Synthesis on page 114.


The block is trial routed, extracted, and the timing is again analyzed, this time with propagated clocks.



10. Run high-effort in-place optimization (IPO).User Guide: See Timing: IPO.

Tcl Script: BI: Fix Setup/Hold (IPO High Effort) on page 116.11. Do a clock skew.

Do a post clock tree synthesis clock skew analysis.

User Guide: See Clock.

Tcl Script: BI: Fix Setup/Hold (IPO High Effort) on page 116.September 2003 47 Product Version 3.2




The block is trial routed, extracted, and the timing is again analyzed, this time with propagated clocks.



13. Do routing with SI prevention.

Timing Driven (TD) detailed routing and Signal Integrity (SI) prevention are done using NanoRoute. NanoRoute is integrated natively into the Encounter executable and runs off of the same in-memory data structures as Encounter.

Tcl Script: BI: Routing w/SI Prevention on page 120.

14. Run extraction.

Extract the design using detailed extraction.


Tcl Script: BI: Extraction on page 122.

15. Go to the Timing/Signal Integrity Closure Sub Flow.

ImportantAt this point, timing should be met before proceeding to the Timing/SI Closure sub flow. See Timing/SI Closure Sub Flow on page 75.

16. Run power grid analysis.

Assuming that the netlist is clean, a power grid analysis is performed by Encounter and then IR drop analysis is done via VoltageStorm. At this point, the block is essentially complete and the rest of the steps involve creating various representations of the block to use during top-level implementation and chip assembly.


Tcl Script: BI: Power Rail Analysis (VoltageStorm) on page 132.17. Create noise model.

An Echo noise model for the block can be created by running CeltIC from within Encounter in standalone mode.

Tcl Script: BI: Create Noise Model on page 134.September 2003 48 Product Version 3.2

18. Output LEF, DEF, GDS/OA, netlist, SPEF.



A GDSII representation of the block can be generated directly from Encounter. In addition, an OpenAccess database (OA DB) can be created for the block. The OpenAccess database can be read by DFII during chip assembly in place of the GDSII. A block power model consisting of a power grid model and a power consumption value can be created to represent the block during top-level power analysis.

Tcl Script: BI: Generate DEF, GDSII, Netlist, OA DB on page 135.

19. Create timing model.

In order to create a characterized TLF blackbox timing model of the block, PKS must be run with the blocks netlist and SPEF parasitics. The TLF created during partitioning in the Hierarchical Floorplan Generation was only a simple one-dimensional representation of the block and contained no load or slew dependent timing information.

Tcl Script: BI: Final Xtalk and Timing Analysis on page 131.

Once all the block models are created, proceed to the Top-Level Implementation on page 51.

20. Do equivalence check.

Use the the Verplex tool to perform an equivalence check.September 2003 49 Product Version 3.2




Tcl Scripts

See Block Implementation on page 108.

Timing Closure

For additional information on timing closure, see Appendix D, Timing Closure Strategies.September 2003 50 Product Version 3.2

Encounter Design Flow Guide and Tutorial6Top-Level Implementation

This chapter describes the Top-Level Implementation flow.

Overview on page 52

Flow on page 53

Steps on page 54




OverviewThe top-level netlist, floorplan, timing constraints and LEFs, TLFs, power and noise models for the implemented blocks are read in. The top-level is placed and implementation steps are performed.

Information on performing timing closure is provided in Appendix D, Timing Closure Strategies. This appendix includes examples which use BG/PKS commands.

Inputs Top-level netlist

Floorplan and hard block placements

Top-level constraints

Outputs Top-level GDSII

Top-level netlist

Top-level SPEF

Top-level DEFSeptember 2003 52 Product Version 3.2



Flow

TI:

TI:

TI:

TI: TI:

TI:

TI: Tcl

Tcl

Tcl

Tcl

Tcl

Tcl1

2

3

4

5

6

8

9

7

10

Amoeba Placement (TD)Scan Chain ReOrdering


Repeater Insertion

Congestion Optimization6


TD Routing w/SI Prevention3

Slew Balancing6

Difficult Timing

From Block Implementation on page 43

From Hierarchical Floorplan Generation on page 35

Top-Level Netlist

LEFAbstracts

Timing Models

PowerModels

NoiseModels

15

16

17

11

12

13

14

IPO (High Effort)

Extraction (FE)1

Hier Power Grid Analysis4

GDS, OA, DEF,Netlist, SPEF

Equivalence Check5**

18

19

20



IPO (High Effort)

GDSII

OA DB

SPEF

DEF Netlist

ConstraintsFloorplan

6 SI Prevention

1 QX*2 CeltIC3 NanoRoute4 VoltageStorm*

7 SI Analysis/Repair

5 Optional Steps

TI:

Import Block Model Data

TI:

TI: Tcl

Tcl



Chip Finishing

Logic Synthesis

PKS Physical Optimization Sub Flow5

Timing/SI Closure Sub Flow2,7

IPO (pre CTS)5

Clock Slew (post CTS)5

TI:

TI:

TI:

TI:

TI: TI: Tcl

TI: Tcl

Tcl

Tcl

Tcl

Tcl

Tcl

TI: Tcl

TI: Tcl

TI: Tcl

TI: TclSeptember 2003 53 Product Version 3.2

Go to Chip Assembly and Sign-Off on page 59*License required



StepsTo implement the top-level design, complete the following steps:

1. Import the block model data.

Import the block data from the block implementation procedure. Update the configuration file to point to the timing models and LEFs created for the blocks during implementation, since the TLF models created buring block implementation are more accurate than the one-dimensional models created when saving partitions.

Check the timing before running Amoeba placement.

Tcl Scripts:

TI: Load Data on page 137

TI: Check Timing on page 139


Run timing-driven Amoeba placement to place cells, leaving block placement fixed.


Tcl Script: TI: Detailed Placement on page 140.

3. Do scan chain reordering.

The top level is placed scan chains are reordered to relieve routing congestion.


Tcl Script: TI: Reorder Scan Chains on page 140.

4. Do trial routing, extraction, and timing analysis.

The top level is routed, extracted (using Encounter), and the timing is analyzed pre-IPO. If timing is very tight, it may be necessary to run PKS to optimize timing and restructure the netlist. See the PKS Physical Optimization Sub Flow on page 73 for more information.

Tcl Scripts:

TI: Trial Route/Extract/Timing Analysis on page 141

TI: Physical Synthesis on page 141September 2003 54 Product Version 3.2

For additional information on timing closure, see Appendix D, Timing Closure Strategies.



5. Do in-place optimization.



Tcl Script: TI: Timing Optimization (IPO) on page 141.6. Insert repeaters.

Repeaters are inserted after crosstalk prevention has been implemented.

Tcl Script: TI: Timing Optimization (IPO) on page 141.7. Do congestion optimization.

Optimize for congestion.

Tcl Script: TI: Timing Optimization (IPO) on page 141.8. Balance slews.

Balance slews then do a high-effort trial routing.

Tcl Script: TI: Timing Optimization (IPO) on page 141.9. Do in-place optimization.

Do an IPO before doing a clock tree synthesis.


Tcl Script: TI: Timing Optimization (IPO) on page 141 .10. Do clock tree synthesis.

Do a clock tree synthesis post IPO.

Tcl Script: TI: Clock Tree Synthesis on page 145.

11. Do trial routing, extraction, and timing analysis.

The top level is routed, extracted (using Encounter), and the timing is analyzed (post Clock Tree) . As before, if timing is a problem, it may be necessary to run PKS to optimize timing and restructure the netlist. See the PKS Physical Optimization Sub Flow on page 73 for more information.

Tcl Scripts:

TI: Trial Route/Extract/Timing Analysis on page 145September 2003 55 Product Version 3.2

TI: Physical Synthesis on page 146



12. Run high-effort in-place optimization (IPO).Run high effort IPO with restructuring to fix setup and hold violations.

User Guide: See Timing: IPO.

Tcl Script: TI: Fix Setup/Hold (IPO High Effort) on page 146.13. Do clock skew.

Do a useful clock skew post CTS.

Tcl Script: TI: Fix Setup/Hold (IPO High Effort) on page 146.14. Do trial routing, extraction, and timing analysis.

The top level is once again routed, extracted (using Encounter), and the timing is analyzed (post Clock Tree). As before, if timing is a problem, it may be necessary to run PKS to optimize timing and restructure the netlist. See the PKS Physical Optimization Sub Flow on page 73 for more information.

15. Do routing with SI prevention.

Use NanoRoute to do timing-driven routing with signal integrity prevention.

Tcl Script: TI: Routing w/SI Prevention on page 151.

16. Run extraction.

Extract the design using detailed extraction.


Tcl Script: TI: Extraction on page 153.

17. Go to the Timing/Signal Integrity Closure sub flow.

ImportantAt this point, timing should be met before proceeding to the Timing/SI Closure sub flow. See Timing/SI Closure Sub Flow on page 75.

18. Do a hierarchical power grid analysis.

A power analysis is performed by Encounter and then IR drop analysis is done via VoltageStorm.

Tcl Script: TI: Power Rail Analysis (VoltageStorm) on page 163.September 2003 56 Product Version 3.2

Note: VoltageStorm requires an additional license.



19. Output the top-level GDS and/or OA, DEF, netlist, and SPEF.

A GDSII representation can be generated directly from Encounter. In addition, an OpenAccess (OA) database can be created. The OA database can be read by DFII during chip assembly in place of the GDSII.

Tcl Script: TI: Generate DEF, GDSII, Netlist, OA DB on page 166.

20. Run an equivalence check.

Use the the Verplex tool to perform an equivalence check.September 2003 57 Product Version 3.2




Tcl Scripts

See Top-Level Implementation on page 137.

Timing Closure Strategies

The following information relating to step 4 in this flow procedure is provided. The examples use BG/PKS commands in addition to Encounter commands.

See Appendix D, Timing Closure Strategies.September 2003 58 Product Version 3.2

Encounter Design Flow Guide and Tutorial7Chip Assembly and Sign-Off

This chapter describes chip assembly and sign-off.

Overview on page 60

Flow on page 61

Steps on page 62




OverviewThe Chip Assembly and Sign-Off process consists of bringing the detailed information for the top level and all of the blocks together for full chip extraction, power, timing, and crosstalk analysis. Once the sign-off extraction has completed, full-chip power, timing, and crosstalk can be checked. If the methodology calls for dynamic simulation in the sign-off process, an SDF file can be produced for NC-Verilog.

Note: Flattening the design is not required. A flat sign-off is needed only if the hierarchical results from the Top-Level mplementation procedure are suspected of having inaccuracies. These inaccuracies could be due to not taking into account the coupling capacitance between over-the-block routes and inside-the-block routes.

Inputs Top-level DEF

Block-level DEF

Top-level netlist

Timing constraints

Block netlist

Full-chip DEF

Outputs Netlist

OpenAccess Database

Top-Level GDSII

Block GDSII

SDF for Verilog (optional)September 2003 60 Product Version 3.2



Flow

Stitching SPEF or Flat SPEF

Full-Chip Timing Analysis

Full-Chip SI Analysis

Top-Level DEF

Block DEFs

Top-Level SPEF

Block SPEFs

Top-Level OA

Full-Chip SPEF

Block OAs

Block GDSII

Top-Level GDSII

Flatten (unpartition)Full-Chip Power Grid Analysis

Full-Chip Extraction

Full-Chip SDF

Full-Chip Timing Simulation

From Top-Level Implementation on page 51 From Block Implementation on page 43

1

2

3

5

6

7

4

8

Optional

CA: Tcl



Chip Finishing

Logic Synthesis

Top-Level Netlist

BlockNetlist

Timing Constraints

CA:

CA:

CA:

CA:

CA: CA:

Tcl

Tcl

Tcl

Tcl

Tcl

TclSeptember 2003 61 Product Version 3.2

Go to Chip Finishing on page 65



StepsTo assemble the chip and do sign-off, complete the following steps:

1. Flatten the design.

Flatten the design by merging the top-level and block-level DEF files.

Tcl Script: CA: Flatten Design on page 169.

2. Do full-chip power grid analysis.

Use VoltageStorm to perform a power analysis.


Tcl Script: CA: Flat Power Analysis on page 171.

3. Extract full-chip parasitics (optional).Use the Fire & Ice QX extractor to do a flat extraction to derive all parasitics including potential undetected coupling between over-the-block routes and inside-the-block routes.

Note: QX does not support LEF/DEF 5.4 or 5.5.

Comment: Check with Mohammad and Kevin B.


Tcl Script: CA: Extraction on page 170.

4. Create stitching SPEF or flat SPEF.

Either a 64-bit full chip parasitic extraction can be performed on the flattened design, or the SPEFs from the top level and the blocks can be stitched together for 64-bit timing and SI analysis.


5. Run full-chip timing analysis.

Use CTE to perform static timing analysis. Use SignalStorm to calculate sign-off delays. Either a full chip extraction can be performed on the flattened design or the SPEFs from the top level and the blocks can be stitched together for Timing and SI analysis.

User Guide: See Timing: Timing Analysis.September 2003 62 Product Version 3.2

Tcl Script: CA: Flat Timing Analysis on page 173.



6. Do full-chip signal integrity analysis.

Read (into Encounter) the SPEF file generated by the extractor, the top-level netlist, the timing constraints file, and the netlists for all the blocks. Use CeltIC to do a full-chip SI analysis.

User Guide: See SI.

Tcl Script: CA: Flat Xtalk Analysis on page 173.

7. Generate full-chip SDF (optional).If the methodology calls for dynamic simulation in the signoff process, an SDF file can be produced to feed NC-Verilog.

8. Full-chip timing simulation (optional).Do a full-chip timing simulation.

Tcl Script: CA: Flat Timing Analysis on page 173.September 2003 63 Product Version 3.2




Tcl Scripts

See Chip Assembly / Sign-Off on page 168.September 2003 64 Product Version 3.2

Encounter Design Flow Guide and Tutorial8Chip Finishing

This chapter describes the Chip Finishing flow.

Overview on page 66

Flow on page 67

Steps on page 68



Chip Finishing

OverviewThis chapter describes how to obtain physical layouts from the data you have created and perform final verification.

Inputs Top-Level GDSII and Block-Level GDSII

Top-Level OA DB and Block-Level OA DB

Full Chip OA DB

Outputs MasksSeptember 2003 66 Product Version 3.2


Chip Finishing

Flow

Import Std Cell GDSII1

Layout Finishing / Editing1

Run Physical Verification2

Errors? Yes

RTM GDS

Import Top & Block GDSII

No

From Chip Assembly and Sign-Off on page 59

Import Top & Block OA DB

1

2

3



Chip Finishing

Logic Synthesis

1 NanoRoute2 Assura3 First Encounter

Restore OA Design3

Verify/Extract/TA3

OA DB

* Modified OA DB can be read back into Encounter

Modified*

Non-connectivity modifying editsSeptember 2003 67 Product Version 3.2


Chip Finishing

StepsTo finish the chip, complete the following steps:

1. Import the GDSII layouts for the standard cells used in the design into a DFII database, or import the OA DB(s) or GDSII files for the Top/Block, or import the whole chip (OA DB).Import the GDSII file you created during top-level implementation. The GDSII for the standard cells, and either the Top Level and Block GDSII files or the Full Chip OA DB are assembled in the DFII environment in order to complete the steps necessary to mask out the chip.

2. Run layout finishing.

Layout finishing steps include adding scribe lines, adding fiducials, adding alignment marks, adding test fixtures, and so forth. Edits made that dont change the designs logical connectivity (that is, wire edits and cell movement) can be fed back into Encounter via OA DB (modified flow on left).

3. Run physical verification.

Once the layout finishing steps are complete, a rigorous Physical Verification is performed using Assura (in DFII) to look for any design rule violations that may be present in the design. If any are found, they can be corrected and the layout finishing steps may need to be redone. Once the design passes error free, then masks can be generated and the chip fabricated.September 2003 68 Product Version 3.2


Chip Finishing


Tcl Scripts

See Chip Finishing on page 176.September 2003 69 Product Version 3.2


Chip FinishingSeptember 2003 70 Product Version 3.2

Encounter Design Flow Guide and Tutorial9Sub Flows: PKS Physical Optimization, Timing/SI Closure

This chapter describes the PKS Physical Optimization and Timing/SI Closure sub flows.

Overview on page 72

PKS Physical Optimization Sub Flow on page 73

Steps: PKS Physical Optimization on page 74

Timing/SI Closure Sub Flow on page 75

Steps: Timing Analysis/SI on page 76September 2003 71 Product Version 3.2


Sub Flows: PKS Physical Optimization, Timing/SI Closure

OverviewThis chapter describes two sub-flows which branch from the Block Level Implementation and Top-Level Implementation flows:

PKS Physical Optimization Sub Flow on page 73

Timing/SI Closure Sub Flow on page 75September 2003 72 Product Version 3.2



PKS Physical Optimization Sub Flow

Create Path Groups1

2

3

4

5

7

8

6

9

Pre-Clock Optimization


Useful Skew Optimization

TD Global Route

IPO

TD Global Route

IPO

Fix Setup/Hold

Placement Netlist Constraints

StandalonePKS

From Block or Top-Level Implementation

FE/PKS Interface

Full PKS Optimization Capabilities

To Block or Top-Level Implementation

Placed DEF

OptimizedNetlist

SPEF



Chip Finishing

Logic Synthesis


Timing/SI Closure Sub FlowSeptember 2003 73 Product Version 3.2



Steps: PKS Physical Optimization

You can use either Encounter or PKS to perform PKS Physical Optimization. The Encounter flow is described here.

Tcl scripts:

BI: Physical Synthesis on page 111

TI: Physical Synthesis on page 141

1. Create the path groups.

Path groups are recommended to isolate specific areas of the design. This helps to assist in uncovering areas that are prone to closure issues and allows the optimizer to close timing on the rest of the design.

2. Do a pre-clock optimization.

3. Synthesize the clock tree.

Synthesize the clock tree then analyze the clock tree reports to determine if constraints have been met.

4. Run a useful skew optimization.

5. Do timing-driven global routing.

6. Do in-place optimization (IPO).7. Redo global routing.

Run timing-driven global routing again.

8. Redo in-place optimization (IPO).9. Fix setup/hold times.September 2003 74 Product Version 3.2



Timing/SI Closure Sub Flow

TA (Setup/Hold)12

3

4

5

7

6

8

9

10

11

12

13

14

IPO (Setup Violations)IPO (Hold Violations)SI Aware ECO Route2

SI Analysis3

Fix Crosstalk

Add Filler Cells

Fill Notches

Verify Metal Density

Verify Geom/Conn/Antenna

Extraction1

Add Metal Fill

SI Analysis3

TA (Setup/Hold)

From Block or Top-Level Implementation

1 QX2 NanoRoute

To Block or Top-Level Implementation

Extracted Design (metal fill assumed)

3 CeltIC



Chip Finishing

Logic Synthesis


Timing/SI Closure Sub FlowSeptember 2003 75 Product Version 3.2



Steps: Timing Analysis/SI

Tcl scripts:

BI: Timing/SI Closure Sub Flow on page 128

TI: Timing/SI Closure Flow on page 159

1. Do a timing analysis and fix setup/hold times.

2. Run in-place optimization and fix setup violations.

3. Run in-place optimization and fix hold violations.

4. Do a signal integrity-aware ECO route using NanoRoute.

5. Do a signal integrity analysis.

6. Fix crosstallk.

7. Add filler cells.

8. Add metal fill.

9. Fill notches.

10. Verify metal density.

11. Verify geometry, connectivity, and antenna.

12. Extract the design using Fire & Ice QX. Assume metal fill for the extraction.13. Do a signal integrity-aware ECO route using NanoRoute.

14. Do a timing analysis and fix setup/hold times.September 2003 76 Product Version 3.2

Encounter Design Flow Guide and TutorialATerminology

This appendix provides an alphabetical listing and description of terminology used in the Encounter flow.

Table A-1 Encounter Flow Terminology

Term DescriptionBG/PKS BuildGates and Physically Knowledgeable Synthesis. Integrated

synthesis tools from Cadence.CTE Common Timing Engine (static timing report mode). Two report

mode are available: CTE and FE. See Timing: Timing Analysis in the Encounter User Guide.

DEF Data Exchange Format.Extraction See Parasitics.Fence A fence in an extension of the module guide concept, with

stronger restrictions on placement. The placer must place the modules entire design hierarchy within the fence. Cells and sub-block cells originally placed outside the module guide are placed inside the modules fence. Cells and sub-block cells from other modules are not allowed within a modules fence.

Fire & Ice QX Sign-off quality parasitic extraction tool. A separate license is required for this tool.

First Encounter First Encounter product by Cadence.JTAG Scan test cells (Joint Test Action Group).GDSII/GDS Graphical Design System II. The name of the file format is

Stream, but it is commonly referred to as GDSII.September 2003 77 Product Version 3.2


Terminology

IR drop Generic term used to describe the reduction in voltage that occurs on power supply networks (VDD) or the increase in volt-age (also known as ground bounce) that occurs on ground net-works (VSS)..

LEF Library Exchange Format..lib Synopsys Liberty Timing Library Format.Module Guide A module guide represents a logical module structure in the

imported netlist. The purpose of module guides is to constrain module placement in the floorplan. Module guides constrain the placer to place the module and sub-module cells in the vicinity of the module guide. Not all cells or sub-module cells must be placed within a module guide. The placer allows cells from different modules to be placed within the module guide, and for module guides to overlap.

MSV Multiple Supply Voltages. Sometimes referred to as MSMV (multiple supply multiple voltages).

Nanoroute Integrated routing tool for nanometer designs.OpenAccess OpenAccess Database format.Parasitics Refers to capacitance in a circuit and methods of extracting the

capacitance from the physical circuit design. See Fire & Ice QX.Partition When a fenced module is designated as a partition, it is treated

as a hierarchical sub-block in the design. Committing and saving partitions does the following:

Assigns pins to the sub-blocks based on trial routing

Creates timing budgets

Creates physical and timing budgets

Pushes the top-level power plan and the floorplan objects into the modules

PKS Physically Knowledgeable Synthesis.P/G Power and ground.


Term DescriptionSeptember 2003 78 Product Version 3.2

SDC Synopsys Design Constraints.


Terminology

SDF Standard Delay Format.(SoC) Encounter Combination of First Encounter with other products.SPEF Standard Parasitic Exchange Format.TLF Timing Library Format.VoltageStorm IR drop analysis tool. A separate license is required for this tool.(C) WLM (Custom) Wireload Model.


Term DescriptionSeptember 2003 79 Product Version 3.2


TerminologySeptember 2003 80 Product Version 3.2

Encounter Design Flow Guide and TutorialBList of Tcl Script Examples

This appendix contains the Tcl script examples grouped by procedure. The following abbreviations are used for the procedures.

Example B-1 VP: CTE Timing Analysis (no net loading) 88Example B-2 VP: Load Floorplan (Place I/Os) 89Example B-3 VP: JTAG Placement 89Example B-4 VP: Critical Block Placement 90Example B-5 VP: Auto Floorplan Generation 90Example B-6 VP: MSV Definition 90Example B-7 VP: Initial Power Planning 91Example B-8 VP: Amoeba Placement 93Example B-9 VP: Scan Reorder 93Example B-10 VP: Generate Floorplan Guides 94Example B-11 VP: TrialRoute 95Example B-12 VP: Add Blockages if Necessary 95Example B-13 VP: Extract Parasitics 96Example B-14 VP: Timing Analysis 96

Logical Synthesis and Scan Insertion no scriptsSilicon Virtual Prototyping VPFloorplan Refinement FRHierarchical Floorplanning HFBlock Implementation BITop-Level Implementation TIChip Assembly / Sign-Off CAChip Finishing no scriptsSeptember 2003 81 Product Version 3.2

Example B-15 VP: Block Placement Adjustment 96Example B-16 VP: Floorplan Refinement with Fences 97


List of Tcl Script Examples

Example B-17 VP: Trial Route/Extract 97Example B-18 VP: Timing Analysis 98Example B-19 VP: Clock Tree Synthesis 98Example B-20 VP: Trial Route/Extract 99Example B-21 VP: Timing Analysis 99Example B-22 VP: IPO 99Example B-23 VP: Extract/Timing Analysis 100Example B-24 VP: Power Analysis 100Example B-25

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