“Flying-Adder” Frequency and Phase Synthesis...

February 15, 2005 Slide 1

“Flying-Adder” Frequency and Phase Synthesis Architecture

Liming XIUTexas Instruments Inc, HPA/DAV

01/30/2005


What is it?

An novel frequency synthesis architecture that takes a digital value and generates a signal of requested frequency (and phase).

..0100101...

f (Hz)

Continued


Background MaterialThis presentation is based on five papers:

• IEEE Journal of Solid-State Circuit, 06/2000, “An Architecture of High Performance Frequency and Phase Synthesis”.

• IEEE Trans. on VLSI, 10/2002, “A ‘Flying-Adder’ Architecture of Frequency and Phase Synthesis with Scalability”.

• IEEE Trans. on Circuit & System II, 03/2003, “A New Frequency Synthesis Method based on ‘Flying-Adder’ Architecture”.

• IEEE Journal of Solid-State Circuit, 03/2004, “A Novel All Digital Phase Lock Loop with Software Adaptive Filter”.

• IEEE Trans. on VLSI, 02/2005, “A ‘Flying-Adder’ Frequency Synthesis Architecture of Reducing VCO Stages”.


History

• Started in late 1998, MSP/Video Group.

• Being continuously refined/improved.

• Thanks to Hugh Mair


Presentation Outline

•• The principal IdeaThe principal Idea

• Implementation: First Generation

• Implementation: Second Generation

• Integer-Flying-Adder Architecture


Principal IdeaUsing multiple equally-spaced phases generated from a VCO to synthesis various frequency and phase, by triggering the flip-flops at predestined time.

Frequency and PhaseControl Word

FREQUENCY AND PHASESYNTHESIZER

PFD CHARGEPUMP VCO

DIVIDER

Reference

Z

Z_SHIFT

N

Continued

Filter


Principal Idea, continued

Continued

VCO Output waveforms, for N=32

VCOOUT[30]

VCOOUT[3]

VCOOUT[2]

VCOOUT[1]

VCOOUT[0]

VCOOUT[31]


Principal Idea, continued

ZVCOOUT<31:0>

10-bitAdder

10-bit Reg

FREQ<9:0>

1 23

1 2 3

32 to 1MUX D

Q'

Q

Continued

Triggering the flip-flop at predestined time to generate the desired frequency, by utilizing the multiple VCO outputs.

@ f Hz


Numerical Example

Continued

VCO running at 156.25 MHz (6.4 ns)

=> ∆ = 6.4/32 = 0.2 (ns)

Wanted: 204.08 MHz, or T = 4.9 ns

=> FREQ[9:0] = T/(2∆) = 4.9/0.4 = 12.25 = 01100.01000b

Integer portion is used for selecting tick, fractional portion is for error accumulation.


Numerical Example, continued

000000

1201100

2411000

400100

1710001

2911101

00000.00000+ 01100.01000

01100.01000

01100.01000+ 01100.01000

11000.10000

11000.10000+ 01100.01000

00100.11000

00100.11000+ 01100.01000

10001.00000

10001.00000+ 01100.01000

11101.01000

12 12 13 1212


Key Facts • VCO has to be in multiple-delay-stages style, single-ended or differential.

• The PLL/VCO is running at a fixed frequency, no loop dynamic responds requirement.

• Output frequency range, theoretically: (1/2)fvco <= fout <= (N/2)fvco

• In practice, the high-frequency is limited by the speed of the process in which this architecture is implemented.

• Has inherent jitter if fractional bits are used.

• Frequency resolution (step): 2**2 fkf ∆−−=δ


Inherent Jitter rMTFREQor

FREQT+=∆=

∆=/,

*

∆+=∆=

*)1(*

MTMT

l

s

rPPrP

ls

l

−=−==

11

∆=−=− slpkpk TTJ

0)()( =−+−= TTPTTPJ ssllmean

222 )()( rrTTPTTPJssllrms −∆=−+−=


Output frequency vs. FREQ (an example)


Frequency divider and “Phase divider”

• To generate frequencies, divider can be used. But divider ratio has to be integer → available frequencies are limited.

• “Flying-Adder” architecture can be viewed as “phase divider” which provides additional level of frequency divide → more available frequencies.



• The principal Idea

•• Implementation: First GenerationImplementation: First Generation




Implementation: Problems

ZVCOOUT<31:0>

10-bitAdder

10-bit Reg

FREQ<9:0>

1 23

1 2 3

32 to 1MUX D

Q'

QTwo problems:

•The glitch of the MUX

•The speed of the adder


The Glitch of the MUXIN0IN1IN2

IN31

Z

Sel[4:0]

IN0, “00000”

IN21, “10101”

IN31, “11111”

Z

Z’t


Implementation: Two Paths

Continued

FREQ_B<4:0>

Z

10-bitAdder

5-bitAdder

5-bitReg

10-bit Reg

VCOOUT<31:0>

FREQ_A<9:0>

PATH_B

PATH_A

CLK1

CLK2

D

Q'

Q

D

Q'

Q



Continued

Solved the glitch problem: the two paths are interlocked

CLK2

CLK1

Path_A blocked

MUX_A decoding

Path_B open

MUX_B stable

Path_A open

MUX_A stable

Path_B blocked

MUX_B decoding



Continued

Relaxed the constrain on adders => double the circuit speedOne path generates the rising edge, the other for falling edge

Path A

Path B

Path A

Path B

Accumulator in Path A

Accumulator in Path B


Implementation: Two PathsThis two paths architecture solved the previous two problems, but created a new problem:

the synchronization of the two paths. In other words, MUX_A and MUX_B’s address values are unrelated => duty cycle is uncontrollable.

Path A

Path B

Path A

Location unknownDepend on initial value


Implementation: Synchronized

Continued

FREQ_B<4:0>

Z

10-bitAdder

5-bitAdder

5-bitReg

10-bit Reg

VCOOUT<31:0>

FREQ_A<9:0>

PATH_B

PATH_A

CLK1

CLK2

D

Q'

Q

D

Q'

Q


Implementation: SynchronizedNow MUX_B’s address is related to MUX_A’sNew problem: Adder in PATH_B doesn’t have full cycle to

work

Path A

Path B

Path A

Path B

Accumulator in Path A

Adder in Path B


Implementation: Pipelined

Continued

FREQ<10:6>

ZVCOOUT

<31:0>

PATH_B

PATH_A

CLK1

CLK2

10-bitAdder

10-bit Reg

FREQ<9:0>

5-bitReg

5-bitReg

5-bitAdder

5-bitReg

t1

t2

t3 t4

t5 t6

D

Q'

Q

D

Q'

Q


Implementation: Pipelined• Now both the accumulator in PATH_A and the adder in

PATH_B have full cycle to work.• Timing constrain: see below

a cb

bcttttabtttt

∆≤++∆≤++

654321


Implementation: First GenerationFirst generation development history:• One Path• Two Paths• Synchronized• Pipelined

Key features of this architecture:• interlocking between paths• self-clocking• pipeline


Summary: The Advantages•The output frequency can be changed instantly without any dynamic process.

•With enough fraction bits, any frequency within certain range can be generated with any accuracy.

•Phase shift version of the output signal can be generated.

•Output signal with various duty cycle can be generated.

•Since VCO running at fixed frequency, VCO and PLL design are much simplified, the PLL is much robust against temperature draft, process and voltage variation.

•The ‘increment’ value can be modulated to produce a highly accurate and predictable spread spectrum clock source.


Phase Synthesis: The idea

Continued

Z

VCOOUT<31:0>

10-bitAdder

10-bit Reg

FREQ<9:0>

32 to 1MUX

5-bit Reg

PHASE<4:0>

32 to 1MUX

5-bitAdder

Z_SHIFT

FREQ_GEN

PHASE_GEN

D

Q'

Q

D

Q'

Q


Phase Synthesis: The idea• The MUX address used in PHASE_GEN is the sum of the

MUX_A’s address and PHASE[4:0]• The data used in DFF of PHASE_GEN is the same as data

used in FREQ_GEN• The Z_SHIFT is a delay version of Z. The delay amount:

PHASE[4:0] *∆

Z

Z_SHIFT

∆= *]0:4[PHASEϕ


Phase Synthesis: Implementation

FREQ<32:27>

5-bitAdder

>=31?

'0'

'1'

32-bitAdder

<5:0>

<4:0

>

5-bitAdder

>=31?

'0'

'1'

32-bitAdder

<5:0>

<4:0

>

5-bitReg

5-bitReg

Z_SHIFTVCOOUT

<30:0>

PATH_B_SHIFT

PATH_A_SHIFT

5-bitReg

5-bitAdder

>=31?

'0'

'1'

32-bitAdder

<5:0>

<4:0

>

5-bitReg

5-bitReg

DFTOUT_UP

DFTOUT_LOW

LO

W_T

O_U

P<

4:0

>

PHASE<4:0>

D

Q'

Q

D

Q'

Q


Phase Synthesis: Problems

Problems:• “Dead-zone”• “Dual-stability”





•• Implementation: Second GenerationImplementation: Second Generation



Second Generation Architecture

The new architecture:

• the operating speed is greatly improved.• has scalability for higher output frequency.• has an internal node whose frequency is higher

than that of the synthesized output.• eliminates the “dead-zone” and “dual-stability”

for phase synthesis.Continued


Second Generation Architecture

CLK2

CLK1D Q

CLK

CLK1

CLK1

CLK2

CLK2

CLK2

+

+

TRIGGER

FREQ<31:0>

FREQ<32:28>

EN

EN

32 Bits

5 Bits

5 Bits

5 Bits

VCOOUT<31:0>

32

5

0

1

FREQ<10:6>

ZQ

QSET

CLR

D

Q

Q

SET

CLRD

VCOOUT<31:0>

PATH_B

PATH_A

CLK1

CLK2

10-bitAdder

10-bit Reg

FREQ<9:0>

5-bitReg

5-bitReg

5-bitAdder

5-bitReg

t1

t2t3 t4

t5 t6

Continued


Sec. Gen. Arch.: Scalability

Continued+

+ + +

CLKCNTL D Q

CLK

CLK2

CLK1CLK3CLK4

CLK1

CLK1

CLK1

CLK1

CLK1

CLK2

CLK3

CLK4

FREQ[31:0] FREQ[33:29]

FREQ[32:28]+FREQ[33:29]

FREQ [32:28]+FREQ[27]

MUX1

MUX2

MUX3

MUX4

MUX5

REG1

REG4

REG3

REG2

TRIGGER

SEL2 SEL3 SEL4SEL1

Tick[31:0]

Z

SEL5

ADDER4

ADDER3

ADDER2ADDER

1


Sec. Gen. Arch.: Scalability

Continued

• Multiple paths (more than two) to relax the constrains on adders further -> higher output frequency


Sec. Gen. Arch.: Scalability• The clocks signals and the mechanism of interlocking

01 M U X 2

10 M U X 4

01 M U X 2

10 M U X 4

01 M U X 2

00 M U X 1

11 M U X 3

00 M U X 1

11 M U X 3

2 3 4 5 6 7 8 9 10 11 121

C LK 1

C LK 2

C LK 3

C LK 4

Z and SE L5[1:0]

11 M U X 3

T R IG G E R


Sec. Gen. Arch.: Phase Synthesis

CLK2

CLK1(Z)D Q

CLK

CLK1

CLK1

CLK2

CLK2

CLK2

+

+

TRIGGER

FREQ<31:0>

FREQ<32:28>

EN1

EN1

32 Bits

5 Bits

5 Bits

5 Bits

VCOOUT<31:0>

0

0

1 0

1

1

INIT1

INIT1

D Q

CLK

EN EN1

CLK2

32

5

Fig. 16. The circuitry for Z.

CLK2’

CLK1’(Z_SHIFT)

D Q

CLK

CLK1’

CLK1’

CLK2’

CLK2’

CLK2’

+

+

TRIGGER

FREQ<31:0>

FREQ<32:28>

EN2

EN2

32 Bits

5 Bits

5 Bits

5 Bits

VCOOUT<31:0>

0

0

1 0

1

1

INIT2

INIT2

D Q

CLK

EN1 EN2

CLK2’

1

0CLK1

EN2

32

5

Fig. 17. The circuitry for Z_SHIFT






•• IntegerInteger--FlyingFlying--Adder ArchitectureAdder Architecture


Integer-Flying-Adder Architecture

Issues with current architecture: since PLL/VCO is running at a fixed frequency =>

– need fractional bits to achieve certain frequency, -> periodic carry-in bit,

– frequency modulation of the output signal, or, inherent jitter

Continued


Integer-Flying-Adder Architecture

Idea:

Make PLL programmable

Get ride of fractional bit

→ Eliminate the inherent jitter


Integer-Flying-Adder: MethodFREQ = T/∆ = 1/(f* ∆) = ((fin*N)/(f*P)) *M

Using two integers, FREQ and M, to approximate a real number f .2 <= FREQ <= 2N, M1 <= M <= M2


Integer-Flying-Adder: AlgorithmThe algorithm to search the best control parameters

error_min = very_big_numberfor ( M1<=M<=M2 ) {

freq = ((fin*N)/(f*P))*Merror = min( freq-floor(freq), ceiling(freq)-freq )if (error < error_min ) {

error_min = error Mbest = Mif (freq – floor(freq)) < 0.5 {

FREQ = floor(freq)}else {

FREQ = ceiling(freq)}

}}


Integer-Flying-Adder: Error Upper-Bound

|T-T’|/T = r*∆ /T<= (1/2) * ((fin*N)/(f*P)) / (((fin*N)/(f*P))*M)

= 1/(2*M)<= 1/(2*M1)


Integer-Flying-Adder: Error Distribution Envelope

for (2<=F<=64) {for (M1<=M<=M2) {

F-M-seq(index) = M/F}

}

foreach M/F in F-M-sorted-seq(index) {F-M_curr = M/Fp_max = 2/(F-M_curr + F-M_prev)e_max = (F-M_curr - F-M_prev)/( F-M_curr + F

-M_prev)

F-M_prev = F-M_curr }

ContinuedSee paper on TCASII (3th paper) for mathematical prove





The effect of M2 on the error distribution envelope


Integer-Flying-Adder: Summary

• Comparing to original architecture:eliminate the inherent jitterbut the PLL loop need adjustment

• Comparing to “Integer-N”, the frequency range is much wider.

• Comparing to “Fractional-N”, no need to compensate the spurious signals.


One Application Example: All Digital Phase Lock Loop

“flying-adder” synthesizer

All loop variables are digital values, no analog voltage !


ADPLL: A New Idea

VCO

Synthesizer1

Synthesizer2

FREQ1

FREQ2

MeasureFrequency

fin

Conversion

fout

fhi

frequency of fin

Flying-adder

Known high frequency


ADPLL: A New Idea • Goal: fout = N * fin• Procedure:

– Using synthesizer1 to generate a known high frequency fhi (e.g. > 500 MHz), by FREQ1.

– Using fhi to measure fin.( a simple counter) Get a frequency number of fin.– Multiple this frequency number by N and convert it to FREQ2.– Using synthesizer2 to generate the fout, by FREQ2.

• Advantage:– fout is not directly related to fin electrically, noise in fin is isolated. PFD and filter

are not required.– Especially good for multiplying the input frequency to a large number (N is big).– The VCO used for flying-adder synthesizers can be a very simple one with

minimum analog complexity.– Synthesis1 in above diagram can be a very simple one (no fractional part)


Conclusion

• A novel frequency synthesis architecture is presented.

• This architecture can be used to generate many, many frequencies.


F = p *M

F

F + 1

p, a required frequency

F + 1

F + 2

As M sweepAs M sweep

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