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E N G R . R A S H I D F A R I D C H I S H T I

L E C T U R E R , DE E , F E T , I I U I

C H I S H T I @ I I U . E D U . P K

W E E K 1

D I G I T A L L O G I C D E S I G N R E V I S I O N

FPGA Based System Design

Saturday, July 21, 2012

1

www.iiu.edu.pk

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Combinational Logic

3

Has no memory

Output depends only on the present input

x1

x2

xn

z1

z2

zm

Note:

Positive Logiclow voltage corresponds to a logic 0, high voltage to a logic 1

Negative Logiclow voltage corresponds to a logic 1, high voltage to a logic 0

CombinationalLogic

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Types of Boolean Equations Canonical Form

Sum of Min Terms

F(A,B,C) = ABC + ABC' + AB'C + AB'C' + A'B'C

Product of Max Terms

F(A,B,C) = (A+B+C ) (A+B'+C) (A+B'+C' )

Standard Form

Sum of Products (SOP)F(A,B,C) = A + B'C

Product of Sums (POS)

F(A,B,C) = (A+B+C) (A+B')

Boolean Equations

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Min Max Terms

(Canonical Form)

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F = A + B'C= A (B + B') + B'C (A + A')

= AB + AB' + AB'C + A'B'C

= AB(C + C') + AB'(C+C')+ AB'C + A'B'C

= ABC + ABC' + AB'C + AB'C'+ AB'C + A'B'C

= ABC + ABC' + AB'C (1 + 1) + AB'C'+ A'B'C

= ABC + ABC' + AB'C (1) + AB'C'+ A'B'C

= ABC + ABC' + AB'C + AB'C' + A'B'C= 111 + 110 + 101 + 100 + 001

= 7 + 6 + 5 + 4 + 1

= (1,4,5,6,7) = (0,2,3)

Example: Express the Boolean function F=A+B'C as

a sum of min terms and product of max terms

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Convenient way to simplify logic functions of 2,3, 4, 5, (6)

variables

In a Four-variable K-map

each square corresponds to one

of the 16 possible minterms

1 = minterm is present;

0 (or blank) = minterm is absent;

X = dont care

the input can never occur, or the input occurs but the output is not specified

adjacent cells differ in only one value =>

can be combined

K-maps

Location

of minterms

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K-maps

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Three Variable K-maps

1

1

1 1

00 01 11 10

0

1

x

y zy z

After Simplification F = yz + xz'

Map for F(x,y,z) = (3,4,6,7)

x z '

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Four Variable K-maps

K-Map for F(A,B,C,D) = (0,1,2,6,8,9,10)

A B

1 1 1

1

00 01 11 10

00

01

11

10

C D

1 1 1

After Simplification F(A,B,C,D)= B'D' + B'C' + A'CD'

A'CD'B'C'

B'D'

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Four Variable K-maps

K-Map for F(A,B,C,D) = (0,1,2,5,8,9,10)

A B

1 1

0 1

0 1

0 0

00 01 11 10

00

01

11

10

C D

0 0

1 1

0 0

0 1

After Simplification

F'(A,B,C,D)= AB + CD + BD'

So F(A,B,C,D)= (A'+B') (C'+D') (B'+D)

CD

AB

BD'

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Using Dont Care in K-maps

F = yz + w'x' F = yz + w' z

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Five Variable K-maps

F = ACE + A'B'E' + BD'E

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Six Variable

K-maps

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21/07/201215

Hazards in Combinational Networks

What are hazards in Combinational Network?

Unwanted switching transients at the output (glitches)

Example

ABC = 111, B changes to 0 Assume each gate has propagation delay of10 ns

B = 1 0 F = 1 0 1

A = 1

C = 1

F = AB' + BC

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0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns

B

D

E

F

B = 1 0 F = 101

A = 1

C = 1

F = AB' + BC

E

D

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21/07/201217

Hazards in Combinational Networks

Occur when different paths from input to output havedifferent propagation delays

Static 1-hazard a network output momentarily go to the 0 when it should remain a

constant 1

Static 0-hazard a network output momentarily go to the 1 when it should remain a

constant 0

Dynamic hazard if an output change three or more times, when the output is supposed

to change from 0 to 1 (1 to 0)

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21/07/201218

Removing Hazard

BCABf ' ACBCABf '

To avoid hazards:

every pair of adjacent 1s should be covered by a 1-term

1

1

1 1

00 01 11 10

0

1

CA B

1

1

1 1

00 01 11 10

0

1

CA B

A

CF = AB' + BC

D

E

BA

C F=AB'+BC+AC

D

E

B

A

G

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21/07/2012

UAH-CPE/EE422/522

AM

19

A

C F=AB'+BC+AC

E

D

B

A

G

0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns

B

D

E

G

F

Removing Hazard

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21/07/201220

Hazards in Combinational Circuits

Why do we care about hazards?

Combinational networks dont care the network will function correctly

Synchronous sequential networks dont care - the input signals must be stable

within setup and hold time of flip-flops

Asynchronous sequential networks hazards can cause the network to enter an incorrect state

circuitry that generates the next-state variables must be hazard-free

Power consumption is proportional tothe number of transitions

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Removing Static 1- Hazard

F(A,B,C,D) = (0,1,4,5,6,7,14,15) = A'C' + BC

A B

1 1

1 1

0 0

1 1

00 01 11 10

00

01

11

10

C D

0 0

0 0

1 1

0 0

A'C'

BC

Cover the cube by

addingA'B to eliminate

the static 1-hazard

F = A'C' + BC + A'B

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In the logic diagram of

F = A'C' + BC

With a = 0, b = 1, and D = 1, a glitch can occur as c

changes from 1 to 0 or visa-versa. So we add the redundant termA'B by overlapping the two

groups to eliminates the static 1-Hazard

Removing Static 1- Hazard

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Removing Static 0- Hazard

F(A,B,C,D) = (0,1,4,5,6,7,14,15) = (A' + C) (B + C')

A B

1 1

1 1

0 0

1 1

00 01 11 10

00

01

11

10

C D

0 0

0 0

1 1

0 0

AC'

Add AB' to

eliminate static-0hazard

Note:AB'D covers

too, but is not

minimal.

F' = AC' + B'C + AB' So F = (A' + C) (B + C') (A' + B)

B'C

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Dynamic hazards are a consequence of multiple static hazards

caused by multiply re-convergent paths in a multilevel circuit.

Dynamic hazards are not easy to eliminate.

Elimination of all static hazards eliminates dynamic hazards.

Approach: Transform a multilevel circuit into a two-level

circuit and eliminate all of the static hazards.

Dynamic Hazard (Multiple glitches)

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Dynamic Hazard (Multiple glitches)

The redundantcube eliminatesthe static 1-hazardand assures thatF_dynamic willnot depend on thearrival of the effectof the transition inC.

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Dynamic Hazard (Multiple glitches)

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Designing with NAND and NOR Gates (1)

21/07/2012UAH-CPE/EE 422/522 AM

27

Any logic function can be realized using only NAND or

NOR gates

Implementation of NAND and NOR gates is easier than

that of AND and OR gates (e.g., CMOS)

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NAND Gate

28

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NAND Gate

29

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NAND Gate

30

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NAND Gate

31

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