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FPGA-BASED LOW LEVEL CONTROL OF CERN’S LINAC 3 CAVITIES
Javier Serrano
CERN, Geneva, Switzerland
Summary
ContextThe problemTraditional analog solutionsThe LRFSC cardControl system designImplementation and results
Ions in the LHC
ECR
RFQLINAC
3
LEIR
PSSPS
LHC
Pb27+
upgradedto 200 A
Linac Repetitionrate 200ms to
400ms
4.2 MeV/nucl
StripperPb27+ to Pb54+
50 A Energy rampingcavity to be added
72 MeV/nucl
5.9 GeV/nucl
177 GeV/nucl
Accumulation of9x108 ions in two
bunches every 3.6s(to 4 LHC bunches)
StripperPb54+ to Pb82+
4 bunchlet pairs(to reduce SPS tune shift)
every 3.6s
Accumulation of 8 to 13LEIR/PS batches, deliveryof 32 to 52 bunches to the
LHC per cycle
592 bunches of 0.7x108 ions per ringfilling time: ~10min/ring
Luminosity: ~ 1027cm-2s-1
The problem
The amplitude A and phase φ of the RF electric field in a cavity are subject to external perturbations (50 Hz power, temperature, the beam…).
A feedback system is needed to control it, i.e. measure it, compare it and adjust it.
A
ωt
φ
I
Q
x(t) = A cos(ωt - φ)orx(t) = I cos(ωt) + Q sin(ωt) withI = A cos(φ)Q = A sin(φ)
φ
A
Overview of feedback system
CAVITY
Pickup
Solid state amplifier
Controller
Forward
Reflected
Cavity
Set Points from Control RoomQ
I
Analog demodulation
X
x(t)
LO (Local Oscillator)
Low passfilter
Low passfilter A
φ
Phase detector has limited range and exhibits AM to PM coupling.
X
X
LO0º
90º
Low passfilter
x(t)
Low passfilter
I
Q
Both paths must be identical: perfect splitter, perfect 90º, etc.
Digital IQ demodulation
XLow pass
filter
x(t)
LO (Local Oscillator) ADC
clkFPGA
xd(t)
FPGA implements multiplication by sine and cosine tables and digital low pass filtering.
If clk’s frequency is exactly four times that of xd(t):
De-mux
xs(t)
xs(t) +/-1
+/-1
LPF
LPF
I
Q
One single analog path
LRFSC card block diagram
14A/D20.256 MHz
BPF
81.024 MHz
14A/D20.256 MHz
BPF
81.024 MHz
14A/D20.256 MHz
BPF
81.024 MHz
IQ
2x2
IsetQset
IrFwdQrFwd
ICav
QCav
PID
IrRef QrRef
IrCavQrCav
Q
L
Amp
(-fAmp)
IlrnQlrn
IeCavQeCav
ResonanceControl
Algorithm
IFwd
QFwd
IRef
QRef
IRefQRef
IFwdQFwd
IOutQOut
DAC101.28 MHz
BPF
81.024 MHzLO
101.28 MHzReflected
101.28 MHzForward
101.28 MHzCavity
101.28 MHzOutput
81.024 MHz
162.048 MHz
Sin Cos
20.256 MHzBPF
14
IpreQpre
2x2
A B C DABCD
A B C DABCD
PI
PILPF LPF
|IQ|
|IQ|
AB
AB
-++-
os os
RAMRAM
S.P.RAM
F.F.RAM
DiagnosticTest Point
IQ RAM
40.512 MHz
DUALCHANNEL
DAC
To FrontPanel
To VME
Diagnostic Output (1 of 4)
FPGAXilinx
XC2V2000
IQ
2x2
IQ
2x2DigitalFilter
RF EnvelopeOutput (-20 dBc)
ICav
QCav
ICav QCav
RFON/OFF
ToPLD
BEAMON/OFF
ToPLD
FASTPROTECT
ToPLD
20.256 MHzClock
ToPLD
40.512 MHzClock
ToPLD
81.024 MHzClock
ToPLD
DAC
100 kHz
±5V signal
AD6645WJ HMJ-5
WJ AH31
WJ AH31 AD9755
18x256k SRAM6.4 ms of full IQ data
AMPAMP
The LRFSC card
Control system design: the cavity model
20
2 2s
2σ C(s)
s
s
σ C(s)
2
2
)C(j
|)C(j|
dB3
0
2
|)C(j|
dB3
2
)C(j
Transfer functions:
RF I and Q
Control system design: methodology
1. Plot frequency response of open loop system (PI controller followed by cavity).
2. Set KI/KP = so that the controller zero cancels the cavity pole. This gives us one equation.
3. The other equation needed comes from the requirement that the cabling delay should represent 45° at the frequency where the open loop gain is 1. This gives a total phase margin of 45°, ensuring global stability.
s
K K I
P
PI Controller
s Cavity
F-sTe
ForwardDelay
R-sTe
ReverseDelay
OutputSetPoint
I(s) O(s)
+-
+
Control system design: implementation
Digital PI using rectangular rule for integration.
28 bit integrator with anti-windup.Saturation preferred to scaling
throughout except in IQ Modulator.Data paths vary between 14 and 41 bits
inside the design. Tradeoff between speed and accuracy.
HW/SW interaction
RF ON
400 s200 ms
VME InterruptPowerPC VME master writes control information and reads back diagnostics
Results
Trace Kp Ki(kHz)
f -3dB
(kHz)
f -3dB
(kHz)*
f 0dB
(kHz)
f 0dB
(kHz)*
1 (top) 10.25 227.6 472 468 390 386
2 (middle) 9.25 205.1 425 425 322 336
3 (bottom) 8.0 177.3 359 360 200 246
Theory Experiment
Thanks!