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Chapter 2

Hardware Description

2.1 Circuit diagram

Figure 2.1 Circuit Diagram Fpga Based Motor Drive

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2.2 SPARTAN 3A/3AN STARTER KIT

2.2.1 FPGA

Field-programmable gate array (FPGA) is an integrated circuit designed to be

configured by the customer or designer after manufacturing—hence "field-programmable".

FPGAs are programmable digital logic chips. The FPGA configuration is generally

specified using a hardware description language (HDL), similar to that used for

an application-specific integrated circuit (ASIC).

Before the advent of programmable logic, custom logic circuits were built at the

board level using standard components, or at the gate level in expensive application-

specific (custom) integrated circuits. The FPGA is an integrated circuit that contains many

(64 to over 10,000) identical logic cells that can be viewed as standard components.  Each

logic cell can independently take on any one of a limited set of personalities. The

individual cells are interconnected by a matrix of wires and programmable switches. A

user's design is implemented by specifying the simple logic function for each cell and

selectively closing the switches in the interconnect matrix.  The array of logic cells and

interconnects form a fabric of basic building blocks for logic circuits.  Complex designs

are created by combining these basic blocks to create desired circuit.

Figure 2.2.1 Comparison of ASIC and FPGA

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2.2.2 FPGA ARCHITECTURE

The architecture of the FPGA is as shown in the figure. It consists of logic block, routing

block, Input output or I/O Blocks.

Figure2.2.2 logic blocks

Basically the fundamental units of FPGA are a Logic Block. It is programmable in nature

so sometimes it is also called as Programmable Logic Block. Inside these logic blocks

additional digital circuitry is present that makes it actually programmable in nature.

Basically a logic block constitutes of LUTs that stands for Look up Tables. FPGAs are

built from one basic "logic-cell", duplicated hundreds or thousands of time. A logic-cell is

basically a small lookup table ("LUT"), a D-flip-flop and a 2-to-1 mux (to bypass the flip-

flop if desired).The LUT is like a small RAM and has typically 4 inputs, so can implement

any logic gate with up to 4-inputs.

Figure 2.2.3 Logic cell

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Figure 1.1 FPGA Architecture

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Routing Blocks

A) Interconnects

Each logic-cell can be connected to other logic-cells through interconnect

resources (wires/MUXs placed around the logic-cells).

Each cell can do little, but with lots of them connected together, complex logic

functions can be created.

FPGAs also have fast dedicated lines in between neighboring logic cells.

The most common type of fast dedicated lines is “carry chains".

Carry chains allow creating arithmetic functions (like counters and adders)

efficiently (low logic usage & high operating speed).

Older programmable technologies (PAL/CPLD) don't have carry chains and so

are quickly limited when arithmetic operations are required.

Also a programmable switch is present in order to switch the interconnections

between various Logic blocks and I/O Blocks.

Figure2.2.2 Interconnects

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B) I/O Blocks

Input Output blocks that are present in the FPGAs acts as an interface to the external

environment, which can help connect FPGAs to the outside world.

Today’s FPGAs provide support for dozens of I/O standards thus providing the ideal

interface bridge in your system. I/O in FPGAs is grouped in banks with each bank

independently able to support different I/O standards. Today’s leading FPGAs provide

over a dozen I/O banks, thus allowing flexibility in I/O support.

2.3 XILINX

XILINX invented the FPGA. Basically it is the Technology leader. Its General philosophy

is to provide all the features possible, at the cost of extra complexity. The Spartan 3 FPGA

can be programming directly from the Xilinx ISE package, greatly simplifying and

expediting the design process. Programming the FPGA using a schematic, state diagram,

or verilog module is a universally simple and straightforward process.

The Spartan 3 FPGA board is a robust board containing many features. A list of key

features and their location on the board is listed below, and all of these features are

explained in great detail in the manual provided with the FPGA(UG334).

1. VGA (HD-15) Monitor Port 9. Switches (8)

2. 9-pin (DB-9) 10. Buttons (4)

3. Power Connector 11. LEDs (8)

4. A1 Expansion Port 12. Power LED

5. A2 Expansion Port 13. Spartan 3 FPGA Core

6. B1 Expansion Port 14. Program LED

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7. PS/2 Port 15. JTAG Port (used to program the FPGA)

8. Seven Segment Displays

Figure 1.3 FPGA Overview

3. PicoBlaze 8-bit Microcontroller

Pico Blaze™ is a fully embedded 8-bit RISC microcontroller core optimized for 7-series

and older Xilinx FPGA architectures. This reference design is offered free to Xilinx users,

and comes with an easy-to-use code assembler KCPSM6 (or KCPSM3 for older FPGA

families),VHDL and Verilog source code, simulation models, comprehensive

documentation and reference designs.

3.4.1Key Features

Supports Virtex-7, Kintex-7, Artix-7and older Xilinx FPGA families

Very small size as small as 26 slices depending on device family

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Up to 4K 18-bit instructions

Up to 240MHz performance

Everything in FPGA - no external components required

Highly integrated for implementing non-time critical state machine

Predictable fast interrupt response

3.5Extended Spartan-3A Family Features

3.5.1 General Description

The Extended Spartan®-3A family of Field-Programmable Gate Arrays (FPGAs) solves

the design challenges in many high volume, Cost-sensitive electronic applications. With 12

devices ranging from 50,000 to 3.4 million system gate, the Extended Spartan-3A family

provides a broad range of densities and package options, integrated DSP MACs, and low

total system cost while increasing functionality. The Extended Spartan-3A family includes

the Spartan-3A devices and the higher density Spartan-3A DSP devices. It also includes

the non-volatile Spartan-3AN devices, which combine leading-edge FPGA and flash

technologies to provide a new evolution in security, protection and functionality, ideal for

space-critical or secure applications.

The Extended Spartan-3A family improves system performance and reduces the cost of

configuration. These enhancements, combined with proven 90 nm process technology,

deliver more functionality and bandwidth per dollar. Because of its exceptionally low cost,

the Extended Spartan-3A family is ideally suited to a wide range of consumer electronics

applications, including broadband access, home networking, display/projection, and digital

television equipment.

The Extended Spartan-3A family is a superior alternative to mask-programmed ASICs.

FPGAs avoid the high initial cost, lengthy development cycles, the inherent inflexibility of

conventional ASICs, and permit field design upgrades.

3.5.2Summary of Extended Spartan-3A Family Features

• Very low-cost, high-performance logic solution for high volume, cost-conscious

applications

• Low-cost QFP and BGA packaging, Pb-free options

• Flexible power management

• Leading connectivity platform

• Abundant, flexible logic resources

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• Dedicated resources for high-speed digital signal processing applications

• Precise clock management with up to eight Digital Clock Managers (DCMs)

• Integrated flash memory in Spartan-3AN devices

• Eight low-skew global clock networks, eight additional clocks per half device, plus

abundant low-skew routing

• Hierarchical Select RAM memory architecture

• Configuration interface to industry-standard PROMs

• Complete Xilinx® ISE® and free Web PACK development system software support

• Micro Blaze and PicoBlaze™ embedded processors reduce risk

• Low-cost starter kits from Xilinx, distributors, and third parties

• XA versions available for automotive applications

• Use fewer standard components

• Increase system reliability

• Flexible power management

• Low 1.2V core voltage

• Selectable I/O voltage with 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

• Full 3.3V ±10% compatibility and hot swap compliance

• Dual-range auxiliary voltage allows 3.3V setting to simplify 3.3V-only design

• Suspend and hibernate modes reduce system power

• Leading connectivity platform

• Multi-standard SelectIO™ interface pins support most popular and emerging signaling

standards

• Up to 519 I/O pins or 227 differential signal pairs

• LVCMOS, LVTTL, HSTL, SSTL single-ended I/O

• Selectable output drive, up to 24 mA per pin

• QUIETIO standard reduces I/O switching noise

• 640+ Mb/s data transfer rate per differential I/O

• LVDS, RSDS, mini-LVDS, HSTL/SSTL differential

I/O with integrated differential termination resistors

• Enhanced Double Data Rate (DDR) support

• Compliant to 32-/64-bit, 33/66 MHz PCI™ technology

• Abundant, flexible logic resources

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• Densities up to 53,712 logic cells, including optional shift register or distributed RAM

support

• Efficient wide multiplexers and wide logic improve performance and density

• Fast look-ahead carry logic

• IEEE 1149.1/1532 JTAG programming/debug port

• Dedicated resources for high-speed digital signal processing applications

• 18-bit by 18-bit multiplier with optional pipeline

• 250 MHz XtremeDSP™ DSP48A block in the largest two devices

- 48-bit accumulator for multiply-accumulate (MAC) operation

- Integrated 18-bit pre-adder for multiply or multiply-add operation

- Optional cascaded Multiply or MAC

- Fills the DSP performance gap between DSP processors and high-end custom solutions

• Precise clock management with up to eight Digital Clock Managers (DCMs)

• Clock skew elimination (delay locked loop)

• Frequency synthesis, multiplication, division

• High-resolution phase shifting

• Wide frequency range (5 MHz to over 320 MHz)

• Integrated flash memory in Spartan-3AN devices

• Up to 16 Mb of internal flash for configuration and application storage

• Up to 11 Mb of user storage available for embedded processing, code shadowing, or

scratchpad memory

• Enables single-chip board designs for spaceconscious applications

• Enhanced design security with flash memory protection and security register

• Eight low-skew global clock networks, eight additional clocks per half device, plus

abundant low-skew routing

• Hierarchical SelectRAM memory architecture

• Up to 2.2 Mb of fast block RAM with byte write enables for processor applications

• Up to 373 Kb of efficient distributed RAM

• External DDR/DDR2 SDRAM support up to 400 Mb/s

• Configuration interface to industry-standard PROMs

• Low-cost, space-saving SPI serial flash PROM

• x8 or x8/x16 parallel NOR flash PROM

• Low-cost Xilinx Platform Flash with JTAG

• Load multiple bitstreams under FPGA control with MultiBoot capability

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• Complete Xilinx ISE and free WebPACK development system software support

• Industry’s most comprehensive IP library

• MicroBlaze and PicoBlaze embedded processors

• Integrate soft processor into FPGA to reduce Bill of Materials

• Reduce obsolescence risks with soft processors

• Low-cost QFP and BGA packaging, Pb-free options

• Common footprints support easy density migration

• Low-cost starter kits from Xilinx, distributors, and third parties

• Complete starter kits designed for cost-sensitive, high-volume applications.

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Figure 3.6 Spartan-3A packages

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3.6Architectural Overview

The Extended Spartan-3A family architecture consists of five fundamental programmable

functional elements:

• Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that

implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide

variety of logical functions as well as store data.

• Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the

internal logic of the device. IOBs support bidirectional data flow plus 3-state operation.

Supports a variety of signal standards, including several high-performance differential

standards. Double Data-Rate (DDR) registers are included.

• Block RAM provides data storage in the form of 18-Kbit dual-port blocks.

• Multiplier or DSP48A Blocks accept two 18-bit binary numbers as inputs and calculate

the product. The DSP48A blocks in the two largest members of the Extended Spartan-3A

family add an 18-bit pre-adder and 48-bit accumulator.

• Digital Clock Manager (DCM) Blocks provide selfcalibrating, fully digital solutions for

distributing, delaying, multiplying, dividing, and phase-shifting clock signals.

Configuration

The Extended Spartan-3A family is programmed by loading configuration data into robust,

reprogrammable, static CMOS configuration latches (CCLs) that collectively control all

functional elements and routing resources. The FPGA configuration data is stored

externally in a PROM or some other nonvolatile medium, either on or off the board, or

stored within the FPGA in the nonvolatile Spartan-3AN devices. After applying power, the

configuration data is written to the FPGA using any of eight different modes:

• Master Serial from a Xilinx Platform Flash PROM

• Serial Peripheral Interface (SPI) from an industrystandard SPI serial flash

• Internal SPI flash memory (Spartan-3AN devices)

• Byte Peripheral Interface (BPI) Up from an industrystandard x8 or x8/x16 parallel NOR

flash

• Slave Serial, typically downloaded from a processor

• Slave Parallel, typically downloaded from a processor

• Boundary Scan (JTAG), typically downloaded from a processor or system tester

• MultiBoot configuration MultiBoot configuration allows two or more FPGA

configuration bitstreams to be stored in a single SPI serial flash or a parallel NOR flash.

The FPGA application controls which configuration to load next and when to load it.

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Additionally, each FPGA in the Extended Spartan-3A family contains a unique, factory-

programmed Device DNA identifier useful for tracking purposes, anti-cloning designs, or

IP protection.

I/O Capabilities

The Select I/O interface of the Extended Spartan-3A family supports many popular single-

ended and differential standards. The maximum number of user I/Os and input-only pins

for each device/package combination.

FPGAs in the Extended Spartan-3A family support the following single-ended standards:

• 3.3V low-voltage TTL (LVTTL)

• Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,1.5V, or 1.2V

• 3.3V PCI at 33 MHz or 66 MHz

• HSTL I, II, and III at 1.5V and 1.8V, commonly used in memory applications

• SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used for memory applications

FPGAs in the Extended Spartan-3A family support the following differential standards:

• LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or 3.3V

• Bus LVDS I/O at 2.5V

• TMDS I/O at 3.3V

• Differential HSTL and SSTL I/O

• LVPECL inputs at 2.5V or 3.3V

3.7 Clock Sources

3.7.1 Overview

The Spartan®-3A/3AN FPGA Starter Kit board supports three primary clock input

Sources.

The board includes an on-board 50 MHz clock oscillator.

Clocks can be supplied off-board via an SMA-style connector. Alternatively, the

FPGA can generate clock signals or other high-speed signals on the SMA-style

connector.

A 133 MHz clock oscillator is installed in the CLK_AUX socket. Optionally

substitute a separate eight-pin DIP-style clock oscillator in the provided socket.

1)CLK_SMA(U12)

2)CLK_AUX(V12)

3)CLK_50MHZ(E12)

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Figure 3.7 clock sources

3.7.2Clock Connections

Each of the clock inputs connect directly to a global buffer input.Each of the clock inputs

also optimally connects to an associated DCM.

Only the CLK_AUX or the CLK_SMA input can use the associated DCM at any time.

However, both inputs are available as clock inputs.

50 MHz On-Board Oscillator

The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The

oscillator is accurate to ±2500 Hz or ±50 ppm.

Auxiliary Clock Oscillator Socket

A 133 MHz clock oscillator is installed in the auxiliary clock oscillator socket. The

provided eight-pin socket accepts clock oscillators that fit the eight-pin DIP (8DIP)

footprint. Substitute the oscillator in this socket if the FPGA application requires a

frequency other than 50 MHz or 133 MHz. Alternatively, use the FPGA’s Digital

Clock Manager (DCM) to generate or synthesize other frequencies from the on-board

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50 MHz or 133 MHz oscillator. Caution! Be aware of the pin 1 orientation on the

crystal oscillator when installing it in the associated socket.

3.7.3 SMA Clock Input or Output Connector

To provide a clock from an external source, connect the input clock signal to the SMA

connector. The FPGA can also generate a single-ended clock output or other high-speed

signal on the SMA clock connector for an external device.

3.7.4 UCF Constraints

The clock input sources require two different types of constraints. The location constraints

define the I/O pin assignments and I/O standards. The period constraints define the clock

period and consequently the clock frequency and the duty cycle of the incoming clock

signal.

NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33;

NET "CLK_AUX" LOC = "V12"| IOSTANDARD = LVCMOS33;

NET "CLK_SMA" LOC = "U12"| IOSTANDARD = LVCMOS33;

3.7.5 Clock Period Constraints

The Xilinx ISE® development software uses timing-driven logic placement and routing.

Set the clock PERIOD constraint as appropriate. An example constraint appears down for

the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which

equates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to

60%.

# Define clock period for 50 MHz oscillator

NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;

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3.8Slide Switches

These switches are used to make clockwise or anti clockwise movement of stepper

motor and also to start or stop movement in any direction.

SW3 SW2 SW1 SW0

(U8) (T9) (U10) (V8)

The slide switches are located in the lower right corner of the board and are labeled SW3

through SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.When

in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High. When

DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low.

The switches typically exhibit about 2 ms of mechanical bounce. There is no active

debouncing circuitry, although such circuitry could easily be added to the FPGA design

programmed on the board.

The UCF constraints for the four slide switches, including the I/O pin assignment and the

I/O standard used. The PULLUP resistor is not required, but it defines the input value

when the switch is in the middle of a transition.

NET "SW<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;

NET "SW<1>" LOC = "U10"| IOSTANDARD = LVCMOS33 ;

NET "SW<2>" LOC = "U8" | IOSTANDARD = LVCMOS33 ;

NET "SW<3>" LOC = "T9" | IOSTANDARD = LVCMOS33 ;

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UCF Constraints for Slide Switches

Push-Button Switches

The Spartan-3A/3AN Starter Kit board has four momentary-contact push-button switches,

shown in Figure 2-5. The push buttons are located in the lower right corner of the board and are

labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The FPGA pins that connect to the

push buttons appear in parentheses in Figure 2-5, and the associated UCF is listed in Figure 2-7.

Operation

Pressing a push button connects the associated FPGA pin to 3.3V, as shown in Figure 2-6. Use an

internal pull-down resistor within the FPGA pin to generate a logic Low when the button is not

pressed. Figure 2-7 shows how to specify a pull-down resistor within the UCF. There is no active

debouncing circuitry on the push button.

6 Discrete LED’s

Output from ADC is displayed on LCD as well as is displayed on eight discrete

LED’s.For logic 1 LED glows and for logic 0 it is off.Hence 8-bit binary value can be

displayed and can be cross checked against analog value from potentiometer.

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Figure 2.7 Discrete LED’s

operation

Each LED has one side connected to ground and the other side connected to a pin on the device

via a 390Ω current limiting resistor. To light an individual LED, drive the associated FPGA control

signal High. If the FPGA is not yet configured, the LEDs may be dimly lit because pull-up resistors

are enabled during configuration. The FPGA’s PUDC_B pin is connected to GND on the board.

Optional Discrete LEDs

The Spartan-3A/3AN Starter Kit board provides two optional LEDs, shown in Figure 2-14.

Depending on which features are used by an application, these LED connections may be also used

as user-I/O pins.

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Figure AWAKE and init_B LEDs

AWAKE LED

The yellow-colored AWAKE LED connects to the FPGA’s AWAKE pin and is used if the FPGA

Suspend mode is enabled in the bitstream. If the Suspend mode is not used, then the FPGA’s

AWAKE pin is available as a full user-I/O pin. If the FPGA is not yet configured, the FPGA’s AWAKE

pin is dimly lit because pull-up resistors are enabled during configuration. The FPGA’s PUDC_B pin

is connected to GND on the board. To light the AWAKE LED in an application, drive the AWAKE pin

High.

INIT_B LED

The red-colored INIT_B LED serves multiple purposes:

• At power-up or when the PROG_B button is pressed, the LED flashes momentarily while

theFPGA clears its configuration memory.

• If configuration fails for any reason, then the FPGA’s DONE LED will be unlit and the INIT_B LED

will light. This indicates that the FPGA could not successfully configure.

• After the FPGA successfully completes, the INIT_B pin is available as a generalpurpose user-I/O

pin. If no signal drives INIT_B, then it is defined as an input pin with a pull-down resistor.It

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might appear that the LED dimly glows. Drive the INIT_B pin High to turn off the LED or

Low to light the LED.

• If using the Readback CRC feature, the INIT_B pin is reserved and signals a CRC error after

configuration. If such an error occurs, the FPGA drives INIT_B Low, lighting the LED. If

using the INIT_B pin as a user-I/O pin after configuration, drive the pin Low to light the

LED and High to shut it off. Jumper J46, shown in Table 4-2, page 40, must be in either the

“Disabled” or “Enabled during Configuration” setting.

The “Always Enabled” setting for Jumper J46 allows the FPGA A to read additional data from the

Platform Flash PROM after configuration, as described in Xilinx application note XAPP694.

Expansion Connectors

The Spartan®-3A/3AN FPGA Starter Kit board provides a variety of expansion connectors for easy

interface flexibility to other off-board components. The board includes the I/O expansion

headers shown in Figure 15-1.

• A Hirose 100-pin edge connector with 43 associated FPGA user-I/O pins

• Two stake pin headers, each that supports up to five differential data channels plus a differential

clock or 12 single-ended I/O signals.

• Two six-pin Peripheral Module connections, plus mounting holes for a third module.

• Landing pads for an Agilent or Tektronix connectorless probe

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Expansion Connectors

Six-Pin Accessory Headers

The six-pin accessory headers provide easy I/O interface expansion using the various Digilent

Peripheral Modules.

J18 Header

The J18 header, shown in Figure 15-8, is located in the bottom right corner of the board, along the

right edge, adjacent to the BTN_EAST push button. It uses a female six-pin 90° socket.

Four FPGA pins connect to the J18 header, J18_IO. The board supplies 3.3V to the

accessory board mounted in the J18 socket on the bottom pin.

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FPGA Connections to the J18 Accessory Header

J19 Header

The J19 header, shown in Figure 15-9, is left unpopulated on the board. Four FPGA pins connect

to the J19 header, J19_IO. The board supplies 3.3V to the accessory board mounted in the

J19 socket on the bottom pin.

FPGA Connections to the J19 Accessory Header

J20 Header

The J20 header, shown in Figure 15-10, is the top-most six-pin connector along the right edge of

the board. It uses a female six-pin 90° socket. Four FPGA pins connect to the J20 header,

J20_IO. The board supplies 3.3V to the accessory board mounted in the J20 socket on the

bottom pin.

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FPGA Connections to the J20 Accessory Header

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2.2.1 MCT2E Opto-coupler

Opto coupler is used as interface between IR sensor and FPGA board. We use this

because the logic levels of IR sensor and that of FPGA are different. FPGA logic 0 is 0V

and logic 1 is 3.3v where as IR sensor’s logic 0 is 0V and logic 1 is 5V hence in order to

make both of them compatible with each other we use this opto coupler.

2.2.1.1 Description

Standard Single Channel Phototransistor Couplers. The MCT2/ MCTE family is an

Industry Standard Single Channel Phototransistor. Each optocoupler consists of gallium

arsenide infrared LED and a silicon NPN phototransistor. These couplers are Underwriters

Laboratories (UL) listed to comply with a 5300 VRMS isolation test voltage. This isolation

performance is accomplished through Vishay double molding isolation manufacturing

process. Compliance to DIN EN 60747-5-2(VDE0884)/ DIN EN 60747-5-5 pending

partial discharge isolation specification is available for these families by ordering option 1.

These isolation processes and the Vishay ISO9001 quality program results in the highest

isolation performance available for a commercial plastic phototransistor optocoupler.

The devices are available in lead formed configuration suitable for surface mounting and

are available either on tape and reel, or in standard tube shipping containers.

2.2.1.2Features of MCT2E

• Interfaces with common logic families

• Input-output coupling capacitance < 0.5 pF

• Industry Standard Dual-in line 6-pin package

• 5300 VRMS isolation test voltage

2.2.1.3Applications

AC mains detection

Reed relay driving

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Switch mode power supply feedback

Telephone ring detection

Logic ground isolation

Logic coupling with high frequency noise rejection

Figure 2.2 MCT2E chip

Figure 2.3 pin diagram of MCT2E

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2.2.2 ULN2003A

When pulses are sent from fpga to stepper motor ,the pins at which pulses are

going will not have enough current level to drive the motor and hence level of current must

be increased and therefore we use ULN2003A to amplify current level. This has

Darlington pair which increases current levels.

DESCRIPTION

The ULN2001A, ULN2002A, ULN2003 andULN2004A are high voltage, high

current Darlington arrays each containing seven open collector Darlington pairs with

common emitters. Each channel rated at 500mA and can withstand peak currents of

600mA. Suppression diodes are included for inductive load driving and the inputs are

pinned opposite the outputs to simplify board layout.

These versatile devices are useful for driving a wide range of loads including

solenoids, relays DC motors, LED displays filament lamps, thermal printheads

and high power buffers. The ULN2001A/2002A/2003A and 2004A are supplied

in 16 pin plastic DIP packages with a copper leadframe to reduce thermal resistance. They

are available also in small outline package (SO-16) as ULN2001D/2002D/2003D/2004D.

Figure 2.4 ULN2003A chip

Features

SEVEN DARLINGTONS PER PACKAGE OUTPUT CURRENT 500mA PER

DRIVER

(600mA PEAK) OUTPUT VOLTAGE 50V INTEGRATED SUPPRESSION

DIODES FOR

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INDUCTIVE LOADS OUTPUTS CAN BE PARALLELED FOR

HIGHER CURRENT TTL/CMOS/PMOS/DTL COMPATIBLE INPUTS INPUTS

PINNED OPPOSITE OUTPUTS TO

SIMPLIFY LAYOUT

Figure 2.5 Pin diagram of ULN2003A

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Figure 2.6 Schematic of ULN2003A

Table 2.1 Absolute maximum rating

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Table 2.2Electrical characteristics

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Stepper motor and drivers

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A stepper motor is a brushless, synchronous electric motor that converts digital pulses into mechanical shaft

rotation. Every revolution of the stepper motor is divided into a discrete number of steps, in many cases 200

steps, and the motor must be sent a separate pulse for each step. The stepper motor can only take one step at a

time and each step is the same size. Since each pulse causes the motor to rotate a precise angle, typically 1.8°, the

motor's position can be controlled without any feedback mechanism. As the digital pulses increase in frequency,

the step movement changes into continuous rotation, with the speed of rotation directly proportional to the

frequency of the pulses. Step motors are used every day in both industrial and commercial applications because

of their low cost, high reliability, high torque at low speeds and a simple, rugged construction that operates in

almost any environment.

1.4Stepper Motor Advantages

1. The rotation angle of the motor is proportional to the input pulse.

2. The motor has full torque at standstill (if the windings are energized).

3. Precise positioning and repeatability of movement since good stepper motors have an accuracy of 3 to 5%

of a step and this error is non-cumulative from one step to the next.

4. Excellent response to starting/stopping/reversing.

5. Very reliable since there are no contact brushes in the motor. Therefore the life of the step motor is

simply dependant on the life of the bearing.

6. The stepper motors response to digital input pulses provides open-loop control, making the motor simpler

and less costly to control.

7. It is possible to achieve very low speed synchronous rotation with a load that is directly coupled to the

shaft.

8. A wide range of rotational speeds can be realized as the speed is proportional to the frequency of the

input pulses.

1.5Types of Step Motors

There are three basic types of step motors: variable reluctance, permanent magnet, and hybrid. This discussion

will concentrate on the hybrid motor, since these step motors combine the best characteristics of the variable

reluctance and permanent magnet motors. They are constructed with multi-toothed stator poles and a permanent

magnet rotor. Standard hybrid motors have 200 rotor teeth and rotate at 1.8º step angles. Because they exhibit

high static and dynamic torque and run at very high step rates, hybrid step motors are used in a wide variety of

commercial applications including computer disk drives, printers/plotters, and CD players. Some industrial and

scientific applications of stepper motors include robotics, machine tools, pick and place machines, automated

wire cutting and wire bonding machines, and even precise fluid control devices.

1.6Step Modes

Keshav memorial

1.9Driver Technology Overview

The stepper motor driver receives step and direction signals from the indexer or control system and converts them

into electrical signals to run the step motor. One pulse is required for every step of the motor shaft. In full step

mode, with a standard 200-step motor, 200 step pulses are required to complete one revolution. The speed of

rotation is directly proportional to the pulse frequency. Some drivers have an on-board oscillator which allows the

use of an external analog signal or joystick to set the motor speed.

Speed and torque performance of the step motor is based on the flow of current from the driver to the motor

winding. The factor that inhibits the flow, or limits the time it takes for the current to energize the winding, is

known as inductance. The effects of inductance, most types of driver circuits are designed to supply a greater

amount of voltage than the motor's rated voltage. The higher the output voltage from the driver, the higher the

level of torque vs. speed. Generally, the driver output voltage (bus voltage) should be rated at 5 to 20 times higher

than the motor voltage rating. In order to protect the motor from being damaged, the step motor drive should be

current-limited to the step motor current rating.

1.10Choosing a Stepper Motor and Drive

The choice of a step motor depends on the application's torque and speed requirements. Use the motor's torque-speed curve

(found in each drive's specifications, example in figure C) to select a motor that will do the job. Every stepper drive in the

Omegamation line shows the torque-speed curves for that drive's recommended motors. If your torque and speed

requirements can be met by multiple step motors, choose a drive based upon the needs of your motion system-

step/direction, stand-alone programmable, analog inputs, microstepping- then choose one of the recommended motors for

that drive. The recommended motor list is based on extensive testing by the manufacturer to ensure optimal performance of

the step motor and drive combination.

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A stepper motor is a brushless, synchronous electric motor that converts digital pulses into mechanical shaft

rotation. Every revolution of the stepper motor is divided into a discrete number of steps, in many cases 200

steps, and the motor must be sent a separate pulse for each step. The stepper motor can only take one step at a

time and each step is the same size. Since each pulse causes the motor to rotate a precise angle, typically 1.8°, the

motor's position can be controlled without any feedback mechanism. As the digital pulses increase in frequency,

the step movement changes into continuous rotation, with the speed of rotation directly proportional to the

frequency of the pulses. Step motors are used every day in both industrial and commercial applications because

of their low cost, high reliability, high torque at low speeds and a simple, rugged construction that operates in

almost any environment.

1.4Stepper Motor Advantages

1. The rotation angle of the motor is proportional to the input pulse.

2. The motor has full torque at standstill (if the windings are energized).

3. Precise positioning and repeatability of movement since good stepper motors have an accuracy of 3 to 5%

of a step and this error is non-cumulative from one step to the next.

4. Excellent response to starting/stopping/reversing.

5. Very reliable since there are no contact brushes in the motor. Therefore the life of the step motor is

simply dependant on the life of the bearing.

6. The stepper motors response to digital input pulses provides open-loop control, making the motor simpler

and less costly to control.

7. It is possible to achieve very low speed synchronous rotation with a load that is directly coupled to the

shaft.

8. A wide range of rotational speeds can be realized as the speed is proportional to the frequency of the

input pulses.

1.5Types of Step Motors

There are three basic types of step motors: variable reluctance, permanent magnet, and hybrid. This discussion

will concentrate on the hybrid motor, since these step motors combine the best characteristics of the variable

reluctance and permanent magnet motors. They are constructed with multi-toothed stator poles and a permanent

magnet rotor. Standard hybrid motors have 200 rotor teeth and rotate at 1.8º step angles. Because they exhibit

high static and dynamic torque and run at very high step rates, hybrid step motors are used in a wide variety of

commercial applications including computer disk drives, printers/plotters, and CD players. Some industrial and

scientific applications of stepper motors include robotics, machine tools, pick and place machines, automated

wire cutting and wire bonding machines, and even precise fluid control devices.

1.6Step Modes