FPGA based system design

Programmable logic. FPGA Introduction FPGA Architecture Advantages & History of FPGA FPGA-Based System Design

Goals and Techniques Hierarchical Design Design Abstraction Methodologies

Prepared By

AJIT SARAF

Programmable logic.

Simple Programmable Logic Device (SPLD) The SPLD was the original PLD and is still available

for small-scale applications. Generally, an SPLD can replace up to ten fixed-

function ICs and their interconnections, depending on the type of functions and the specific SPLD.

Most SPLDs are in one of two categories: PAL and GAL.

A PAL (programmable array logic) is a device that can be programmed one time.

It consists of a programmable array of AND gates and a fixed array of OR gates, as shown in Figure.

Simple Programmable Logic Device (SPLD) A GAL (generic array logic) is a device that is

basically a PAL that can be reprogrammed many times.

It consists of a reprogrammable array of AND gates and a fixed array of OR gates with programmable outputs, as shown in Figure.

Block diagrams of SPLDs

Complex Programmable Logic Device (CPLD) Essentially, The CPLD is a device containing multiple

SPLDs and can replace many fixed-function ICs. Figure shows a basic CPLD block diagram with four

logic array blocks (LABs) and a programmable interconnection array (PIA).

Depending on the specific CPLD, there can be from two to sixty-four LABs.

Each logic array block is roughly equivalent to one SPLD.

Generally, CPLDs can be used to implement any of the logic functions ,for example, decoders, encoders, multiplexers, demultiplexers, and adders.

General block diagram of a CPLD

FPGA An FPGA is generally more complex and has a much

higher density than a CPLD. As mentioned, the SPLD and the CPLD are closely

related. FPGA, however, has a different internal structure

(architecture), as illustrated in Figure. The three basic elements in an FPGA are the logic

block, the programmable interconnections, and the input/output (I/O) blocks.

The logic blocks in an FPGA are not as complex as the logic array blocks (LABs) in a CPLD, but generally there are many more of them.

Basic structure of an FPGA

FPGA When the logic blocks are relatively simple, the FPGA

architecture is called fine-grained. When the logic blocks are larger and more complex,

the architecture is called coarse-grained. The I/O blocks are on the outer edges of the structure

and provide individually selectable input, output, or bidirectional access to the outside world.

The distributed programmable interconnection matrix provides for interconnection of the logic blocks and connection to inputs and outputs.

Large FPGAs can have tens of thousands of logic blocks in addition to memory and other resources.

FPGA A typical FPGA ball-grid array package is shown in

Figure. These types of packages can have over 1000 input and

output pins.

FPGA Field Programmable Gate Arrays (FPGA) provide

the next generation in the programmable logic devices.

Field – Ability of the gate arrays to be programmed for a specific function by the user instead of by the manufacturer of the device.

Array – To indicate a series of columns and rows of gates that can be programmed by the end user.

As compared to standard gate array, the FPGA are larger devices.

Basic cell structure for FPGA is some what complicated than the basic cell structure of standard gate array.

FPGA FPGA uses read/write memory cell to control the

state of each connection. Read/write memory cells are volatile. (they do not

retain their state when power is removed) When power is first applied to the FPGA, all of its

read/write memory must be initialized to a state specified by a separate, external non volatile memory.

Memory typically is either a programmable read-only memory (PROM) chip attached directly to the FPGA.

Architecture of FPGA Architecture differs from those of PALs and Actel

PLDs. It consist of a large number of programmable logic

blocks surrounded by programmable I/O block. The programmable logic blocks of FPGA are smaller

and less capable than a PLD. But FPGA chip contains a lot more logic blocks to

make it more capable. These logic blocks can be interconnected with

programmable inter connections.

Architecture of FPGA The programmable logic blocks in the Xilinx family

of FPGA are called Configurable Logic Blocks (CLBs).

Xilinx architecture uses CLBs, I/O blocks (IOBs), switching interconnect matrix and an external memory chip to realize a logic function.

It uses external memory to store the interconnection information.

Therefore, the device can be reprogrammed by simply changing the configuration data stored in the memory.

Architecture of FPGA The low-end FPGAs support three kinds of

interconnects: Direct General-purpose and Long-line interconnections.

The direct interconnects connect CLBs to adjacent CLBs for localized applications with minimum propagation delay.

The general-purpose interconnects connect CLBs to other CLBs via the horizontal and vertical interconnect lines and switching matrices.

Architecture of FPGA Finally. the long-line interconnects are reserved for

signals that must be distributed to many CLBs and/or IOBs with minimum time delay distribution problems..

Internal View OF FPGA

Segment of a Xilinx 2000 series logic cell architecture showing configurable logic blocks CLBs), I/O blocks(lOBs), switching matrices and vertical and horizontal interconnect lines.

Difference Microprocessors

Used in variety of environments. Rely on software to implement functions. Generally slower and more power-hungry than custom

chips. FPGAs Complementary to the role played by microprocessors. Not custom parts. So they aren’t as good at any particular function as a

dedicated chip designed for that application. Slower and burn more power than custom logic. Relatively expensive

Advantages of FPGAs No wait time from completing the design to obtaining

a working chip. (The design can be programmed into the FPGA and tested immediately.)

Excellent prototyping vehicles (jump from prototype to product is much smaller and easier to negotiate)

Same FPGA can be reused in several different designs.

Reducing inventory costs.

PLDs Programmable logic devices. Early 1970 Two level logic structure (Fixed And & variable OR) Programmed by antifuses. (large voltages) Glue logic (needed to connect together the major

components of the system) Not seen as the main components of the system. PLDs were usually not seen as the principal

components of the system in which they were used. As digital systems became more complex, more dense

programmable logic was needed, and the limitations of PLD’s two-level logic became clear.

PLDs Two-level logic is useful for relatively small logic

functions. As levels of integration increases, it became too

inefficient.

FPGAs Multi-level logic of arbitrary depth. Used both programmable logic elements and

programmable interconnect.

History of the FPGA Ross Freeman His FPGA Consist of both programmable logic

elements and programmable interconnect structure. FPGA was also programmed using SRAM, not

antifuses. Antifuses: Switch is a device that, when electrically

programmed, forms a low resistance path SRAM: Switch is a pass transistor controlled by the

state of the SRAM bit Saving money and providing more manufacturing

options. FPGA can be reprogrammed while it was in-circuit.

History of the FPGA Xilinx and Altera uses SRAM-based FPGAs.

(Reconfigurable) Actel uses antifuses (not reconfigurable).

Application Specific Integrated Circuits (ASICs) The main alternative to an FPGA is ASIC. An ASIC is basically an integrated circuit designed

specifically for a special purpose or application.  Built only for one and only one customer. An example of an ASIC is an IC designed for a

specific line of cellular phones of a company, whereby no other products can use it except the cell phones belonging to that product line.

ASIC must be fabricated on a manufacturing line, a process that takes several months, before it can be used or even tested.

Application Specific Integrated Circuits (ASICs) They are generally faster and lower power than FPGA

equivalents. When manufactured in large volumes, they are also

cheaper. FPGA uses more transistors for a given function than

ASICs.

Goals and Techniques The logical function to be performed is only one of the

goals that must be met by an FPGA or any digital system design.

Many other attributes must be satisfied for the project to be successful.

Performance: The logic must run at a required rate. Throughput Latency Clock rate Power/energy: The chip must often run within an

energy or power budget. (battery powered system)

Goals and Techniques Design time:

FPGA are standard parts, have several advantages in design time.

Can be used as prototype. Can be programmed quickly. Can be used as parts in the final design Design cost: Depends on design time. Also depends on required support tools. FPGA tools are often less expensive than custom

VLSI tools.

Goals and Techniques Manufacturing cost: Cost of replacing the system many times. FPGA are more expensive than ASICs. FPGA are standard parts help to reduce their cost.

Design challenges Multiple level of abstraction:

FPGA design requires refining an idea through many levels of detail.

Designer can expand architecture which performs the required function into a logic design.

Multiple and conflicting costs: Expense of a particular piece of software needed to

design some piece. Depends on performance. Depends on power consumption.

Design challenges Short design time: Fast design (reducing cost & increasing revenue) Late design (not making any money at all)

Requirements and specifications Requirements:

What the system is to do. Specifications: More formal description of the function e.g.

simulator program Non-functional requirements: Performance Power consumption cost

Hierarchical Design Standard method for dealing with complex degital

designs. Commonly used in programming. A procedure is written not as a huge list of primitive

statements but as calls to simpler procedures. Each procedure breaks down the task into smaller

operations until each step is refined into a procedure simple enough to be written directly.

This technique is known as divide-and-conquer. The procedure’s complexity is conquered by

recursively breaking it down into manageable pieces.

Hierarchical Design A full adder which is the top level module being

composed of three lower level modules that are; half adder and OR gate.

Design hierarchy simplifies the design procedure and manageability in case of complex designs.

Component types

Chip designers divide and conquer by breaking the chip into a hierarchy of components.

Component consist of a body and a number of pins Full adder has pins a, b, cin, cout and sum. If we consider this full adder the definition of a type,

we can make many instances of this type.

a

b

sum

cin

Fulladder

cout

Repeating commonly used components is very useful. E.g. in building an n-bit adder from n full adders, we

typically give each component instance a name. Since all components of the same type have the same

pins, we refer to the pins on a particular component by giving the component instance name and pin name together.

Separating the instance and pin names by a dot is common practice.

If we have 2 full adders, add1 and add2, we can refer to add1.sum and add2.sum as distinct terminals.

Component types

A hierarchical logic design

Nets and Components

a b

c

i1 o2o1

p1

p2

p4

p3

b1(w)

net2 cxnet o2net

o1netnet1

Sand(x)

Large(bx)

Nets and Components The electrical connections which make up in either of

two equivalent ways: a net list or a component list. A net list gives, for each net, the terminals connected

to that net. A component list gives, for each component, the net

attached to each pin.

Net list

net2: large.p1, b1.a; net1: large.p2, b1.c; cxnet: b1.b, sand.i1; o1net: large.p3, sand.o1; o2net: sand.o2, large.p4

a b

c

i1 o2o1

p1

p2

p4

p3

b1(w)

net2 cxnet o2net

o1netnet1

Sand(x)

Large(bx)

Component list

large: p1: net2, p2: net1, p3: o1net, p4: o2net; b1: a: net2, b: cxnet, c: net1; sand: i1: cxnet, o1: o1net, o2: o2net;

a b

c

i1 o2o1

p1

p2

p4

p3

b1(w)

net2 cxnet o2net

o1netnet1

Sand(x)

Large(bx)

Hierarchical Design We can always transform one form of connectivity

description into the other form. Depends upon application, any format can be used. Some are best performed net-by-net and others

component-by-component. Any file which describes electrical connectivity is

usually called a netlist file, even if it is in component list format.

Component hierarchies

A component hierarchy

Large(bx)

b1(w) Sand(x)

componentComponent pointed to is an element in the component which points to it.

We may refer to either large/bw or large/sand.

Component hierarchies Each component is used as a black box To understand how the system works,

We only have to know each component’s input-output behavior.

Not how that behavior is implemented inside the box.

To design each black box, we build it out of smaller, simpler black boxes.

Internals of each type define its behavior in terms of the components used to build it.

If we know the behavior of our primitive components, such as transistors, we can conclude the behavior of any hierarchically described component.

Component hierarchies People can much more easily understand a 1,00,00,000

gate hierarchical design than the same design expressed directly as a million gates wired together.

The hierarchical design helps you organize your thinking The hierarchy organizes the function of a large

number of transistors into a particular, easy to summarize function.

Hierarchical design also makes it easier to reuse pieces of chips, either by modifying an old design to perform added functions or by using one component for a new purpose.

Design Abstraction Critical to hardware system design. Abstraction defines how much detail about the design

is specified in a particular description Hardware designers use multiple levels of design

abstraction to manage the design process and ensure that they meet major design goals, such as speed and power consumption.

The simplest example of a design abstraction is the logic gate.

We choose the design abstraction that is best suited to the design task.

Level of Abstraction Different styles are adopted for writing VHDL code. Abstraction defines how much detail about the design

is specified in a particular description. Four levels are:

Layout level Logic level Register Transfer level Behavioral level

Layout Level This is the lowest level and describes the CMOS

layout level design on silicon.

Logic Level Design has information about

Function Architecture Technology Detailed timings

Layout information and analog effects are ignored.

Register Transfer Level Using HDL every register in the design and the logic

in between is defined. Design contains:

Architecture information No details of technology No specification of absolute timing delays

Behavioral Level Describing function of a design using HDL without

specifying the architecture of registers. Contains timing information required to represent a

function

FPGA Abstraction Behavior:

A detailed executable description of what the chip should do, but not how it should do it.

E.g. C program may be used as behavioral description. Program does not bother about clock cycle by clock

cycle behavior of the chip. Register-transfer:

The system’s time behavior is fully specified We know the allowed input and output values on every

clock cycle but the logic is not specified as gates. The system is specified as Boolean functions stored in

abstract memory elements.

FPGA Abstraction Logic:

The system is designed in terms of Boolean logic gates, latches, and flip-flops.

Configuration: The logic must be place into logic elements around

the FPGA and the proper connections must be made between those logic elements.

Placement and routing perform these important steps.

Design always requires working down from the top of the abstraction hierarchy and up from the least abstract description.

Top-down design adds functional detail. Create lower levels of abstraction from upper

levels. But top down design decisions are made with

limited information. Best speed, area and power requirements. Cannot accurately judge those costs until we have

an initial design.

Top-down vs. bottom-up design

Bottom-up design spreads cost information back to higher levels of abstraction. Experience will help to judge costs before

completion of the implementation. Good design needs cycle of top-down design

followed by bottom-up redesign.

Top-down vs. bottom-up design

FPGA Abstraction

Complex problems can be tackled using methodologies.

Lessons we learn on one system to help us design the next system.

Built up over several decades of experience. Provides us with a set of guidelines for

What to do? When to do? How to know when we are done.

Methodologies

Modern digital designers rely on HDLs to describe digital systems.

Schematics are rarely used to describe logic. Block diagrams are often drawn at higher levels of the

system hierarchy but usually as documentation, not as design input.

HDLs are tied to simulators that understand the semantics of hardware.

They are also tied to synthesis tools that generate logic implementations.

Hardware description languages

Correct functionality The chip must work. Satisfaction of performance and power goals Aspect of making the chip work. Catching bugs early Latter a bug is caught, the more expensive it is to fix. Good methodologies check pieces of the design. Good documentation To check when mistakes were made To ensure that things were done properly.

Methodologies goals