FPGA CONTROLLER DESIGN AND SIMULATION OF A PORTABLE …

FPGA CONTROLLER DESIGN AND SIMULATION

OF A PORTABLE DOUGH MIXING MACHINE

Joseph O. Inwelegbu and Thomas A. Nwodoh

Department of Electrical Engineering, Faculty of Engineering, University of Nigeria,Nsukka, Nigeria

Abstract

Biscuit and chocolate cookies are normally produced by industrial based processesand machinery using analog and IC gate-based Controllers. With the advent ofMicrocontrollers, Application Specific Integrated Circuits, Digital Signal Proces-sors (DSP) and Programmable Logic Devices, complex industrial systems and con-trols can now be integrated into portable embedded household electronic systems.In this paper, the design and simulation of a Dough Mixer Controller (DMC)with Proportional Integral Derivative (PID) closed-loop motor feedback control,is undertaken for a home-based biscuit Cookie machine. DC motor behaviour ismodelled and simulated with Matlab/Simulink. Synthesizable VHDL Design andSimulation is carried out with Quartus II Web-Edition 9.0 and ModelSIM EDAsoftware tools, using an Altera Field Programmable Gate Array (FPGA) devel-opment system to verify the PID algorithm applied. Simulation results show thatthe PID algorithm programmed into the FPGA-based controller, effectively main-tained the Permanent Magnet (PM) DC motor of the mixer at constant torqueover an operational 3-speed range. The mixer agitated the 10g dough ingredientsfed into the mixing compartment. Subsequently, the mixture resulted in the for-mation of a proteinous and coherent viscoelastic dough structure, consistent withpublished works on dough mix-texture. The dough can subsequently be baked intobiscuit cookies.

Keywords: FPGA, VHDL, PID controller, Pulse Width Modulation, Full H-Bridge DCmotor driver

1. Introduction

The DC motor, a power actuator is widelyused in industrial applications. The speed of aDC motor can be adjusted with electronic con-trollers to a great extent, so as to provide easycontrol and high performance [1,2]. By meansof various combinations of shunt, series, and

separately-excited field windings, DC motors(DCM) can be designed to display a wide va-riety of volt-ampere or speed-torque controlcharacteristic; hence they have found use inmany applications [3,4].

In general, electronic controllers can beclassified as analog and digital. Analog con-trollers which only presented low cost and sim-

Nigerian Journal of Technology Vol. 30, No. 1, March 2011.

48 J.O. INWELEGBU and T.A. NWODOH

plicity of use characterized earlier controllers.With rapid advances in control technology,more and more research on digital controllerswith computer-based systems have been donein recent years [5,6,7]. Usually, when a Micro-processor or Digital Signal Processor (DSP)is used for digital control, the control algo-rithm is executed sequentially. Migrating toprogrammable logic control, offers high speed,parallel processing, concurrent processing andshort development time, resulting in a fasttime to market.

FPGAs consist of three major configurableelements, namely: Configurable Logic Blocks(CLBs) that provide the functional elements;Input/Output (I/O) Blocks (IOBs) that pro-vide interface between the package pins andinternal signal lines; and Programmable in-terconnect resources that connect I/O ofCLBs and IOBs onto the appropriate network.FPGA based digital controllers have becomethe most favorable choice for prototyping dig-ital systems. The control algorithms are de-veloped in VHDL which is now one of themost popular standard digital logic HardwareDescription Languages (HDLs). It is sup-ported by all major Computer Aided Engi-neering (CAE) platforms, making it very ver-satile [8,9,10].

FPGA advantage lies in customizing pre-viously fixed generic hardware in Microcon-troller units (MCUs) or DSP chips. Hence,the optimized application-specific PWM blockin the DMC of this paper, can replace thestandard PWM block found in a MCU orDSP-based motor-control chip, and reduce theTotal Harmonic Distortion (THD) due to themotor, by nearly 50% at a high modulationindex [11]. Here, an Altera FPGA controlleris designed and programmed to control thespeed of the Permanent Magnet (PM) DCM ofa portable dough mixing machine, using theProportional Integral Derivative (PID) algo-

rithm with Pulse Width Modulated (PWM)signals.

2. Relevant Literature

FPGA-based PID control scheme have beenwidely applied to DCM control applicationsby many researchers. Abdelati presented theimplementation of PID controller for a DCMon an FPGA board. Several modules neces-sary for building PID controllers on FPGAswhich improve speed, accuracy, power, com-pactness, and cost effectiveness were outlinedin the work [12,18].

Li et al implemented a parallel PID al-gorithm with fuzzy gain conditioner on anFPGA and conducted a simulation-basedstudy [21]. Chen et al implemented a com-plete wheelchair controller on FPGA with par-allel PID algorithm [13]. Correia et al alsopresented a standard DCM speed control de-sign for a test car [14]. The LED, display andpushbutton modules were automatically gen-erated by an EDA system. The implementedplatform permits: (a) to control directly thereal vehicle using control commands that aresent using a keyboard and (b) to simulate thecontrol process in a virtual environment, usinga virtual instrumentation approach.

Gras et al reported the development of aprototype Micro Z-arm Mixer for measuringflour [17]. The instrument consists of a tem-perature controlled mixing bowl and a speed-controlled DCM. Results obtained with themixer were highly correlated with those ob-tained with the conventional equipment.

Mei et al reported the development of a realtime simulation system for modeling electricmotors based on a FPGA chip (Altera FLEX10KEPF10K70). The internal design of theFPGA was carried out using a combination ofVHDL and schematic/graphical entry meth-ods [14].

Nigerian Journal of Technology Vol. 30, No. 1. March 2011.

Portable Dough Mixing Machine FPGA Controller 49

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Figure 1: General model of a DCM.

Figure 2: Mathematical model of a DCM.

Kowalski et al presented the position con-trol of an unmanned electrical dual rotor he-licopter. The experimental tests were per-formed with the National Instruments indus-trial computer with RIO PXI- 783 1R card us-ing LABVIEW software. The rotor speed wasmeasured by an encoder for comparison withthe estimated speed. A prototyping board isthe central piece with a PC and motor drivecircuit attached [36].

2.1. Mathematical model of a DCM

The general model of the DCM is depictedin Figure 1. The applied voltage V(t) con-trols the angular velocity (t). The relations forthe armature controlled DC motor are shownschematically in Figure 2.

The dynamical model of the DCM is givenby the following equations [15],

Va(t) = Ladia(t)

dt+ Raia(t) + Vemf(t) (1)

Tm = Jdωm(t)

dt+ Bωm(t) + T (t) (2)

Where the parameters and variables are de-fined in Table 1 following.

Table 1: Motor Parameters.Va Applied armature/input voltage

(volts)La Armature inductance (H)Ia Armature current (A)Ra Armature resistance (Ω)Kb Back emf constant (volt.sec/rad)Kf Motor constant (kg m)ω Motor shaft angular velocity (rad/s)Tm Output torque (Nm)Im Moment of inertia of motor & load

(kgm)Bm Vicious friction constant of load and

motor (Nm.sec)Jm Moment of inertia of load & rotor (kg

m)

The output torque Tm of the motor is pro-portional to the armature current ia, i.e. Tm =Ktia. By omitting the static friction, if oneregards the applied armature voltage Va(t) asthe input and the angular velocity ωo(t) of themotor shaft as the output and also assumeLaIm ≈ 0, the transfer function from (1) and(2), is given as [15]:

G(s) =Kωo

s + ωo

(3)

DC Motor at Constant Torque Oper-ationMany industrial applications such as convey-ors, mixers, squeeze rolls, processing machin-ery, etc., require nearly constant torque overtheir operating speed range [16]. A PM DCMwas chosen for this research, because they ex-hibit an approximate constant torque charac-teristic over their speed range as shown in Fig-ure 3, to deliver a constant torque to the agi-tator over varying speeds for uniform mixingof biscuit dough.

PWM ControlThe Control of DCM and power electronicsby PWM signal is very well known [17,7]. In



Figure 3: PM DCM Constant torque characteristics.

PWM, a time dependent varying output volt-age is achieved in the process of varying thepulse by controlling the switching of the inputvoltage for the off and on duration. Figure 4shows a square wave PWM pulse with 50%duty cycle.

As shown, if the input voltage Vin can beswitched on and off frequently at the uniformrate then the total period T will be:

T = Ton + Toff (4)

Where: Ton = ON time and Toff = OFFtime. For a 50% duty cycle, the output volt-age is 0.5 * Vin. In this design, the Vin =FPGA input voltage = 3V dc. This is boostedby the full H-bridge IC at 24V DC, to drivethe mixer DCM. In general, the output volt-age is:

Vavg =

Ton

Ton + Toff

∗ Vm

→ Vavg = (D) ∗ Vm (5)

Where: Vavg = average output voltage, andD = duty cycle. The PWM signal from thePWM block of FPGA controls on and off pe-riod of each terminal of the full H-Bridge tran-sistor controlling the motor, and hence thespeed.

Speed Control Methods of DC MotorsThe speed of a motor can be controlled by

open loop and closed loop control strategies.In the PID closed-loop control as applied inthis research, the control value is dependenton the output speed of the motor. An openloop control does not. Figure 5, illustrates thelosed-loop control of a DCM to maintain thecontrolled speed at the desired reference speed[18,19,20].

The control objective is to make the motorspeed follow the reference input speed changeby designing an appropriate controller. Thegoal is to eliminate the error between P thecontrolled variable (motor speed) and the de-sired speed Pd. The value of P is measured bythe sensor, an optical speed encoder, which iscompared with Pd to generate the error e(t).The controlled output u(t), is a function ofe(t). In this research, this is the PWM sig-nal, which is fed to the full H-Bridge driver topower the mixer motor.

PID Control AlgorithmThe PID algorithm has been demonstrated tobe effective for DC servo motor speed control.The PID controller is used to reduce or elimi-nate the steady-state error between the mea-sured motor speed and the reference speed tobe tracked. It is therefore applied for controlof the dough mixer PM DCM. The generalequation of a PID controller, is the summa-tion of the proportional, derivative and In-



Figure 4: Square wave with 50% duty cycle.

Figure 5: Closed-loop speed control system

tegral terms, giving U(t) the output signal,as found in relevant literatures [21,22]. Con-sider the ideal PID controller written (assum-ing Uo = 0) in the continuous (analog) timedomain form as:

U(t) = Kpe(t)+Ki

∫ t

o

e(t)dt+Kdde(t)

dt(6)

Where: Kp = proportional gain; Ti = integraltime; Td = derivative time; e(t) = trackingerror. There are several methods to calculateP , I and D terms. The references [22,23] pro-vides the detail of all tuning methods, withtheir functional graphs. To design the dig-ital PID controller in an MCU or FPGA de-vice requires the standard PID controller withschematics in Figure 4, to be discretised. Tp,Ti, and Td denote the time constants of the P ,I and D terms.

To discretise the controller requires the inte-gral and the derivative terms to approximateto forms suitable for computation by a com-puter. The transfer function of the system in

&

Figure 6: PID controller schematics.

Figure 6 is given as:

u

e(s) = H(s) = Kp

(1 +

1

Tis+ Tds

)(7)

The discretized digital controller is given as adifference equation by [24]:

U(n) = Kpe(n) + Ki

n∑j=0

e(j)

+Kd(e(n)− e(n− 1)) (8)

Where e = error, K = KpT

Tiis the integral

coefficient, and K = is the derivative coeffi-



cient. To compute the sum, all past errors,e(0) . . . e(n), have to be stored. From equa-tion (8), the digital controller U(n) is givenas:

Kp(en−en−1)+Kien+Kd(en−2en−1+en−2)(9)

This form of the digitized PID equation willbe used for implementation of the DMC.

PID Tuning MethodsTuning is the process of calculating the P , Iand D parameters for optimal gains to getan ideal response from a control system. TheTrial and Error, Ziegler-Nichols, Cohen-Coonand Software tools, are Methods cited in sev-eral literatures to accomplish this [25]. Trialand Error Method was applied in this re-search.

Trial and Error MethodIn this method, I and D terms are set to zerofirst and the proportional gain is increased un-til the output of the loop oscillates. Once theP andI have been set to get the desired fastcontrol system with minimal steady state er-ror, the derivative term is increased until theloop is acceptably quick to its set point.

The DoughDough is a paste made out of cereals by mix-ing flour with a small amount of water and/orother liquid. It is precursor to making breads,pancakes, noodles, crusts, pastry, cookies andsimilar items [26]. Dough is usually a non-Newtonian and viscoeleastic material, exhibit-ing bimgham plastic properties[27]. Cookiedough refers to a blend of cookie ingredientswhich has been mixed into a malleable form,later to be baked to individual cookies [28].Biscuit dough may be composed of ingredi-ents listed in Table 2.

Dough can be mixed by an electric mixer[27]. Lindley has proposed a detailed reviewof mixing operations [29]. Biscuit cookies aremade with the mixed dough by setting oventemperature of about 200C and baking time

Table 2: Typical Biscuit dough ingredients.

Item % by weightFlour 45%Soft white sugar 2.3%Water 43%Butter 2.6%Eggs 3%Baking powder 1%Salt 1.1%Oil 2%

of about 5 minutes, depending on the oven.The mixing time is related to the mixing indexM , by the formula:

lnM = −Ktm (10)

(10) Where K = mixing rate constant, whichvaries with the type of mixer and the nature ofthe components, and t(sec.) = mixing time.The smaller the mixing index is, the betterthe mixing will be. The mixing rate constantK, depends on the characteristics of both themixer and the liquids. The effect of the mixercharacteristics on K is given by:

K ∝ D3N

D2TZ

(11)

Where D (metres) = the diameter of theagitator, N(rev/s) = the agitator speed,Dt(metres) = the vessel diameter andZ(metres) = the height of liquid.

3. Material use for implementation

The materials required to accomplish thedesign of the DMC Controller can be catego-rized into Software, hardware and the MixerCompartment and Apparatus. They are de-scribed below.



3.0.1. Software:

(a.) FPGA design software Quartus II WebEdition/Ver. 4.0

(b.) The latest Quartus II service packs (ForCyclone II 2C35 FPGA FPGA)

(c.) A logic simulator (Model-SIM)/(Simulink)

3.0.2. Hardware:

(a.) DE2 FPGA development board from Al-tera

(b.) A computer system(c.) 24V, DCM(d.) (d.) L298 (46V, 4A) Full H-bridge motor

driver IC(e.) PC type ATX-300Watts power pack(f.) Optical speed encoder(g.) Dough mixer container and planetary

mixing apparatus(h.) Tachometer for measuring motor speed

in RPM(i.) Laboratory Microscope, for observing

dough microstructure(j.) Wattmeter, for measuring motor power

consumption(k.) Connectors and cables

3.0.3. Mixer Compartment and Apparatus

Aluminum alloy dough pan with non-stickcoating is used. The dimensions of the panare 5.29 X 5.29 X 5.49 (inches). The taperingand rounded corners of the pan produces anapproximate volume of 2230 cm3 [31].

4. Methodology

Figure 7 shows the design steps for anyprogrammable logic device [32].

A detailed explanation of the designmethodology steps can be found in relevantliteratures [32].

Figure 7: Programmable logic design methodol-ogy.

4.1. Hardware implementation

This section discusses the functional mod-ules of the Dough-Mixer Controller shown inFigure 8.DE2 FPGA development systemThe Altera DE2 board block diagram shownin Figure 9 below features a state-of-the-artCycloneTM II EP2C35 FPGA in a 672-pinpackage [30]. All important components onthe board are connected to pins of this device,allowing the user to control all aspects of theboard’s operation.

User InterfaceIn this research, through the 3-switch/key in-built in the DE2 system shown above, theuser inputs an 8-bit value, that specifies themixer motor LOW/MEDIUM/HIGH speedsof (100/200/300) RPM. This module also han-dles the bounce effect and associated scanningof the switches and the multiplexed 7-segmentdisplay units [18].

Optical speed Encoder functionThe speed output of the motor is mechanicallycoupled through an optical encoder. The volt-age encoded speed output (Vf ), is fed back toFPGA through the ADC block. The refer-ence input (Vr) from the speed switch, is thencompared with Vf . The difference (ef ) (er-ror signal), which is the control signal effectsspeed adjustment of the PM DCM through



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Figure 8: DMC Architecture and functional modules.

Figure 9: Altera DE2 FPGA development system.



PWM and PID algorithm. Speed control isachieved when the sensed speed equals refer-ence speed and error signal (e) given by equa-tion (12) equals zero.

ef = Vr − Vf (12)

In Figure 10(a) and (b), a rotating slotteddisk was mounted on motor shaft with a fixed10 tracks, slotted disk. The frequency of theoutput waveform fout is given by:

fout =N rpm

60(13)

Where rpm = speed in revolutions per minute,and N = number of slots in disc. So, fromequation (13), the maximum speed of the PMDCM is given by,

rpm =fout60

N=

50 ∗ 60

10= 300RPM

From Figure 10(b), Chip LM324 is used toconvert the output square pulses to digi-tal form, readable by ADC block of FPGA.When the Vout of photodiode is less than Vref ,the output of LM324 will be 0V (Low) and5V (High), if vice-versa. The output signalfrom LM324 has a frequency given by equa-tion (13), and is read by the ADC block ofthe FPGA, as a representation of the actualswitch programmed speed.

PM DC Motor (24V)The mixer motor and dough container usedis same as that used in [31]. Motor and Pul-ley specifications : ECM Motor CA-161200-T,01R06, 24 V DC, 30 W.

Motor Shaft: 2275 RPM Full speed, 1800RPM Pulse SpeedPulley Ratio: (130 teeth on kneading bladeshaft / 20 teeth on motor shaft) = 6.5 turndown ratioMixer Blade Rotation: 350 RPM, MaximumPWM SpeedMotor maximum Load = 0.58 Amps, 67Watts.

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Figure 11: DCM drive shaft and Mixer agitatorshaft and pulley system.

PWM Block PWM systems control direc-tion, speed, and average torque of a motor.The PWM block of the FPGA interfaces tothe motor through the H-bridge driver. Itsends speed modulated signals to control dutycycle of full H-bridge DCM driver, throughMOSFETs (IRFZ 740). Power is supplied tothe motor in square wave of constant voltagebut varying pulse-width, determined by equa-tion (4). The speed of a DCM is a functionof the input power and drive characteristics.The modulating signal is supplied in 8-bit dig-ital format. With the 50MHz synchronizationclock, a minimum pulse width of 100 ns forthe synchronization clock period is obtained.A PWM frequency of about 50 Hz is foundsuitable. To generate this, the modulating sig-nal is multiplied by 212 and a 20-bit counterwith 50MHz clock is fired. This counter iscompared with the scaled modulating signal.If the scaled modulating signal is larger, thePWM output is set to one, otherwise, it is setto zero, thus the PWM algorithm flowchartshown in Figure 12, is implemented success-fully.

Mixing ApparatusDough and paste are mixed in machines,which of necessity must be powerful; based onthe size of the materials to be mixed to formthe dough. This research is based on mix-ing about 10g weight of material as shown inTable 2 to form dough for the biscuit cookie;



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Figure 12: PWM flowchart.

therefore a small mixer with planetary agita-tor is adequate.

4.2. Software implementation

The controller software embedded withinthe target CyclonerII 2C35 FPGA runningat 50 MHz clock calculates the necessary dutycycle and generates PWM signals for the fullH-bridge driver through the PWM block. Us-ing the PID algorithm (shown in Figure 13)implemented in the PID block, the DCMspeed is maintained at the required constantvalue. Figure 14, shows the DMC system con-trol blocks, Figure 15, shows the digital PID

controller equation block. Figure 16 shows thehierarchical diagram of the PID controller Im-plementation. Quartus II Ver. 4.0 and Mod-elSim XE III 6.3c software tools were used forbuilding and testing these modules.

PID Algorithm DescriptionThe PID block is implemented in VHDL lan-guage using dedicated libraries from Altera.The flowchart of the algorithm is shown inFigure 13.

Software Implementation of the PIDAlgorithmVHDL software modules used include the keyscanning and 7-segment multiplexed displayroutines, PWM block and the PID block andthe system reset. To resolve the digital PIDequation (8) of the PID block, VHDL librariesbuilt for algebraic manipulation in VHDL areused. Several works aided this research [33,34]. A digital PID controller can be repre-sented by the following expression [33]:

u[k] = u[k − 1] + e[k](kp + kd + ki)

+e[k − 1](ki − kp − 2kd)

+e[k − 2]kd (14)

This is another form of equation (8). Equation(14) is represented in Figure 15. The registererror block stores values of e[k], e[k − 1] ande[k − 2] (error), and makes shift operations



Figure 14: DMC system control blocks.

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Figure 13: Flowchart for PID algorithm.

. ( 5 >2 25 Figure 15: Digital PID controller equation blockimplementation in programmable logic.

(e[k − 1] = e[k] and e[k − 2] = e[k − 1]). Theoutput register block stores u[k] and u[k− 1].The implemented controller can be visualizedin the blocks presented in Figure 14. Fourmain blocks are observed:

• Error Detecting Block: This block is usedfor the comparison of the signs TRA-JECTORY (user motor speed, through3-switches) and ENCODER (Feedbackspeed read from optical encoder). (+ orsign).

• PID Controller Block: it implements aPID digital controller, using the gain pa-rameters contained in the control regis-ters.



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Figure 16: Hierarchical Diagram of PID controllerImplementation.

• Control Register Block: it implementsthe control registers, responsible forthe programming of parameters in theFPGA.

• Power Interface Block: it converts the bi-nary word supplied by PID controller ina pattern of digital signs to control thePWM block [36].

4.2.1. Hierarchical structure of the PID con-troller Software

The hierarchical structure of the PID con-troller software implementation is shown inFigure 16. It consists of a top level modulecalled PID controller Top, with functionalsub-modules.

PID Controller Top ModuleThe PID Controller Top module, instantiatesthe sub modules ADC interface, ADC Data

Read and Motor control. It interconnectsall the signals and interacts with the externalworld.

Coregen Divider ModuleThis is Xilinx/Altera specific module Divgen v1 0, used in the present design. In-

stantiated in Motor Control Module to dividethe calculated PID value Vn to get the equiv-alent binary value, which has to be sent toDAC. PID Equation Calculation ModuleThe calculated errors en, en-1 and en-2 withtheir polarities, is fed to this module from mo-tor control module. This module calculatesthe PID equation,

Kp(en−en−1)+Kien+Kd(en−2en−1+en−2)(15)

(15) This is a form of the discretized digitalcontroller in equation (8). The constants Kp,Ki and K values are 3, 2 and 1 respectively,calculated by trial and error method of PIDdescribed in section (1.6.1).

5. Simulation of the Controller

The complete design is simulated for veri-fication using Modelsim 6.5 Simulation tool,which has pre-compiled libraries for all Al-tera FPGAs. The inputs like Clock, Reset,Switch data and ADC data are defined andthe output can be observed in the simulationwindow. The sub modules are instantiatedin Top module and internal signals are alsoobserved in the waveform window of the sim-ulator. Once all the signals are taken into thewaveform window, the simulation is run for1000 microsecond and the required changes inthe signals are observed. Observations fromthe software simulation window for the setspeed of 300 RPM shows that after certaintransitions, when the errors en, en-1 and en-2become zero, the current speed locks at 300RPM, which is equal to set speed through ap-plication of the PID control algorithm. Table3, shows the Design Summary, Altera tool de-vice utilization summary and reports the per-centage of available resources used for the cur-rent FPGA design.



Figure 17: PID Controller Top module with sub modules.

Figure 18: DMC - FPGA experimental setup. Courtesy: http://dev.emcelettronica.com/print/51811.

Table 3: Synthesis report of the controller (CycloneTM II EP2C35 FPGA logic elements utilization).

Device Spec. of the CycloneTM II EP2C35 FPGA Used by this designNumber of CLBs used 1536 757Number 4- input LUTs 6144 2648Number of IOBs 142 39Number of gates used for design 300000 24585



6. Results and Discussions

6.1. Experimental setup

Figure 18 in the next page, shows the ex-perimental setup. The HP laptop PC runningSIMULINK, Quartus II and ModelSIM soft-wares is connected to the DE2 board, througha serial (RS-232) interface. The input inter-faces to the DE2 development system includesthe optical speed encoder circuit, the mixer3-speed toggle switch and the power supplypack, providing +5V DC for logic, +3V DCfor the FPGA and +24V DC for the Mixermotor and H-bridge driver. The DE2 out-put interface includes the 3-element seven-segment display and the full H-Bridge mo-tor driver, activated by the controllers PWMblock.

Dough Mixing ResultsApproximately 10 grams of dough ingredientslisted in Table 1 was placed within the mixerchamber. While mixing, torque responses andshaft speeds were collected with tachometerat mixing speeds of 300, 200 and 100 RPM,representing the 3-speed range of the con-troller. For each scenario, torque responsesand agitator speeds were collected over a 10-minute interval. Results show that typicaldough development times at 100 RPM (LOW-speed) are about 12 minutes, 8 minutes at 200RPM (MED-speed) and about 5 minutes at300 RPM (HIGH-speed), averaging optimumdough development time at about 8 minutes.This result agrees fairly well with reviewed lit-eratures, using horizontal and planetary mix-ers [35].

Dough Tensile PropertiesThe tensile properties of the dough alsochanged systematically as the dough develops.The maximum tensile force that the dough ex-erts on the agitator as it adheres to the doughsurface gets smaller. This is a combination ofsurface thickness and dough’s cohesive prop-erties. This is supported by results of fun-

damental rheological measurements [35], andalso observed from the mixing curve shown inFigure 19.

Mixer power consumption profileThe dough mixing curve also shows that themotor power consumption reduced (measure-ments with a wattmeter) after about 6 min-utes, typical of dough when the tensile forceexerted on the agitator declined as doughcomplete development time was approached.

Dough MicroscopyDough structure was observed under a micro-scope. The microstructure of the dough sam-ples mixed at 100 RPM was quite differentfrom the microstructure of dough mixed at300 RPM. The 100 RPM set was less devel-oped with coarser protein network, than thedough developed at 300 RPM. Indeed by com-parison, the general effect of higher mixingspeed is a finer, more homogenous protein net-work [35].

6.2. Experimental results

Experiment is conducted to verify the con-ventional PID control of the PM DCM ofthe DMC for speed control. Trial and Er-ror Method was used to tune the PID con-troller. Effective motor speed control wasachieved with optimum PID coefficients ofP=4, I=0.001 and D=4. In Figure 20, theresult of the speed control experiment showednoise behaviour. This is due to the change insign of error as the motor speed changes togradually lock at 300 RPM when speed errorapproaches zero.

To verify the performance of the controllerhardware design, the VHDL code (Bit file)was downloaded into the target FPGA deviceand the complete system was reset. The setspeed of 300 RPM was assigned to switchesand the capture control switch was enabled.ADC block reads the set speed and PID blockcalculates the equivalent PID value, which



Figure 19: Dough Mixing curve.

feeds back to the motor through DAC block.The motor started running at set speed as ob-served from a tachometer when the currentoutput speed equals the set speed. For an-other speed, the above procedure is repeatedby changing the switch selection. Changingthe speed, the ADC voltage also changed.Measured ADC and equivalent Hex values fordifferent set speeds were tabulated in Table 4.It was observed that the current speed, whichdisplays on the onboard 7- segment display,equals the set speed value. The change in themotor speed for different switch combinationscan also be observed accordingly.

7. Conclusions

A closed-loop PID algorithm, implementedon FPGA was proposed, designed and simu-lated. The performance is verified and tested.The results demonstrate that FPGAs are wellsuited for implementation of complex motorcontrol and estimation algorithms due to theirparallel and high speed execution character-istics. The VHDL software developed, con-tains a set of building blocks, each geared to-wards a specific algorithm. The test resultsalso showed that with PID algorithm control,the steady-state error is eliminated and thedesired output speed is obtained. The FPGA

Table 4: Results of DCM speed control system forvarious set speeds.

SW.No

ToggleSwitchPosi-tion

SetSpeed(rpm)

Equiv-alentHEXvalue

MeasuredADCvolt-age(V)

1. 000 300 12C 4.52. 001 200 C8 2.43. 010 100 64 0.64

implementation reduced the total hardwarecomplexity and cost. Simulation results showthat when the speed is changed, the motorspeed locks to the set speed, when the currenterror en, previous error en-1 and previous tothe previous error en-2 becomes zero.

References

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Figure 20: Experimental result of conventional PID control (motor speed scale = X 10 RPM).

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