FPGA Design Using VHDL - Janamejaya Channegowdajanamejayachannegowda.com/vhdl.pdf · FPGA Design...

FPGA Design UsingVHDL

By

Janamejaya Channegowda

Power Electronics Group

Department of Electrical Engineering

Indian Institute of Science

Bangalore - 560 012

India

February 2013

Contents

1 Introduction 71.1 Procedure for creating a VHDL based project in quartus . . . . . . . . . . 8

1.1.1 Procedure for simulating a VHDL based project . . . . . . . . . . . 26

2 Outputting a constant value through DAC 412.1 Flow of logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412.2 VHDL code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422.3 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3 Generating a ramp and outputting the same through DAC 463.1 Flow of logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.2 VHDL code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.3 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4 Generating chopper mode PWM pulses 494.1 Flow of logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.2 VHDL code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.3 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5 Using DAC and ADC (Taking input through ADC and outputting thesame through DAC) 525.1 Flow of logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525.2 VHDL code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535.3 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6 Generating a sine wave of variable frequency by accepting frequencycommand through ADC 576.1 Flow of Logic: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.1.1 Formulae and their importance: . . . . . . . . . . . . . . . . . . . . 576.2 Generation of the rom code using mega-wizard plug-in manager . . . . . . 60

1

Development of Off-line and Real-Time Simulator for Electric vehicle /Hybrid Electric Vehicle Systems

6.3 VHDL codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776.4 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836.5 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

7 Generating a triangle wave 857.1 Flow of logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857.2 VHDL codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857.3 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8 Generating SPWM pulses 898.1 Flow of logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898.2 VHDL codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898.3 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

22/02/2013 Department of Electrical Engg, IISc, Bangalore Page 2

List of Tables

2.1 Output of DAC for specific input of constant 12-bit words . . . . . . . . . 42

5.1 Voltage inputs and corresponding digital outputs of the ADC . . . . . . . . 52

3

List of Figures

1.1 For creating a new project go to New project wizard . . . . . . . . . . . . 81.2 Click ”Next” to proceed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.3 Enter the names and links as shown . . . . . . . . . . . . . . . . . . . . . . 101.4 Click ”Next” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.5 Window for selecting device family and the specific device . . . . . . . . . 121.6 Window for EDA tool selection . . . . . . . . . . . . . . . . . . . . . . . . 131.7 Window representing the project summary . . . . . . . . . . . . . . . . . . 141.8 Window for opening a new VHDL file . . . . . . . . . . . . . . . . . . . . . 151.9 A blank VHDL file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.10 The ”Start Analysis and Synthesis” button . . . . . . . . . . . . . . . . . . 171.11 The Analysis and Synthesis report . . . . . . . . . . . . . . . . . . . . . . . 181.12 Choose ”Pins” in ”Assignments” menu . . . . . . . . . . . . . . . . . . . . 191.13 Pin assignment window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.14 The ”Assignments” menu . . . . . . . . . . . . . . . . . . . . . . . . . . . 211.15 The ”Settings” window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221.16 ”Reserve all unused pins” settings . . . . . . . . . . . . . . . . . . . . . . . 231.17 The ”Start Compilation” button . . . . . . . . . . . . . . . . . . . . . . . 241.18 The full compilation pop-up window . . . . . . . . . . . . . . . . . . . . . 251.19 The ”File” menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261.20 Selecting the waveform file . . . . . . . . . . . . . . . . . . . . . . . . . . . 271.21 A blank waveform file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281.22 Save the file in the project directory . . . . . . . . . . . . . . . . . . . . . . 291.23 Select the ”Node Finder” . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301.24 List of inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 311.25 Click on ”End Time” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321.26 Give end time as 1 ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331.27 Right click on the ”clk” and select ”Clock” . . . . . . . . . . . . . . . . . . 341.28 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351.29 A raw waveform file before simulation is shown . . . . . . . . . . . . . . . 361.30 The Start Simulation button . . . . . . . . . . . . . . . . . . . . . . . . . . 371.31 The simulated output file . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381.32 Programmer button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391.33 Start button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4


2.1 Constant DAC output of 000h . . . . . . . . . . . . . . . . . . . . . . . . . 442.2 Constant DAC output of 7FFh . . . . . . . . . . . . . . . . . . . . . . . . 442.3 Constant DAC output of FFFh . . . . . . . . . . . . . . . . . . . . . . . . 442.4 Voltage corresponding to 000h is −10V . . . . . . . . . . . . . . . . . . . . 452.5 Voltage corresponding to 7FFh is 0V . . . . . . . . . . . . . . . . . . . . . 452.6 Voltage corresponding to FFFh is +10V . . . . . . . . . . . . . . . . . . . 45

3.1 The simulated ramp wave . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.2 The generated ramp wave . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.1 The simulated PWM pulses . . . . . . . . . . . . . . . . . . . . . . . . . . 504.2 The generated PWM pulses . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.1 Observe the 800h difference between the ADC output and DAC input word 555.2 Another example highlighting the addition of 800h . . . . . . . . . . . . . . 555.3 Output of DAC when input to the ADC channel is −10V . . . . . . . . . . 565.4 Output of DAC when input to the ADC channel is 0V . . . . . . . . . . . 565.5 Output of DAC when input to the ADC channel is +10V . . . . . . . . . . 56

6.1 Generation of ∆θ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586.2 The D Flip Flop operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 596.3 ∆θ ”and’ed” with 3FFFh/16383d . . . . . . . . . . . . . . . . . . . . . . . 596.4 Select ”MegaWizard Plug-In Manager” from ”Tools” menu . . . . . . . . . 606.5 Select ”Create a new custom megafunction variation” option. . . . . . . . . 616.6 The selection window in megawizard plug-in manager . . . . . . . . . . . . 626.7 The ROM window indicating memory and width of output bus . . . . . . . 636.8 Un-check ”q” port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646.9 Memory initialization window of ROM: 1-PORT . . . . . . . . . . . . . . . 656.10 The excel sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666.11 Observe column E and column F . . . . . . . . . . . . . . . . . . . . . . . 676.12 Select a new ”Memory Initialization File” . . . . . . . . . . . . . . . . . . 686.13 Enter the required values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696.14 A filled-up mif file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706.15 The last rows of the mif file . . . . . . . . . . . . . . . . . . . . . . . . . . 716.16 selecting the sinewave.mif file . . . . . . . . . . . . . . . . . . . . . . . . 726.17 EDA tools window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736.18 EDA tools window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746.19 The generated VHDL file . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756.20 The settings window where the design files have been included . . . . . . . 766.21 Output of DAC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836.22 Output of DAC is a sine wave of frequency 50Hz when input to the ADC

channel is +5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846.23 Output of DAC is a sine wave of frequency 15Hz when input to the ADC

channel is 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84



7.1 The triangle wave generation illustrated with the implementation of a 3-bitup-down counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7.2 Output of DAC is a triangle wave of frequency 4.88kHz . . . . . . . . . . . 88

8.1 SPWM pulses are produced as shown in the figure above . . . . . . . . . . 97


Chapter 1

Introduction

This Lab-manual is an extension of the document already prepared. The previous doc-uments stressed on a block-diagram approach to program the FPGA. The current docu-ment provides VHDL codes to all the experiments which were done by block-diagrams.Procedures involved in creating VHDL based projects and all the codes used have beenillustrated in this document.

7


1.1 Procedure for creating a VHDL based project in

quartus

1. Step 1:Open the Quartus software. Go to ”File” menu and click on the ”New projectwizard”.

Figure 1.1: For creating a new project go to New project wizard



2. Step 2:After clicking the ”New project wizard” a window as shown in Figure 1.2 appears.Click ”Next” to proceed.

Figure 1.2: Click ”Next” to proceed



3. Step 3:In the next window, type the address of the working directory of the project. Typethe project name and top level entity name. Top level entity is the name of thedesign file used to compile the project. The usage of top level entity structure willbe understood when the first exercise is completed, so at present proceed with samename as project name itself.

Figure 1.3: Enter the names and links as shown



4. Step 4:This window is used to add a existing VHDL file. Since there is no such file present,click ”Next” and proceed.

Figure 1.4: Click ”Next”



5. Step 5:In this window select the Device Family as ”Cyclone” and the specific device as”EP1C12Q240C8”. Click ”Next” to continue.

Figure 1.5: Window for selecting device family and the specific device



6. Step 6:This window is used to add extra tools, since none of them are used in the presentproject, click ”Next” to proceed.

Figure 1.6: Window for EDA tool selection



7. Step 7:This window shows the summary of the current project. Click ”Finish” to end theproject wizard.

Figure 1.7: Window representing the project summary



8. Step 8:Go to ”File” menu and click ”New” to create the design file, the window will appearas shown in Figure 1.8. Then click on ”VHDL File” to open a new VHDL designfile.

Figure 1.8: Window for opening a new VHDL file



9. Step 9:A blank VHDL file appears as shown in Figure 1.9; type in the code and save it inyour project directory.

Figure 1.9: A blank VHDL file



10. Step 10:After saving the VHDL file click the ”Start Analysis and Synthesis” button to verifythe code written.

Figure 1.10: The ”Start Analysis and Synthesis” button



11. Step 11:If the entered code in the VHDL file is error free then messages similar to the oneshown in Figure 1.11 will appear, here when the dac ramp.vhd file was analyzed thecode in the file was free from errors, so the following messages appeared.

Figure 1.11: The Analysis and Synthesis report



12. Step 12:Now to assign the pins, go to ”Assignments” menu and choose ”Pins”.

Figure 1.12: Choose ”Pins” in ”Assignments” menu



13. Step 13:Refer to the schematics of the board and assign the pins.

Figure 1.13: Pin assignment window



14. Step 14:Go to ”Assignments” menu and choose ”Settings”.

Figure 1.14: The ”Assignments” menu



15. Step 15:In settings, go to ”Device” and click on ”Device and Pin Options”.

Figure 1.15: The ”Settings” window



16. Step 16:In the ”Reserve all unused pin” section. Please select option as ”As inputs tris-tated”. Make sure that this first option is selected. The default option will be ”As outputs driving ground ”. The default option will heat up the device andit may get damaged. Always before programming make sure that the option ” Asinputs tristated ” is selected. In every project this setting should be changedwhen you create the project so that you wont forget this point. The setting to beselected is shown in Figure 1.16.

Figure 1.16: ”Reserve all unused pins” settings



17. Step 17:Now click on the ”Start Compilation” button to compile the project.

Figure 1.17: The ”Start Compilation” button



18. Step 18:A pop-up appears as shown in Figure 1.18; after successful compilation of theproject.

Figure 1.18: The full compilation pop-up window



1.1.1 Procedure for simulating a VHDL based project

The following steps have to be followed to simulate any project created in quartus.

(a) In the ”File” menu open a ”New” file.

Figure 1.19: The ”File” menu



(b) Select the ”vector waveform file”.

Figure 1.20: Selecting the waveform file



(c) A blank file with .vwf extension will appear.

Figure 1.21: A blank waveform file



(d) Save the file in the project directory.

Figure 1.22: Save the file in the project directory



(e) Now, right-click on the icons as shown in the figure and select the ”NodeFinder” option.

Figure 1.23: Select the ”Node Finder”



(f) Here click on the ”List” button to get the list of inputs and outputs listed inthe original program.

Figure 1.24: List of inputs and outputs



(g) Now go to ”Edit” menu and select ”End Time”.

Figure 1.25: Click on ”End Time”



(h) Select 1 ms from the drop-down menu.

Figure 1.26: Give end time as 1 ms



(i) Go back to the waveform file and set the clock time period by right-clicking onthe ”clk” and selecting ”Clock”.

Figure 1.27: Right click on the ”clk” and select ”Clock”



(j) Select the time period as 10ns or any other convenient time period.

Figure 1.28: Setting the clock



(k) On setting the clock, a similar figure as shown below will appear.

Figure 1.29: A raw waveform file before simulation is shown



(l) Start the simulation by pressing the ”Start Simulation” button.

Figure 1.30: The Start Simulation button



(m) Finally, the file is simulated and input and output digital words can be anal-ysed.

Figure 1.31: The simulated output file



19. Step 19:Once the simulated waveform is found to be satisfactory, click on the ”Programmer”button.

Figure 1.32: Programmer button



20. Step 20:Now load the automatically generated .sof file to your device by clicking on the startbutton.

Figure 1.33: Start button


Chapter 2

Outputting a constant value throughDAC

2.1 Flow of logic

The details related to the DAC can be found in the device datasheet. The interconnectionof the DAC with the FPGA is clearly described in the previous document(FPGA boarddocument (Author: Venugopal.S)). In this document the 12-bit word is given as inputto the program and the corresponding analog value is obtained from the DAC output.The following table gives the relation between the 12-bit digital word and the analogoutput voltage.

41


12-bit wordOutputvoltage

FFF +10VFCF +9.5VF6B +9VE3F +7VCAF +6VB1F +4V98F +0.5V863 +0.3V807 +0.2V7FF 0V3FF -5V1FF -7.50FF -8.507F -9V03F -9.5000 -10V

Table 2.1: Output of DAC for specific input of constant 12-bit words

2.2 VHDL code

-- Constant value from DAC

library ieee;

use ieee.std_logic_1164.all; -- standard ieee libraries

use ieee.std_logic_unsigned.all;

entity dac_interface is

port(clk: in STD_LOGIC; -- Clock is the input to the quartus block/Cyclone

FPGA. Here, on-board system clock freq is 20MHz

dac_cs,dac_rw,dac_sel: out STD_LOGIC; -- CS/RW/SEL are output signals of

the FPGA, given as input to the DAC

dac_out: out STD_LOGIC_VECTOR (11 downto 0)); -- (11 downto 0)/12-bit

word to be entered to the DAC

end dac_interface;

architecture archdac of dac_interface is

signal count:std_logic_vector(10 downto 0):="00000000000";

--"00000000000"---> the 11-bit counter being intialized to zero

signal clk_2:std_logic; -- Declaring the derived clock as signal



begin

dac_rw<=’0’; -- R/W pin grounded so that read function is always disabled

dac_sel<=’0’; -- DAC"A" selected, see pg 9 of AD5447 datasheet(Pin Function

Descriptions)

dac_out<=x"000"; -- Giving the constant twelve bit data

process(clk)

begin

if(clk’event and clk=’1’) then

count<=count+1; -- counting/incrementing the counter at every positive

edge of the 20MHz system clock

end if;

end process;

clk_2<=’0’ when (count<1024) else ’1’; -- The derived clock. The value of the

counter increases from ’0’ to ’2047’, then the counter resets to zero. The

signal clk_2 remains ’1’ when the value of the count is equal to or more

than ’1024’. Hence the freq of clk_2 is 9.76kHz (20MHz/2048).

dac_cs <= clk_2; -- Chip select being given the derived clock, for clear

understanding refer to the Timing Diagram of the AD5447 (page 5)

end archdac; -- end of the architecture



2.3 Simulation results

Figure 2.1: Constant DAC output of 000h

Figure 2.2: Constant DAC output of 7FFh

Figure 2.3: Constant DAC output of FFFh



2.4 Experimental results

Figure 2.4: Voltage corresponding to 000h is −10V

Figure 2.5: Voltage corresponding to 7FFh is 0V

Figure 2.6: Voltage corresponding to FFFh is +10V


Chapter 3

Generating a ramp and outputtingthe same through DAC

3.1 Flow of logic

The generation of a ramp wave is a relatively simple affair. In the VHDL code givenbelow, a derived clock is used. The 12-bit counter responsible for the generation of theramp wave is incremented at every positive edge of the derived clock. Therefore frequencyof derived clock is 20MHz

212, which comes to 4.88kHz. And the frequency of the ramp wave

is 4.88kHz212

, which is 1.19Hz.

3.2 VHDL code

-- dac ramp

library ieee;

use ieee.std_logic_1164.all;


entity dac_ramp is

port(clk: in STD_LOGIC;

dac_cs,dac_rw,dac_sel: out STD_LOGIC;

dac_out: out STD_LOGIC_VECTOR (11 downto 0));

end dac_ramp;

architecture archdac of dac_ramp is

signal count:std_logic_vector(11 downto 0):="000000000000"; -- Counter for

the derived clock

signal rampcounter:std_logic_vector(11 downto 0):="000000000000"; -- Counter

for ramp, make two seperate sounters.

46


signal clk_1:std_logic:=’0’; -- NOTE: a single counter cannot be used for

both, generating derived clock and for generating the ramp.

begin

dac_rw<=’0’;

dac_sel<=’0’;

process(clk)

begin


count<=count+1; -- Derived clock counter

end if;

end process;

process(clk_1)

begin

if(clk_1’event and clk_1=’1’) then

rampcounter<=rampcounter+1; -- At the derived clock positive edge, ramp

counter is incremented

end if;

end process;

clk_1<=’0’ when (count<2048) else ’1’; -- UNRELATED NOTE: when generating a

enable signal use clk_1<=’1’ when(count==2048) else ’0’. Use this command

when only a pulse is required

dac_out<=rampcounter; -- 12-bit ramp counter output is given as input to the

DAC

dac_cs <= clk_1;-- chip select of DAC being given the derived clock

end archdac;




Figure 3.1: The simulated ramp wave


Figure 3.2: The generated ramp wave


Chapter 4

Generating chopper mode PWMpulses

4.1 Flow of logic

This experiment has been explained clearly using block diagram approch in FPGA boarddocument (Author: Venugopal.S) the logic remains the same, a constant dc voltagevalue is compared with a ramp wave and whenever the ramp wave’s voltage value ata certain point is lesser than or equal to the reference(constant dc voltage value), theoutput, given to a general purpose input/output(GPIO) pin turns high and at all otherinstances the GPIO pin’s output remains low.

4.2 VHDL code

--ramp_chopper

library ieee;



entity ramp_chop is


pwm_out,dir_1: out STD_LOGIC); --1DIR = 64 and 1A1/IO33/pwm_out = 65

(part U28) (Pin numbers)

end ramp_chop;

architecture arc_ramp_chop of ramp_chop is

signal count:std_logic_vector(11 downto 0):="000000000000"; -- counter for

the ramp wave

49


begin

dir_1<=’1’; -- See FPGA Doc-1 (Author: Venugopal) for explanation

process(clk)

constant comp_const: std_logic_vector:=X"400"; -- The constant with which the

generated ramp wave is compared

begin


count<=count+1;

if (count<=comp_const) then -- Generating the pulses based on the ’if’

condition

pwm_out<=’1’;

else

pwm_out<=’0’;

end if;

end if;

end process;

end arc_ramp_chop;


Figure 4.1: The simulated PWM pulses




Figure 4.2: The generated PWM pulses


Chapter 5

Using DAC and ADC (Taking inputthrough ADC and outputting thesame through DAC)

5.1 Flow of logic

The goals of this experiment are:

1. Output of the DAC should be equal to the input voltage value being given to theADC’s input channel

2. The Output of the DAC should judiciously follow the input voltage varitions thatoccur at the ADC’s input channel

The ADC being used on the board is the AD7864-1, it has been configured to operatein the ±10V range. The FSR(Full Scale Range) is 20V. Now, on reading the datasheetcarefully, we can observe that for the ±10V range, 1 LSB is 4.88mV. Now, coming tothe input voltage value and the corresponding digital outputs the following table can beobtained. It should be noted that the data sheet digital word calculation considers theLSB as well, but as it is in the millivolt range, it has been ignored while forming theanalog input and its corresponding digital word table.

We observe that for 0V, output of the ADC is FFF but, for the output of the DACto be 0V, the input word given to the DAC should be 7FF. Similarly, -10V input to theADC produces a digital word of 800 but for DAC to produce -10V output, we should give

Analog Input Digital Word+10V 7FF

0V FFF-10V 800

Table 5.1: Voltage inputs and corresponding digital outputs of the ADC

52


a digital input word of 000 to the DAC. So what we observe here is that there is alwaysa 800h mismatch between the ADC and DAC. To compensate for this mismatch an offsetof 800h is always added to the output of the ADC, before giving it as input to the DAC.This offset is added in the future VHDL programs as well, in general, whenever the ADCand DAC are working together care should be taken to ensure that such type of mismatchis taken into account.

5.2 VHDL code

-- ADC to DAC prgrm

library ieee;



entity adc_to_dac is


adc_convst,adc_cs,adc_wr,adc_rd,dac_rw,dac_cs,dac_sel : out STD_LOGIC; --

control signals generated by the quartus block/FPGA which are given to

the ADC(ad7864) and DAC(ad5447)

adc_out: inout STD_LOGIC_VECTOR (11 downto 0); -- specifying the width

of the adc_out signals (12 bit output)

dac_out: out STD_LOGIC_VECTOR (11 downto 0)); --specifying the width of

the dac_out signals (12 bit output), words obtained from ADC are

stored in the fpga before being given to the dac.

end adc_to_dac;

architecture arc_adc_to_dac of adc_to_dac is

signal count:std_logic_vector(10 downto 0):="00000000000"; -- specifying the

width of the 11 bit counter

signal clk_1:std_logic; -- derived clock

signal clk_2:std_logic; -- inverted derived clock

begin

adc_wr<=’1’;

adc_cs<=’0’; -- understanding the timing diagrams of the ADC and DAC are

necessary to interpret these code lines

dac_rw<=’0’;

dac_sel<=’0’;

dac_out<=adc_out+x"800"; -- The reason for adding Hex number 800 has been

explained in the earlier part of this chapter

process(clk)



begin


count<=count+1; -- counter for generating the derived clock

end if;

end process;

clk_1<=’0’ when (count<1024) else ’1’; -- Derived clock

clk_2<=’1’ when (count<1024) else ’0’; -- not(Derived clock)

adc_convst<=clk_2;

adc_rd<=clk_1; -- Refer timing diagrams

dac_cs <= clk_1;

end arc_adc_to_dac;




Figure 5.1: Observe the 800h difference between the ADC output and DAC input word

Figure 5.2: Another example highlighting the addition of 800h




Figure 5.3: Output of DAC when input to the ADC channel is −10V

Figure 5.4: Output of DAC when input to the ADC channel is 0V

Figure 5.5: Output of DAC when input to the ADC channel is +10V


Chapter 6

Generating a sine wave of variablefrequency by accepting frequencycommand through ADC

6.1 Flow of Logic:

6.1.1 Formulae and their importance:

1. ∆θ∆t

= ω is the general forlmula for instantaneous angular velocity, here ∆t or Ts isthe sampling time period 102.4µs.

2. Ts = 20MHz(On−boardclock)211(11−bitcounter) =9.765kHz or 102.4µs. Ts is the time period of the derived

clock. The derived clock is needed because the DAC and ADC cannot sample theirchannels at 20MHz, they need a slower clock.

3. ∆θ = ω · Ts = 2 · π · f · Ts

4. we know that Xpu = Xactual

Xbasetherefore the above formula can be written as,

∆θpu · ∆θbase = 2 · π · fpu · fbase · Ts

5. The goal is to find a relationship between ∆θpu and fpu

Therefore, substituting other quantities as:

(a) ∆θbase = 2π

(b) Ts = 102.4µs and

(c) fbase = 50Hz

the above equation can be simplified as ∆θpu = (5.12 · 10−3)fpu

The equation ∆θpu = (5.12 · 10−3)fpu establishes the relationship between ∆θpu andfpu. Considering these pu values to be represented in 16-bit digital system the equationcan be written as:

57


L.H.S · 1pu=R.H.S · 1pu=(3FFF )h · (5.12 · 10−3) · fpu=(16383)d · (5.12 · 10−3) · fpu=(84)d · fpu=(54)h · fpu

∆θpu=(0054)h · fpuNote that 0054 is used so that the number always remains 16 bit. We can conclude that:

θ(n)=θ(n− 1) + ∆θor

Final value=Penultimate value + The differenceThe realization of the above equation is achieved as follows. The 16 bit frequency reference

Figure 6.1: Generation of ∆θ

is nothing but the 12-bit ADC output with four zero’s added to the LSB of the 12-bitnumber. Go through the program for better understanding. Now this 16 bit frequencyreference is multiplied with the constant (0054)h as shown in Figure 6.1 .The product isa 32-bit number.

Now the 32-bit product is reduced to 16 bit number by dividing it by 3FFF(as it is thechosen 1pu) as shown in Figure 6.2. The result is a 16-bit number. The 32 - bit number’s13 to 0 bits and the 30th and 31st bit are eliminated as division right shifts the dividendby the number of bits of the divisor which are ’1’. See below for graphic explanation.

32-bits:31 30 29 28

∣∣27 26 25 24∣∣23 22 21 20

∣∣19 18 17 16∣∣15 14

(13 12

∣∣11 10 9 8∣∣7 6 5 4

∣∣3 2 1 0)

Binary representation of 3FFF :( 1 1

∣∣1 1 1 1∣∣1 1 1 1

∣∣1 1 1 1)As shown in the above illustration, 3FFF contains 14 ”high” bits, so the 32 bit number

is shifted by 14 bits to the right. Now there are 18 bits remaining. But as the width ofall the hex numbers involved in calculation is 16-bit, bits from 14 to 29 form the required∆θ. Therefore the result is ∆θ[29..14]. Now this ∆θ[29..14] is given to a D flip flop. Atevery rising edge of the clock pulse ∆θ (at D) is added to the previous result(at Q). The



Figure 6.2: The D Flip Flop operation

Figure 6.3: ∆θ ”and’ed” with 3FFFh/16383d

clock for this flip flop is a derived clock. The rising edge occurs only when the counterhas counted upto the 11th bit, this is the meaning of counter10.

Finally ∆θ[29..14] is anded with 3FFFh/16383d so that it does not exceed the limitof (3FFF )h as shown in Figure 6.3. The result of this and operation is the address ofa rom table. The corresponding location will have the word that has to be given to thedac. Based on the address-location-word combination the appropriate word is enteredinto DAC. Before proceeding further, details about the generation of the rom code isexplained in the following section.



6.2 Generation of the rom code using mega-wizard

plug-in manager

1. Step 1: Go to ”Tools” menu and select ”MegaWizard Plug-In Manager”.

Figure 6.4: Select ”MegaWizard Plug-In Manager” from ”Tools” menu



2. Step 2:

In the next window select ”Create a new custom megafunction variation” option.

Figure 6.5: Select ”Create a new custom megafunction variation” option.



3. Step 3:

A window similar to the one shown in the figure below appears. Here,

(a) From the megafunction list select ”ROM: 1-PORT”

(b) Device family as ”Cyclone”

(c) Type of output file as VHDL

(d) Give a name to the output file, in this example the name ROM CODE hasbeen given

(e) Do not modify the ”current user library directories”, leave it as it is

Figure 6.6: The selection window in megawizard plug-in manager



4. Step 4:

In the next window, enter output bus width ”q” to be 16-bits and the numberof words as 1024. Now, automatically the width of the address bus is changedto 10 bits by the quartus software. This is because we know that 2AddressWidth =Numberofwords. here, 2AW = 1024, taking logarithm to the base e(ln) on bothsides and solving the equation for ”AW”, we get the width to be 10-bits.

Figure 6.7: The ROM window indicating memory and width of output bus



5. Step 5: In the next window from the options, un-check the output port ”q” frombeing given the clock pulse.

Figure 6.8: Un-check ”q” port



6. Step 6: In this window a memory file containing the hexadecimal values necessaryfor generation of a sine wave has to be fed to the ROM: 1-PORT. Minimize themegawizard plug-in manager for now and follow the steps given in the next section.

Figure 6.9: Memory initialization window of ROM: 1-PORT



7. Step 7:

The required hexadecimal values required for generation of a sine wave can begenerated by using the Microsoft’s Excel Sheet program. The following procedurehas to be followed.

(a) Open a new excel sheet file.

(b) Enter the following data in the corresponding columns.

i. Column A: Numbers 0 to 1023d

ii. Column B: Enter formula (=DEC2HEX(A1)), to get values 0 to 3FF

iii. Column C: Enter formula (=A1*2*PI()/1024) to divide 2π into 1024 parts

iv. Column D: Enter formula (=SIN(C1)) to find sine values in radians, of allthe 1024 parts

v. Column E: Enter formula (=ROUND(D1*16383,0)) to multiply column Delements with 3FFFh/16383d and rounding it off to zero decimal places

vi. Column F: Enter formula(=DEC2HEX(E1,4)) to convert all column Eelements to hexadecimal and restricting them to 16-bits

A part of the excel sheet screenshot has been shown in the figure below.

Figure 6.10: The excel sheet



(c) NOTE: Negative decimal numbers when converted to hexadecimal system willresult in the output numbers to have a width of 32 to 40 bits as shown in thefigure below. Do not panic. Let the numbers be as they are in the excel sheet,this issue will be resolved in the following section.

Figure 6.11: Observe column E and column F



8. Step 8:

Once the excel sheet sine values are ready, go to ”File” menu and create a ”New””Memory Initialization File”.

Figure 6.12: Select a new ”Memory Initialization File”



9. Step 9: Enter number of words as 1024 and word size as 16. And press ”ok”

Figure 6.13: Enter the required values



10. Step 10:

(a) A blank mif file appears, select all the hexadecimal values from column F ofthe excel sheet, click on the first block of the mif file and paste all the values.A filled up mif file as shown in Figure 6.14; will appear. Save it in the projectdirectory, here it has been saved as sinewave.mif.

Figure 6.14: A filled-up mif file



(b) If we closely observe the last rows of the mif file we find that only the last16-bits of all the hexadecimal numbers of column F are entered in the tableas shown in the figure below.

Figure 6.15: The last rows of the mif file



11. Step 11:

Now, maximize the ”Megawizard Plug-In Manager” window and ”Browse” for thesaved mif file, and click next.

Figure 6.16: selecting the sinewave.mif file



12. Step 12:

(a) Now, the following EDA window will appear as shown in the figure, click nextto proceed.

Figure 6.17: EDA tools window



(b) The final ”Summary” of the ROM CODE will appear. Click next to obtainthe VHDL file.

Figure 6.18: EDA tools window



13. Step 13:

Finally the ROM CODE.vhd file will be created, as shown in the figure below.

Figure 6.19: The generated VHDL file



14. Step 14:

(a) The ROM CODE file has to included in the design files of the project. Thiscan be done by going to ”Project” menu and selecting the ”Add/Remove Filesin Project” option. As seen from the figure below, all the files adc sine dac,only adc, only dac, ROM CODE and sinewave.mif files have been added. Nowthe project is complete, compile the program and dump the generated .sof fileinto the FPGA.

Figure 6.20: The settings window where the design files have been included

(b) NOTE: The hexadecimal numbers stored in the .mif file are 16-bit wide. Theyhave to be reduced to 12-bits before being given to DAC. Therefore the output”q” has to be reduced from q[15 downto 0] to q[15 downto 4](see the code). TheMSB bits are untouched as they contain the sign information of the number(a”low/0” MSB bit indicates negative number and a ”high/1” MSB bit indicatesa positive number). A hexadecimal constant value of ”800” should also beadded to the output ”q” before sending the word to the DAC.



6.3 VHDL codes

-- ADC sine DAC prgrm

library ieee;



entity adc_sine_dac is


adc_in: in STD_LOGIC_VECTOR (11 downto 0);

adc_convst,adc_cs,adc_wr,adc_rd : out STD_LOGIC;

dac_rw,dac_cs,dac_sel : out STD_LOGIC;


end adc_sine_dac;

architecture arc_adc_sine_dac of adc_sine_dac is


signal freq_ref:std_logic_vector(15 downto 0);

signal del_theta:std_logic_vector(31 downto 0);

signal del_theta_shft:std_logic_vector(15 downto 0);

signal theta:std_logic_vector(15 downto 0);

signal theta1:std_logic_vector(15 downto 0);

signal theta_addr:std_logic_vector(15 downto 0);

signal sin_val:std_logic_vector(15 downto 0);

signal clk_1:std_logic;

component rom_code

PORT

(

address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);

clock : IN STD_LOGIC ; -- Linking

lpm_rom/ROM-1 entity from rom_code.vhd

q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

);



END component;

component only_dac



dac_in: in STD_LOGIC_VECTOR (11 downto 0); -- Linking DAC entity from

only_dac.vhd


end component;

component only_adc


adc_convst,adc_cs,adc_wr,adc_rd : out STD_LOGIC; -- Linking ADC entity

from only_adc.vhd

adc_in: in STD_LOGIC_VECTOR (11 downto 0));

end component;

begin

only_adc1: only_adc port map(clk,adc_convst,adc_cs,adc_wr,adc_rd,adc_in); --

for port map explanation, read the book "A VHDL Primer" by "Jayaram

Bhaskar"

only_dac1: only_dac port map(clk, dac_rw,dac_cs,dac_sel,sin_val(15 downto

4)+x"800",dac_out);

process(clk)

begin


count<=count+1; -- counting up a [10..0] counter

end if;

end process;

clk_1<=’0’ when (count<1024) else ’1’; -- generating a derived clock

process(clk_1)

constant data1_const: std_logic_vector:=X"0054"; -- declaring the constant

(84)d

begin


freq_ref<=adc_in &"0000"; -- making output 12-bit data to 16-bit data i.e ex

"1111 1111 1111" to "1111 1111 1111 0000"

del_theta<= freq_ref*data1_const; --Multiplying freq_ref[15..0] and the

16-bit constant

end if;

end process;



del_theta_shft <= del_theta(29 downto 14); -- the downto command removes 14

LSB bits and also removes the bit 31 and 30 so that del_theta[29..14] is

generated

process(clk_1 )

begin


theta1<=theta;-- DFF operation

end if;

end process;

theta<= del_theta_shft+theta1; -- theta(n) = theta(n-1) + del_theta

theta_addr<= theta and x"3fff"; -- limiting the address to maximum 3FFF

r1:rom_code port map(theta_addr(13 downto 4),clk_1,sin_val);

end arc_adc_sine_dac;

-- only adc

library ieee;



entity only_adc is




end only_adc;

architecture arc_only_adc of only_adc is




begin

adc_wr<=’1’;

adc_cs<=’0’;



process(clk)

begin



end if;

end process;


clk_2<=’1’ when (count<1024) else ’0’;

adc_rd<=clk_1;

adc_convst<=clk_2;

end arc_only_adc;

-- only DAC

library ieee;



entity only_dac is


dac_rw,dac_cs,dac_sel : out STD_LOGIC; -- signals given from the fpga to

the DAC

dac_in: in STD_LOGIC_VECTOR (11 downto 0); -- A input signal has been

specified just to provide completeness to the program

dac_out: out STD_LOGIC_VECTOR (11 downto 0)); -- The 12 bit word is

provided to the DAC from this signal

end only_dac;

architecture arc_only_dac of only_dac is

signal count:std_logic_vector(10 downto 0):="00000000000"; -- 11 bit counter

provided to produce a derived clock


begin

dac_rw<=’0’; -- read function of the DAC is disabled

dac_sel<=’0’; -- only DAC"A" is selected

process(clk)



begin



end if;

end process;


dac_cs <= clk_1; -- CS needs a inverted derived clock

dac_out<=dac_in; -- as mentioned earlier, input is equal to output here

end arc_only_dac;

-- Automatic ROM code generated by Mega Wizard plug-in manager

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY rom_code IS

PORT

(


clock : IN STD_LOGIC ;


);

END rom_code;

ARCHITECTURE SYN OF rom_code IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);

COMPONENT altsyncram

GENERIC (

address_aclr_a : STRING;

init_file : STRING;

intended_device_family : STRING;

lpm_hint : STRING;

lpm_type : STRING;

numwords_a : NATURAL;



operation_mode : STRING;

outdata_aclr_a : STRING;

outdata_reg_a : STRING;

widthad_a : NATURAL;

width_a : NATURAL;

width_byteena_a : NATURAL

);

PORT (

clock0 : IN STD_LOGIC ;

address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);

q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

);

END COMPONENT;

BEGIN

q <= sub_wire0(15 DOWNTO 0);

altsyncram_component : altsyncram

GENERIC MAP (

address_aclr_a => "NONE",

init_file => "sinewave.mif",

intended_device_family => "Cyclone",

lpm_hint => "ENABLE_RUNTIME_MOD=NO",

lpm_type => "altsyncram",

numwords_a => 1024,

operation_mode => "ROM",

outdata_aclr_a => "NONE",

outdata_reg_a => "UNREGISTERED",

widthad_a => 10,

width_a => 16,

width_byteena_a => 1

)

PORT MAP (

clock0 => clock,

address_a => address,

q_a => sub_wire0

);

END SYN;




Figure 6.21: Output of DAC register




Figure 6.22: Output of DAC is a sine wave of frequency 50Hz when input to the ADCchannel is +5V

Figure 6.23: Output of DAC is a sine wave of frequency 15Hz when input to the ADCchannel is 0V


Chapter 7

Generating a triangle wave

7.1 Flow of logic

The generation of a triangle wave depends on the implementation of a simple updowncounter. A selection signal/derived clock is used, which drives the counter to count-upwhen it is high and count-down when it is low. In order to see the output triangle wave inthe scope, we need to use the 12-bit DAC, in this experiment the chip select pin is givena clock of 625kHz. Always the clock frequency of the chip select of the DAC should befaster than the clock frequency of the selection signal/derived clock.

7.2 VHDL codes

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tri_wave is

Port ( clk : in STD_LOGIC;


dac_out:out std_logic_vector(11 downto 0));

end tri_wave;

architecture behav of tri_wave is

signal temp:STD_LOGIC_VECTOR (11 downto 0);

signal count_2: std_logic_vector(11 downto 0);

signal clk_2: std_logic;

component only_dac



85


dac_in: in STD_LOGIC_VECTOR (11 downto 0); -- Linking DAC entity from

only_dac_triangle.vhd


end component;

begin

only_dac1: only_dac port map(clk,dac_rw,dac_cs,dac_sel,temp+x"800",dac_out);

process(clk)

begin


count_2<=count_2+1;

end if;

end process;

clk_2<=’1’ when(count_2<2048) else ’0’; -- Generating the derived

clock/selection signal

process(clk,clk_2)

begin


if clk_2=’1’ then

temp<=temp+1; -- count up

else

temp<=temp-1; -- count down

end if;

end if;

end process;

end behav;

-- only DAC

library ieee;



entity only_dac is



dac_in: in STD_LOGIC_VECTOR (11 downto 0);


end only_dac;






begin

dac_rw<=’0’;

dac_sel<=’0’;

process(clk)

begin



end if;

end process;

clk_1<=’0’ when (count<16) else ’1’; -- generating a derived clock of freq

625k Hz

dac_cs <= clk_1;

dac_out<=dac_in;

end arc_only_dac;




Figure 7.1: The triangle wave generation illustrated with the implementation of a 3-bitup-down counter


Figure 7.2: Output of DAC is a triangle wave of frequency 4.88kHz


Chapter 8

Generating SPWM pulses

8.1 Flow of logic

This experiment involves the generation of PWM pulses, by comparing a triangular carrierwave with a sine wave. The frequency of the sine wave is controlled by the voltage givento the ADC’s input channel. The two signals are compared and whenever the amplitudeof the triangular wave is greater than or equal to the amplitude of the sine wave, theoutput(given to a GPIO pin) goes high, at all other instances the output of the GPIO pinremains low.

8.2 VHDL codes

-- ADC sine DAC prgrm

library ieee;



entity adc_sine_dac is


pwm_out,dir_1: out STD_LOGIC;

adc_in: in STD_LOGIC_VECTOR (11 downto 0);



tri_out:inout std_logic_vector(11 downto 0);


end adc_sine_dac;

architecture arc_adc_sine_dac of adc_sine_dac is

89



signal freq_ref:std_logic_vector(15 downto 0);

signal del_theta:std_logic_vector(31 downto 0);

signal del_theta_shft:std_logic_vector(15 downto 0);

signal theta:std_logic_vector(15 downto 0);

signal theta1:std_logic_vector(15 downto 0);

signal theta_addr:std_logic_vector(15 downto 0);

signal sin_val:std_logic_vector(15 downto 0);


component tri_rom_code

PORT

(




);

END component;

component only_dac





end component;

component only_adc




end component;

component tri_wave

port(clk: in std_logic;

tri_out: out std_logic_vector(11 downto 0));

end component;

begin



dir_1<=’1’;

only_adc1: only_adc port map(clk,adc_convst,adc_cs,adc_wr,adc_rd,adc_in);

only_dac1: only_dac port map(clk, dac_rw,dac_cs,dac_sel,sin_val(15 downto

4)+x"800",dac_out);

tri_wave1: tri_wave port map(clk,tri_out);

process(clk)

begin



end if;

end process;


process(clk_1)

constant data1_const: std_logic_vector:=X"0054"; -- declaring the constant

(84)d

begin


freq_ref<=adc_in &"0000"; -- making output 12-bit data to 16-bit data

del_theta<= freq_ref*data1_const; --Multiplying freq_ref[15..0] and the

16-bit constant

end if;

end process;

del_theta_shft <= del_theta(29 downto 14); -- logical shift right 14 bits and

removing bit 31 and 30 so that del_theta[31..14] is generated

process(clk_1 )

begin


theta1<=theta;-- DFF operation

end if;

end process;

theta<= del_theta_shft+theta1; -- theta(n) = theta(n-1) + del_theta

theta_addr<= theta and x"3fff"; -- limiting the address to maximum 3FFF

r1:tri_rom_code port map(theta_addr(13 downto 4),clk_1,sin_val);

process(clk)

begin




if (tri_out>=(sin_val(15 downto 4)+x"800")) then

pwm_out<=’1’;

else

pwm_out<=’0’;

end if;

end if;

end process;

end arc_adc_sine_dac;

-- only adc spwm

library ieee;



entity only_adc is




end only_adc;

architecture arc_only_adc of only_adc is




begin

adc_wr<=’1’;

adc_cs<=’0’;

process(clk)

begin



end if;

end process;


clk_2<=’1’ when (count<1024) else ’0’;



adc_rd<=clk_1;

adc_convst<=clk_2;

end arc_only_adc;

-- only DAC for spwm

library ieee;



entity only_dac is





end only_dac;




begin

dac_rw<=’0’;

dac_sel<=’0’;

process(clk)

begin



end if;

end process;


dac_cs <= clk_1;

dac_out<=dac_in;

end arc_only_dac;



-- ROM Code for sine wave

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY tri_rom_code IS

PORT

(




);

END tri_rom_code;

ARCHITECTURE SYN OF tri_rom_code IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);

COMPONENT altsyncram

GENERIC (

address_aclr_a : STRING;

init_file : STRING;

intended_device_family : STRING;

lpm_hint : STRING;

lpm_type : STRING;

numwords_a : NATURAL;

operation_mode : STRING;

outdata_aclr_a : STRING;

outdata_reg_a : STRING;

widthad_a : NATURAL;

width_a : NATURAL;

width_byteena_a : NATURAL

);

PORT (

clock0 : IN STD_LOGIC ;

address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);

q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

);

END COMPONENT;



BEGIN

q <= sub_wire0(15 DOWNTO 0);

altsyncram_component : altsyncram

GENERIC MAP (

address_aclr_a => "NONE",

init_file => "sinewave.mif",

intended_device_family => "Cyclone",

lpm_hint => "ENABLE_RUNTIME_MOD=NO",

lpm_type => "altsyncram",

numwords_a => 1024,

operation_mode => "ROM",

outdata_aclr_a => "NONE",

outdata_reg_a => "UNREGISTERED",

widthad_a => 10,

width_a => 16,

width_byteena_a => 1

)

PORT MAP (

clock0 => clock,

address_a => address,

q_a => sub_wire0

);

END SYN;

-- Triangle wave generation

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tri_wave is

Port ( clk : in STD_LOGIC;

tri_out:inout std_logic_vector(11 downto 0));

end tri_wave;

architecture behav of tri_wave is

signal temp:STD_LOGIC_VECTOR (11 downto 0);

signal count_2: std_logic_vector(11 downto 0);

signal clk_2: std_logic;



begin

process(clk)

begin


count_2<=count_2+1;

end if;

end process;

clk_2<=’1’ when(count_2<2048) else ’0’;

process(clk,clk_2)

begin


if clk_2=’1’ then

temp<=temp+1;

else

temp<=temp-1;

end if;

end if;

end process;

tri_out<=temp;

end behav;




Figure 8.1: SPWM pulses are produced as shown in the figure above


References

[1] A VHDL Primer, 3rd Edition by Jayaram Bhasker

[2] Digital Electronics - A Practical Approach with VHDL, 9th Edition by William Kleitz

[3] FPGA board document by Venugopal.S

[4] FPGA DOCUMENT-2 by N. Praveen Kumar

[5] FPGA Board Document, Ver.1.3, Revision 2, February 20, 2007 by Parag AnandRajne, Jayalakshmi and Ravi Krishna

[6] Digital Systems Design with FPGA, course material by Kuruvilla Varghese

98

Date post:	12-Apr-2018
Category:	Documents
Upload:	ngokhanh
View:	221 times
Download:	1 times

FPGA Design Using VHDL - Janamejaya Channegowdajanamejayachannegowda.com/vhdl.pdf · FPGA Design...

Documents