Nov 22 Nov 22 nd nd , 2011 , 2011 Tuusula Tuusula , , Soome Soome FPGA-Enabled Embedded Instrumentation Platform for JTAG Test FPGA-Enabled Embedded Instrumentation Platform for JTAG Test Sergei Devadze, Artur Jutman, Igor Aleksejev Tallinn Univ. of Technology / Testonica Lab Tallinn, ESTONIA Sergei Devadze, Sergei Devadze, Artur Artur Jutman Jutman , Igor , Igor Aleksejev Aleksejev Tallinn Univ. of Technology / Tallinn Univ. of Technology / Testonica Testonica Lab Lab Tallinn, ESTONIA Tallinn, ESTONIA
Transcript
Nov 22Nov 22ndnd, 2011, 2011
TuusulaTuusula, , SoomeSoome
FPGA-Enabled Embedded Instrumentation Platform for JTAG Test
FPGA-Enabled Embedded Instrumentation Platform for JTAG Test
Sergei Devadze, Artur Jutman, Igor Aleksejev
Tallinn Univ. of Technology / Testonica LabTallinn, ESTONIA
Sergei Devadze, Sergei Devadze, ArturArtur JutmanJutman, Igor , Igor AleksejevAleksejev
Tallinn Univ. of Technology / Tallinn Univ. of Technology / TestonicaTestonica LabLabTallinn, ESTONIATallinn, ESTONIA
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AgendaAgenda
•• IntroductionIntroduction–– Concept of embedded test instrumentsConcept of embedded test instruments
•• Applications for FPGAApplications for FPGA--enabled PCB testenabled PCB test•• ChipVORXChipVORX FPGA instrumentation platformFPGA instrumentation platform•• ChipVORXChipVORX InstrumentsInstruments
–– Flash accelerationFlash acceleration–– RAM testRAM test–– Frequency measurementsFrequency measurements
•• ConclusionsConclusions
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AgendaAgenda
•• IntroductionIntroduction–– Concept of embedded test instrumentsConcept of embedded test instruments
•• Applications for FPGAApplications for FPGA--enabled PCB testenabled PCB test•• ChipVORXChipVORX FPGA instrumentation platformFPGA instrumentation platform•• ChipVORXChipVORX InstrumentsInstruments
–– Flash accelerationFlash acceleration–– RAM testRAM test–– Frequency measurementsFrequency measurements
•• Embedded instrument is a Embedded instrument is a specialized IP corespecialized IP core
•• Instruments can implement wide range of target functionsInstruments can implement wide range of target functions
•• Dedicated embedded instruments are used for various Dedicated embedded instruments are used for various testtest, , measurementmeasurement,, debugdebug andand ISPISP taskstasks
•• Instruments are Instruments are specifically designed specifically designed to communicate to communicate with a target devicewith a target device or to test/diagnose specific faultsor to test/diagnose specific faults
•• Embedded instruments can be used when system is in Embedded instruments can be used when system is in operational mode operational mode (normal functional mode)(normal functional mode)
•• Typically Typically 1149.1 1149.1 JTAGJTAG protocol is used as physical layer protocol is used as physical layer for communication with onfor communication with on--chip instrumentationchip instrumentation
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Boundary scan testBoundary scan test
System Under Test (SUT)System Under Test (SUT)
TAPport
I/O
I/O
DATA
ADDR
CONTROL
DATA
CTRL
ADDRA D C
FPGAFPGA
uPuP / ASIC/ ASIC
Core logic is not used
Core logic is not used
System is in test mode. Internal logic of IC is not used for tesSystem is in test mode. Internal logic of IC is not used for testingting
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Embedded instruments based testEmbedded instruments based test
System Under Test (SUT)System Under Test (SUT)
TAPport
I/O
I/O
DATA
ADDR
CONTROL
DATA
CTRL
ADDRA D C
FPGAFPGA
System is in operation mode. Instruments act as embedded testerSystem is in operation mode. Instruments act as embedded tester
Instruments embedded by IC vendor
FPGA-embedded instruments
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Types of embedded instrumentsTypes of embedded instruments
•• Instruments embedded by IC vendors (ASIC / Instruments embedded by IC vendors (ASIC / μμP)P)–– Normally designed for IC test/debugNormally designed for IC test/debug
•• Integrity monitors, BIST, temperature sensors, voltage monitors,Integrity monitors, BIST, temperature sensors, voltage monitors, etcetc•• Debug facilities of processors are often used for board testDebug facilities of processors are often used for board test
–– Often unsuitable for PCB testOften unsuitable for PCB test•• Propriety communication protocolsPropriety communication protocols•• Accessible only by IC vendor or using the tools from IC vendorAccessible only by IC vendor or using the tools from IC vendor•• Coming IEEE P1687 (IJTAG) and NEXUS IEEEComing IEEE P1687 (IJTAG) and NEXUS IEEE--ISTO 5001 standardsISTO 5001 standards
•• Instruments embeddable into FPGA (softInstruments embeddable into FPGA (soft--core core IPsIPs) ) –– Intended for PCB test beyond the FPGA itselfIntended for PCB test beyond the FPGA itself–– Do not introduce overhead, embedded only in test phaseDo not introduce overhead, embedded only in test phase
•• In operational mode FPGA contains functional designIn operational mode FPGA contains functional design–– Instruments can be designed by thirdInstruments can be designed by third--party vendorparty vendor
•• not necessarily by FPGA vendor or board designernot necessarily by FPGA vendor or board designer
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Synthetic instrumentsSynthetic instruments
•• Synthetic instruments from NISynthetic instruments from NI•• GeotestGeotest FPGA InstrumentsFPGA Instruments
–– essentially they provide a essentially they provide a reconfigurable IO + protocolreconfigurable IO + protocol–– used mainly for used mainly for functional testingfunctional testing–– access the System Under Test (SUT) from access the System Under Test (SUT) from edge connectorsedge connectors onlyonly–– do not provide access to do not provide access to SUTsSUTs internal signalsinternal signals–– cannot replace Boundary Scan test (bad test access)cannot replace Boundary Scan test (bad test access)
External to SUT External to SUT instrumentationinstrumentation
SUT BoardInstrumentCard
JTAGJTAG
FPGA
Synthetic Instrument
IP
DUT
Control Software
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Benefits of FPGA embedded instrumentsBenefits of FPGA embedded instruments
•• Naturally integrated into designNaturally integrated into design–– No hardware changes required / additional DFT structuresNo hardware changes required / additional DFT structures–– FPGA is typically FPGA is typically connected to main system buses and is JTAG accessibleconnected to main system buses and is JTAG accessible
•• Run in system operational modeRun in system operational mode–– Instruments are capable for highInstruments are capable for high--speed/atspeed/at--speed/realspeed/real--time testtime test–– Can natively support signaling protocol of target deviceCan natively support signaling protocol of target device
•• Extremely flexible due to reconfigurable nature of Extremely flexible due to reconfigurable nature of FPGAsFPGAs–– Instruments are reconfigurable for meeting the requirements of pInstruments are reconfigurable for meeting the requirements of particular articular
PCB and testPCB and test--casecase•• Reuse of IEEE1149.1 JTAG protocolReuse of IEEE1149.1 JTAG protocol
–– Compatible with existing test hardware (JTAG controllers)Compatible with existing test hardware (JTAG controllers)–– Can be integrated with automatic Boundary Scan test flowCan be integrated with automatic Boundary Scan test flow
•• Less costs due to replacing external T&M equipment with Less costs due to replacing external T&M equipment with embedded testerembedded tester
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AgendaAgenda
•• IntroductionIntroduction–– Concept of embedded test instrumentsConcept of embedded test instruments
•• Applications for FPGAApplications for FPGA--enabled PCB testenabled PCB test•• ChipVORXChipVORX FPGA instrumentation platformFPGA instrumentation platform•• ChipVORXChipVORX InstrumentsInstruments
–– Flash accelerationFlash acceleration–– RAM testRAM test–– Frequency measurementsFrequency measurements
•• ConclusionsConclusions
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Application of FPGA embedded instrumentsApplication of FPGA embedded instruments
•• AtAt--speed / highspeed / high--speed testspeed test•• RealReal--time test applicationtime test application•• HighHigh--speed inspeed in--system programming (ISP)system programming (ISP)•• Signal measurementsSignal measurements
Bottleneck for at-speed and real-time test
JTAGJTAGFPGA
DUT
Bottleneck for ISP and real-time test
I/O standard should be configured for accurate signal measurements
CLK
None of abovementioned tasks is solvable by pure BS:None of abovementioned tasks is solvable by pure BS:
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FPGA-based at-speed testFPGA-based at-speed test
•• Accelerating static structural testAccelerating static structural test–– communication test of highcommunication test of high--speed buses and interfacesspeed buses and interfaces
•• Meeting minimum speed requirements of certain devicesMeeting minimum speed requirements of certain devices–– RAM interconnect testRAM interconnect test
•• Maximum refresh interval specs of DDR RAM could be Maximum refresh interval specs of DDR RAM could be <100<100μμss•• BS test may impose delay of BS test may impose delay of 200200--300ms300ms between refreshbetween refresh
–– Passing test signals through Passing test signals through PLLsPLLs•• Clock lines can contain PLL between FPGA and device under testClock lines can contain PLL between FPGA and device under test•• PLL typically operates in a highPLL typically operates in a high--frequency range (frequency range (1010--100MHz100MHz) ) •• BS can provide test application speed (not TCK!) of BS can provide test application speed (not TCK!) of 11--100KHz100KHz
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FPGA-based real-time testFPGA-based real-time test
•• Enabling JTAGEnabling JTAG--controlled dynamic testingcontrolled dynamic testing–– Testing delay and signal integrity faultsTesting delay and signal integrity faults
•• Achieving speed of functional operation of target DUTAchieving speed of functional operation of target DUT–– Performance test Performance test –– Stress test (soak test)Stress test (soak test)–– BitBit--error rate test (BERT)error rate test (BERT)
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FPGA-based test measurementsFPGA-based test measurements
•• Measurement of periodic signals (clock)Measurement of periodic signals (clock)–– Frequency countersFrequency counters
•• Signal analysisSignal analysis–– Embedded atEmbedded at--speed logic signal analyzerspeed logic signal analyzer
•• Analog measurements using onAnalog measurements using on--chip A/D convertorschip A/D convertors–– Some Some FPGAsFPGAs are capable to measure voltage/current levelsare capable to measure voltage/current levels
•• Conformance to specific I/O signaling standardsConformance to specific I/O signaling standards–– In BS mode nonIn BS mode non--configured FPGA uses default I/O standard configured FPGA uses default I/O standard
(e.g. single(e.g. single--ended LVCMOS 3.3V)ended LVCMOS 3.3V)–– Embedded instrument can configure FPGA to select target Embedded instrument can configure FPGA to select target
standard on specific I/O pins (e.g. LVDS)standard on specific I/O pins (e.g. LVDS)
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AgendaAgenda
•• IntroductionIntroduction–– Concept of embedded test instrumentsConcept of embedded test instruments
•• Applications for FPGAApplications for FPGA--enabled PCB testenabled PCB test•• ChipVORXChipVORX FPGA instrumentation platformFPGA instrumentation platform•• ChipVORXChipVORX InstrumentsInstruments
–– Flash accelerationFlash acceleration–– RAM testRAM test–– Frequency measurementsFrequency measurements
•• ConclusionsConclusions
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ChipVORX TechnologyChipVORX Technology
ChipVORXChipVORX is:is:–– a a technologytechnology for controlling embedded instruments using for controlling embedded instruments using
standard 1149.1 JTAG portstandard 1149.1 JTAG port–– a a platformplatform for building various testfor building various test--related IP coresrelated IP cores–– a a librarylibrary of readyof ready--made instrumentsmade instruments
ChipVORXChipVORX supports:supports:–– Seamless integration into Boundary Scan test flow Seamless integration into Boundary Scan test flow –– Use of automatically generated BS test patternsUse of automatically generated BS test patterns–– Conversion of BS tests into FPGAConversion of BS tests into FPGA--based testsbased tests
ChipVORXChipVORX is being developed by:is being developed by:–– TestonicaTestonica Lab, Lab, –– GoepelGoepel Electronic Electronic –– Tallinn University of TechnologyTallinn University of Technology
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ChipVORX test flow (universal IP)ChipVORX test flow (universal IP)Universal IP (onUniversal IP (on--thethe--fly reconfigurable for target PCB)fly reconfigurable for target PCB)
–– IPsIPs are preare pre--synthesized and readysynthesized and ready--toto--useuse–– No FPGA design tools / licenses are required for IP usageNo FPGA design tools / licenses are required for IP usage
IP reconfigfor specific test case
Test data transfer
Test / measure-
ment
Fetching test
results
IP core upload
to FPGA
Boundary Scan test station
Test patterns, ISP dataBS project
data
JTAG
IP library
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ChipVORX test flow (custom IP)ChipVORX test flow (custom IP)ProjectProject--specific IP (for particular PCB design)specific IP (for particular PCB design)
–– Should be synthesized from a template for each testShould be synthesized from a template for each test--casecase–– Synthesized either by IP vendor or by IP endSynthesized either by IP vendor or by IP end--useruser–– Is fineIs fine--tuned to meet the requirements of specific test casetuned to meet the requirements of specific test case
•• AlteraAltera–– Cyclone, Cyclone II / III / IVCyclone, Cyclone II / III / IV–– StartixStartix, , StratixStratix II / III / IVII / III / IV–– ArriaArria, , ArriaArria IIII
•• The library contains more than The library contains more than 250 250 IP cores in total IP cores in total
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AgendaAgenda
•• IntroductionIntroduction–– Concept of embedded test instrumentsConcept of embedded test instruments
•• Applications for FPGAApplications for FPGA--enabled PCB testenabled PCB test•• ChipVORXChipVORX FPGA instrumentation platformFPGA instrumentation platform•• ChipVORXChipVORX InstrumentsInstruments
–– Flash accelerationFlash acceleration–– RAM testRAM test–– Frequency measurementsFrequency measurements
•• ConclusionsConclusions
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ChipVORX instrumentsChipVORX instruments
•• Each instrument is preEach instrument is pre--synthesized IP which is readysynthesized IP which is ready--toto--useuse–– Universal instrument IP core can be customized on demandUniversal instrument IP core can be customized on demand
Flash acceleratorFlash accelerator
AtAt--speed RAM testspeed RAM test
Frequency counterFrequency counter
•• Currently implemented instruments:Currently implemented instruments:
•• Planned instruments:Planned instruments:–– Bit Error Rate Tester (BERT)Bit Error Rate Tester (BERT)–– Embedded logic signal analyzerEmbedded logic signal analyzer
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•• Fully automated Fully automated ““pushpush--buttonbutton”” solutionsolution•• 10x10x average speedaverage speed--up compared to Boundary Scanup compared to Boundary Scan•• Up toUp to 100x100x for serial Flashes (SPI) and for serial Flashes (SPI) and PROMsPROMs•• No extra hardware or engineering efforts requiredNo extra hardware or engineering efforts required
•• Full controlFull control over the Flash model and protocolover the Flash model and protocol•• ProjectProject--specific IP customization allows to achieve specific IP customization allows to achieve
maximal possiblemaximal possible Flash programming speedFlash programming speed
ChipVORX Flash Accelerator IPChipVORX Flash Accelerator IP
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Typical BS vs. ChipVORX accelerationTypical BS vs. ChipVORX acceleration
Flash Programing Flash Verification
Test time
Typical Boundary Scan test batch run time breakdown
Accelerated test batch run time
#Example: SPI Flash 4MB
0,1 7,12,88
36,18
0
5
10
15
20
25
30
35
40
KB
ytes
/s
SPI Flash @10MHz Flash @20MHz
JTAG-Based ISPChipVORX ISP
Infrastructure, Interconnect,RAM & Cluster Tests
Flash ProgrammingFlash Verification
Data Throughput
FPGA
BS Register
JTAG
Traditional ISP Flash AcceleratorFlash programming using Boundary Scan Register
IP Core acts as an embedded Flash Programmer
6 hours# 5 minutes#75x faster!
FPGA
JTAG
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BS Flash ProgrammingBS Flash Programming
Cells used in testCells not used
•• LongLong Boundary Scan register (BSR) with Boundary Scan register (BSR) with fewfew cells usedcells used•• Test data is transported to BSR over JTAG portTest data is transported to BSR over JTAG port•• One test patternOne test pattern transported at a time using long DRtransported at a time using long DR--shiftshift•• EXTEST EXTEST instructioninstruction is used to apply test data to UUTis used to apply test data to UUT•• FPGA logic is FPGA logic is notnot used in testused in test
FPGAFPGA
FPGA logic not used in testFPGA logic not used in testFPGA logic not used in testJTAGJTAG
•• Boundary Scan register (BSR) is Boundary Scan register (BSR) is notnot usedused•• FPGA logic is programmed withFPGA logic is programmed with ChipVORXChipVORX IP coreIP core•• Test data is transported to IP over JTAG portTest data is transported to IP over JTAG port•• Test patterns are transported using Test patterns are transported using short short DRDR--shiftsshifts•• ChipVORXChipVORX IP IP handles test data application to UUThandles test data application to UUT
FPGAFPGA
JTAGJTAGUniversal Flash Programming IPUniversal Flash Programming IPUniversal Flash Programming IP
ChipVORX at-speed memory testChipVORX at-speed memory test
•• HighHigh--speed or atspeed or at--speed applicationspeed application of test patternsof test patterns–– Capable to discover more potential faults than static testingCapable to discover more potential faults than static testing–– Refresh rate requirements are metRefresh rate requirements are met–– PLL on clock net is not a problem due to atPLL on clock net is not a problem due to at--speed testspeed test
•• Memory test includes diagnostic informationMemory test includes diagnostic information–– 10x speed10x speed--up of diagnostic memory tests in comparison with BSup of diagnostic memory tests in comparison with BS
•• Universal IP Universal IP –– no adaptation for specific PCB is neededno adaptation for specific PCB is needed•• Full automation for DDR RAM test generationFull automation for DDR RAM test generation
–– Generated BS test patterns are applicable for Generated BS test patterns are applicable for ChipVORXChipVORX testtest
ChipVORX at-speed RAM test IPChipVORX at-speed RAM test IP
•• Boundary Scan register (BSR) is Boundary Scan register (BSR) is notnot usedused•• FPGA logic is programmed withFPGA logic is programmed with ChipVORXChipVORX RAM test IP coreRAM test IP core•• Pins attached to RAM are configured to corresponded I/O standardPins attached to RAM are configured to corresponded I/O standard•• Test data is transported to IP over JTAG port and stored insideTest data is transported to IP over JTAG port and stored inside•• Test patterns are applied to DUT atTest patterns are applied to DUT at--speedspeed•• Test results are fetched from IP for diagnosisTest results are fetched from IP for diagnosis
FPGAFPGA
JTAGJTAGDDR RAM test IPDDR RAM test IPDDR RAM test IP
USER1USER1USER1JTAG portJTAG portData
AccumulationAt-speed test
application unit DDR RAM
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ChipVORX Frequency Measurement IPChipVORX Frequency Measurement IP
•• Boundary Scan can only test if clock signal is changingBoundary Scan can only test if clock signal is changing–– Clock frequency canClock frequency can’’t be measuredt be measured
•• ССhipVORXhipVORX IP for precise clock measurementsIP for precise clock measurements–– Current measurements range:Current measurements range: 1MHz1MHz to to 200MHz200MHz–– Instrument precision (current version): Instrument precision (current version): ~20ppm (200Hz / 100Mhz)~20ppm (200Hz / 100Mhz)–– Accuracy depends on precision of TCK frequencyAccuracy depends on precision of TCK frequency–– Measurement takes about Measurement takes about 11 second (second (10MHz10MHz TCKTCK))
•• Experimental resultsExperimental results
64.001121
48.000996Measured
0.0018%10MHz64.0MHzxc3s200
0.0021%10MHz48.0MHzxc3s50aErrorTCKClockFPGA
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Frequency measurement principleFrequency measurement principle
……JTAG TCK(known freq.)
clock signal(unknown freq) ……
Start to count clock pulses N
Stop clock pulses counting
Clock frequency is: f = N / TCauses of potential measurement error:
• Inaccurate TCK signal frequency• Phases of TCK and measured clock differ
Known period of time T
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AgendaAgenda
•• IntroductionIntroduction–– Concept of embedded test instrumentsConcept of embedded test instruments
•• Applications for FPGAApplications for FPGA--enabled PCB testenabled PCB test•• ChipVORXChipVORX FPGA instrumentation platformFPGA instrumentation platform•• ChipVORXChipVORX InstrumentsInstruments
–– Flash accelerationFlash acceleration–– RAM testRAM test–– Frequency measurementsFrequency measurements
•• ConclusionsConclusions
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ConclusionsConclusions
•• FPGAFPGA--embedded instruments bring new dimension to embedded instruments bring new dimension to PCB testingPCB testing–– Capable to overcome many drawbacks of Boundary Scan testsCapable to overcome many drawbacks of Boundary Scan tests–– Extend the limits of existing test methodsExtend the limits of existing test methods
•• ChipVORXChipVORX technology offers a platform for usage of technology offers a platform for usage of embedded instrumentationembedded instrumentation–– ReadyReady--made universal made universal ChipVORXChipVORX IPsIPs embeddable into FPGA embeddable into FPGA
((Flash Accelerator, RAM test, Clock testFlash Accelerator, RAM test, Clock test))–– Platform for development of customized Platform for development of customized IPsIPs for specific test for specific test
