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Field Programmable Gate Array
Tutorial&
SystemVue implementation
Dang PhamEMLab
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Part 1: Tutorial on FPGA
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Tutorial on FPGA
Programmable (= reconfigurable) Digital System Component
o Basic components
Combinational logics (CL)
Flip Flops (FF)
o Macro components
Multiplier ( large combinational logic)
Random Access Memory RAM (Large Density)
Read Only memory ROM (Large Density)
CPU
o Programmable Interconnection
o Programmable Input/Output circuit
o Programmable Clock Generator
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FPGA Combination Logic
What is Combination Logic
If output f, g are function of only inputs (A, B, C, D)then the circuit is combinational circuit. In another word, output signal is determined by only the combination of
input signals.o f = func1(A, B, C, D)
o g = func2(A, B, C, D)
Combinational logic does NOT include memories such as Flip-Flops. Combinational logic can be constructed by just primitive gates such as NOT,
NAND, NOR, etc. (But no feedback loop).
CLABCD
f
g
A, B, C, D, f, g are all binary signal.
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FPGA Combination Logic
There is no signal loop in the circuit. In combinational logic, signal loop is prohibitedsince the loop makes states (Memory).
Function is not configurable.
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FPGA Clock D Latch
1 bit memory by NOR cross-loop When CLK=1, Q = D, /Q=not(D) When CLK=0, Q holds previous data.
D
CLK
Q
Q
Q
Q
When CLK=1
D Q
Q
When CLK=0
D Q
CLKCIRCUIT SYMBOL:
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Master-Slave D Flip-Flop
2 LATCHES in series Still work as 1 bit memory CLK edge Trigger Operation Most commonly used memory element in the
state-of-the-art synchronous Digital Design.
Q only changes CLK edge (once in one cycle).D Q
D Q
CLK
D Q
CLK
CLK
D Q
CIRCUIT SYMBOL:
CLK
D
Q 1 1 0 1 0
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FPGA = CL + FF
FPGA supports such digital circuit with configurability. FPGAs basic element is CL + FF
CL
D Q
D Q
D Q
D Q
CL
CL
D Q
D QCL
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Xilinx XC3000 FPGA structure
XC3000 used original FPGA structure with IOB, CLB, Memory
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Xilinx XC3000 IOB
Summary of I/O Options
Inputs
- Direct
- Flip-flop/latch- CMOS/TTL threshold (chip
inputs)
- Pull-up resistor/open circuit
Outputs
- Direct/registered
- Inverted/not
- 3-state/on/off- Full speed/slew limited
- 3-state/output enable
(inverse)
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Xilinx XC3000 CLB
Each CLB includes a combinatorial logic
section, two flip-flops and a program
memory controlled multiplexer selection of
function. It has the following:
- 5 logic variable inputs A, B, C, D, and E
- a direct data in DI- an enable clock EC
- a clock (invertible) K
- an asynchronous direct RESET RD
- two outputs X and Y
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Xilinx XC3000 CLB Interconnection
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Xilinx XC3000 CLB Interconnection
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Xilinx Virtex Structure
Xilinx introduces Virtex structure with new FPGA products: includingVirtex-4, Virtex-5 upto Virtex-7.
CLB contains of 2 slices
- No connection between slices in
same CLB
- Each slice connect to Switch matrix
to route the sequence.
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Xilinx Virtex structure
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Xilinx Virtex structure
Slice contains of:
- 4 LUT for logical functiongenerator
- MUXs- Carry logic
Slice can provide:
- logic, arithmetic, ROMfunction.- Store data using Block
RAM and shift data with
32bit reg
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Xilinx Virtex structure
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Xilinx Virtex structure
To increase performance of FPGA in DSP, Xilinx provides MacroBlock, such as: DSP48 Slice, CLK Management and PLL, LowPower Gigabit Transceivers, Interface with PCIe
Digital Signal Processing DSP48 SliceSome highlights of the DSP functionality include:
o 25 18 two's complement multiplier/accumulator high-resolution
(48 bit) signal processor
o Power saving pre-adder to optimize symmetrical filter
applications
o Advanced features: optional pipelining, optional ALU, and
dedicated buses for cascading
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Summary of Xilinx Virtex-7
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Part 2: FPGA prototypingwith Agilent SystemVue
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Fixed-Point Representation
SystemVue FixedPoint Data Type has the computational behavior ofSystemC TM 2.2 fixed point type based on IEEE Std. 1666 TM LanguageReference Manual (LRM). The fixed point representation based on thatstandard is as follows:
FxpDataTypewhere,o WL - total wordlength,
o IWL - integer wordlength,
o IsSigned - Unsigned number for Zero and Signed Number for One.
o Q_mode - Quantization mode; determines the behavior when the number to be represented
requires more precision than is availableo S_mode - Saturation mode; determines the behavior when the number to be represented is
outside the dynamic range covered
o n_bits - number of saturated bits (used by Saturation mode)
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Fixed-Point Representation
FxpDataType
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Fixed-Point Representation
Same bits, different fixed-point representation
interprets to dif ferent value!
Read more on Saturation and Quantization in SystemVue Tutorials
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Fixed-Point HDL Blockin Agilent SystemVue
Fixed-Point for CL Fixed-Point for Multirate Fixed-Point for Macro Hdl Cosimulation
ABS Fxp DownSampleFxp CORDIC RotationFxp HDL
BitMergeFxp UpSampleFxp CORDIC VectoringFxp HIL
CompareConstFxp CounterFxp XilinxIPIntegrator
CompareFxp ParToSerFxp FFT Fxp
ConstFxp SerToParFxp FIR Fxp
ExtractFxp PulseTrainMuxFxp TriggeredWaveFormFxp
LookUpTableFxp
MapperFxp SPRamFxp
AND Fxp MpyFxp
NAND Fxp DivFxp
NOR Fxp GainFxp
NOT Fxp SqrtFxpOR Fxp AddFxp
XNOR Fxp AddCarryFxp
XOR Fxp AccumulatorFxp
LatchFxp SubFxp
RegisterFxp
FloatToFxp ShiftFxp
FxpToFloat DPRamFxp
FxpToFxp DelayFxp
Simple Combination logic Block
- Bit Manipulation
- Fixed-Point Conversion
- LUT
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Fixed-Point HDL Blockin Agilent SystemVue
Fixed-Point for CL Fixed-Point for Multirate Fixed-Point for Macro Hdl Cosimulation
ABS Fxp DownSampleFxp CORDIC RotationFxp HDL
BitMergeFxp UpSampleFxp CORDIC VectoringFxp HIL
CompareConstFxp CounterFxp XilinxIPIntegrator
CompareFxp ParToSerFxp FFT Fxp
ConstFxp SerToParFxp FIR Fxp
ExtractFxp PulseTrainMuxFxp TriggeredWaveFormFxp
LookUpTableFxp
MapperFxp SPRamFxp
AND Fxp MpyFxp
NAND Fxp DivFxp
NOR Fxp GainFxp
NOT Fxp SqrtFxpOR Fxp AddFxp
XNOR Fxp AddCarryFxp
XOR Fxp AccumulatorFxp
LatchFxp SubFxp
RegisterFxp
FloatToFxp ShiftFxp
FxpToFloat DPRamFxp
FxpToFxp DelayFxp
HDL Block with different Clock
of Data Input and Data Output
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Fixed-Point HDL Blockin Agilent SystemVue
Fixed-Point for CL Fixed-Point for Multirate Fixed-Point for Macro Hdl Cosimulation
ABS Fxp DownSampleFxp CORDIC RotationFxp HDL
BitMergeFxp UpSampleFxp CORDIC VectoringFxp HIL
CompareConstFxp CounterFxp XilinxIPIntegrator
CompareFxp ParToSerFxp FFT Fxp
ConstFxp SerToParFxp FIR Fxp
ExtractFxp PulseTrainMuxFxp TriggeredWaveFormFxp
LookUpTableFxp
MapperFxp SPRamFxp
AND Fxp MpyFxp
NAND Fxp DivFxp
NOR Fxp GainFxp
NOT Fxp SqrtFxpOR Fxp AddFxp
XNOR Fxp AddCarryFxp
XOR Fxp AccumulatorFxp
LatchFxp SubFxp
RegisterFxp
FloatToFxp ShiftFxp
FxpToFloat DPRamFxp
FxpToFxp DelayFxp
Complex HDL Block with pre-
designed function:
- Multiply
- FFT- RAM, ROM, Register
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Fixed-Point HDL Blockin Agilent SystemVue
Fixed-Point for CL Fixed-Point for Multirate Fixed-Point for Macro Hdl Cosimulation
ABS Fxp DownSampleFxp CORDIC RotationFxp HDL
BitMergeFxp UpSampleFxp CORDIC VectoringFxp HIL
CompareConstFxp CounterFxp XilinxIPIntegrator
CompareFxp ParToSerFxp FFT Fxp
ConstFxp SerToParFxp FIR Fxp
ExtractFxp PulseTrainMuxFxp TriggeredWaveFormFxp
LookUpTableFxp
MapperFxp SPRamFxp
AND Fxp MpyFxp
NAND Fxp DivFxp
NOR Fxp GainFxp
NOT Fxp SqrtFxpOR Fxp AddFxp
XNOR Fxp AddCarryFxp
XOR Fxp AccumulatorFxp
LatchFxp SubFxp
RegisterFxp
FloatToFxp ShiftFxp
FxpToFloat DPRamFxp
FxpToFxp DelayFxp
Co-simulation block:
- To use available HDL code
- To co-simulation IP fromVendor.
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HDL Code Generationwith Fixed-Point
The HDL Code Generation capability in SystemVue provides an easypath from schematic design to hardware. The flow starts by creatingSystemVue sub-network model using synthesizable Fixed-Point partsfrom Hardware Design Library, as well as imported HDL code throughthe HDL cosim block and XilinxIPIntegrator.
1. HDL only: generates the HDL files of the synthesizeable fixed point parts inside the sub-
network in addition to several additional HDL files for simulation, clock and reset handling.
2. Xilinx FPGA: in addition to the HDL files, a Xilinx ISE project is created to target Xilinx FPGA
devices (Virtex 4/5/ and 6)
3. Altera FPGA: in addition to the HDL files, a Quartus II project is created to target Altera FPGA
devices (Cyclone IV E/GX,Stratix IV, Stratix V).
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E.g: HDL Code Generationwith Fixed-Point
Modulo CounterIf (Reset = 1)
Output = 0;
else
if(En = 0)
Output(n) = Output(n-1);else
Output(n) = Output(n-1) + CountStep;
if (Output > Count2Thres)
Output = 0;
endif
endif
endif
Parameter:
CountStep: Increase value (default=1)
Count2Thres: Count from 0 to this value
IntLen: number of bit
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E.g: HDL Code Generationwith Fixed-Point
Modulo Counter
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E.g: HDL Code Generationwith Fixed-Point
Modulo Counter Subnetwork
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E.g: HDL Code Generationwith Fixed-Point
Modulo Counter Timing
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E.g: HDL Code Generationwith Fixed-Point
HDL Code Generation.
Target:
1. HDL file only
2. Xilinx FPGA3. Altera FPGA
Select Xilinx FPGA and
detail option to trigger
Xilinx ISE Project.
More detail information in Help and
Examples
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E.g: HDL Code GenerationSetup and Config
Paths of Mentor Graphics
Modelsimand Xilinx ISEfor HDL Code Generation,
Co-simulation.
!Note:
- Modelsim Student Edition cannot
be used for co-simulation.
- SystemVue only uses ModelSimSE 32-bit for Cosimulation.
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E.g: HDL Code GenerationSetup and Config
SystemVue:- Fixed-point design and simulation- Generate VHDL/Verilog codes- Cosimulate custom VHDL/Verilog code- Export project to Xilinx ISE for FPGA Prototype
ModelSim- Verify HDL codes with testbed- To program custom
VHDL/Verilog
Xilinx ISE Design Suite- FPGA Prototype
- Timing Constrains andArea Constrain
- Floor Planning- I/O pins- Interfaces: UART, PCIe,
DDR.- XilinxIP Cores: FFT, Error
Corrections..
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E.g: HDL Code Generationwith Fixed-Point
ModelSim Project.Test Vector and Testbed generated by SystemVue
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E.g: HDL Code Generationwith Fixed-Point
Xilinx ISE -> View RTL Schematic
View with HDL block and Macro
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E.g: HDL Code Generationwith Fixed-Point
Xilinx ISE -> View Technology Schematic
View with actual CLB
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E.g: HDL Code Generationwith Fixed-Point
Xilinx ISE -> Design Summary
Slices used = 18
4LUT = 32
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Read more
[1]. SystemVue 2013.01 Tutorial
[2]. FPGA Prototype with Agilent SystemVue
[3]. Examples in SystemVue
Practice more!
Enjoy more!
https://docs.google.com/a/emlab.info/file/d/0B_dZN_DDQNnNM2RqeGE1eUdPVDA/edit?usp=sharinghttps://docs.google.com/a/emlab.info/file/d/0B_dZN_DDQNnNM3N6Q0U1UHJMNGc/edit?usp=sharinghttps://docs.google.com/a/emlab.info/file/d/0B_dZN_DDQNnNM3N6Q0U1UHJMNGc/edit?usp=sharinghttps://docs.google.com/a/emlab.info/file/d/0B_dZN_DDQNnNM2RqeGE1eUdPVDA/edit?usp=sharing