FPGA

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Virtex-4 FPGA PCB Designers Guide

UG072 (1.2) June 24, 2008

Virtex-4 FPGA PCB Designers Guide www.xilinx.com UG072 (1.2) June 24, 2008

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.

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Revision HistoryThe following table shows the revision history for this document.

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Version Revision

08/02/04 1.0 Initial Xilinx release. Chapter 15 in printed Handbook is Chapter 4 in version 1.1.

09/09/04 1.1 Added Preface and Chapters 1, 2, and 3. Minimal revisions to Chapter 4.

06/24/08 1.2 Removed SSTL3 rows from Table 2-1, page 14. Updated Appendix A, References.

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 1: PCB Technology BasicsPCB Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Pads and Anti-Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Lands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Return Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 2: SelectIO SignalingInterface Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Single-Ended versus Differential Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13SDR versus DDR Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Single-Ended Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Modes and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Input Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Topologies and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Unidirectional Topologies and Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Bidirectional Topology and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Bidirectional Multi-Point Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Chapter 3: Multi-Gigabit Serial Signaling

Chapter 4: Power Distribution SystemPower Distribution Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Basic Decoupling Network Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

What is the Role of Inductance? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Capacitor Parasitic Inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Inductance from PCB Current Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mounting Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Plane Inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35PCB Stackup and Layer Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table of Contents


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Capacitor Effective Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Capacitor Anti-Resonance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Capacitor Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

PDS Design and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Step 1: Determining Critical Parameters of the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . 42Step 2: Designing the Generic Bypassing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Step 3: Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Step 4: Building the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Step 5: Measuring Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Noise Magnitude Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Noise Spectrum Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Step 6: Optimum Bypassing Network Design (Optional) . . . . . . . . . . . . . . . . . . . . . . . 49Other Concerns and Causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Possibility 1: Excessive Noise from Other Devices on Board . . . . . . . . . . . . . . . . . . . . 50Possibility 2: Parasitic Inductance of Planes, Vias, or Connecting Traces . . . . . . . . . . 50Possibility 3: I/O Signals in PCB are Stronger Than Necessary . . . . . . . . . . . . . . . . . . 51Possibility 4: I/O Signal Return Current Travelling in Sub-Optimal Paths . . . . . . . . 51

Calculation of Via Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52SPICE Simulation Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

HSPICE Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53HSPICE Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Schematic Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

EDA Tools for PDS Design and Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Appendix A: References


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Preface

About This Guide

This designers guide provides information on the design of PCBs for Virtex-4 devices. It considers all aspects of the PCB from the system level down to the minute details. Instead of providing information on device features and specifications, this design guide focuses on strategies for making design decisions at the PCB and interface level.

Guide ContentsThis manual contains the following chapters:

Chapter 1, PCB Technology Basics Discusses the basics of current PCB technology focusing on physical structures and common assumptions.

Chapter 2, SelectIO Signaling Contains information on the choice of SelectIO standards, I/O topologies, and termination strategies as well as information on simulation and measurement techniques.

Chapter 3, Multi-Gigabit Serial SignalingProvides PCB information and electrical requirements related to serial transceivers.

Chapter 4, Power Distribution SystemCovers the power distribution system for Virtex-4 FPGAs, including all details of decoupling capacitor selection, use of voltage regulators and PCB geometries, simulation and measurement.

Appendix A, ReferencesProvides additional information on references listed in this document.

Additional DocumentationThe following documents are also available for download at http://www.xilinx.com/virtex4.

Virtex-4 Family OverviewThe features and product selection of the Virtex-4 family are outlined in this overview.

Virtex-4 FPGA Data Sheet: DC and Switching CharacteristicsThis data sheet contains the DC and Switching Characteristic specifications for the Virtex-4 family.

http://www.xilinx.comhttp://www.xilinx.com/virtex4

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Preface: About This GuideR

Virtex-4 FPGA User GuideThis guide includes chapters on:

Clocking Resources

Digital Clock Manager (DCM)

Phase-Matched Clock Dividers (PMCD)

Block RAM and FIFO memory

Configurable Logic Blocks (CLBs)

SelectIO Resources

SelectIO Logic Resources

Advanced SelectIO Logic Resources

System Monitor

XtremeDSP Design ConsiderationsThis guide describes the XtremeDSP slice and includes reference designs for using DSP48 math functions and various FIR filters.

Virtex-4 FPGA Configuration GuideThis all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG configuration, reconfiguration techniques, and readback through the SelectMAP and JTAG interfaces.

Virtex-4 FPGA Packaging and Pinout SpecificationThis specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

Virtex-4 RocketIO Multi-Gigabit Transceiver User GuideThis guide describes the RocketIO Multi-Gigabit Transceivers available in the Virtex-4-FX family.

Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User GuideThis guide describes the Tri-mode Ethernet Media Access Controller available in the Virtex-4 FX family.

PowerPC 405 Processor Block Reference GuideThis guide is updated to include the PowerPC 405 processor block available in the Virtex-4 FX family.

Additional Support ResourcesTo search the database of silicon and software questions and answers, or to create a technical support case in WebCase, see the Xilinx website at:http://www.xilinx.com/support.

http://www.xilinx.comhttp://www.xilinx.com/support

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Typographical ConventionsR

Typographical ConventionsThis document uses the following typographical conventions. An example illustrates each convention.

Convention Meaning or Use Example

Italic font

References to other documentsSee the Virtex-4 FPGA Configuration Guide for more information.

Emphasis in text The address (F) is asserted after clock event 2.

Underlined Text Indicates a link to a web page. http://www.xilinx.com/virtex4

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Preface: About This GuideR



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Chapter 1

PCB Technology Basics

Printed Circuit Boards (PCBs) are electrical systems, having electrical properties just as complicated as the discrete components and devices mounted to them. The PCB designer has complete control over many aspects of the PCB. At the same time, current technology places constraints and limits on the geometries and resulting electrical properties. The following information is provided first as a primer, but also as a guide to the freedoms, limitations, and techniques for PCB designs using FPGAs.

This chapter contains the following sections:

PCB Structures Transmission Lines Return Currents

PCB StructuresPCB technology has not changed significantly in the last few decades. An insulative substrate material (usually FR4, an epoxy/glass composite) with copper plating on both sides has portions of copper etched away to form conductive paths. A number of layers of plated and etched substrates are glued together in a stack with additional insulative substrates in-between the etched substrates. Holes are drilled through the stack. Conductive plating is applied to these holes, selectively forming conductive connections between the etched copper of different layers.

While there are advancements the areas of material properties, number of stacked layers, geometries, and drilling techniques (allowing holes that only penetrate only a portion of the stackup), the basic structures of PCBs have not changed. These structures, formed through the processes outlined above, are abstracted to a set of physical/electrical structures: Traces, Planes (or planelets), vias, and pads.

TracesA trace is a physical strip of metal (usually copper) making an electrical connection between two or more points on an X-Y coordinate of a PCB. Traces carry signals between these points.

PlanesA plane is an uninterrupted area of metal covering the entirety of a PCB layer. A planelet, a variation of a plane, is an uninterrupted area of metal covering only a portion of a PCB layer. Typically a number of planelets exist in one PCB layer. Planes and planelets distribute power to a number of points on a PCB. They are very important in the transmission of signals along traces.



Chapter 1: PCB Technology BasicsR

ViasA via is a physical piece of metal making an electrical connection between two or more points in the z-space of a PCB. Vias carry signals or power between layers of a PCB. In current plated-through-hole (PTH) technology, a via is formed by plating the inner surface of a hole drilled through the PCB. A via is formed in current microvia technology (also known as High Density Interconnect or HDI) with a laser by ablating the substrate material and deforming the conductive plating, in the process forming a conductive connection. These types of Microvias formed cannot penetrate more than one or two layers, however, they can be stacked or stair-stepped to form vias traversing the full board thickness.

Pads and Anti-PadsPads are small areas of copper in prescribed shapes. Anti-pads are small areas in prescribed shapes where copper is removed. Pads are used both with vias and as exposed outer-layer copper for mounting of surface-mount components. Anti-pads are used mainly with vias.

Since plated through-hole vias are conductive over the whole length, a method is needed to selectively making electrical connections to traces, planes and planelets of the various layers of a PCB. This is the function of pads and anti-pads.

For a via to make a solid connection to a trace on a PCB layer, a pad must be present for mechanical stability. The size of the pad must meet drill tolerance/registration restrictions.

Anti-pads are used in a similar capacity but in reverse. Since plane and planelet copper is otherwise uninterrupted, any via travelling through it makes an electrical connection to it. Where vias are not intended to make an electrical connection to the planes or planelets passed through, an anti-pad removes copper in the area of the layer where the via penetrates.

LandsFor the purposes of soldering surface mount components, pads on outer layers are typically referred to as lands or solder lands. Making electrical connections to these lands usually requires vias. Due to manufacturing constraints of PTH technology, it is rarely possible to place a via inside the area of the land. Instead, this technology uses a short section of trace connecting to a surface pad, and minimum dimension specifications exist defining the minimum length of the connecting trace. Microvia technology is not constrainted and vias can be placed directly in the area of a solder land.

DimensionsThe major factors defining the dimensions of the PCB are FPGA package geometries, PCB manufacturing limits, and system compliance. Other factors such as Design For Manufacturing (DFM) and reliability impose further limits, but as these are application specific, they are not covered here.

The dimensions of the FPGA package, in combination with PCB manufacturing limits define most of the geometric aspects of the above structures, both directly and indirectly. This in itself constrains the PCB designer significantly. The package ball pitch (1.0 mm for FF packages; 0.8 mm for SF packages) defines the land pad layout. The minimum surface feature sizes of current PCB technology define the via arrangement in the area under the device. Minimum via diameters and keep-out areas around those vias defined by the



Transmission LinesR

PCB manufacturer limit the amount of space available in-between vias for routing of signals in and out of the via array underneath the device. This defines the maximum trace width in these breakout traces. PCB manufacturing limits constrain the minimum trace width and minimum spacing.

The number of signal layers necessary to accommodate an FPGA is defined by the number of signal layers and the number of plane layers. The number of signal layers are defined by the number of I/O signal traces to routed in and out of an FPGA package (usually following the total User I/O count of the package). The number of plane layers is defined by the number of power and ground plane layers necessary to bring power to the FPGA and to provide references and isolation for signal layers. Most PCBs for large FPGAs range from 12 to 22 layers.

System compliance often defines the total thickness of the board. Along with the number of board layers, this defines the maximum layer thickness, and therefore the spacing in the z direction of signal and plane layers to other signal and plane layers. Z-direction spacing of signal trace layers to other signal trace layers affects crosstalk. Z-direction spacing of signal trace layers to reference plane layers affects signal trace impedance. Z-direction spacing of plane layers to other plane layers affects power system parasitic inductance.

Z-direction spacing of signal trace layers to reference plane layers (defined by total board thickness and number of board layers) is a defining factor in trace impedance.Trace width (defined by FPGA package ball pitch and PCB via manufacturing constraints) is another factor in trace impedance. A designer has little control over trace impedance in area of the via array beneath the FPGA. When traces escape the via array, their width can change to the width of the target impedance (usually 50 single-ended or 100 differential).

Bypass capacitor placement and discrete termination resistor placement are other areas of trade-off optimization. DFM constraints often define a keep-out area around the perimeter of the FPGA (device footprint) where no discrete components may be placed. The purpose of this is to allow room for rework where necessary. For this reason, the area just outside the keep-out area is one where components will compete for placement. It is up to the PCB designer to determine the high priority components. Bypass capacitor placement constraints are described in Chapter 4, Power Distribution System. Termination resistor placement constraints must be determined through signal integrity simulation, using IBIS or SPICE.

Transmission LinesThe combination of a signal trace and a reference plane forms a transmission line. All I/O signals in a PCB system travel through transmission lines.

For single-ended I/O interfaces, both the signal trace and the reference plane are necessary to transmit a signal from one place to another on the PCB. For differential I/O interfaces, the transmission line is formed by the combination of two traces and a reference plane. While the presence of a reference plane is not strictly necessary in the case of differential signals, it is necessary for practical implementation of differential traces in PCBs.

Good signal integrity in a PCB system is dependent on having transmission lines with controlled impedance. Impedance is determined by the geometry of the traces and the dielectric constant of the material in the space around the signal trace and between the signal trace and the reference plane.

The dielectric constant of the material in the vicinity of the trace and reference plane is a property of the PCB laminate materials, and in the case of surface traces, a property of the air or fluid surrounding the board. PCB laminate is typically a variant of FR4, though it can also be an exotic material.



Chapter 1: PCB Technology BasicsR

While the dielectric constant of the laminate varies from board to board, it is fairly constant within one board. Therefore the relative impedance of transmission lines in a PCB is defined most strongly by the trace geometries and tolerances.

Return CurrentsAn often neglected aspect of transmission lines and their signal integrity is return current. It is incorrect to assume that a signal trace by itself forms a transmission line. Currents flowing in a signal trace have an equal and opposite complimentary current flowing in the reference plane beneath them. The relationship of the trace voltage and trace current to reference plane voltage and reference plane current defines the characteristic impedance of the transmission line formed by the trace and reference plane. While interruption of reference plane continuity beneath a trace is not as dramatic in effect as severing the signal trace, the performance of the transmission line and any devices sharing the reference plane is affected.

It is important to pay attention to reference plane continuity and return current paths. Interruptions of reference plane continuity, such as holes, slots or isolation splits, cause significant impedance discontinuities in the signal traces. They can also be a significant contributor to ground bounce and Power Distribution System (PDS) noise from simultaneously switching outputs. The importance of return current paths cannot be underestimated.



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Chapter 2

SelectIO Signaling

The SelectIO term in the Virtex-4 device family refers to the general-purpose I/O and its various settings. With over 20 I/O standards and over 110 variants within these standards, the highly flexible SelectIO resource offers a wide array of choices for designing I/O interfaces.

This chapter provides some strategies for choosing I/O standard, topology, and termination, and offers guidance on simulation and measurement for more detailed decision making and verification. In many cases, higher-level aspects of the system (other device choices or standards support) define the I/O interfaces to be used. In cases where such constraints are not present, it is up to the system designer to choose I/O interface standards and optimize them according to the purpose of the system.


Interface Types Single-Ended Signaling

Interface TypesTo better address the specifics of the various interface types, it is necessary to first break interfaces into categories. Two relevant divisions are made:

Single-Ended interfaces versus Differential interfaces Single Data Rate (SDR) interfaces versus Double Data Rate (DDR) interfaces

Single-Ended versus Differential InterfacesTraditional digital logic uses single-ended signaling a convention that transmits a signal and assumes a Ground common to the driver and receiver. In single-ended interfaces, a signals assertion (whether it is High or Low) is based on its voltage level relative to a fixed voltage threshold that is referenced to Ground. When the voltage of the signal is higher than the VIH threshold, the state is considered High. When the voltage of the signal is lower than the VIL threshold, the state is considered Low. TTL is one common example of a single-ended I/O standard.

Higher-performance interfaces typically make use of differential signaling a convention that transmits two complementary signals referenced to one another. In differential interfaces, a signals assertion (whether it is High or Low) is based on the relative voltage levels of the two complementary signals. When the voltage of the p signal is higher than the voltage of the n signal, the state is considered High. When the voltage of the n signal is higher than the voltage of the p signal, the state is considered Low. Typically the p and n signals have similar swing relative to Ground, although this is not always the case. LVDS is one common example of a differential I/O standard.



Chapter 2: SelectIO SignalingR

SDR versus DDR InterfacesThe difference between Single Data Rate (SDR) and Double Data Rate (DDR) interfaces has to do with the relationship of the data signals of a bus to the clock signal of that bus. In SDR systems, data is only registered at the input flip-flops of a receiving device on either the rising or the falling edge of the clock. One full clock period is equivalent to one bit time. In DDR systems, data is registered at the input flip-flops of a receiving device on both the rising and falling edges of the clock. One full clock period is equivalent to two bit times. The distinction of SDR and DDR has nothing to do with whether the I/O standard carrying the signals is single-ended or differential. A single-ended interface may be SDR or DDR, and a differential interface may also be SDR or DDR.

Single-Ended SignalingA variety of single-ended I/O standards are available in the Virtex-4 FPGA IOB configuration options. Table 2-1 lists all available single-ended I/O standards. The checkmarks indicate which features are available or can be configured for each I/O standard.

Table 2-1: Virtex-4 FPGA Single-Ended I/O Standards

I/O StandardVREF Input Threshold

Configurable Attribute Recommended Mode

Drive Strength

Slew Rate

Pull-up Pull-downWeak

KeeperUnidirectional Bidirectional

LVTTL

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVDCI33

LVDCI25

LVDCI18

LVDCI15

HSLVDCI33

HSLVDCI25

HSLVDCI18

HSLVDCI15

HSTL Class I

HSTL Class II

HSTL Class III

HSTL Class IV

HSTL18 Class I

HSTL18 Class II

HSTL18 Class III



Single-Ended SignalingR

HSTL18 Class IV

HSTL Class I DCI

HSTL Class II DCI

HSTL Class III DCI

HSTL Class IV DCI

HSTL18 Class I DCI

HSTL18 Class II DCI

HSTL18 Class III DCI

HSTL18 Class IV DCI

SSTL2 Class 1

SSTL2 Class 2

SSTL18 Class 1

SSTL18 Class 2

SSTL2 Class 1 DCI

SSTL2 Class 2 DCI

SSTL18 Class 1 DCI

SSTL18 Class 2 DCI

GTL

GTL+

GTL DCI

GTL+ DCI

PCI-33

PCI-66

PCI-X

Table 2-1: Virtex-4 FPGA Single-Ended I/O Standards (Continued)

I/O StandardVREF Input Threshold

Configurable Attribute Recommended Mode

Drive Strength

Slew Rate

Pull-up Pull-downWeak

KeeperUnidirectional Bidirectional




Modes and AttributesSome of these I/O standards can be used only in unidirectional mode, while some can be used in bidirectional mode or unidirectional mode.

Some I/O standards have attributes to control drive strength and slew rate, as well as the presence of weak pull-up or pull-down and weak-keeper circuits (not intended for use as parallel termination). Drive strength and slew rate can be used to tune an interface for adequate speed while not overdriving the signals. Weak pull-ups, weak pull-downs, and weak keepers can be used to ensure a known or steady level on a floating or 3-stated signal. Table 2-1 denotes which standards support these attributes. See the SelectIO chapter in the Virtex-4 FPGA User Guide for more information.

LVCMOS_6F drivers and other weak drivers have an output impedance close to 50 , allowing them to be used as a crude approximation of a controlled-impedance driver. Note that the impedance match of the weak driver to the transmission line is only approximate and varies with voltage and temperature. LVDCI, a true controlled-impedance driver, is adaptive, maintains a much closer impedance match, and remains constant over voltage and temperature.

Input ThresholdsThe input circuitry of the single-ended standards listed in Table 2-1 fall into two categories: those with fixed input thresholds and those with input thresholds set by the VREF voltage. The use of VREF has three advantages:

It allows for tighter control of input threshold levels It removes dependence on die Ground for the threshold reference It allows for input thresholds to be closer together, which reduces the need for a large

voltage swing of the signal at the input receiver

Two 2.5V I/O standards that illustrate this are LVCMOS25 and SSTL2 Class 1. The thresholds for 2.5V LVCMOS are set at 0.7V and 1.7V (necessitating that the signal at the receiver swing a full 1.0V at minimum to make a logic transition). The thresholds for SSTL2 Class 1 are set at VREF 0.15V and VREF + 0.15V, or for a nominal VREF of 1.25V, set at 1.1V and 1.4V (necessitating that the signal at the receiver only swing 0.3V at minimum to make a logic transition). This smaller required swing allows for higher frequency of operation in the overall link. A smaller swing at the driver means reduced DC power is required with less transient current. The one drawback to the use of VREF is that the semi-dedicated VREF pins of the bank cannot be used as I/Os they must all be connected to an external reference voltage with a decoupling capacitor for each VREF pin. For more information on VREF decoupling and decoupling of all other supplies, see Chapter 4, Power Distribution System.

Topologies and TerminationTopology generally refers to the arrangement of drivers, receivers, interconnect and terminations in an interface. The techniques used in unidirectional topologies are different from those used in bidirectional topologies, so these are treated separately.

The SelectIO standards can be used in countless topologies depending on the requirements of the system. SelectIO drivers and receivers adhering to a standard (SSTL, LVCMOS, etc.) either can be used according to the letter of the standard (published by a standards body such as EIA/TIA or JEDEC) or they can be mixed and matched with drivers or receivers from another standard or hybrid I/O. An I/O standard specification might define




something as limited as the VIL and VIH of the receiver, or it might define every aspect of the interface, including driver impedance and slew rate, PCB trace length and topology, value and position of passive termination, the maximum input capacitance of a receiving device, and even the maximum number of receivers.

It is up to the designer to apply the standard in question to the system in which it is working. There are many decisions to make with respect to topologies and termination, which determine the signal integrity of the interface. It is of utmost importance that the signal integrity of each interface is verified through both simulation and measurement.

Termination generally refers to impedance-matching or impedance-compensating devices that are used to maintain signal integrity in an interface. While many types of elements can be used as terminators (such as, resistors, capacitors, diodes), this discussion is limited to resistive termination. In general, capacitor and diode termination techniques are more complicated and are not covered here.

Unidirectional Topologies and Termination

The two basic subsets of unidirectional topologies are point-to-point and multi-drop. A point-to-point topology has one driver and one receiver, while a multi-drop topology has one driver and many receivers. Whether or not a topology is point-to-point or multi-drop defines important aspects of the interface that determine which termination strategies are appropriate and which are not.

Unidirectional Point-to-Point Topologies

The simplest unidirectional topology is point-to-point. That is, there is one driver and one receiver. Termination, if present, can consist of parallel termination at the receiver (Figure 2-1), series termination at the driver (Figure 2-2), or a controlled-impedance driver (Figure 2-3 and Figure 2-4). Always use IBIS simulation to determine the optimal resistor values, VTT voltage level, and VRN/VRP reference resistors for these terminations.

Figure 2-1: Parallel-Terminated Unidirectional, Point-to-Point Topology

Figure 2-2: Series-Terminated Unidirectional, Point-to-Point Topology

Z0 (50 )

ug072_c3_01_082904

RP = Z0 (50 )

VTT

RO (25 )

ug072_c3_02_082904

RS = Z0 R0 (25 )Z0 (50 )

RO (25 )




In general, parallel resistive termination (RP) has a value equal to the characteristic impedance (Z0) of the transmission line it is terminating. Series resistive terminations (RS) have a value equal to the characteristic impedance of the transmission line (Z0) minus the output impedance of the driver (RO) to which they are connected. Controlled-impedance drivers are tuned such that the driver output impedance (RO) is equal to the characteristic impedance (Z0) of the transmission line it is terminating.

Assuming transmission lines with 50 characteristic impedance and a driver output impedance (RO) of 25 , a 25 series termination (Figure 2-2) or a 50 parallel termination (Figure 2-1) is appropriate. Controlled-impedance drivers, whether implemented with DCI or with weak LVCMOS drivers, should be sized to have an output impedance (RO) of 50 . This corresponds to VRN and VRP resistors equal to 50 for DCI. Weak LVCMOS drivers of 6 mA to 8 mA drive strength have an output impedance approximately equal to 50 (Figure 2-3).

Typically, parallel terminations have best performance when VTT (the voltage source connected to the parallel termination resistor) is equal to half of the signaling voltage. For 2.5V signals (VCCO = 2.5V), VTT is ideally 1.25V. In cases where this voltage is not available, it is advisable to use a Thevenin parallel termination. Thevenin parallel termination consists of a voltage divider with a parallel equivalent resistance (RPEQ) equal to the characteristic impedance of the transmission line (50 in most cases). The divided voltage point is designed to be at VTT. Figure 2-5 illustrates a Thevenin parallel termination powered from 2.5V VCCO, made up of two 100 resistors, resulting in a VTT of 1.25V and a parallel equivalent resistance (RPEQ) of 50 .

Parallel termination can be less desirable than series termination or controlled-impedance drivers because it dissipates more power. This trade-off must be weighed against other trade-offs to determine the optimum termination topology for an interface.

Figure 2-3: DCI-Controlled Impedance Driver Unidirectional, Point-to-Point Topology

Figure 2-4: Weak Driver Unidirectional, Point-to-Point Topology

ug072_c3_03_082904

RO = RVRN = RVRP Z0 (50 )LVDCI

Z0 (50 )

ug072_c3_04_082904

LVCMOS_6F

Z0 (50 )

RO Z0 (50 )




Table 2-2 lists I/O interface types that can be used with the unidirectional point-to-point topology.

LVTTL and LVCMOS do not specify any canonical termination method. Series termination at the driver or parallel termination at the receiver are both appropriate.

LVDCI implicitly uses controlled-impedance driver termination. No form of termination is needed at the receiver.

HSTL Class I and HSTL Class III specify a parallel termination at the receiver. In the case of HSTL Class I, the termination voltage VTT is defined as half of the supply voltage VCC. In the case of HSTL Class III, the termination voltage VTT is defined as equal to the supply voltage VCC. The designer may elect either not to use termination at all or to use a different termination, such as series termination at the driver. There are a number of reasons why this selection might be advantageous in a given system. It is up to the designer to verify through simulation and measurement that the signal integrity at the receiver is adequate.

SSTL Class I specifies both series termination at the driver and parallel termination at the receiver. The termination voltage VTT is defined as half of the supply voltage VCC. The designer may elect either not to use termination at all or to use a different termination, such as only series termination at the driver or only parallel termination at the receiver. There are a number of reasons why this might be advantageous in a given system. It is up to the

Figure 2-5: Thevenin Parallel Termination

Table 2-2: I/O Interface Type for Unidirectional Point-to-Point Topologies

LVTTL

LVCMOS

LVDCI

SSTL Class I

HSTL Class I

HSTL Class III

GTL

GTL+

GTLDCI

GTL+DCI

ug072_c3_05_082904

RPT = 2 x Z0 (100 )

RPT = 2 x Z0 (100 )

VCCO = 2.5V

Parallel Equivalent Resistance

VTTEQ = 1.25V

RPEQ = ( 1100 1

100 +)1 = 50

Z0 (50 )

RO (25 )




designer to verify through simulation and measurement that the signal integrity at the receiver is adequate.

GTL and GTL+ specify and require parallel termination both at the driver and at the receiver. The designer may not elect to omit either of these terminations because the driver is open drain, meaning that the driver is not capable of driving a High signal and depends on the parallel termination to generate High logic levels.

Unidirectional Multi-Drop Topologies

In more complex topologies, a single driver can drive multiple receivers. The receivers represent loads that must be fed by individual transmission line stubs. From a signal integrity standpoint, the best topology to use in this case is a single long transmission line with the driver at one end and parallel termination at the other, with receivers connected to the main trace by short stubs in between. This type of topology is often referred to as a flyby multi-drop topology.

There are two critical aspects of this topology. The first is the presence of parallel termination at the far end of the transmission line. Series termination at the driver must never be used. Parallel termination is the only applicable termination type for this topology. The second critical aspect is the length of the connecting stubs at each receiver. These must remain short: no more than 8 mm in length. As the stubs become longer, they present a larger impedance discontinuity to the signal travelling down the transmission line, and can support significant reflections. These impedance discontinuities corrupt the signal. With increasing numbers of loads and increasing length of stubs, the signal is corrupted to the point where it is no longer usable.

Star topologies are not recommended. The constraints involved in designing a star topology with good signal integrity are beyond the scope of this document.

As stated in Unidirectional Point-to-Point Topologies, ideal parallel resistive termination has a value equal to the characteristic impedance of the transmission line it is terminating. The best performance is achieved when VTT is equal to half of the signaling voltage, and when this voltage is not available, a Thevenin parallel termination is recommended, as defined in the previous subsection.

Figure 2-6 illustrates a Thevenin parallel termination powered from VCCO, made up of two 100 resistors, resulting in a VTT of VCCO/2 and a parallel equivalent resistance of 50 . This figure shows a topology with one driver (an LVCMOS driver) and four receivers. The driver is on the left side, the receivers are spaced at interim points across the 50 transmission line, and the Thevenin parallel termination of two 100 resistors is on the right side.




The main transmission line should be kept as short as possible. Lengths up to 20 inches or more are practical for most I/O standards as long as precise trace impedance is maintained and crosstalk sources are avoided. The lengths of interim segments of the main transmission line need not be equal. Their relative lengths may be arbitrary. Receivers at different points along the main transmission line receive the signal with varying amounts of delay, but all signal rise times are similar.

Stubs stretching from the main transmission line to the individual receivers must be kept as short as possible. The longer these stubs become, the more corrupted the received waveforms are. Simulation and measurement are required to assess signal integrity at the individual receivers.

Table 2-3 lists I/O interface types that can be used with the unidirectional point-to-point multi-drop topology.

LVTTL and LVCMOS do not specify any canonical termination method. Parallel termination at the end of the long t-line is the only appropriate termination method.

Bidirectional Topology and Termination

The two basic subsets of bidirectional topologies are point-to-point and multi-point. A point-to-point topology has two transceivers (driver and receiver sharing one device pin), while a multi-point topology may have many transceivers. Whether or not a topology is point-to-point or multi-point defines important aspects of the interface that determine which termination strategies are appropriate and which are not.

Bidirectional Point-to-Point Topologies

The simplest bidirectional topology is point to point. That is, there are two transceivers connected by a transmission line. Because bidirectional interfaces need to operate equally well in both directions, symmetry of the topology is desirable. While asymmetrical topologies can be designed with reasonably good signal integrity, the easiest way to ensure

Figure 2-6: Basic Multi-Drop Topology

OutputMain Transmission Line

Z0 (50 )

Input 4

Z0 (50

)

2 x Z0 (100 )

2 x Z0 (100 )

VCCO

Z0 (50 )

Z0 (50

)

Input 2

length < 8m

m

Z0 (50 )

Z0 (50

)

Input 3

length < 8m

m

Z0 (50 )

Z0 (50

)

Input 1

length < 8m

m

ug072_c3_06_082904

Table 2-3: I/O Interface Types for Multi-Drop Point-to-Point I/O Topologies

LVTTL

LVCMOS




good signal integrity is to keep the topology symmetrical. Thus any termination used on one side of the link should also be used on the other side of the link. Series termination (Figure 2-8) is rarely appropriate for bidirectional interfaces as incoming signals are attenuated by the series resistor of the receiving transceiver. Parallel termination (Figure 2-7) always achieves better signal levels at both receivers. Controlled-impedance drivers, whether crudely controlled in the form of a weak LVCMOS driver or adaptively controlled in the form LVDCI or HSLVDCI, also can have good results as shown in Figure 2-9, Figure 2-10, and Figure 2-11 (implemented with a low-drive strength LVCMOS driver). Always use IBIS simulation to determine the optimal resistor, VTT voltage level and VRN/VRP reference resistor values for these terminations.

Figure 2-7: Parallel Terminated Bidirectional Point-to-Point Topology

Figure 2-8: Series Terminated Bidirectional Point-to-Point Topology: Not Recommended

Figure 2-9: DCI Controlled Impedance Bidirectional Point-to-Point Topology

ug072_c3_07_082904

VTTVTT

Z0 (50 )

RP = Z0 (50 )RP = Z0 (50 )RO (25 )

RO (25 )

ug072_c3_08_082904

RS = Z0 R0 (25 )RS = Z0 R0 (25 )Z0 (50 )

RO (25 )

RO (25 )

ug072_c3_09_082904

LVDCI

LVDCI

Z0 (50 )

RO = RVRN = RVRP Z0 (50 )





In general, parallel resistive termination (RP) has a value equal to the characteristic impedance Z0 of the transmission line it is terminating. Controlled-impedance drivers are tuned such that the driver output impedance (RO) is equal to the characteristic impedance (Z0) of the transmission line it is terminating.

Assuming transmission lines with 50 characteristic impedance and a driver output impedance of 25 , 50 parallel terminations are appropriate (Figure 2-7). Controlled-impedance drivers, whether implemented with DCI or with weak LVCMOS drivers, should be sized to have an output impedance (RO) of 50 . This corresponds to VRN and VRP resistors equal to 50 for DCI (Figure 2-9 and Figure 2-10). Weak LVCMOS drivers of 6 mA to 8 mA drive strength have an output impedance approximately equal to 50 (Figure 2-11).

Typically, parallel terminations have the best performance when VTT (the voltage source connected to the parallel termination resistor) is equal to half of the signaling voltage. For 2.5V signals (VCCO = 2.5V), VTT is ideally 1.25V. In cases where this voltage is not available, it is advisable to use a Thevenin parallel termination. Thevenin parallel termination consists of a voltage divider with a parallel resistance equal to the characteristic impedance of the transmission line (50 in most cases). The divided voltage point is designed to be at VTT. Figure 2-12 illustrates a Thevenin parallel termination powered from 2.5V VCCO, made up of two 100 resistors, resulting in a VTT of 1.25V and a parallel equivalent resistance (RPEQ) of 50 .

Parallel termination can be less desirable than series termination or controlled-impedance drivers because it dissipates more power. This trade-off must be weighed against other trade-offs to determine the optimum termination topology for an interface.

Figure 2-10: HSLVDCI Controlled Impedance Driver Bidirectional Point-to-Point Topology

Figure 2-11: Weak Driver Bidirectional Point-to-Point Topology

ug072_c3_10_082904

HSLVDCI

HSLVDCI

VREF

VREF

Z0 (50 )



ug072_c3_11_082904

LVCMOS_6F

Z0 (50 )

RO Z0 (50 )

LVCMOS_6F

RO Z0 (50 )




Table 2-4 lists I/O interface types that can be used with the bidirectional point-to-point topology.

LVTTL and LVCMOS do not specify any canonical termination method. Series termination is not recommended for bidirectional interfaces. Parallel termination and weak drivers, however, are both appropriate.

LVDCI and HSLVDCI both implicitly use controlled-impedance driver termination.

HSTL Class II and HSTL Class IV specify parallel termination at both transceivers. In the case of HSTL Class II, the termination voltage VTT is defined as half of the supply voltage VCCO. In the case of HSTL Class IV, the termination voltage VTT is defined as equal to the supply voltage VCCO. The designer may elect either not to use termination at all or to use a different termination. It is up to the designer to verify through simulation and measurement that the signal integrity at the receiver is adequate.

Figure 2-12: Thevenin Parallel Termination (Bidirectional Point-to-Point Topology)

ug072_c3_12_082904

RPT = 2 x Z0 (100 ) RPT = 2 x Z0 (100 )

RPT = 2 x Z0 (100 )RPT = 2 x Z0 (100 )

VCCO = 2.5V

VTTEQ = 1.25V

VCCO = 2.5V

Z0 (50 )

RO (25 )

RO (25 )

Table 2-4: I/O Interface Types for Bidirectional Point-to-Point I/O Topologies

LVTTL

LVCMOS

LVDCI

HSLVDCI

SSTL CLASS II

SSTL CLASS II DCI

HSTL CLASS II

HSTL CLASS II DCI

HSTL CLASS IV

HSTL CLASS IV DCI

GTL

GTL+

GTL DCI

GTL + DCI




SSTL Class II specifies both series termination and parallel termination. The termination voltage VTT is defined as half of the supply voltage VCCO. While the canonical standard calls for this, better performance is achieved when only parallel termination is used at both transceivers. The designer may elect to use either the canonical standard termination or a modified termination (or no termination at all). It is up to the designer to verify through simulation and measurement that the signal integrity at the receiver is adequate.

GTL and GTL+ specify and require parallel termination at both transceivers. The designer may not elect to omit either of these terminations because the driver is open drain, meaning that the driver is not capable of driving a High signal and depends on the parallel termination to generate High logic levels.

Bidirectional Multi-Point Topologies

In more complex topologies, any transceiver in a multi-point bus can transmit to all other transceivers. Usually these topologies can only run at very slow clock rates because they only support very slow signal rise times (10 ns to 50 ns). While useful in some situations, the drawbacks usually outweigh the benefits. The constraints involved in designing these topologies with good signal integrity are beyond the scope of this document.



R

Chapter 3

Multi-Gigabit Serial Signaling

This chapter is intentionally left blank for further updates.



Chapter 3: Multi-Gigabit Serial SignalingR



R

Chapter 4

Power Distribution System

This chapter covers the power distribution system for Virtex-4 FPGAs, including all details of decoupling capacitor selection, use of voltage regulators and PCB geometries.


Power Distribution Design Overview Basic Decoupling Network Principles PDS Design and Verification Other Concerns and Causes Calculation of Via Inductance SPICE Simulation Examples EDA Tools for PDS Design and Simulation

Power Distribution Design OverviewFPGA designers are faced with a unique task when it comes to designing power distribution systems (PDS). Most other large, dense ICs (such as large microprocessors) come with very specific bypass capacitor requirements. Since these devices are only designed to implement specific tasks in their hard silicon, their power supply demands are fixed and only fluctuate within a certain range. FPGAs do not share this property. Since FPGAs can implement a practically infinite number of applications at undetermined frequencies and in multiple clock domains, it can be very complicated to predict what their transient current demands will be.

Since exact transient current behavior cannot be known for a new FPGA design, the only choice when designing the first version of an FPGA PDS is to go with a conservative worst-case design.

Transient current demands in digital devices are the cause of ground bounce, the bane of high-speed digital designs. In low-noise or high-power situations, the power supply decoupling network must be tailored very closely to these transient current needs, otherwise ground bounce and power supply noise will exceed the limits of the device. The transient currents in an FPGA are different from design to design. This chapter provides a comprehensive method for designing a bypassing network to suit the individual needs of a specific FPGA design.

The first step in this process is to examine the utilization of the FPGA to get a rough idea of its transient current requirements. Next, a conservative decoupling network is designed to fit these requirements. The third step is to refine the network through simulation and modification of capacitor numbers and values. In the fourth step, the full design is built and in the fifth step it is measured. Measurements are made consisting of oscilloscope and possibly spectrum analyzer readings of power supply noise. Depending on the measured



Chapter 4: Power Distribution SystemR

results, further iterations through the part selection and simulation steps could be necessary to optimize the PDS for the specific application. A sixth optional step is also given for cases where a perfectly optimized PDS is needed.

Basic Decoupling Network PrinciplesBefore starting into the PDS design flow, it is important to understand the basic electrical principles involved. This section discusses the purpose of the PDS and the properties of its components. It also describes important aspects of discrete capacitor placement and mounting as well as PCB geometry and stackup recommendations.

Each device in a system not only has its own wattage requirements for its operation, but also its own requirement for the cleanliness of that power. Most digital devices, including all Virtex-4 FPGAs, have a requirement that on all supplies, VCC must not fluctuate more than 5% above or 5% below the nominal VCC value. In this document VCC is used generically to refer to all FPGA power supplies: VCCINT, VCCO, VCCAUX, and VREF. Multi-gigabit transceiver (MGT) and system monitor analog supplies (AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, AVDD, AVSS) are not covered here. For specific instructions on these supplies, see the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (Reference #1) and the Virtex-4 FPGA User Guide (Reference #2).

This requirement specifies a maximum amount of noise present on the power supply, often referred to as ripple voltage. If the device requirements state that VCC must be within 5% of the nominal voltage, that means peak to peak voltage ripple must be no more than 10% of the nominal VCC. This assumes that nominal VCC is exactly the nominal value given in the data sheet. If this is not the case, then VRIPPLE must be adjusted to a value correspondingly less than 10%.

The power consumed by a digital device varies over time, and this variance occurs on all frequency scales. Low frequency variance of power consumption is usually the result of devices or large portions of devices being enabled or disabled. This can occur on time scales from milliseconds to days. High frequency variance of power consumption is the result of individual switching events inside a device, and this happens on the scale of the clock frequency and the first few harmonics of the clock frequency.

Since the voltage level of VCC for a device is fixed, changing power demands are manifested as changing current demand. The PDS must accommodate these variances of current draw with as little change in power supply voltage as possible.

When the current draw in a device changes, the power distribution system cannot respond to that change instantaneously. For the short time before the PDS responds, the voltage at the device changes. This is where power supply noise appears. There are two main causes for this lag in the PDS corresponding to the two major components of the PDS.

The first major component of the PDS is the voltage regulator. It observes its output voltage and adjusts the amount of current being supplied to keep the voltage constant. Most common voltage regulators make this adjustment on the order of milliseconds to microseconds. They are effective at maintaining output voltage for events at all frequencies from DC to a few hundred kilohertz (depending on the regulator). For all transient events that occur at frequencies above this range, there is a time lag before the voltage regulator can respond to the new level of demand. For example, if current demand in the device increases in a matter of nanoseconds, the voltage at the device sags by some amount until the voltage regulator can adjust to the new, higher level of current it must provide. This lag might take from microseconds to milliseconds, during which time the voltage sags.

The second major component of the PDS is the bypass or decoupling capacitors. In this document, the words bypass and decoupling are used interchangeably. Their function



Basic Decoupling Network PrinciplesR

is to act as local energy storage for the device. They cannot provide DC power, as only a small amount of energy is stored in them (the voltage regulator is present to provide DC power). The function of this local energy storage is to respond very quickly to changing current demands. The capacitors are effective at maintaining power supply voltage at frequencies from hundreds of kilohertz to hundreds of megahertz in the milliseconds to nanoseconds range. Decoupling capacitors are of no use for all events occurring above or below this range. For example, if current demand in the device increases in a few picoseconds, the voltage at the device sags by some amount until the capacitors can supply extra charge to the device. If current demand in the device changes and maintains this new level for a number of milliseconds, the voltage regulator circuit, operating in parallel with the bypass capacitors, effectively takes over for them, changing its output to supply this new current.

Figure 4-1 shows the major components of the PDS: the power supply, the decoupling capacitors, and the active device being powered (in this case, an FPGA).

Figure 4-2 shows a further simplified PDS circuit, showing all reactive components decomposed to a frequency-dependent resistor.

What is the Role of Inductance?There is a property of the capacitors and of the PCB current paths that retards changes in current flow. This is the reason why capacitors cannot respond instantaneously to transient currents, nor to changes that occur at frequencies higher than their effective range. This property is called inductance.

Inductance can be thought of as momentum of charge. Where charge is moving at some rate through a conductor, this implies some amount of current. If the level of current is to change, the charge must move at a different rate. Because there is momentum (stored magnetic field energy) associated with this charge, it takes some amount of time for the charge to slow down or speed up. The greater the inductance, the greater the resistance to change, and the longer it takes for the current level to change.

Figure 4-1: Simplified PDS Circuit

Figure 4-2: Further Simplified PDS Circuit

+

FPGAV

ug072_4_01_080104

ltransient

FPGA

ug072_4_02_080104

ZP VRIPPLE

+

+

V




The purpose of the PDS is to accommodate whatever current demands the device(s) could have, and respond to changes in that demand as quickly as possible. When these demands are not met, the voltage across the device's power supply changes. This is observed as noise. Since inductance retards the abilities of bypass capacitors to quickly respond to changing current demands, it should be minimized.

Figure 4-1 shows inductances between the FPGA device and capacitors, and between the capacitors and the voltage regulator. These inductances arise as parasitics of the capacitors themselves and of all current paths in the PCB. It is important that each of these be minimized.

Capacitor Parasitic InductanceOf a capacitor's various properties, the capacitance value is often considered the most important. However in the domain of PCB PDS design, the property of parasitic inductance (ESL or Equivalent Series Inductance) is of the same or greater importance.

The one factor that influences parasitic inductance more than any other is the dimensions of the package. Very simply, physically small capacitors tend to have lower parasitic inductance than physically large capacitors. Just as a short wire has less inductance than a long wire, a short capacitor has less inductance than a long capacitor. Likewise, as a fat or wide wire has less inductance than a narrow wire, so too does a fat capacitor have less inductance than a narrow capacitor.

For these reasons, when choosing decoupling capacitors, the smallest package should be chosen for a given value. Similarly, for a given package size (essentially a fixed inductance value), the highest capacitance value available in that package should be chosen.

Surface-mount chip capacitors are the smallest capacitors available, making them a good choice for discrete bypass capacitors. For values from 2.2 F down to very small values such as 0.001 F, X7R or X5R type capacitors are usually used. These have low parasitic inductance, and an acceptable temperature characteristic. For larger values, such as 1000 F, tantalum capacitors are used. These have low parasitic inductance and a relatively high equivalent series resistance (ESR), giving them a low-quality factor and consequently a very wide range of effective frequencies. They also provide a comparatively high capacitance value in a small package size, thus reducing board real-estate costs. In cases where tantalum capacitors are not available, low-inductance electrolytic capacitors can be used. Other new technologies with similar characteristics are also available.

A real capacitor has characteristics not only of capacitance but also inductance and resistance. Figure 4-3 shows the parasitic model of a real capacitor. A real capacitor should be treated as an RLC circuit.

Figure 4-4 shows the impedance characteristic of a real capacitor. Overlaid on this plot are the curves corresponding to the capacitors capacitance and parasitic inductance (ESL).

Figure 4-3: Parasitics of a Real, Non-Ideal Capacitor

C

ESL

ESR

ug072_4_03_080104




These two curves combine to form the total impedance characteristic of the RLC circuit formed by the parasitics of the capacitor.

As capacitive value is increased, the capacitive curve moves down and to the left. As parasitic inductance is decreased, the inductive curve moves down and to the right. Since parasitic inductance for capacitors in a given package is essentially fixed, the inductance curve remains fixed. As different capacitor values are selected in that same package, the capacitive curve moves up and down relative to the fixed inductance curve. The only way to decrease the total impedance of a capacitor if the package is fixed is to increase the value of the capacitor. The only way to move the parasitic inductance curve down (and consequently lower the total impedance characteristic), is to connect additional capacitors in parallel.

Inductance from PCB Current PathsThe parasitic inductance of current paths in the PCB have two distinct sources: the capacitor mounting, and the power and ground planes of the PCB.

Mounting Inductance

In this context, the mounting refers to the capacitor's solder land on the PCB, the trace (if any) between the land and via, and the via itself.

The vias, traces, and pads of a capacitor mounting contribute anywhere from 300 pH to 4 nH of inductance depending on the specific geometry. Since the inductance of a current path is proportional to the area of the loop the current traverses, it is important to minimize the size of this loop. The loop consists of the path through one power plane, up through one via, through the connecting trace to the land, through the capacitor, through the other

Figure 4-4: Contribution of Parasitics to Total Impedance Characteristics

Frequency

Impedance

CapacitiveContribution (C)

InductiveContribution (ESL)

Total Impedance Characteristic

ug072_4_04_08010




land and connecting trace, down through the other via, and into the other plane, as shown in Figure 4-5.

By shortening the connecting traces, the area of this loop is minimized and the inductance is reduced. Similarly, by reducing the via length through which the current flows, loop area is minimized and inductance is reduced.

Figure 4-5: Cutaway View of PCB with Capacitor Mounting

Solderable End Terminal

0402 Capacitor BodySurface Trace

Capacitor Solder Land

Via

PCB

GND

VCC

Power and Ground planes

Mounted Capacitor Current Loop

ug072_4_05_080104




The existence and/or length of a connecting trace has a big impact on parasitic inductance of the mounting. Wherever possible, there should be no connecting trace (Figure 4-6a) - the via should butt up against the land itself (Figure 4-6b). Additionally, the connecting trace should be made as wide as possible. Further improvements can be made to the mounting by placing vias to the side of capacitor lands (Figure 4-6c), or doubling the number of vias (Figure 4-6d). Currently, very few PCB manufacturing processes allow via-in-pad geometries, but this is another good option. The technique of using multiple vias per land is important when using ultra-low inductance capacitors, such as reverse aspect ratio capacitors (AVXs LICC).

Many times in an effort to squeeze more parts into a small area, PCB layout engineers opt to share vias among multiple capacitors. This technique should not be used under any circumstances. The capacitor mounting (lands, traces, and vias) typically contributes about the same amount or more inductance than the capacitor's own parasitic inductance. If a second capacitor is connected into the vias of an existing capacitor, it only improves the PDS by a very small amount. It is better to reduce the total number of capacitors and maintain a one-to-one ratio of lands to vias.

Plane Inductance

The power and ground planes of a PCB have some amount of inductance associated with them. The geometry of these planes determines their inductance.

Since power and ground planes are by definition a planar structure, current does not just flow through them in one direction. It tends to spread out as it travels from one point to another, in accordance with a property similar to skin effect. For this reason, inductance of planes can be described as spreading inductance, and is specified in units of henries per square. The square is dimensionless, as it is the shape of a section of plane, not the size, that determines its inductance.

Spreading inductance acts like any other inductance to resist changes to the amount of current in a conductor. In this case, the conductor is the power plane or planes. This

Figure 4-6: Example Capacitor Land and Mounting Geometries

0402 Land Pattern, end vias, long traces, 4nH - BAD

0402 Land Pattern, end vias, 0.8nH

(A) (B) (C) (D)

0402 Land Pattern, double side vias, 0.4nH

0402 Land Pattern, side vias, 0.6nH

20 mil

30 mil

15 mil

25 mil

15 mil

30 mil

20 mil

15 mil

20 mil

30 mil

ug072_4_06_080104




quantity should be reduced as much as possible, since it retards the ability of capacitors to respond to transient currents in the device. Since the X-Y shape of the plane is typically something the designer has little control over, the only controllable factor is the spreading inductance value. This is primarily determined by the thickness of the dielectric separating a power plane from its associated ground plane.

In high-frequency power distribution systems of the type discussed here, power and ground planes work in pairs. Their inductances do not exist independently of each other. The spacing (and the dielectric constant of the material) between power and ground planes determines the spreading inductance of the pair. The closer the spacing (the thinner the dielectric), the lower the spreading inductance. Table 4-1 gives approximate values of spreading inductance for different thicknesses of FR4 dielectric (Reference #3).

Since closer spacing results in decreased spreading inductance, it is best, wherever possible, to place VCC planes directly adjacent to GND planes in the stackup. Facing VCC and GND planes are sometimes referred to as sandwiches. While the use of VCC GND sandwiches was not necessary in the past for previous technologies, the speeds involved and the sheer amount of power required for fast, dense devices demands it.

Besides offering a low-inductance current path, power-ground sandwiches also offer some high-frequency decoupling capacitance. As plane area increases and as the separation between power and ground planes decreases, the value of this capacitance increases. At the same time, since the parasitic inductance of this capacitance is decreasing, its effective frequency band center frequency increases. Capacitance per square inch is also given in Table 4-1.

This capacitance alone is usually not enough to give power-ground sandwiches a compelling advantage. However, when viewed as a bonus on top of low spreading inductance, it is an advantage most designers gladly take.

PCB Stackup and Layer Order

The placement of VCC and Ground planes in the PCB stackup (determined by layer order) has a significant impact on the parasitic inductances of power current paths. For this reason, PCB designers need to consider layer order in the early stages of the design cycle, putting high-priority supplies in the top half of the stackup and low-priority supplies in the bottom half of the stackup.

Power supplies with high transient current should have their associated VCC planes close to the top surface (FPGA side) of the PCB stackup to decrease the distance in the vertical direction that currents travel through VCC and GND vias before reaching the associated VCC and GND planes. As mentioned in the previous section, every VCC plane should have a GND plane adjacent to it in the stackup to reduce spreading inductance. Since high-frequency currents couple tightly due to skin effect, the GND plane adjacent to a given VCC

Table 4-1: Capacitance and Spreading Inductance Values for Various Thicknesses of FR4 Power-Ground Plane Sandwiches

Dielectric Thickness (mil, microns)

Inductance (pH/square)

Capacitance(pF/in2, pF/cm2)

4, 102 130 225, 35

2, 51 65 450, 70

1, 25 32 900, 140




plane tends to carry the majority of the current complementary to that in the VCC plane. For this reason, adjacent VCC and GND planes are considered as a pair.

Not all VCC and GND plane pairs can reside in the top half of the PCB stackup, because manufacturing constraints typically require the PCB stackup to be symmetrical about the center with respect to dielectric thicknesses and etched copper areas. The PCB designer must determine which VCC and GND plane pairs have high priority or carry high-frequency energy, and which pairs have low priority or carry lower frequency energy.

Capacitor Effective FrequencyEvery capacitor has a narrow frequency band where it is most effective as a decoupling capacitor. Outside this band, it does have some contribution to the PDS but in general it is much smaller. The frequency bands of some capacitors are wider than others. The ESR of the capacitor determines the quality factor (Q) of the capacitor, which determines the width of the effective frequency band. Tantalum capacitors generally have a very wide effective band, while X7R and X5R chip capacitors, with their lower ESR, generally have a very narrow effective band.

The effective frequency band corresponds to the capacitor's resonant frequency. While an ideal capacitor only has a capacitive characteristic, real non-ideal capacitors also have a parasitic inductance ESL and a parasitic resistance ESR. These parasitics act in series to form an RLC circuit (Figure 4-3). The resonant frequency associated with that RLC circuit is the resonant frequency of the capacitor.

To determine the resonant frequency of an RLC circuit, Equation 4-1 is used:

Equation 4-1

Alternatively, a frequency sweep SPICE simulation of the circuit could be performed, and the frequency where the minimum impedance value occurs would be the resonant frequency.

It is important to distinguish between the capacitor's self-resonant frequency and the effective resonant frequency of the mounted capacitor when it is part of the system. This is simply the difference between taking into account only the capacitor's parasitic inductance, and taking into account its parasitic inductance as well as that of the vias, planes, and connecting traces lying between it and the FPGA. The self-resonant frequency of the capacitor FRSELF (the value reported in a capacitor data sheet), is considerably higher than its effective mounted resonant frequency in the system, FRIS. Since the mounted capacitor's performance is what is important, it is the mounted resonant frequency that is used when evaluating a capacitor as part of a larger PDS.

The main contributors to mounted parasitic inductance are the capacitor's own parasitic inductance, the inductance of PCB lands and connecting traces, the inductance of vias, and power plane inductance. Vias traverse a full board stackup on their way to the device when capacitors are mounted on the underside of the board. These vias contribute something in the range of 300 pH to 1,500 pH on a board with a finished thickness of 60 mils; vias in thicker boards have higher inductance. Because there are two of these paths in series with each capacitor, twice this value should be added to the capacitor's parasitic inductance. This quantity, the parasitic inductance of the capacitor mounting, is designated LMOUNT. To determine the total parasitic inductance of the capacitor in-system, LIS, the capacitor's parasitic inductance LSELF is added to the parasitic inductance of the mounting, LMOUNT:

LIS = LSELF + LMOUNT

F 1

2 LC-------------------=




Example

X7R Ceramic Chip capacitor (AVX capacitor data used here)

C = 0.01 F

LSELF = 0.9 nH

FRSELF = 53 MHz

LMOUNT = 0.8 nH

To determine the effective in-system parasitic inductance (LIS), add the via parasitics:

LIS = LSELF + LMOUNT = 0.9 nH + 0.8 nH = 1.7 nH

LIS = 1.7 nH

Plugging in the values from the example:

FRIS: Mounted Capacitor Resonant Frequency: 38 MHz

Since a decoupling capacitor is only effective at a narrow band of frequencies around its resonant frequency, it is important that the resonant frequency be taken into account when choosing a collection of capacitors to build up a decoupling network.

Capacitor Anti-ResonanceOne common problem associated with capacitors in an FPGA PDS is anti-resonant spikes in the PDS aggregate impedance. These spikes can be caused by bad combinations of energy storage devices in the PDS (such as discrete capacitors, parasitic inductances, power and ground planes). If the inter-plane capacitance of the power and ground planes has an especially low Z with a high-quality factor, the crossover point between the high-frequency discrete capacitors and this plane capacitance might exhibit a high-impedance anti-resonance peak. If the FPGA has high transient current demand at this frequency (acting as a stimulus), a large noise voltage results. The PDS can be improved only by bringing down the impedance of the anti-resonant spike. To mitigate this problem, either the characteristics of the high-frequency discrete capacitors or the characteristics of the VCC and Ground planes must be changed.

Capacitor PlacementCapacitors need to be close to the device to perform the decoupling function. There are two basic reasons for this requirement.

First, increased spacing between the device and decoupling capacitor increases the distance travelled by the current in the power and ground planes, and hence, the inductance of the current path between the device and the capacitor. Since the inductance of this path (the loop followed by current as it goes from the VCC side of the capacitor to the VCC pin[s] of the FPGA, and from the GND pin[s] of the FPGA to the GND side of the capacitor[s]), is proportional to the loop area, decreasing its inductance is a matter of decreasing the loop area. Shortening the distance between the device and the decoupling capacitor(s) reduces the inductance resulting in a less impeded transient current flow.

FRIS1

2 LISC-------------------------=

FRIS1

2 1.7 12 10 H( ) 1 8 10 F( )------------------------------------------------------------------------------------ 3.8

7 10 Hz==




Because of the dimensions of PCBs, this reason tends to be less important with regard to placement than the second reason.

The second reason deals with the phase relationship between the FPGA noise source and the mounted capacitor. Their phase relationship determines the capacitors effectiveness. For a capacitor to be effective in providing transient current at a certain frequency (for instance, the optimum frequency for that capacitor), it must be within a fraction of the wavelength associated with that frequency. The placement of the capacitor determines the length of the transmission line interconnect (in this case, the power and ground plane pair) between the capacitor and FPGA. The propagation delay of this interconnect is the relevant factor.

Noise from the FPGA falls into certain frequency bands, and different sizes of decoupling capacitors take care of different frequency bands. For this reason, capacitor placement is determined based on the effective frequency of each capacitor.

When the FPGA initiates a change in its current demand, it causes a small local disturbance in the voltage of the PDS (a point in the power and ground planes). For a decoupling capacitor to counteract this, the capacitor has to first see a voltage difference. There is a finite time delay between the start of the disturbance at the FPGA power pins and the start of the capacitor's view of the disturbance. This time delay is equal to the distance from FPGA power pins to capacitor, divided by the propagation speed of current through FR4 dielectric (the substrate of the PCB where the power planes are embedded). There is another delay of the same duration for the compensation current from the capacitor to reach the FPGA.

Therefore, for any transient current demand in the FPGA, there is a round-trip delay to the capacitor before any relief is seen at the FPGA. For placement distances greater than one quarter of a wavelength of some frequency, the energy transferred to the FPGA is negligible.

For decreasing distances less than a quarter wavelength, the energy transferred to the FPGA increases to 100% at zero distance. Efficient energy transfer from the capacitor to the FPGA requires placement of the capacitor at a fraction of a quarter wavelength of the FPGA power pins. This fraction should be small because the capacitor is also effective at frequencies slightly above its resonant frequency, where the corresponding wavelength is shorter.

In practical applications, one tenth of a quarter wavelength is a good target. This leads to placing a capacitor within one fortieth of a wavelength of the power pins it is decoupling. The wavelength corresponds to FRIS, the capacitor's mounted resonant frequency.

Example

0.001 F X7R Ceramic Chip capacitor, 0402 package

LIS = 1.6 nH

Equation 4-2 calculates TRIS, the mounted period of resonance, from FRIS.

Equation 4-2

FRIS1

2 LC------------------- 1

2 1.6 9 10 0.001 6 10--------------------------------------------------------------------------- 125.8MHz===

TRIS1

FRIS------------- 1

125.86 10

---------------------------- 7.95 ns===




Equation 4-3 computes the wavelength based on TRIS and the propagation velocity in FR4 dielectric.

Equation 4-3

where

Equation 4-4

In this example, the effective frequency, equal to the resonant frequency, can be determined by Equation 1. This effective frequency is determined to be 125.8 MHz. The reciprocal of this is taken to give the resonant period, 7.95 ns using Equation 2. Using the propagation speed of current in FR4 (approximately 166 ps per inch), the wavelength associated with this capacitor is computed to be approximately 48 inches using Equation 3. As computed in Equation 4, one fortieth of this is 1.2 inches. Therefore the target placement radius (RPLACE) for capacitors of this size is within 1.2 inches (3.0 cm) of the power and ground pins they are decoupling.

All other capacitor sizes follow in the same manner. A radius of 1.2 inches is not terribly difficult to achieve in current PCB technology. It does not require placing capacitors directly underneath the device on the opposite side of the PCB. It is acceptable for capacitors to be mounted around the periphery of the device, provided the target radius is maintained. The 0.001 F capacitors are among the smallest in the decoupling network, so placement radii less than an inch are unnecessary. For larger capacitors, the target placement radius expands quickly as the resonant frequency goes down. A 4.7 F capacitor, for example, can be placed anywhere on the board, as its target radius of 98 inches is much bigger than most PCBs (corresponding to the resonant frequency of 1.56 MHz).

Example Capacitor Layout

Figure 4-7 is an example of the bottom-side PCB artwork showing the capacitor layout. Black fill and hatch represents plated copper, red represents vias, blue represents silkscreen labels, and purple represents package outlines. The FPGA footprint can be seen as the regular array of red via dots in the upper portion of the figure at the center. The absence of vias in a cross pattern at the center of the device indicates that solder lands on the top surface had their associated vias escape out toward the corners.

WavelengthTRIS

VPROP--------------------==

VPROP 16612 10 s

inch------------=

TRIS

VPROP-------------------- 7.95

9 10

16612

Date post:	17-Nov-2015
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