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Fractionally Injection-Locked Frequency Synthesizer Ultra-Low-Power Frequency Synthersizer Power consumption [mW] 16 12 8 4 0 Output frequency [GHz] 0 2 4 6 8 10 PE=2.3 PE=0.94 JSSC12 TCAS11 VLSI07 JSSC09 TCAS10 TCAS01 Target I-phase Q-phase Unwanted input point Phase correction point V inj 4×T in T in t Conventional Proposed 2000 2005 2010 2015 2020 2025 Supply voltage [V] 0 1.2 0.8 0.4 Year -70dB -65dB 34.6MHz Charge Pump Loop Filter Phase Frequency Detector Ref Divider Prescaler ILFD ÷4 ÷40 LC-VCO PN norm [dBc/Hz] PE [mW/GHz] PLL (LC QVCO) PLL (LC VCO) PLL (Ring VCO) This work -150 -160 -170 -180 -190 6.0 5.0 4.0 3.0 2.0 1.0 0 This work LC-VCO LF PFD,CP Divider 800μm 800μm V inj + - + - + - + - V inj V DD V bn V bp Delay cell Inverter -80 -120 -100 -140 Offset frequency [Hz] Phase noise [dBc/Hz] 10 3 10 4 10 5 10 6 10 7 -60 -40 -105 dBc/Hz W/o FBB W/ FBB Output frequency [GHz] 5.546 5.542 5.538 5.534 5.530 5.526 ILFD control voltage [mV] 300 320 340 360 380 400 W/ FBB (nMOS×2) (proposed) Injection signal amplitude [V] 0.1 0.2 0.3 0.4 0.2 0 0.4 0.6 0.8 1.0 Lock range [GHz] W/o FBB (nMOS×2) W/ FBB (nMOS×1) W/o FBB (nMOS×1) LC VCO core Bias control circuit V DD V DD V tune V ctrl V ctrl V out V outb Tech. [nm] [GHz] [V] PN [dBc /Hz] Power [mW] This work 65 5.54 0.5 -105 1.6 [1] 180 1.9 0.5 -120 4.5 [2] 180 2.56 0.5 -105 14.4 [3] 90 2.59 0.5/0.65 -113 6.0 [4] 130 9.12 0.5/0.8 -105 12 [5] 90 2.24 0.5 -87 2.1 [1] H. -H. Hsieh, et al., VLSI 2007 [4] C. -Y. Yang, et al., TCAS 2001 [2] C. -T. Lu, et al., TCAS 2010 [5] K. -H. Cheng, et al., TCAS 2011 [3] S. -A. Yu, et al., JSSC 2009 V DD f out CT<2:0> CT<2:0> CT<2:0> V bs2 CT<2:0> V b V bs1 V inj1 V inj2 + - - + + - - + + - - + + - - + V out180 V out0 V out45 V out225 V out135 V out315 3-bit coarse tuning Fine tuning V out270 V out90 V bs2 V b V bs1 V inj3 V inj4 V bs2 V b V bs1 V bs2 V b V bs1 PFD (DZ) CP Ref. 4 f ref ÷N ÷2 ∆T PG PS 4 f inj LF f 0 8-phase ring VCO Injection locking f PFD PLL/FLL V b C 1 C 2 R V inj Phase corrections by injection signals T pw T 0 V out V outb (a) T inj01 = 2.5 × T 0 V inj01 T inj01 T 0 V out V outb (b) T inj02 = 1.25 × T 0 V inj02 T inj02 Unwated pulses are injected T pw T 0 V out V outb V inj0 T inj0 ΔФ T 0 V out,I V outb,I V inj03 T inj03 V inj0,I V inj0,Q V out,Q V outb,Q VCO Div. LF LF Dum. 250 μm 330 μm CP, PFD PG, etc V out225 V out45 V out135 V out315 V out225 V out135 V out45 V out315 V inj V inj1 V inj2 V inj3 V inj4 V out315 V out225 V a1 V a1 V inj V inj1 V out0 V out180 NAND operation Phase selecting NOR operation VCO Jitter Conv. PLL ILPLL w/ DZ ILPLL CP noise reduction -80 -40 -60 -20 0 -100 -120 -140 -160 Phase noise [dBc/Hz] 10 3 10 4 10 5 10 6 10 7 4×10 7 Offset frequency [Hz] 1.8 2.05 1.55 Frequency [GHz] 0 -20 -40 -60 -80 -100 Measured spectrum [dBm] -35 dBc Ref. Pulse generator VCO f ref f inj M×f inj V b V inj1 V inj2 V inj3 V inj4 V inj V out0 V out180 V out0 V out180 V out90 V out270 V out90 V out270 Ref. VCO f inj M×f inj V b Ref. VCO f inj (M+1/4)×f inj V b ? Process 90 nm CMOS Supply voltage 1.0 V Input frequency (f ref ) 80 MHz Injection frequency (f inj ) 160 MHz Output frequency (f 0 ) 1.8 GHz 2.0 GHz f 0 /f inj 11.25 12.5 Phase noise@ 1 MHz -106 dBc/Hz -103 dBc/Hz Power consumption 22 mW (w/ I/O buffers) VCO: 50% Injection path: 36% PLL blocks: 14% {19 mW (sim.), w/o I/O buffers} Motivation:Low phase-noise without LC Proposed Frequency Synthesizer Fractional Subharmonic Locking Conventional Subharmonic Locking Proposed Pulse-Selection Technique Measurement Results Motivation:Low voltage operation Proposed Frequency Synthesizer Proposed ILFD Measurement Results Subharmonic locking Fractional subharmonic locking PLL with injection locking 8-phase ring VCO Pulse for injection locking Output signal spectram Phase noise ・Devided-by-4 ILFD ・Class-C VCO ・Forward body bias (FBB) Output signal spectram ITRS01~09 ITRS11 [1] [3] [4] [5] [2]
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