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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007-2008.

MSC8144 Primer

June, 2007

Boaz KfirDSP Application Engineer

TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007-2008. 2

Agenda

►Objectives of this presentation►MSC8144 Architecture (65 minutes)

• DSP core sub system architecture• Interconnect• Memory hierarchy• Peripherals and interfaces• System

►MSC8144—present some tools and support for easy start (25 minutes)►Questions (10 Minutes)


Objectives

►Exploring MSC8144 architecture and functional unit• Participants will be familiar with the powerful SoC• Participants will understand MSC8144 system and will be able to gain

higher performance within shorter time

►Exploring available knowledge resource and tools for MSC8144 users• Participants will know what information is available in order to get

maximal performance from MSC8144• Participants will gain basic knowledge about available tools for

enhanced utilization of MSC8144


Theme

MSC8144 is the strongest DSP in the market.Computation resource combined with peripherals.

Freescale prepared a set of resources which enables MSC8144 users to gain high

performance from the device.


MSC8144 Block Diagram

Other DeviceModulesCCSRs

CLASS

Boot ROM

Semaphores

VirtualInterrupts

JTAG

M2512KByte

(ECC protected)

UART

Clocks

Timers

Reset

MSC8144 Memory Die M3 Controller

MSC8144 Memory DieM3

10MByte(ECC Protected)

DDRController

MSC8144 Main Die

I2C

PCIController

CLASS - 64/128 bits Non-Blocking Switching Fabric

MSC8144 Memory Die

L2Instruction

Cache128Kbyte

SRIO

MUDMA

QUICC Engine

UTO

PIA

Ethe

rnet

Ethe

rnet

DSP coreSC3400

Sub-System

DMA


MSC8144 Main Features

► 4 DSP core sub systems running up to 1GHz, each one includes• SC3400 DSP Core—six execution units• 16KByte Instruction cache• 32KByte Data cache• Memory Management Unit (MMU)• Debug and Profiling Unit (DPU)

► Chip-Level Arbitration and Switching System (CLASS)—Fabric interconnect

► Memory• Shared L2 Icache 128KByte• M2 512KByte• M3 10Mbyte• DDR controller—up to 400MHz data rate, 16/32 bit data width

►DMA with 16 Bi-directional Channels


MSC8144 Main Features (cont.)

►QUICC Engine Subsystem• Dual-RISC engine• 2 Ethernet controllers each support 10/100/1000 Mbps• One ATM controller up to 50MHz• SPI

►Serial RapidIO interface supports 1x/4x at 1.25/2.5/3.125 Gbaud Yield 10Gbit data rate

► PCI interface - 33/66 MHz, 32bit, agent mode► TDM - up to 2048 channels

TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007-2008.

Technical Details


SC3400 Features

►Up to six instructions execute in a single clock cycle: 4 Data Arithmetic units and 2 Address arithmetic units

►2 Data bus – 64 bit each►128 bit – Program bus►16 data registers, 40 bits each►27 address registers, 32 bits each►Hardware support for fractional and integer data types►Dynamic interlocking for friendlier programming and more efficient

compiler support►User and supervisor privilege levels supporting a protected software

model►Branch target buffer (BTB) accelerates change-of-flow operations► Improve instruction set over the SC140


MSC8144 DSP Core Subsystem—Block Diagram

SC3400CORE

128 P-bus64 xa-bus64 xb-bus

L1 Ins.CacheMMU

PIC

DPU I/FI/F

L1 DataCache

Timer

Instruction128 bit bus

Data128 bit bus


DSP Subsystem—Instruction Cache

►16KByte L1 Instruction cache

►Cache partition to 8 ways—Flexible cache allocation

►Prefetch mechanism for high hit ratio

►Software coherency support


DSP Subsystem—Data Cache

►32KByte L1 data cache►Cache partition to 8 ways—flexible cache allocation►Prefetch mechanism for high hit ratio►Software coherency support►Write Back and Write Through are supported—reduce system load

and latencies


DSP Subsystem—Additional Features

►Memory management unit (MMU)• Critical for efficient multi-core application• Virtual-to-physical address translation• Task protection• Cache policy

►Embedded programmable interrupt controller (EPIC)• Up to 256 interrupts• 32 priorities

►Two general-purpose 32-bit timers►Debug and Profiling Unit—DPU

• On-chip emulator (OCE30) for core-related debug and profiling support• Breakpoints on PC, data address, and data bus values• More than 40 event counting options in 6 parallel counters used for

profiling• Real-time tracing of PC and profiling information


CLASS


Boot ROM

Semaphores

VirtualInterrupts

JTAG

M2512KByte

(ECC protected)

UART

Clocks

Timers

Reset




DDRController

MSC8144 Main Die

I2C

PCIController


MSC8144 Memory Die

L2Instruction

Cache128Kbyte

SRIO

MUDMA

QUICC Engine

UTO

PIA

Ethe

rnet

Ethe

rnet

DSP coreSC3400

Sub-System

DMA


Chip-Level Arbitration and Switching System - CLASS

►A full fabric that allows any master to access any slave

►Masters: 4 DSP cores, L2 Icache, DMA, QUICC Engine, PCI, Serial RapidIO, TDM

►Slaves: M2 memory, M3 memory, DDR, PCI, configuration registers

►Non-blocking—allows parallel accesses from multiple initiators to multiple targets

►Fully pipelined

►Per target arbitration highly optimized to the target characteristics using prioritized round-robin arbitration

►Profiling capabilities


CLASS Maximum Achievable Port Bandwidth

M2SRAM Memory

512KByte

DMA

Arrow direction indicates Initiator/target relations

StarCoreDSPSub-

systemStarCore

DSPSub-

systemStarCore

DSPSub-

system

MSC8144 Memory Die M3Memory

Controller

MSC8144 Memory DieM3Memory10MByte

MSC8144 Main Die


L2Instruction

Cache128 KByte

6.4GB/s6.4GB/s6.4GB/s

6.4G

B/s

25.6GB/s

Memory Die

12.8GB/s

6.4GB/s

6.4GB/s6.4GB/s

StarCoreDSPSub-

system

19.2

GB

/s

DDR SDRAMMemory

@200MHz

1.6GB/s


Direct Memory Access—DMA

►16 bidirectional channels, providing up to 16 memory-to-memory channels

►Buffer descriptors can reside in M2, M3, or DDR memory►Channel arbitration

• priority-based time-multiplexing between channels, using four internal priority groups with round-robin arbitration between channels on equal priority group.

• Early Deadline First (EDF) priority scheme that assures task completion on time (First In First serve)

►No completion interrupt, interrupt only if dead line reached before task was done


Direct Memory Access—DMA (cont.)

►A flexible buffer configuration, including• Simple buffers• Cyclic buffers• Single address buffers (I/O device)• Incremental address buffers• Chained buffers

►up to 4 Dimensions buffers for reordering data in memory►Optimized for DDR memory►One touch programming—activation by timer


MSC8144 Memory Hierarchy


MSC8144 Internal Memory Hierarchy

Level 1

Level 2

L1I: 16 KByte private Instruction CacheL1D: 32 KByte private Data Cache

L2I: 128 KByte shared Instruction CacheM2: 512 KByte shared Memory

M3: 10 MByte shared MemoryLevel 3

Three levels of memory hierarchy for optimized performance/costExternal (DDR 16/32 bit) memory for extreme cases


M2 Memory

►Storage area for critical data

• 512 KBytes SRAM• Running up to 400MHz• Low latency accesses• Four 128-bits wide ports,

for simultaneous access• Four address interleaved

banks• ECC protected

CLASS

Memory Bank 3

Memory Bank 2

Core 0 Core 1 Core 2 Core 3

Memory Bank 1

Memory Bank 0

DMA Others

128 bit 128 bit 128 bit 128 bit

Master D Master C Master B Master A


Class 3m 1s 128bit

Class 4m 3s 128bit interleaved mode

Cache Bank 1

Cache Bank 0

Control

Core 0 Core 1 Core 2 Core 3

Non

CacheableS/B

Memory

Core B Core ACore C

L2 Instruction Cache► Allows large code programs to efficiently

execute from M2, M3 and DDR • Shared multi-port 128 KByte instruction

cache• 2 banks• S/W coherency Support• Critical word first and pre-fetch until end-

of-line• ECC protected• Debug and profiling capabilities

Hit, miss statisticsCacheable, Non cacheable statisticsDirect access to cache array and tag array

• Up to three simultaneous accesses (one per bank and one non-cacheable)


M3 Memory

►Main storage area for code, channel data and I/O buffers

• 10 MBytes burstable memory • Allows application execution

w/o external memory • 128 bit wide data bus running at

400MHz • Hidden refresh with SRAM

behavior• Sustained throughput of

6.4GB/sec• ECC Protected

Main DieMSC8144

M310 MbyteMemory

DieMSC8144response, controls,

strobes

Data 128 bit

Address, controls, strobes

MSC8144


Instruction Miss in L1 ICache


CLASS

Boot ROM

Semaphores

VirtualInterrupts

JTAG

M2512KByte

(ECC protected)

UART

Clocks

Timers

Reset




DDRController

MSC8144 Main Die

I2C

PCIController


MSC8144 Memory Die

L2Instruction

Cache128Kbyte

SRIO

MUDMA

QUICC Engine

UTO

PIA

Ethe

rnet

Ethe

rnet

DSP coreSC3400

Sub-System

DMA


Instruction Miss in L1 Icache and L2 Icache


CLASS

Boot ROM

Semaphores

VirtualInterrupts

JTAG

M2512KByte

(ECC protected)

UART

Clocks

Timers

Reset




DDRController

MSC8144 Main Die

I2C

PCIController


MSC8144 Memory Die

L2Instruction

Cache128Kbyte

SRIO

MUDMA

QUICC Engine

UTO

PIA

Ethe

rnet

Ethe

rnet

DSP coreSC3400

Sub-System

DMA


Data Miss in L1 Data Cache


CLASS

Boot ROM

Semaphores

VirtualInterrupts

JTAG

M2512KByte

(ECC protected)

UART

Clocks

Timers

Reset




DDRController

MSC8144 Main Die

I2C

PCIController


MSC8144 Memory Die

L2Instruction

Cache128Kbyte

SRIO

MUDMA

QUICC Engine

UTO

PIA

Ethe

rnet

Ethe

rnet

DSP coreSC3400

Sub-System

DMA


MSC8144 Interfaces


QUICC Engine™

►QUICC Engine™ is used for IO management, it can offload some of the IO handling from the cores thus allowing improved DSP performance

►MSC8144 QUICC Engine is derived from MPC8360—implementing only part of the interfaces

• Dual RISC engine• Two GigE interfaces supporting MII, RMII, SMII, SGMII,

RGMII• UTOPIA port supporting AAL0, AAL2, AAL5• Micro-code based packet termination, and data queuing

per DSP core with multiple filtering fields• Embedded DMA engine

►Open QUICC Engine

SPI UCC1 UCC2 UCC3

POS xMII xMII

32 bitRISC0 SDMA

ROM0192kB

IRAM124kB

DRAM48kB

ROM1192kB

IRAM124kB

32 bitRISC1


SPI UCC1 UCC2 UCC3

POS xMII xMII

32 bitRISC0 SDMA

ROM0192kB

IRAM124kB

DRAM48kB

ROM1192kB

IRAM124kB

32 bitRISC1

►Two Ethernet controllers supporting 10/100/1000 Mbps

►Each Ethernet controller has 8 Rxqueues and 8 Tx queues allowingeasy multi-core usage

►Different physical interfaces10/100Mbps IEEE802.3 MII(only on one)10/100Mbps RMII 10/100Mbps SMII (only on one)10/100/1000Mbps RGMII1000Mbps SGMII

►MAC-to-MAC Connection in all modes►Full and half-duplex support

Ethernet Controller Features


Ethernet Controller Features (Cont.)

►Detection of all erroneous frames as defined by IEEE® Std. 802.3-2002™

►Multi-buffer data structure. Interruptper frame or based on threshold(size or time)

►Diagnostic modes: Internal andexternal loopback mode andecho mode

►Serial management interface MDC/MDIO►Queuing decision for IP/MAC/UDP filtering based on

MAC destination addresses, IP destination address, and UDP destination port

►Programmable maximum frame length

SPI UCC1 UCC2 UCC3

POS xMII xMII

32 bitRISC0 SDMA

ROM0192kB

IRAM124kB

DRAM48kB

ROM1192kB

IRAM124kB

32 bitRISC1


UTOPIA & ATM Features

►UTOPIA level II slave modes 8/16 bit at 25/50MHz

►ATM adaptation layers support AAL0, AAL2, AAL5 protocols implemented in hardware

►User-defined cells up to 65 bytes►Full duplex segmentation and reassembly

at 622 Mbps for AAL5►Full duplex segmentation and reassembly

at 155 Mbps for AAL2

SPI UCC1 UCC2 UCC3

POS xMII xMII

32 bitRISC0 SDMA

ROM0192kB

IRAM124kB

DRAM48kB

ROM1192kB

IRAM124kB

32 bitRISC1


UTOPIA & ATM Features (cont.)

►Separate TxBD and RxBD tables for each virtual channel (VC)

►Interrupt report per channel using four priority interrupt queues

►Compliant with ATMF UNI 4.0 and ITU specification

►Support for user-defined cells►ATM pace control (APC) unit

SPI UCC1 UCC2 UCC3

POS xMII xMII

32 bitRISC0 SDMA

ROM0192kB

IRAM124kB

DRAM48kB

ROM1192kB

IRAM124kB

32 bitRISC1


► MSC8144 SRIO is derived from MPC8548/E• Serial RapidIO port support up to 3.125Gbaud 4X lane port—yielding up to

10Gbit data rate• Comply with the following parts of Specification 1.2 of the RapidIO Specification

Part I (Input/Output Logical Specifications)Part II (Message Passing Logical Specification)Part III (Common Transport Specification)Part VI (Physical Layer 1x LP-Serial Specification)Part VIII (Error Management Extension Specification)

• SERDES interface Using four wires for each lane(two for receive and two for transmit)

• Messaging unittwo outbound message queuestwo inbound message queuesone outbound doorbell queueone inbound doorbell queuesone inbound port-write queue

• QUICC Engine™ microcode to distribute input to 4 cores

MSC8144—Serial RapidIO™


Transactions Supported By MSC8144 Serial RapidIO™ Interface

► I/O Inbound—memory mapped access• NREAD • NWRITE, NWRITE_R, SWRITE

► I/O outbound- SRIO DMA based memory mapped access.• NREAD • NWRITE, NWRITE_R, SWRITE

►Message functions – Inbound and Outbound • DOORBELL (generate an interrupt)• MESSAGE (write to port)

►System support functions• MAINTENANCE (read or write configuration, control, and status

registers)


PCI

►Used by single chip application to “master” the board, used by some application as a simple “host” interface

►PCI specification revision 2.2 compliant

►Agent only ()►Master and Slave Functionality►Supports 33MHz and 66MHz►32-bits PCI interface►PCI 3.3-V compatible►Supports accesses to all PCI

address spaces


CLASS

Boot ROM

Semaphores

VirtualInterrupts

JTAG

M2SRAM Memory

512KByte(ECC protected)

UART

IO InterruptConcentrator

Clocks

Timers

Reset

2048 ch.

1X1.25Gbps

sRIOMU

Ocean

Pacsun Memory Die M3 Memory

Controller

Pacsun Memory DieM3Memory10MByte

(ECC Protected)

DDRMemory

Controller

32/16bit port

Pacsun Main Die

I2C

PCIController

32 bit 66 MHz16-bit

port

101001000Mbps

QUICC Engine

101001000Mbps

UTO

PIA

Ethe

rnet

Ethe

rnet


Pacsun Memory Die

TDM

L2Instruction

Cache128Kbyte

TitaniumSub-

System

TitaniumSub-

System

TitaniumSub-

System

TitaniumSub-

System

DMA


TDM

►Eight independent TDM modules, each supporting• Up to 256 channels• Glue-less interface to E1/T1 framers• Hardware a-law/u-law conversion• Up to 62.5 MHz clock• Up to 16 MBytes buffer per channel• All channels share the same word size 1, 2, 4, 8, or 16-bit• Two programmable receive and two transmit threshold

levels with interrupts generation• Configurable TDM Transmitter Sync Signal (TxTSYN) as

either input or output►In Total the TDM supports 2048 channels►TDM modules can share signals►TDM modules can be synchronized


MSC8144 Additional Low Bandwidth Interfaces

► SPI• 4 signal interface• Master or slave

► UART• Up to 6.25Mbps• Full duplex

► I2C►JTAG—testing and debugging►GPIO—32 GPIO ports


MSC8144 General Blocks

►Timers• Two timers in each DSP core sub system• 16 general purpose timers• 5 software watchdog timers

►Virtual interrupts• Generated by simple write access• Can be used for core to core communication or host to core

► Hardware semaphores—for shared resource management


System On Chip


Pin Multiplexing

SerialRapidIO™ 4X and SGMII share pinsPin multiplexing tool


MSC8144 Clock Scheme Highlights

►Configurable 15 clock branches allow different clocks to different functional units

• Stop clock of unused units• Different frequencies to each unit

►3 PLLs (and SERDES PLL) each with 5 output dividers

►The configuration parameters are set by MODCK[5:0] 64 modes

►Relock capability allows to change configuration parameters after reset

DIV

DIV

DIV

DIV

DIV

PLL0 - SystemMFPD

DIV

DIV

DIV

DIV

DIV

PLL1 - CoreMFPD

DIV

DIV

DIV

DIV

DIV

PLL2 - GlobalMFPD

0

2

1

3

4

5

6

7

89

1011

1213

14

SERDES PLL ser_clk

main CLKIN

PCI CLKIN

SERDES CLKIN

PLL1 CAS

PLL2 CAS


MSC8144 Clock Domains and Typical Frequencies

►Each clock domain is set to the lowest possible frequency that will allow it to give the required performance

►Clock configuration tool

QE

DSP0 Sub-SystemDSP1 Sub-SystemDSP2 Sub-SystemDSP3 Sub-System

PCI Controller

DDR Controller

M3 & M3 Controller

Typical frequency (MHz):

800 or 1000 MHz

400MHz (class 128)

400MHz

200 MHz

400 MHz

400 MHz

CLASS - 64/128200MHz (class 64)


MSC8144 Reset Configuration Word

►MSC8144 uses 64 bit RCW for initial device configuration

► Reset Configuration Word Source• Load 64bit RCW from I2C EEPROM• Load partial RCW (17 bit) from configuration pin and Default value

for the remaining bits• Use one of four hard coded default RCW


MSC8144 Boot Procedure

►MSC8144 can boot over the following interfaces:• I2C• Ethernet• Serial RapidIOTM

• PCI►The MSC8144 boot code consists of the following stages

1) Private configuration: Each core configures itself and its environment (sp, vba etc.)

2) Shared configuration. Core #0 configures the MSC8144 system (CLASS, peripherals etc.)

3) User code load. Core #0 loads the user code to the MSC81444) End of boot5) Core #0 clears system configurations made during and for the boot6) All cores jump to address programmed by the user during the boot

process►The MSC8144 boot code is based on the SmartDSP OS


MSC8144 Interrupts Scheme—System

►Each DSP core sub system contains programmable interrupt controller (EPIC) supporting up to 256 interrupts

• 34 Sub system internal interrupts• 172 Device interrupts • 16 IRQ_B inputs to MSC8144 • One NMI_B input to MSC8144• 16 virtual interrupts • 4 virtual NMIs

►All interrupts are connected to all cores• Allowing flexible resource allocation• Allow symmetrical or non symmetrical application architecture

►External interrupt pin and External non mask-able interrupt based on virtual interrupt

► In most cases the interrupt source represent single event• Shorten the interrupt latency


MSC8144 Debug and Profiling—Overview

►MSC8144 SOC support real time and non intrusive debug and profiling features

• Debug features are used to monitor, trace, develop and debug applications

• Profiling features are used to characterize, understand system and increase system performance

► Interfaces• JTAG—chained multi-core debug, embedded in the tools• PCI, Serial RapidIO™—Direct “low”-intrusive access to all the internal

memory space• UART & ETH—general purposes including debug and remote debug

using SW drivers


MSC8144 Debug and Profiling Features Diagram


CLASS

Boot ROM

Semaphores

VirtualInterrupts

JTAG

M2SRAM Memory

512KByte(ECC protected)

UART

IO InterruptConcentrator

Clocks

Timers

Reset

2048 ch.1X

1.25Gbps

sRIOMU

MSC8144 Memory Die M3 Memory

Controller


Memory10MByte

(ECC Protected)

DDRMemory

Controller

32/16bit port

MSC8144 Main Die

I2C

PCIController

32 bit 66 MHz16-bit

port

101001000

Mbps

QUICC Engine

101001000

Mbps

UTO

PIA

Ethe

rnet

Ethe

rnet


MSC8144 Memory Die

TDM

L2Instruction

Cache128Kbyte

TitaniumSub-

SystemTitanium

Sub-SystemTitanium

Sub-System

TitaniumSub-

System

DMA

WDT

Support Debug Features

Support Profiling Features


DSP Core Subsystem Debug and Profiling Features

►MSC8144 SOC contains four DSP Core Subsystems. Each includes debug and profiling capabilities (OCE, DPU, Trace buffer)

► In Debug mode, an external debugging agent can access all internal registers and memory locations in order to develop and debug theapplication that is intended to run on the architecture

►The I-Cache and D-Cache blocks have block-specific debug modes. In debug mode, the internal state of the caches (tags, valid bits, PLRU table and cache array) can be read with JTAG-inserted core commands

►Each DSP Core Subsystem support• Managing the Virtual Trace Buffer (VTB)• Parallel counting of different events characterizing the operation of the

DSP core sub system


DPU—Application Partitioning For Profiling


Debug and Profiling Unit—Application Partition Example


Debug and Profiling Unit—Cache Performance Example


General Debugging and Profiling Resource

►L2 Icache—Hit ratio and statistics

►DMA—Debug mode and statistics

►QUICC EngineTM—performance monitoring, trace, loopback

►Serial RapidIOTM—performance monitoring, error identification, loopback

►TDM—Error identification, loopback

►PCI—Error identification


CLASS and DMA Profiling Example—Results

************** CLASS PROFILING RESULTS **************Profiling ran for 3834 cycles (on the relevant CLASS)Profiling ran on Class Initiator. Profiling type - INITATOR_BWThe Initiator received read datum on 0 cycles (%0.000000 of total cycles)The Initiator sent write datum on 640 cycles (%16.692749 of total cycles)*********** END OF CLASS PROFILING RESULTS ***********

************** DMA PROFILING RESULTS **************Ran profiling on DMA channel 0Profiling ran for 1730 cyclesChannel requested access to the bus 161 times (including BD fetching)Channel won arbitration on the bus 161 times (including BD fetching)Channel was active for 970 cycles (%56.069363 of cycles - including BD fetching)Channel reported 'End of Buffer' 2 times (including BD fetching)Channel was in the status of consecutive grant (BTSZ < TSZ) 708 cycles (%40.924854 of

cycles)********** END DMA PROFILING RESULTS **************

TEST PASSED!!!


Software Data Flow Models


VoIP—Data Flow Example—Cache SW Architecture

SamplesM3

Channels StateDSPCore

SamplesTDM ETH

Packet, BD’sM3

Packet, BD w

Channel State

ENCODING PROCESSENCODING PROCESS

TDM M3Samples

DSPCore

Channel State

SamplesM3 ETH

Packet, BD rJitter Buffer Packet, BD’s

Channel State

DECODING PROCESSDECODING PROCESS


VoIP—Data Flow Example—DMA SW Architecture

SamplesM3

DMA

M2

Swap In Channels State

DSPCore

Channel State

Samples

DMASwap OutChannels State

TDM ETHPacket, BD’s

M3Packet, BD w

M2Channel State

ENCODING PROCESSENCODING PROCESS

TDM M3Samples

DMA

M2

Swap Out Channels State

DSPCore

Channel State

Samples

M2

DMA

M3

Swap InChannels State

ETHPacket, BD rJitter Buffer Packet, BD’s

Channel State

DECODING PROCESSDECODING PROCESS


Operation Models

►Cache Model: DCache—access data in shred M3 memory• “Infinite” Memory space for Data and Instruction• No need for DMA, less configuration, less shared resources

management• Less traffic in the system (no swapping)• Lower system performance vs. DMA model

►DMA Model: DCache access data in M2. Data is swapped by DMA from M3 / DDR

• Higher system performance vs. Cache model• More deterministic behavior (still not fully deterministic)• Requires DMA “go” command• In some cases more traffic in the system (swapping)


Jumping Into the Water


►MSC8144 is the third generation of Freescale multi-core DSP

►Here at Freescale we have already gain huge experience with multicore DSP by working with our customers and by developing in- house operating system, VoIP frame work, video application, WiMAX application, reference design boards and more

►When selecting MSC8144 in addition to power full SoC you get supporting tools, reference designs, operating system and access to plenty of relevant information based on experience


CodeWarrior® Integrated Development Environment

►Used for developing and running on MSC8144 ADS►Used for developing and debugging on customer board►User friendly interface to MSC8144

• Cache window to view cache content and status (L1I, L1D, L2I)• GUI interface to use Debug and Profiling Unit• Register view

►Simulators of SC3400 and MSC8144• Allow user to analyze performance

►Profiling – interactive text representation of code behavior►Stationary project with default settings and ‘one click’ to move from

debugging settings to high performance settings• “debugging target” —for code debugging• “optimized target” —for high performance


SmartDSP Operating System—SDOS

►Freescale DSP operating system—FREE to used on MSC8144 application

►Includes low level drivers for peripherals and interfaces. User does not have to study programming model

►Support for multi-core application

►Very easy migration from Freescale DSP to new generation of Freescale DSP

►Small footprint


SmartDSP Operating System—Kernel Awareness

Event statistics

Event Names

Loa

Load (Core Utilization) Graph


Application Development System—ADS

►MSC8144 ADS—allow users to develop and test code with 8144

►Allow different settings for MSC8144 interfaces

►Includes MSC8560 as host

►Stand alone mode

►AMC card mode to interface another MSC8144 ADS


Documentation and Information Source

►MSC8144 Reference Manuals is available online

►MSC8144 Application notes• Interface and peripherals related application notes explaining

performance and how to achieve high performance• C – Coding guide lines for coding that will allow the compiler generating

efficient code• System profiling and optimizations – step by step instructions describing

how to measure performance and how to increase performance• Implementations examples and guidelines for specific functionality

►Customer training by Freescale experts at customer site(according to opportunity size)


MSC8144 Registers Illuminator►Tool that check

all MSC8144 registers setting and verify them with a set of known rules

►Any setting that does not meet the rules will be reported to user


Migrating from Single Core to Multi-core (1 of 2)

►Most commonly used approach for using the multi-core is as “multiple—single core”

• Each core runs independently• Shared resource are partitioned between cores• Shared resource which can not be partitioned are used with

arbitration► MSC8144 was designed to support this approach

• Most shared resource can be partitioned easily between cores• Simple mechanism for arbitration between cores (semaphores)• Interrupt scheme• Shared L2 Icache for symmetric processing (SMP)

►SDOS functions and drivers that support this model


Migrating from Single Core to Multi-core (2 of 2)

►Second approach for multi-core application is asymmetric processing

• Cores may be dependent on each other (data is send from one core to another)

• Imbalance use of peripherals / resources►MSC8144 was designed to support this approach as well

• Peripherals and resource are not tied to specific cores• Interrupt scheme allow any source to trigger any core• Virtual interrupt for core to core communication

►Multicore demo at FTF—presents implementation of this approach—based on SDOS


Theme

MSC8144 is the strongest DSP in the market.

Freescale prepared a set of resources which enable MSC8144 users gain high

performance from the device.

TM

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Freescale PowerPoint Template - NXP Semiconductors · Freescale™ and the Freescale logo are...

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