Freescale PowerPoint Template - NXP Semiconductors · TM Freescale, the Freescale logo, AltiVec,...

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

FTF-AUT-F0561

Continental Virtual Platform for a Chassis and Safety Application

June 23, 2010

Dr. D. Baumeister – ContinentalManfred Thanner - Freescale

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 22

Abstract

►This joint Continental and Freescale presentation will give an overview about the development and deployment on a virtual platform used in electronic stability control application for pre-silicon software development, design exploration and performance analysis. The presentation will give an overview on the used simulation technologies, example model implementations and coupling technologies. The deployed software use cases will be shown and how it accelerated the development process due to pre-silicon availability.


Agenda

►Overview

►Model Approach

►Electronic Control Unit Simulation Setup

►Use Cases

►Error Injection

►Summary


Overview


Background on Continental and Freescale Virtual Platforms

5

Continental & Freescale are working in a long-term development partnership over 5 uController Generations

►Enabled continuous development of virtual platforms

• Two generations of virtual platforms frameworks delivered since 2001

• Covering several devices with virtual platforms

►Enabled infrastructure and workflows for seamless model exchange

►Extending use cases • Validation• Software driver development and test• Full applications


Improving the Schedule

►Goal: All hardware related software implemented and tested when first silicon arrives

►Prerequisite: Virtual Model Availability pre-silicon • Started when specification is mostly finished• Runs in parallel with hardware design• Simulator must be made available at least 6 months ahead of silicon

►Low level driver development started with early simulator releases ►Decouples SW development from the HW design schedule

Spec Design Spec

DesignVirtual Model

Software Integration

HW Design Virtual model Releases

HW Related SW DevelopmentHW / SW Integration, Bring up

First Silicon

Parallel HW/SW Development


Virtualization Merits

► Early System Trade-Off Analysis• Manage the complexity• Analysis beyond CPU MIPs and memory footprint

► System evaluation of new IP ahead of first Silicon.

► Prepare system/user oriented test cases► Early software development start► MCU / system operation insight

(perhaps not available in hardware)• Potential for fault injection scenario analysis• Potential for FMEA case scenario analysis

► Etc….Increase new product introduction efficiency by using tools in the concept/definition phase then leveraging the tools to launch verification/validation ahead of silicon availability.


Virtualization History►Virtualization has been used by many years in the industries

• Initial company proprietary solutions • Future is in standardized, inter operable models in an ecosystem

TLM, model to tool APIs, model to model standard definitions►Automotive modeling standards and best practices evolving

1980s 1990s 2000s 2010s

• Company internal solutions

• Semi’s, Tier1, OEMs

• Proprietary by nature

• Target to few use cases

• Commercial Solutions become available

• Often based on outplaced company solutions

• First standardization efforts visible

• Standards evolve

• Model reuse • Wider number of

use cases addressed

• Commercial ecosystems become available

• Wider use cases addressed

• Standardization on

• TLM• Model to tool• Model exchange

• Model guide lines

• Standards & automations


Model Completeness Overview

Model Type Scope Use Case

Core modelISS only

Core only, Instruction set covered (no exceptions), e.g., Lauterbach build in ISS

Running cross compiled code without interaction to peripherals

Core ISSWith exceptions

Core model takes any exception into account; used often in high end speed models without timing

Code running with exceptions, e.g., software interrupts

Core model cycle count accurate

Used for profiling requires accurate memory models

Used for profiling, cycle count accuracy; periphery stub as memory

Platform model Core, memory, IRQ, xbarCan be used for memory profiling

For OS porting/development, minimal peripheral features covered (max IRQ, timer)

Full chip model Used all models Covering all peripherals, EVB equivalent

Full chip model with plant model

Application development Additional models are connected or co-simulated

Target for Continental and Freescale Virtual Platform Development


Model Approach


Power Architecture® Core & Peripheral Models

Core Models ►Available today

• e200z4, e200z6, e200z3, e200z0, e200z7

ADL/uADL Core models• Based on FSL open source architectural

description languagehttp://opensource.freescale.com/fsl-oss-projects

• Integrated today into CoWare’s SystemC simulation platform

• ADL Focus Functional ISS models validated vs. FSL testbench

• uADL focus on micro architecture implementation

pipeline, architecture, TimingFocus on cycle counts accuracyValidation against RTL

• Integration in any simulator framework possible

Peripheral Models ►Available today

• Large set of automotive peripherals • FlexCAN, FlexRay, Timer, eSCI, SPI

Interrupt controller, xbar, SIU

Peripheral models• Model kernel is C/C++• Base Class used for mapping to

SystemC simulation platformTarget to migrate to TLM2.0

• Vendor agnostic• Transaction based

Event drivenbus access, CAN and FlexRay communication transaction based

• Mapped to SCML for CoWare VPA visibility & functionality support

• Cycle count accurateTimer, memories, xbarscycle time validation vs. silicon on-going


►e200 Core models are available or in progress• FSL models can be integrated in commercial tools

e.g., CoWare, OSCI• Tool vendor core models available

e.g., VaST• Source level integrations possible

Freescale open source ADL model frameworkhttp://opensource.freescale.com/fsl-oss-projects/

►Active used frameworks• CoWare • VaST• OSCI – SystemC kernel

6464MHzMHz

z0z0

z7z7

300300MHzMHz

8080MHzMHz 120120MHzMHz

z6z6

200200MHzMHz

z1z1 z3z3

same instruction set / memory map / interrupt map / software

z4z4

150150MHzMHz

Single Issue

DualIssue

Power Architecture®: e200 Automotive Platform

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLinkand VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 131313

20xx 20xx

General High Level Timeline for Virtual Platform Creation

J F M A M J J A S O N D

Phase 0• Prototype Platform

Phase 1• Initial Platform

J F M A M J J A S O N D J F M A M J J A S O N D

Phase 2• Extended Platform

Phase 3• Full Platform

First Silicon

Phase 4• Full Platform Error Injection

20xx

Maintenance and Support Phase (silicon validation)

Core Model

Peripheral Models

Top Level Integration

Interface development

Incremental Core Model drops

Incremental Peripheral Model drops

• Time line to be adapted on detailed requirements

• Timeline based on previous simulator developments

• Releases 6-9 months ahead of silicon

Incremental levels of SoC integration

Maintenance Release

Mile

ston

esK

ey D

evel

opm

ent E

ffort

s

Tool Integration Phases


Continental Multi Core Setup in Platform Architect

Core 2

Core 1

xBAR

FMPLL

Bridge

Flash

RAM ► Sample graphical representation of virtual model

► Block based► Scriptable► Full view of model

implementations► Basis for Virtual

Platform export and generation

► Parameterization accessibility


Overview Simulator Structure

►All runs on WXP• similar look and feel than EVBs

• ECU level models included for ABS/ESP

►Debugger integrations• e.g., Lauterbach

►Log files and Traces• deeper insight than HW

►Configurability• selectable cores• accuracies

Sim.log

sim.vcd

Lauterbach ►source debugging►run time control►break points

HW View►simulator control►HW view►watch points►Config►TCL Scripting

Log►errors,►trace log

Signal Tracing►Virtual scope logic analyzer►selectable on module basis

config.xml

config.xml►Configuration►Core selection►logging on/off►VCD tracing►model parameters


Infrastructure and Features Overview

► Full Device model developed • PowerPC Multi Core simulation (e200z650 and e200z0)• Switchable Cores between functional and cycle count

accurate• Xbars, Memories (Flash, RAM), Interrupt controllers• Automotive peripherals (CAN, FlexRay™, LIN)• Timers, PLL, etc.

► Debug interface for source level debugging• Lauterbach debugger integration• Multicore debug capable

► Tracing capabilities• Signal traces with VCD files (Virtual Logic Analyzer)

► Error Injection capability• Scripts for error injection

► Connectivity• reconnect to provide loops

pin to pin, CAN to CAN, FlexRay stimulus node, SPI to SPI ► Scriptability

• Fully scriptable to run and exit simulation• Log files for regression result tracking

►Virtual Platform Analyzer►OS Aware►Hardware and Software

parallel view

►Source Level ►Lauterbach Debugger ►Multicore Debugging

Debugger connection

►Currently used for pre-silicon SW development • Virtual Platform shipped months ahead of Silicon• Driver development• Basis for SW development

Chassis & SafetyEBS DevelopmentElectronics

Electronic Control Unit Simulation Setup

17 / Dr. D. Baumeister / IC Development CETE-IA / Date © Continental AG

18 © Continental AG

ContiTech

Air Spring SystemsBenecke-Kaliko GroupConveyor Belt GroupElastomer CoatingsFluid TechnologyPower Trans-mission GroupVibration ControlOther Operations

Passenger and Light Truck Tires

OriginalEquipmentReplacementBusinessEMEA ReplacementBusinessThe AmericasReplacementBusinessAsia PacificTwo-Wheel Tires

Commercial Vehicle Tires

Truck Tires EuropeTruck TiresThe AmericasTruck Tires Asia Pacific

Industrial Tires

Chassis & Safety

ElectronicBrake SystemsHydraulicBrake SystemsSensoricsPassive Safety& ADASChassis Components

Powertrain

Engine SystemsTransmissionsHybrid & Electric VehicleSensors & ActuatorsFuel Supply

Interior

Instrumentation & Driver HMIInfotainment & ConnectivityBody & SecurityCommercial Vehicles & Aftermarket

Continental Corporation: Strong Divisions and Business Units

Continental Corporation

Automotive Group Rubber Group

19 © Continental AG

Chassis & Safety Division – Business Units

Electronic brake systems, e.g. ABS and ESCElectric-hydraulic combi brake (EHC)Control units for motorcycle brakesABS for motorcyclesRegenerative brake systemsSoftware for extended brake control functions and assistance systemsHydraulic valves

Brake disksDrum brakesBrake calipersParking brakesElectric parking brakesBrake boostersTandem master cylindersMechanical, electronic and hydraulic brake assist devicesBrake actuation modulesBrake pressure regulatorsBrake hosesDuo-servo parking brake systems

Inertial sensors for stability and ESC applicationsSensors for active chassis controlSteering angle and torque sensorsSpeed sensors for wheels, engines and transmissionSensors and switches for seat belt locks and seat position

Passive safetyDriver assistance systemsOccupant classificationProduct integration and validation

Steering systemsAir suspension systemsChassis electronicsElectronic componentsWindshield and headlamp cleaning systems

ElectronicBrake Systems

HydraulicBrake Systems Sensorics Passive Safety

& ADASChassis

Components


Contintental’s Motivation for C-based IC Modeling: BenefitsReduction of developing time / time-to-market

- Evaluation of hardware components to be developed in complex hardware/software environment- Parallelizing development of hardware and software

Cost Reduction- Simple PC setup instead of physical test equipment

(setups of various devices can be easily distributed, installed and maintained)- Reduction of Silicon Redesign (e.g. ROM masks)

Quality improvement by verification enhancement- Verification of software components- Verification of complex analog/mixed signal systems- Verification of complex hardware/software systems

Enhanced System Visibility and Fault Coverage- Error Injection: Setup of fault conditions which are difficult to provoke in silicon device- Higher System Visibility: ECU-level actuators being modeled; Input of sensor data streams supported

1st Silicon MCUCycle-approximateMCU Model

3 months3 months

Cycle-accurateMCU Model



Simulation Target System:EBS ECU with Focus on Integrated Circuits

Target System:

Electro-hydraulic Control Unit for Electronic Stability Control (ESC)

Car Sensors required to execute software on virtual platform

Components:

Safety Integrity Level 3 (SIL3) certified Chip-Set:

Full-Custom leading edge automotive safety MCU

Full-Custom leading edge mixed-signal IC

Actuators: Valves, Motor

Sensors: Acceleration-, Pressure-, Wheel-speed-Sensors



IC-Level Simulation EnvironmentMicrocontroller Models

Instruction- and cycle-accurate at MCU pin-border:100% S/W-compatible to silicon targetFast simulation execution compared to RTL-simulation (slow compared to IS emulator)Monolithic IP blocks delivered by FreescaleMCU-Family Simulator covering portfolio of target configurations

Mixed-Signal IC ModelsComplete modeling by Continental(no IC supplier contribution)Model implementation depending on use case:

Fast simulation execution (behavioral models)

⇒ Allows fast ECU-level simulations (not feasible on RTL level) Accurate (linear/non-linear analog solvers based on SystemC-AMS)

⇒ thourough investigations of complex mixed-signal system functionalities


CPU

FlashPGM

RAM

COM

CPU

ECC

RAM

Red

unda

ncy

Ch e

c ke r

SensorSignalCond.

ADC

Bus I/F

Watchdog

ValveDrivers

uCPowerSupply

PWMValve

ControlCOM Failsafe


Continental EBS ECU-Level Simulation Environment

Heterogeneous Simulation Environment representing target ECUVarious domains

Digital circuit modeling

Analog circuit modeling- Behavioral models (SDF: signal data flow)

- Conservative models (linear/non-linear solvers)Various implementation languages

C++ (with proprietary C++ class library extension)SystemC (v2.2 with TLM2.0 1) library extension)

SystemC-AMS 2) (v0.15)Proprietary IP and IP blocks by IC vendor

1) TLM: Transaction Level Modeling2) AMS: Analog Mixed-signal

Digital

Mixed Signal



24

IC Simulation: Technology Leapfrom Proprietary to Standard Simulation Platform

Technology Status:

Full XML based tool flow within Cadence IDE, including automated net list generation

>> required for efficient modeling of complex systems with distributed development teams worldwide

Leading simulator coupling technology

>> allowing coupling of different SystemC Kernels

>> supporting coupling of different model IP blocks


Proprietary Simulation PlatformDevelopment

of newSimulation Technology

SystemC/SystemC-AMS Platform

2007-2009 2010--20061998-

uCGeneration 2

uCGeneration 3

uCGeneration 4

uCGeneration 5


Simulator of First Triple-Core Automotive MCU

Model Features

Cores: Redundant main core, I/O processor

Full memory system: Flash, SRAM, Cache

Failsafe system emulation (100% S/W compliant to silicon)

Peripheral set: Timer, QSPI, FlexCAN, FlexRay, SIU, eSCI

Implementation Language: SystemC

SystemC Simulation kernel: CoWare Virtual Platform

OSCI 1)

SystemC(-AMS)Kernel(Slave)

(S)PACESystemC C

dllTCP/IP C

CoWareSystemCKernel

(Master)

LauterbachDebugger

Digital/AnalogComp.

SystemC/SystemC-AMS

By Freescale

MCU PCU/ECU

1) OSCI: Open SystemC InitiativeBy Continental


Configurable Umbrella Simulator

Model Accuracy

Target Config. 1

Target Config. 2

Target Config. 3

Cycle Approximate

MCU-1(ADL)

MCU-2(ADL)

MCU-3(ADL)

Cycle Accurate

MCU-1(uADL)

MCU-2(uADL)

MCU-3(uADL)

MCU Family Approach

Selection of MCU target configuration and accuracy level done by configuration file at

simulation start-up


Analog/Mixed-signal Modeling: Technical Goals ContinentalConservative modeling of analog components with SystemC-AMS

Behavioral modeling of analog components (with SystemC-AMS)

Goals:

Enhancement of analog model fidelity

Performance Enhancement:

Speed-up the system simulation platform for analog and digital ICs by at least one order of magnitude by using behavioral analog modeling (SystemC-AMS)

Cancellation of proprietary technology solutions

Move away from proprietary modeling techniques (AVSL) to industry-standard techniques (SystemC-AMS) in order to benefit from tool availability and model reuse

double t=sc_time_stamp().to_secoif (en.event()) {t0=t;

}double rel_t=t-t0;if (en) {o=factor1 * (a-e1)*exp(-rel_t/t);

}else {o=factor1 * (a-e2)*(1-exp(-rel_t/t));

}



XML-based Design Flow

OSCISystemC/SystemC-AMS Kernel

(Slave)

WrapperSystemC/AVSL

SystemC

Non-OSCISystemC

Kernel(Master)

C++/AVSLSystemCC

dll SystemC-AMSC

CadenceICMS

ICMSNetlisterPlugin

Librariesincl.

SystemC-AMS

SimulationData

Scope

SystemC-AMSSystemCAVSL

AVSL: Continental Proprietary Modeling Standard


Cadence ICMS-based tool flow featuring:

Script automation

Dedicated user interface for non-modeling experts

Flow enabling:

Robust, distributed model development at different sites world wide

Reduced model development time

Modeling of large and complex systems

Heterogeneous Simulation Target


28

Use Cases


Software-related use cases

(Pre-silicon) Software Development of hardware-dependant software parts

⇒ low-level drivers, AUTOSAR drivers, hardware-dependant S/W-functions

(Post-silicon) Software Verification

- MCU connections on ECU Level (MCU I/O Test)

- Failsafe concepts Microcontroller / Mixed-signal ASIC

- Hardware/Software Interface (mutual failsafe requirements, Flash/ROM compatibility)

Cross-correlation to silicon; silicon performance evaluation

Hardware-related use cases

ASIC circuit development/design exploration

Functional Partitioning Microcontroller/Mixed-Signal IC

Functional Partitioning Hardware/Software

Top-level Mixed-Signal IC Design Verification

Certification of automotive safety chip-set (enabling verification diversity)

IC Simulation Use Cases




Pre-silicon Benchmarking/Design-Exploration on a Virtual PlatformP

erfo

rman

ce/F

unct

iona

lity

TimeTypical MCU Roadmap

MCU_Ain series

120

120 M

Hz

MH

z z3z3z4z4

150

150 M

Hz

MH

z

z6z6

200

200 M

Hz

MH

z

z7z7

300

300 M

Hz

MH

z

Target: Design-Exploration on a Virtual Platform to define MCU Roadmap

Benchmarking of CPU Core Options within Continental’s target architecture

Evaluation of peripheral enhancements

Evaluation of architectural options

under developmentUnder definition

MCU_B

MCU_CMCU_E

MCU_D

MCU_F

MCU_G

Virtual Platform enablingDesign Space Exploration


Pre-silicon software development

S/W driver development at supplier (6 months ahead of 1st silicon)

S/W driver verification at Conti (3 months ahead of 1st silicon)

Silicon validation code development (6 months ahead of 1st silicon)

- 100% complete verification database when silicon samples are available

S/W development of new application functions (3 months ahead of 1st silicon)

H/W-S/W integration (3 months ahead of 1st silicon)


0-3-6 +3

1st SiliconSamples

TapeOut

RTLFreeze

S/W driver developmentS/W driver verification

Validation Code DevelopmentDevelopment of new appl. functions

H/W-S/W Integration


S/W Analysis on Virtual PlatformMCU/PCU Co-Simulation Result: Signal Trace

Function Trace:

Other supported traces:

- Instruction trace

- OS task trace

- Memory access

~2 s real-time vcd-trace of an application software run

MC

UP

CU

MC

UP

CU



33

Error Injection

Fault Fault


Error InjectionTarget:

Functional safety software verification: exception handling in case of system fail stateBenefit of simulator approach:

Access to failure modes, which are hard to provoke with silicon setupMethod:

Injection of errors into IC models by simulation backplane during program executionExamples:

MCU errors:Memory System: Flash data/ECC error, ECC correction error, RWW ErrorBus Systems: Data/Address/Control Bus errorClock System: Loss-of lock reset, Loss-of clock resetFailsafe System: Watchdog timer reset, Checkstop resetReset/Interrupt System

Mixed-signal IC errors:Watchdog Failures: Initialization/Command/Redundancy ErrorsADC Failures: Data Corruption Errors, Shutdown ErrorsActuator Failures: Leakage Errors, Load Driver Failures



Summary


Summary: Continental’s Chassis and Safety Virtual Platform


Continental EBS IC Development is committed to virtual prototype development

Based on Freescale’s MCU model portfolio, Continental established ECU-level mixed-signal, mixed-level Virtual Platform

ECU-level Virtual Platform enables pre- and post-silicon use cases for software development, verification and analysis as well as hardware design exploration

Coupling technology for IP model integration being developed by Continental

Scripted Tool Flow for model generation mandatory to manage complex system modeling


Simulation Summary

37

Partnership enabled►Eco system setup for

• Inter company model exchange

►Organizational support for effective virtual platform deployment►High level model quality to achieve productivity based on Virtual platforms►Reuse of existing models on-going►Full device models available 6-9 months ahead of silicon

Challenges►Inter-company model exchange

• Standards don’t support dynamic model plug- in

►Emerging virtualizations needs and requirements►Few customers today, many more tomorrow in varying stages of virtualization►Support and maintenance infrastructure

• Long model life cycle in automotive

►Change of EDA infrastructure and standards


Summary

► Pre-silicon SW development is possible today• Driver development• OS porting• Validation code development

► Simulator technology is not the bottle neck anymore• Standard Need and Solutions, For inter-company model exchange • Standardized model interfaces on ECU level• Communication interface abstraction (), FlexRay, CAN,

Signal interface

► MCU virtual prototypes aim to address key SW development challenges Integration with Tool ECO systems

► Collaboration between tools developers, model developers and services providers plus our collective customers is essential to realize the full potential of virtualization from which all can benefit.

► Virtual prototype simulation can be seen in the Tech Lab• Virtual Multicore Power Architecture Platform for

Automotive Running AUTOSAR OS Aware Debugging • Pedestal A12

TM

Date post:	29-Jun-2020
Category:	Documents
Upload:	others
View:	31 times
Download:	0 times

Freescale PowerPoint Template - NXP Semiconductors · TM Freescale, the Freescale logo, AltiVec,...

Documents