+ All Categories
Home > Documents > Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean...

Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean...

Date post: 22-Mar-2020
Category:
Upload: others
View: 1 times
Download: 0 times
Share this document with a friend
68
Frequent Subtree Mining on the Automata Processor: Challenges and Opportunities Elaheh Sadredini, Reza Rahimi, Ke Wang, Kevin Skadron Department of Computer Science University of Virginia Presenting in: International Conference on Supercomputing, June 13-16, 2017
Transcript
Page 1: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

FrequentSubtree MiningontheAutomataProcessor:ChallengesandOpportunities

ElahehSadredini,RezaRahimi,Ke Wang,KevinSkadronDepartmentofComputerScience

UniversityofVirginia

Presentingin:InternationalConferenceonSupercomputing,June13-16,2017

Page 2: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Motivation

11/21/17 InternationalConferenceonSupercomputing2017 2

Page 3: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Motivation

11/21/17 InternationalConferenceonSupercomputing2017 3

Page 4: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Motivation

11/21/17 InternationalConferenceonSupercomputing2017 4

Page 5: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

WhatIstheFrequentSubtree Mining(FTM)?Ø To efficiently enumerate all frequent subtrees in a forest (database of trees) according to a given

minimum supportØ The support of a subtree is the number of subtrees in D that contains one occurrence of SØ A subtree S is frequent if its support is more than or equal to a user specified minimum support

value

11/21/17 InternationalConferenceonSupercomputing2017 5

AC

A

B C

D B

A

BA

DB

C

B C

AD

Relative support threshold: 60%

Page 6: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

WhatIstheFrequentSubtree Mining(FTM)?Ø To efficiently enumerate all frequent subtrees in a forest (database of trees) according to a given

minimum supportØ The support of a subtree is the number of subtrees in D that contains one occurrence of SØ A subtree S is frequent if its support is more than or equal to a user specified minimum support

value

11/21/17 InternationalConferenceonSupercomputing2017 6

AC

A

B C

D B

A

BA

CB

C

B C

AD

Relative support threshold: 60%

Support = 3

Is frequent:

Page 7: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Preliminaries

Inducedsubtree

11/21/17 InternationalConferenceonSupercomputing2017 7

Embeddedsubtree

B

A

C

B

A C

C

B

A

C

Tree

Subtree

0

1

2

3

6

5

4

B

A

C

B

A C

C

B

A

C

Tree

Subtree

0

1

2

3

6

5

4

Page 8: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

IssueswiththeCurrentFTMSolutions(1)Pros Cons

BFS Massive pruningMemory efficient

Multi-pass of datasetslow

DFS Fast Little pruning opportunityMemory-hungry

11/21/17 InternationalConferenceonSupercomputing2017 8

BFSandDFSrefertocandidategenerationapproach,nottreetraversalJ

Page 9: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

IssueswiththeCurrentFTMSolutions(2)

11/21/17 InternationalConferenceonSupercomputing2017 9

Page 10: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

IssueswiththeCurrentFTMSolutions(2)

11/21/17 InternationalConferenceonSupercomputing2017 10

Page 11: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Wouldthatbeacceptabletoachievehundreds-X speedup attheexpenseofloosingacoupleofpercentaccuracy?

Contributionofthisresearch:

• Proposing a memory efficient and fast solution to the frequentsubtree mining problem on the Automata Processor

• Achieving 350X and more speed up, when allowing 7.5% falsepositive subtrees

11/21/17 InternationalConferenceonSupercomputing2017 11

Page 12: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

TheRestofThisTalk• AutomataProcessor• FTMChallengesandOpportunitiesontheAP• ExperimentalEvaluation• Takeaways

11/21/17 InternationalConferenceonSupercomputing2017 12

Page 13: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

TheAutomataProcessor(1)• TheMicronAutomataProcessor(AP)isareconfigurablenon-vonNeumann

architecture,whichimplementsnon-deterministicfiniteautomata(NFA)withBooleanlogicgatesandcountersinhardwarebasedonDRAMtechnology.

RowAdd

ress

(Inpu

tSym

bol)

RowAccessresultsin49,152match&routeoperations(thenBooleanANDwith“active”bit-vector)

RoutingMatrix

Automata Processor

11/21/17 InternationalConferenceonSupercomputing2017 13

Page 14: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

TheAutomataProcessor(2)• Amassivelyparallel‘MISD’architecture• 1Gbps dataprocessing• Hardwareresourcesondevelopmentboard

– StateTransitionElements(STE):1.5M– ReportingSTEs:200K– CounterElements:25K– BooleanElements:74K

11/21/17 InternationalConferenceonSupercomputing2017 14

Page 15: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

ApplicationsontheAP• Datamining

– Frequentitemset mining– Sequentialpatternmining

• Machinelearning– Randomforest– Entityresolution– String/treekernel

• Bioinformatics– Motifdiscovery– DNAalignment

• …

11/21/17 InternationalConferenceonSupercomputing2017 15

Page 16: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Challenges:ExactFTMontheAP

The AP supports regular languages

Tree can be represented using context-free-grammar [Ivn07]

11/21/17 InternationalConferenceonSupercomputing2017 16

Page 17: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Challenges:ExactFTMontheAP

The AP supports regular languages

Tree can be represented using context-free-grammar [Ivn07]

The AP can not efficiently implement exact FTM

11/21/17 InternationalConferenceonSupercomputing2017 17

Page 18: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Challenges:ExactFTMontheAP

Exact solutions (e.g., stack implementation on the AP)InefficientDatabase dependent Impractical

The AP supports regular languages

Tree can be represented using context-free-grammar [Ivn07]

The AP can not efficiently implement exact FTM

11/21/17 InternationalConferenceonSupercomputing2017 18

Page 19: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Opportunities:Pruning

• Four-stage pruning strategy– Subset pruning– Intersection pruning– Downward pruning – Connectivity pruning

• Kernel properties– Complementary pruning– Avoiding false negatives

Generatecandidatesofk-subtree

PrunecandidatesontheAP

K<maxK&&K-subtreenotempty

K=K+1

Yes

Writeresults

AP

CPU

FindfinalfrequentsubtreeontheCPU

CPU

Isexactsolutionneeded?

No

Yes

No

11/21/17 InternationalConferenceonSupercomputing2017 19

Page 20: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Background• Frequentitemset mining(FIM)

11/21/17 InternationalConferenceonSupercomputing2017 20

Trans. Items

1 Bread,Milk

2 Bread, Diaper, Beer, Eggs

3 Milk,Diaper, Beer, Coke

4 Bread,Milk, Diaper, Beer,Coke

5 Bread, Milk, Coke,Diaper

sup({Diaper,Milk})=3

Trans. Items

1 <{Bread,Milk},{Coke}>

2 <{Bread, Milk,Diaper}{Beer,Eggs}{Diaper}>

3 <{Milk} {Diaper} {Beer, Coke}>

4 <{Bread,Milk, Diaper}{Beer,Diaper}{Beer,Coke,Eggs}>

5 <{Bread, Milk}{Coke}{Diaper}{Eggs}>

• Sequentialpatternmining(SPM)

Bread Milk

Eggs

Page 21: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Kernel1:SubsetPruning• Maingoal:checksdownwardclosureproperty

*Wang,Ke,etal."AssociationruleminingwiththeMicronAutomataProcessor." ParallelandDistributedProcessingSymposium(IPDPS),IEEE,2015.11/21/17 InternationalConferenceonSupercomputing2017 21

Page 22: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Kernel2:IntersectionPruning• Maingoal:checksifallthesubsetsofacandidatehappensinthesametree

11/21/17 InternationalConferenceonSupercomputing2017 22

Page 23: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Kernel3:DownwardPruning• Maingoal:checksifancestordescendantrelationshipismet

* Wang, Ke, Elaheh Sadredini, and Kevin Skadron. "Sequential pattern mining with the Micron automata processor." Proceedings of the ACM International Conference on Computing Frontiers. ACM, 2016.

11/21/17 InternationalConferenceonSupercomputing2017 23

Page 24: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Kernel4:ConnectivityPruning• Maingoal:checksifsiblingrelationshipismet

11/21/17 InternationalConferenceonSupercomputing2017 24

Page 25: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

11/21/17 InternationalConferenceonSupercomputing2017 25

Framework

1. MakingARMandSPMautomataforeachkernel2. Creatingappropriateinputstream3. ConfiguringtheautomataforeachkernelontheAPand

streamingthecorrespondinginputstream4. GettingthepotentialfrequentsubtreesfrotheAPoutputafter

applyingthekernels

Page 26: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

PerformanceEvaluation• Platform

– CPU:Intel(R)Core™[email protected],Memory:32GB– GPU:TeslaK80,Memory24GB

• Dataset

• Apples-to-applescomparison

11/21/17 InternationalConferenceonSupercomputing2017 26

Page 27: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

GPUImplementation• BFSApproach,because:

– NotbeboundbythefiniteGPUglobalmemory– Exposesmanyready-to-processcandidatesandprovideparallelism

• FTM-GPU– CandidategenerationontheCPU– SubsetpruningontheCPU– EnumerationontheGPU

• Treesinsharedmemory• Candidateinconstantmemory

• Sortingtheinputtrees– Decreasedivergence

11/21/17 InternationalConferenceonSupercomputing2017 27

Page 28: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Algorithmic&ArchitecturalContributions

APkerneloverCPUkernelspeedup:Subset=upto163X

Intersection:upto19XDownward:upto3144XConnectivity:upto2635X

11/21/17 InternationalConferenceonSupercomputing2017 28

Page 29: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Algorithmic&ArchitecturalContributions

APkerneloverCPUkernelspeedup:Subset=upto163X

Intersection:upto19XDownward:upto3144XConnectivity:upto2635X

11/21/17 InternationalConferenceonSupercomputing2017 29

Page 30: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Algorithmic&ArchitecturalContributions

APkerneloverCPUkernelspeedup:Subset=upto163X

Intersection:upto19XDownward:upto3144XConnectivity:upto2635X

11/21/17 InternationalConferenceonSupercomputing2017 30

Redbaroverblackbar:upto1.6XBlackbars:upto215XRedbars:upto353X

Page 31: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

PruningEfficiency

Kerneleffectiveness:Subset=80%

Intersection:0.5%Downward:3.5%Connectivity:4.8%

11/21/1731

Page 32: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

PruningEfficiency

Kerneleffectiveness:Subset=80%

Intersection:0.5%Downward:3.5%Connectivity:4.8%

11/21/1732

Removingintersectionkernel:APoverPatternMatcher:353Xà 2190X

Accuracy:86%à 83%

Page 33: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

FTM-APvsOtherFTMAlgorithmsTrade-offbetweenspeed andaccuracy oftheAPsolutionvstheexistingFTMimplementation

33Dataset:CSLOGS

Page 34: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

FTM-APvsOtherFTMAlgorithmsTrade-offbetweenspeed andaccuracy oftheAPsolutionvstheexistingFTMimplementation

34Dataset:CSLOGS

Page 35: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

FTM-APvsOtherFTMAlgorithmsTrade-offbetweenspeed andaccuracy oftheAPsolutionvstheexistingFTMimplementation

35Dataset:CSLOGS

Page 36: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

FTM-APvsOtherFTMAlgorithmsTrade-offbetweenspeed andaccuracy oftheAPsolutionvstheexistingFTMimplementation

36Dataset:CSLOGS

Speedup

&'(_*++,--./0(,-12./

=upto353X

Memoryusage

'/..(<0./=&'(_*+

=upto5000X

Page 37: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

ExactSolution:AP+TreeMinerD

11/21/17 InternationalConferenceonSupercomputing2017 37

Page 38: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

ExactSolution:AP+TreeMinerD

11/21/17 InternationalConferenceonSupercomputing2017 38

Page 39: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

PerformanceEvaluation:ExactSolution:AP+TreeMinerD

4.14X

5.8X

Intel Xeon CPU, 2.30GHz, 512 GB memory, 2.133GHz Dataset:TREEBANK

Page 40: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Summary• Proposeamulti-stagepruningframeworkontheAP

– ThefirstworktousetheAPasapruningmedia– Novelpruningkernels– Abetterscalabilityandstablebehavior– Proposeanexactsolution

11/21/17 InternationalConferenceonSupercomputing2017 40

Takeaways• Rethinkingthealgorithmwhenhavinganewhardwarearchitecture• AppliestospatialautomatacomputingarchitecturesuchasFPGAs• Thisapproachcanbeadoptedforothercomplexpatternminingproblems• Providessomeinsightforthearchitecturalchanges

Page 41: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

References• Ke Wang, Elaheh Sadredini, and Kevin Skadron. "Hierarchical Pattern Mining with the Micron Automata Processor.“ International Journal of Parallel

Programming (IJPP), 2017.• Ke Wang, Elaheh Sadredini, and Kevin Skadron. "Sequential Pattern Mining with the Micron Automata Processor." ACM International Conference on

Computing Frontiers, May 2016• J. Wadden, V. Dang, N. Brunelle, T. Tracy II, D. Guo, E. Sadredini, K. Wang, C. Bo, G. Robins, M. Stan, K. Skadron. "ANMLZoo: A Benchmark Suite for

Exploring Bottlenecks in Automata Processing Engines and Architectures." IEEE International Symposium on Workload Characterization (IISWC), October2016.

• Elaheh Sadredini, Reza Rahimi, Ke Wang, and Kevin Skadron. "Frequent Subtree Mining on the Automata Processor: Opportunities and Challenges." ACMInternational Conference on Supercomputing (ICS), Chicago, June 2017

• Shirish Tatikonda, Srinivasan Parthasarathy, and Tahsin Kurc. ”TRIPS and TIDES: new algorithms for tree mining.” Proceedings of the 15th ACMInternational Conference on Information and Knowledge Management. ACM, 2006.

• Ke Wang, Elaheh Sadredini, and Kevin Skadron. ”Sequential pattern mining with the Micron automata processor.” Proceedings of the ACM InternationalConference on Computing Frontiers. ACM, 2016.

• Mohammed Javeed Zaki. ”Efficiently mining frequent trees in a forest: Algorithms and applications.” IEEE Transactions on Knowledge and DataEngineering 17.8 (2005): 1021-1035.

• Yun Chi, et al. ”Frequent subtree mining an overview.” Fundamenta Informaticae 21: 1001-1038, 2011. Paul Dlugosch, et al. ”An efficient and scalablesemiconductor architecture for parallel automata processing.” IEEE Transactions on Parallel and Distributed Systems, 25.12:3088-3098, 2014.

• Renta Ivncsy, and Istvn Vajk. ”Automata Theory Approach for Solving Frequent Pattern Discovery Problems.” World Academy of Science, Engineering andTechnology, International Journal of Computer, Electrical, Automation, Control and Information Engineering 1(8): 2556-2561, 2007.

• Fedja Hadzic, Henry Tan, and Tharam S. Dillon. Mining of data with complex structures. Vol. 333. Springer-Verlag, 2011.• John L. Hennessy, and David A. Patterson. Computer architecture: a quantitative approach. Elsevier, 2011.• Ke Wang, et al. ”Association rule mining with the Micron Automata Processor.” Parallel and Distributed Processing Symposium (IPDPS), IEEE

International, 2015.• Wang, Ke, Kevin Angstadt, Chunkun Bo, Nathan Brunelle, Elaheh Sadredini, Tommy Tracy II, Jack Wadden, Mircea Stan, and Kevin Skadron. "An overview

of micron's automata processor." In Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and SystemSynthesis, p. 14. ACM, 2016.

11/21/17 InternationalConferenceonSupercomputing2017 41

Page 42: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

Thank you J

Questions?

11/21/17 InternationalConferenceonSupercomputing2017 42

Page 43: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

BackupSlides

11/21/17 InternationalConferenceonSupercomputing2017 43

Page 44: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

B

A

D

A

C B

StringEncoding:ABC– BA– – – D

C

A

B

BD

B

A

D

ADCA

D

StringEncoding:AA – CD– BDA– C– – BD– A– – – – BD

PDA-basedSubtreeMining:AnExampleTree

Embeddedsubtree

11/21/17 InternationalConferenceonSupercomputing2017 44

Page 45: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

DeterministicPDA

11/21/17 InternationalConferenceonSupercomputing2017 45

Page 46: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:A A – CD– BDA– C– – BD– A– – – – BD

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 46

Page 47: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

A

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 47

Page 48: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 48

Page 49: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – C D– BDA– C– – BD– A– – – – BD

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 49

Page 50: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD – BDA– C– – BD– A– – – – BD

D

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 50

Page 51: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 51

Page 52: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– B DA– C– – BD– A– – – – BD

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 52

Page 53: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BD A– C– – BD– A– – – – BD

D

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 53

Page 54: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA – C– – BD– A– – – – BD

A

D

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 54

Page 55: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

D

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 55

Page 56: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C – – BD– A– – – – BD

<C,2>

D

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 56

Page 57: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

D

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 57

Page 58: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 58

Page 59: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – B D– A– – – – BD

<B,4>

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 59

Page 60: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD – A– – – – BD

D

<B,4>

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 60

Page 61: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

<B,4>

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 61

Page 62: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A – – – – BD

<A,5>

<B,4>

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 62

Page 63: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

<B,4>

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 63

Page 64: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

<B,1>

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 64

Page 65: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

C

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 65

Page 66: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 66

Page 67: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – B D

B

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 67

Page 68: Frequent SubtreeMining on the Automata Processor ...es9bt/papers/ICS_2017_FTM_ppt.pdf · Boolean logic gates and counters in hardware based on DRAM technology. s ) Row Access results

𝑞?,? 𝒒𝟏,𝟏 𝒒𝟐,𝟐 𝒒𝟑,𝟑

𝒒𝟗,𝟏 𝒒𝟖,𝟐 𝒒𝟕,𝟑 𝒒𝟔,𝟒

𝒒𝟓,𝟑

𝒒𝟒,𝟐A,*/<A,0>* B,*/<B,1>* C,*/<C,2>*

A,*/<A,5>*

-,C/𝜀-,<C,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

Inputtree:AA – CD– BDA– C– – BD– A– – – – BD

<D,9>

B

<A,0>

*

𝜆\A,*/𝜆\A*-,*/𝜀

𝒒𝟏𝟎,𝟏 D,*/<D,9>*

B,*/<B,4>*

-,A/𝜀-,<A,*>/𝜀

-,B/𝜀-,<B,*>/𝜀

𝜆\B,*/𝜆\B*-,*\<A,0>/𝜀

𝜆\C,*/𝜆\C*-,*\<B,1>/𝜀

𝜆,*\𝜆*-,*\{C,<C,*>}/𝜀

𝜆\B,*/𝜆\B*-,*\<B,1>/𝜀

𝜆\A,*/𝜆\A*-,*\<B,4>/𝜀

𝜆,*\𝜆*-,*\{A,<A,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆,*\𝜆*-,*\{B,<B,*>}/𝜀

𝜆\D,*/𝜆\D*-,*\<A,0>/𝜀

𝜆,*/*-,*/𝜀

-,<A,0>/ 𝜀-,<B,1>/ 𝜀

-,<B,1>/ 𝜀

-,<B,4>/ 𝜀

-,<A,0>/ 𝜀

11/21/17 InternationalConferenceonSupercomputing2017 68


Recommended