Front-to-Back Alignment and Metrology Performance for Advanced Packaging

G. O. Kenyon, W. Flack, R. Hsieh

Veeco Instruments

• Introduction

• Lithography

• Alignment System; TSV Lithography

• Metrology• Optical Metrology; Tool Induced Shift (TIS)

• Results

• Electrical Correlation

• Summary

Outline

Introduction

Introduction

• Scaling 2D structures has for a long time been considered the most cost effective method for performance gain…

• That is no longer true…

• 2.5D/3D… and Embedded technologies are evolving…

• However, as structures are stacked, complexity

increases, overall visibility decreases

Complexity: Heterogeneous System Integration

• System build up with materials, components, nodes individually generated

Complexity compounded by

multiple die stacking

• As 2.5, 3D and Photonics technologies evolve, critical requirements for intra

and inter silicon processes have emerged

• In-line metrology of these regions is not easily achieved using conventional

methods (microscopy, SEM) and is often only discovered using destructive

methods (C-SEM, FIB) after process completion

Complexity: Heterogeneous Integration

AMD Radeon Series GPU with HBM2 Cross Section

Samsung 8GB HBM2 Cross Section (50µm thick)

• 2.4Gbps pin speed at 1.2V

• 307Gbps data bandwidth

• HBM2 now standard for advanced GPU’s

• 10 metal Layer BGA Substrate

• Matured TSV Middle Process for Interposer and Memory

stacking

• 5000 + TSV’s per die : Total 40,000 + TSV’s

How can we understand or see

these critical regions in-line?

Complexity: Image Sensor Cross Section

BEOL:

Logic = 5 Cu + 1 Al

DRAM = 3 Al

Pixel = 5 Cu + 1 Al

40nM Process

30nM Process

90nM Process

130µ

m P

ackage T

hic

kness

TSV:

Min. Ø = 2.5µm

Min. Pitch = 6.3µm

Total: > 35,000

Line/Space:

Min. 2µm Line

Min. 0.64µm Space

How can we understand

these critical regions in-

line?

Lithography

• Infra red (IR) transmission has emerged as a leading contender for alignmentand metrology applications that consider:

• Embedded target alignment• TSV scaling support, MEMS construction, Photonics packaging

• Die-to-wafer or wafer-to-wafer applications

• Full thickness and thinned silicon support

Preamble

• IR transmits through silicon

• Top directed illumination allows

for flexible placement of targets

on the wafer

• Off axis IR camera implemented

on stepper

• Measure XY positions of two

features at different Z heights

• Together these features make up

the Dual Side Align (DSA)

alignment system

Alignment System

TSV Scaling

TSV module

BEOL modules

FEOL modules

Contact module

Thinning &

BS passivation

Via-last

BS RDL/µbump

• Of three defined TSV methodologies via last offers process

advantages through minimal impact on Back End Of Line

(BEOL) with no requirement for TSV reveal processes

• Performance improvements can be realized by scaling TSV’s

and landing pads, including better electrical performance, lower

power consumption, wider data width (generating improved

bandwidth), smaller/lighter weight, higher density and ultimately

at lower cost (ideally!)

• The scaling challenge focuses attention on back-to-front overlay

performance required to align the TSV to the landing pad at the

metal level …creating a critical parameter for overlay…

• With smaller TSV dimensions, back-

to-front overlay becomes a critical

parameter as via landing pads on first

level metal must be large enough to

include both TSV critical dimension

(CD) and overlay variations

• Current via-last diameters are

approximately 10µm with scaling

projected down to 1µm

TSV-Last

Full Thickness Silicon Imagery

• Silicon thickness is 775µm

• The refractive index of silicon with IR reduces the required focus offset

Topside Resist

(0 µm focus)

Backside metal

(-220 µm focus)

Metrology

DSA-SSM metrology target for 5µm diameter TSV’s (thinned silicon)

• Right: -50µm focus offset. The embedded circle

of metal 1 in focus (blue ring)

• Left: 0µm focus offset. Resist target in focus (red

ring)

• The height difference between the two features is

larger than the focal depth of the camera so one

of the two is always out of focus

Metal 1 pad outer edge

Optical Metrology: Thinned Silicon

Resist feature

Process rules dictate all vias be the same size and so a target has to be integral to the process, but unique

• Overlay settings are optimized using DSA-

SSM metrology measuring “n” fields per

wafer, “n” points per field (product

dependent)

• Parameters are fixed to investigate overlay

stability

• Rework and re-measure lot for a suitable

time period

• Each data set is corrected for TIS on a per

lot basis (discussed in following slides)

Vector plot of overlay measurement

Stepper Self Metrology (SSM) & Optical Registration

• Tool Induced Shift (TIS) is an apparent alignment offset

caused by metrology

• Several parameters can influence TIS:

• Tilt in camera or wafer

• Non-symmetric Illumination

• Photo-resist or wafer processing

• The illustration shows a tilted camera viewing a pattern

in photo-resist and a buried metal reference.

• The resist pattern appears shifted from the viewpoint of

the camera with respect to the vertical

A word about TIS…

Si Carrier

glue

oxide

Si wafer

photoresist

… and can be conceptualized as a vector

diagram

• The apparent error (raw measurement)…

is the sum of actual error…

and TIS

• TIS is an inherent error exhibited in all metrology systems…

TIS Concept

Apparent Error

Actual Error

TIS

For a 180 degree rotation of the wafer the error

associated with the wafer rotates, but the TIS

component is stationary

TIS can now be determined from the sum of the 0

and 180 degree measurement

Actual error can be determined from the difference

Calculating TIS

2 2.

1800 YYTISy

2 1.

1800 XXTISx

2 3.

1800

,0

XXX corrected

2 4.

180

,0

0 YYY corrected

Apparent Error (180 º)

Apparent Error (0 º)

Actual Error TIS

Data Results

• Each die on one wafer (115 die

per wafer) was measured 5

separate times

• Average 3σ is 30nm in X and Y

IR Alignment Capture Repeatability

Reference: IWLPC 2015: Optimization Of Through Si Via

Last Lithography for 3D Packaging

Mean Value

3σ

TSV Optical Metrology: Overlay Stability Data (Thinned Si)

TSV registration trend charts Reference: EPTC 2016: Overlay Performance of TSV Last

Lithography for 3D Packaging

• Lot data 3σ is

consistently < 600nm

over a 2 year period

• Y mean was adjusted to

improve subsequent data

• With a Y mean

correction, mean + 3σ ≤

600nm for the data set

Back-to-Front Overlay Data (Full Thickness Si)

• Silicon thickness @ 775µm

• The refractive index of silicon with IR reduces the required focus offset

Topside Resist (0 µm focus) Backside metal (-220 µm focus)

Nested Box

Overlay Structure

Layout of Resistor Fork Structure

• Electrical verification of TSV alignment is

performed after processing is complete

for an independent verification of DSA

metrology

• Relies on the landing position of a TSV

sited on a fork-to-fork test structure

constructed in metal 1

• TSV will create a short between two sets

of metal forks

• Similar structure is rotated through 90

degrees for Y data

Electrical Metrology for Optical Metrology Validation

Reference: EPTC 2016: Overlay Performance of TSV Last

Lithography for 3D Packaging

• To improve resolution, structures with an offset in TSV location have been placed in the design

• If one of the TSV edges contacts an adjacent bottom branch, a change in R1-2 or R2-3, with a

step pitch of Lu will result

• Combining the two X-positions of the four (shifted) TSV’s reveals an alignment error with a

resolution of 90 nm

Electrical Metrology: TSV Offset

1 3

2

XE1

R1-2

Lu

1

2

3

XE2

R2-3

Reference: EPTC 2016: Overlay Performance of TSV Last

Lithography for 3D Packaging

• Only one electrical measurement position

per die• Correlates to centre of field for optical measurement

• Important note: An extra translation step is

performed between the optical and the

electrical measurement: the TSV etch• TSV etch is assumed to be perfectly vertical

• Registration numbers can be extracted from

these vector plots

Electrical = Black

Optical = Blue

Difference = Red

Vector plot

Electrical Versus Optical: TSV Overlay

Reference: EPTC 2016: Overlay Performance of TSV Last

Lithography for 3D Packaging

Metrology

Type

Wafer D17 Wafer D10

Average stdev Average stdev

X Y X Y X Y X Y

Electrical 137 -51 186 121 90 -4 163 107

Optical 146 -41 132 78 140 -14 129 82

Difference 9 10 76 100 50 -10 63 68

Statistical summary of electrical and optical registration data

• Two wafers were taken through to the completion of processing

• Good correlation between optical and electrical data confirms the accuracy of the in-line optical

metrology method and non-translational etching

Electrical Comparison: TSV Statistical Summary

Reference: EPTC 2016: Overlay Performance of TSV Last

Lithography for 3D Packaging

Summary

• Scaling of TSV’s in the TSV-last process requires tighter specs on overlay

• Direct verification of thinned silicon TSV litho to the embedded reference layer is enabled by using the DSA alignment system combined with dedicated analysis software

• Direct verification of full thickness silicon litho to backside metal with dedicated analysis software is demonstrated

• Mean plus 3σ ≤ 600nm, stable over 2 years at customer site

• Independent electrical assessment of the optical performance was demonstrated

• Good correlation between optical and electrical data confirms the accuracy of the in-line optical metrology method

Summary