1 Front-To-Back MMIC Design Flow with ADS • Speed MMICs to market • Save money and achieve high yield
Transcript
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Front-To-Back MMIC Design Flow with ADS
• Speed MMICs to market • Save money and achieve
high yield
Presenter
Presentation Notes
Hello and welcome to this Front-to-Back MMIC Design Flow with ADS. This presentation will highlight the design flow steps in ADS that will insure a first pass with lowest cost and highest yield. To be competitive, MMIC designers are continually challenged to reduce costs and get their devices to market fast, and ahead of the competition. The Advanced Design System (ADS) from Agilent EEsof EDA allows today’s MMIC designers to meet these challenges. It provides designers with: >> Next 5 pages
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Yield SensitivityHistogram (YSH)to components
Unique Tools for Robust Designs, First Pass, and High Yield
Presenter
Presentation Notes
1) Unique and advanced set of tools to create robust designs, first pass success, and high yield
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Agilent EEsof MMIC Foundry Partners All ADS kits are built and certified by foundriesAtmel austriamicrosystemsBookham Technology Cree, Inc. Filtronic Compound Semiconductors Global Communication Semiconductors, Inc. (GCS) IHP Microelectronics Infineon IBM Microelectronics Jazz Semiconductor Knowledge*on Semiconductor Maxim Integrated Products Northrop Grumman Electronic Systems Northrop Grumman (Velocium) MagnaChip Semiconductor OmmicPeregrine Semiconductor Raytheon RF Components Philips Electronics N.V. Semiconductor Manufacturing International Corporation (SMIC) STMicroelectronics TriquintUMC UMS TSMC WIN X-FAB
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2) Complete and continuously updated process design kits from all major MMIC foundries.
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Advanced Tools Seamlessly Integrated in ADS
Phase Noise at VCO’s Output
Phase Noise atDivider’s Output
AM Noise at Divider’s Output
Convolution
Planar EMMomentum
FEM 3D EM (EMDS)
Linear Simulator
Harmonic Balance
Circuit Envelope
3D Features includes 3D JDEC Bond Wire
Presenter
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3) Complete set of advanced simulation tools, seamlessly integrated in one single environment, from schematic entry to production and packaging of the MMIC.
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EMDS JDEC Bond WireTrue MMIC Design Verification prior to Manufacturing is done by Co-simulating the MMIC inside the package and with bond wires using EMDS in ADS 2008
True MMIC Verification Prior to Manufacturing
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4) The ability to verify, prior to fabrication, that a MMIC meets all specifications in its final package, using seamlessly integrated Planar EM and 3D-EM tools.
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PA Verification to wireless Standards
WIMAX TransmitSource
PA
PA Verification to Wireless Standards
Realistic Input Signals and test benches for all Wireless Standards
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Presentation Notes
5) The ability to provide “True Circuit” verification to all wireless standards, prior to and post fabrication, using a complete set of the most accurate wireless verification tools.
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Part 1
Sche
mat
ic E
ntry
ADS Complete Front-to-Back MMIC Design Flow
Presenter
Presentation Notes
This is a complete front to back MMIC design flow solution in ADS, all in one single environment. Its many features, as we will discover shortly, bring a higher level of productivity to the MMIC design process. It starts by choosing the appropriate Foundry Design kit with all the needed elements and models to start your design. It is then followed by the Schematic Entry phase of the design, and then followed by the Statistical design phase using ADS unique tools that converts your initial design into a highly robust design with first pass and high yield. Next, an early-on Verification to wireless standards specs is shown in order to verify that your design meets its wireless specs prior of starting the physical design part. The right side shows the Physical design section, which includes the creation of the Layout and using the Planar and 3D integrated EM tools to insure design accuracy and first pass success. DRC, LVS, and Packaging the MMIC are all included in this Physical Verification cycle of the design flow. In the next slides I will go over each step in more detail.
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Agilent EEsof EDA MMIC Foundry Partners All ADS Kits are built and Certified by Foundries
Gaetec
Knowledge*on
The only complete MMIC PDK offering in the EDA Market, that is fully supported, maintained, and regularly updated by the foundries.
If we don’t have the PDK kit you need, we’ll create it for you!
Presenter
Presentation Notes
Strategic partnerships with leading MMIC foundries demonstrate Agilent’s established leadership in MMIC design. These relationships ensure that more and more foundry processes support the complete MMIC design flow in ADS, including physical design. Agilent EEsof EDA has more MMIC PDKs than any other EDA vendor in the industry today, providing designers the widest choice of foundries for MMIC design with the best availability and price performance. Agilent’s PDKs are jointly created by Agilent and the foundry, and are fully validated and regularly maintained and updated. So designers always have access to the latest and most up to date foundry models that reflect the most recent processes. In summary, ADS has a complete set of MMIC process design kits (PDK) - the only ones in the industry to be fully verified, supported, maintained, and continuously updated by the foundries
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AMC brings the accuracy of EM simulation and the speed of analytical models into a single, user-defined, compact model.
Arbitrary user-defined parameterized shapes
Generates model, symbol & layout
Advanced Model Composer (AMC) Technology
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Advanced Model Composer Advanced Model Composer (AMC) is a patented ADS technology that allows designers and foundries to create arbitrary passive structures and shapes with built-in EM effects. The resulting compact models can be used for fast tuning and optimization, enabling the designer to converge on specified parameters in seconds. AMC technology brings the accuracy of EM simulation and the speed of analytical models into a single, user-defined, compact model.
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Example: TriQuint MASC Design Kit
Valid Range of models
EM based InductorModels Using AMCTechnology
Presenter
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This is an example taken from the TriQuint .15u PHEMT MASC Design Kit. It shows a Spiral that has a range of widths and lengths that have been generated using AMC. Users can use this Spiral inductor within the simulated range to get an already EM simulated model.
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Modifying the line by inserting an air-bridge with an offset and angle
Fully Parameterized Lines and Discontinuities
Initial Line Lines Information contain Layers and current density
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From the TriQuint .15u PHEMT MASC Design Kit for ADS, here is an example of a line that can be altered by adding a bridge to it and by offsetting the bridge and by changing its angle – all from a dialogue window. The Help menu for these lines give the designer a full set of layers with their current densities. Designers then have a choice on what type lines to use. Each type contains a different set of layers.
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Example: LNA - TriQuint MASC Design Kit
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This is an example of a one stage LNA using various elements from the design kit.
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ADS Complete Front-to-Back MMIC Design Flow
Presenter
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After having found a good design kit and models, now the next step is to start our design using the schematic entry along with the various advanced circuit simulators such as ADS non-linear Harmonic Balance and Circuit Envelope simulators, Transient and Convolution simulators, Linear and System simulators, and planar and 3D EM simulators – all integrated together in one single design environment.
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Demo example – Ku-band LNA Front End Design – FET Characterization
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As I walk through this presentation I will keep referring to this simple one stage LNA demo in order to illustrate the steps taken by designers to build a design. Starting with our FET model (taken from a design kit), we use the “Templates” pull down menu and use the FET Curve Tracer template to generate the Curve tracer I_V curves and power dissipation. This is all done automatically without having to do any set up. Just insert the device in the template and push simulate. This helps designers establish the Q bias point in order to start the design.
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Front End Design Biasing, Stability, Max Gain, Noise and Gain Circles
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Having found the bias point voltage and current, we add the appropriate bias lines and stability resistors that provide the required bias and stability. Next, generating the Gain and Noise circles is done very easily and automatically in ADS. Designers can drag pallets from the side of the page into the schematic page. These pallets are pre-generated functions that automatically produce the gain and noise circles, maximum gain, stability circles, stability measures, and many many other useful functions. The Gain and Noise circles here will help us find a proper matching impedance point that produces the gain and noise figure according to the specs.
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Front End Design
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Markers M1 and M2 are very close and they give us 11.3 dB gain and 1.52 dB NF Without any matching, the circuit now provides 8.758 dB gain and 1.838 dB NF. We are able to match it to get a maximum gain of 12.812 dB gain at the expense of higher NF. We choose to match it to impedance Zo in order to get the 11.3 dB gain and 1.52 dB NF
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Impedance Matching
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Having known the impedance point you want to match to, designers can then use the Impedance Matching Tool in ADS, located in the “Tools” Pull-down menu and which can automatically find a good matching network for the given impedance point of last page.
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Front End Design
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Repeating the same process for the output matching network, this is our final amp with both input and output matching networks. As mentioned earlier, notice on the left hand side, there are many automated measurement equations that designers can drag into the schematic page and get the results automatically done. In this example I have used the Stability icons and the results will be shown automatically once I simulate the design
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Front End Design
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Here are the tabulated results which can be plotted as well. Mu1, Mu Prime, Stability Factor are all greater than one and the Stability Measure is positive. All of these are required to have an Unconditionally Stable Amp.
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Front End Design
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Here are the simulation results of our first cut LNA design. Gain= 11.8 dB NF= 1.751 dB S22 = -25 dB You can optimize the design for lower NF at a price of lower gain. Now, you might think we are done. First, let us see how this LNA perform with the foundry process variation. Let us find out how manufacturable it is and what would be the predicted yield?
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Front End Initial Design – Yield Analysis
Presenter
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With the process variation shown on the top left of the page (in Blue), we see that the LNA has 27 % yield. The specs are shown with vertical red lines: NF spec is 1.85 dB or lower Gain spec is 11 dB or higher S22 spec is -15 dB or lower It is the process variations that have caused the response to shift out from its nominal response and caused all these failures. So what do we do? Next I will introduce you to Unique tools in ADS that will transform this design into Robust design with high yield and low sensitivity. These are the set of DFM tools in ADS that consist of DOE, Yield Sensitivity Histograms, Sensitivity Analysis, and the High Yielding Impedance Matching tool. These tools will help you transform any design into a robust and high yielding design, thus ensuring first pass with lowest cost.
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DFM
ADS Complete Front-to-Back MMIC Design Flow
Presenter
Presentation Notes
In our design process, the DFM part happens up front and before we do the physical design part. It is important to have a solid robust design topology before we proceed to the physical design part. Design iterations and extra wafer runs take time and can cost hundreds of thousands of dollars. Designs employing these DFM design techniques are less sensitive to process variation and result in first-pass success, as well as much higher yield; saving you both time and money.
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The Value of ADS DFM Technology Designing circuits that will work no matter what
The only EDA company with unique DFM design tools that allow MMIC designers to create and manufacture robust circuits with first-pass success and high yield
High manufacturing yield (Lower cost per chip)
Insensitive to changes in temp and supply voltage
First to market
Tremendous amount oftime and $$ savings
Reliable, high quality designs
First pass success
ADS DFM Tools
Presenter
Presentation Notes
By integrating the DFM design tools in your design flow process, these are the values you will end up achieving First pass success First to Market your products High yield – translates to lower cost per chip Robust and quality designs that are insensitive to process variation and to temperature variation and to changes in the voltage supply All these translate to a tremendous amount of saving in time and money
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Real MMIC Designs – Fabricated on the Same Wafer Actual real-world examples
Amp1
U/C 1macro
U/C 2macro
Amp2
A reticle contains a fewcircuits, stepped and repeatedacross the whole wafer
1) Used a standarddesign technique
2) Used a DFM Baseddesign technique
All designs went through the same Wafer Fab Process
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U/C 1 Macrocell / Standard Design U/C 2 Macrocell / DOE Based Design
Amp1
LO
Mixer 1
X-band
Ku-band
K-band Amp2
LO
Mixer 2
X-band
Ku-band
K-band
K-Band Up Converter Wafer Probed Results
Presenter
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Both Amp and Mixer were designed using the DFM based tools (DOE and YSH) in the right plot. Again, notice the consistency in the output and the narrow variability which makes the whole design Robust and insensitive to external variations such as temp, voltage supply, bond wires, package effects, etc.. The unique DFM tools in ADS pinpoint all sources of the design problem and allow you to fix them prior to fabrication.
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Amp1 Amp2
DFM based DesignStandard Design
Amp1 Amp2
Wafer Probed ResultsNote: Foundry process shifted to the left during this run. Amp2 shift was less sensitive to this shift
Presenter
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DFM design yields higher performance and more consistent designs with high yield. In the example plot on the right a DFM technique was used where as the plot on the left, a standard design technique was employed. What is very important here is the reduction in both sensitivity and variability in the response. The DFM based design is very consistent and has much lower variability. It is also much less sensitive than the traditional design. Notice that during fabrication of this wafer, the foundry process shifted a bit to the left. The DFM based design resulted in a much lower shift than that of the traditional design, resulting in meeting specs even the foundry process was not stable. The DFM design will also be well immune from changes in voltage supply and from changes in temperature. It really pays off big times to put the time upfront and go through the DFM process in ADS. The outcome will result in a great amount of time and money savings.
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Amp1
Amp2
Understanding the Difference
Presenter
Presentation Notes
Plotting the gain of both amplifiers on the x-axis, one can see the wide variability of Amp 1 as compared to Amp2. Some designers might suggest to design center the Amp1 in order to increase the yield. It is true, but keep in mind that the variability and sensitivity of the design will remain the same. The only way to make the design insensitive to external effects is to design it using the DFM technique and produce these special matching networks topologies that are insensitive to process variation and external influence. ADS features two unique solutions - Design of Experiments (DOE) and Yield Sensitivity Histograms (YSH) – both of which are designed to turn any standard design into a robust one by providing MMIC designers full insight into the circuit and interaction between its elements. The tools pinpoint any sensitive parts and sensitive matching networks in the design that may cause problems in yield. Designers then are able to fix the problems prior to production, resulting in robust, higher yield designs
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ADS Matching Tool Helps find Robust & High Yield Networks
19 different networks with different topologies to choose from They all include
DFM analysis!
Presenter
Presentation Notes
You might now ask how do we find these robust topologies for our MMIC designs? Well, the Impedance Matching tool in ADS will help you get these Robust insensitive matching networks that will help you achieve first pass with high yield. The tool provide many types of different topologies and includes all of the statistical simulation and analysis. What you see in this slide is a picture of this Matching tool and notice how it provides many different topologies to choose from, and all topologies come with their full statistical analysis.
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Yield SensitivityHistogram (YSH)to components
Using DFM Techniques On a Demo One-Stage LNA
Presenter
Presentation Notes
Back to our Ku Band LNA demo example that we started early on during this presentation. We applied the DOE, YSH and sensitivity analysis tools in ADS and fixed our design and transformed it into a much better design. The results of the fixed design is shown next page. And by the way, we have a full workshop lab on this Demo LNA for you to fully understand how to use these tools in ADS.
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Using DFM Techniques to Transform One-Stage LNA into a Robust Design with High Yield
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Before – shown on top After -- shown at the lower half. Notice the variability is much lower now.
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PA Verification
ADS Complete Front-to-Back MMIC Design Flow
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PA Verification to wireless Standards
WIMAX TransmitSource
PA
PA Verification to Wireless Standards Realistic input signals and test benches for all wireless standards
The most accurate and only tool set that provides true circuit verification to all wireless standards pre- and post-fabrication.
Helps designers not only test and verify their designs, but also get the most performance out of their circuits.
Presenter
Presentation Notes
Power Amplifier (PA) verification to wireless standards plays an important role in the MMIC design flow, because verifying large MMIC/RFIC chips to wireless standards, prior to manufacturing, has been a major design flow barrier. Results accuracy" and simulation speed are the two main factors responsible for this barrier. With the ADS Automatic Verification Modeling (AVM) technology and wireless verification solution, this barrier has been eliminated. The ADS Wireless Verification solution uses both realistic input signals and test benches for all wireless standards that are 100% compliant with the wireless standards (for example, WiMAX, UWB and LTE). The process is fully automated and easy to use. Simply insert the amp and simulate. The solution helps designers not only test and verify designs, but also get the best circuit performance. It offers speed increases of up to 100x over traditional methods.
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Insert WiMAX PA into the Wireless Test Bench and press simulate
An Example – WIMAX PA EVM verification and spectrum
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Here is an example of verifying the EVM spec on a WIMAX PA. All I have to do is to insert the PA in the WIMAX test bench and then push on “Simulate” to see the results.
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An Example – WIMAX PA Small signal gain, S11 and Pin/Pout
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This is my circuit level PA with the small signal analysis using the Linear simulator and Large signal analysis using HB. You can see that I have an 18.13 dB gain and my 1-dB compression takes place around an input level of 6 dBm
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Fast verification!
Simulation Time < 20 secondsUsing Fast Cosim (AVM)
Simulation Time 20 minutesFast Cosim (AVM) Not Used
Example – WiMAX PA EVM Verification
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There are two available ways to simulate and extract the results. One way is to simulate the PA at the transistor level with the fully compliant WIMAX source and test bench. This is exactly like having your real PA tested in the lab using the test equipments. Another way is to use the “Automatic Verification Model” (AVM) or “Fast Cosim” to extract a behavioral model of the circuit and run the WIMAX verification in seconds. Notice how close and accurate the AVM fast Cosim results compare with the transistor level verification.
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Example – WiMAX PA Spectrum
Presenter
Presentation Notes
This is the spectral results of the simulation that shows that our PA spectrum is inside the Spec Mask and it indicates that our PA has passed the WIMAX requirement (shown in red)
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Easy Statistical Analysison PA Verificationat the System Level
50 Monte Carlo trials10 minutes – 2GB RAM
Sweeping EVM as afunction of Input Power, Pin
Swept EVM and Statistical Analysis
Presenter
Presentation Notes
You can also verify your PA to all wireless standards with statistical analysis and process variation. What is shown here is an example of how ADS is able to simulate the WIMAX PA with process variations on the lumped elements and with 50 Monte Carlo Trials. The simulation of these 50 trials took about 10 minutes. Also shown here is input power swept analysis for EVM. It displays the EVM versus input power.
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Physical Design
Part IIADS Complete Front-to-Back MMIC Design Flow
Presenter
Presentation Notes
Now that we have successfully created a solid design in the schematic page, we are ready to take it to the next level which is the Physical Design part. Regularly updated foundry device models and layouts are synchronized in both schematic and layout pages. With ADS, it’s easy to create physical designs, either by auto-generating a layout from the schematic via design synchronization or by manually placing the layout artwork. Let me explain all this in detail in the next slides
ADS 2008 Layout• Synchronization• Simulating Layout in
Schematic page• Layout / Schematic Design
Differences• Physical Connectivity
Engine OR “Lay-con”• DRC• Planar and 3D EM Tools
Presenter
Presentation Notes
Accurate Interconnect Analysis Improving interconnect performance and increasing confidence that the manufactured product will function as simulated is crucial in MMIC design. There are many types of physical layout components such as high speed connectors, bond wires, and dielectric bricks that require three-dimensional electromagnetic analysis for any arbitrary geometry. To better address these concerns, the Momentum Planar EM and 3D Electromagnetic Design System (EMDS) simulators are now fully and tightly integrated into ADS 2008 and can be accessed in the same design environment, allowing you to verify the proximity effect of chip area compaction, as well as effects of bond wires and packaging, and then to take corrective action on performance and yield early in the design process.
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Advanced Backend Physical Design Capability Total flexibility with three synchronization modes
• Ability to switch back and forth between the three different modes• Allows you to efficiently and accurately fit many elements designs into small areas.
The result is a smaller die size and lowered overall cost per chip.
ADS provides three different synchronization modes between schematic & layout, providing optimum flexibility in the development of MMICs
Designers are not constrained by always having schematic and layout “automatically synchronized”
Presenter
Presentation Notes
Creating physical designs in ADS is easy. You can Auto-generate a layout from the schematic via design synchronization or by manually placing the layout artwork.� ADS features three different synchronization modes between schematic and layout, providing optimum flexibility in�the development of MMICs. With ADS, you are not constrained by always having the schematic and layout�“automatically synchronized,” which can introduce the risk of unintended MMIC layout modifications. Instead, �ADS gives you the flexibility to choose from three different modes of synchronization:� • Single representation with No Synchronization.�• Dual representation with Half Synchronization.�• Always Automatic Full Design Synchronization between schematic and layout.� You can even switch back and forth between the three different modes while you are laying out the MMIC, allowing you to efficiently and accurately fit designs with many elements into small areas. The result is a smaller die size and lowered overall cost per chip.
Layout look alikeUsed in the schematic page as:• Full or Sub-network• Graphical Cell Compiler with
parameterized variables• Advanced Model Composer with
parameterized variables
Presenter
Presentation Notes
What is shown on this page is an original circuit schematic that was automatically converted to Layout with the Auto Synchronization Layout generation in ADS. Now (in the Layout form), the design can be immediately used for EM Momentum simulation or, as shown on the top right corner, using the Layout Look alike feature, ADS is able to generate a Layout look-alike component of the design and simulate it and optimize it on the schematic page. You can even parameterize any of the design elements and change these parameters on the schematic page in order to see the resulting effects in the simulation results.
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New Transparency to Layer Configuration
Improved layout visibility for multilayer MMIC designs • Easier to see through the multilayer designs such as traces, grounds, and
vias
Before After
Presenter
Presentation Notes
In ADS 2008, a new Transparency to Layer Configuration was added. It allows designers to set the transparency for easier to see multilayer designs such as traces, grounds, and vias
Identifies• Components in Layout not in Schematic• Components in Schematic not in Layout• Parameter Differences• Nodal Mismatches
Presenter
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A new Design Differences Window identifies components in layout not in schematic, components in schematic not in layout, parameter differences, and nodal mismatches. Routing dense lines and elements to fit into a tiny MMIC chip space without incurring design re-spins requires access to good LVS design check tools. ADS can check the layout for errors and verify that the final layout reflects the schematic design and is correct and error-free prior to manufacture. So what is shown here is a window that tells you all this information.
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Custom LVS Utility Program
Advanced Backend Physical Design Capability Check layout vs. schematic and check layout for errors
Presenter
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What is shown above is a custom LVS Utility Program that can be loaded in ADS in seconds. It sums up many of the LVS functionalities and allow designers to check their designs in many ways. The LVS error check function runs very fast, identifies all errors, and reports them on special windows – as shown here.
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Physical Connectivity Engine allows you to check your layout for any errors.
This capacitor is not shorted. It is fine.
This capacitor is shorted. It is shown by the metallization run.
Next Error check tool is the “Physical Connectivity Engine”, referred to as “LayCon”, which stands for Layout Connectivity. “LayCon” allows designers to check if their lines are routed correctly and it checks if there are any unforeseen opens and shorts. An example of this is shown here. The series capacitor was found shorted (by seeing the red trace running through the capacitor. The shunt capacitor is found OK. The trace stops at the top plate of the capacitor and is not shorted. Designer needs to fix the series shorted Capacitor prior to proceeding to fabrication.
Advanced Backend Physical Design Capability Building reticles in ADS – (TriQuint Foundry)
Presenter
Presentation Notes
What is shown on this slide is ADS being used to build complete Foundry Reticles together. These are sample Reticles taken from the TriQuint Foundry, Texas
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Advanced Backend Physical Design Capability EM simulation with Momentum and EMDSSpiral inductors are the largest devices on-chip and probably least understood.
Spiral Inductors, Transformers, and Transmission Lines are important to model accurately in MMIC.
Bond wires and package effects are very important to design to and verify to. Remember, the MMIC doesn’t end at the chip level.
Both Momentum Planar EM simulator and EMDS 3-D finite-element EM simulator are both seamlessly integrated in ADS and can insure your design success.
Presenter
Presentation Notes
Improving interconnect performance and increasing confidence that the manufactured product will function as simulated is crucial in MMIC design. Spiral inductors are the largest devices on-chip and probably least understood. Spiral Inductors, Transformers, and Transmission Lines are important to model accurately in MMIC. Bond wires and package effects are very important to design to and verify to. Remember, the MMIC doesn’t end at the chip level. It has to work and meet the specs in its final environment. Therefore, to better address these concerns, the Momentum Planar EM and 3D Electromagnetic Design System (EMDS) simulators are now fully and tightly integrated into ADS 2008 and can be accessed in the same design environment, allowing you to verify the proximity effect of chip area compaction, as well as effects of bond wires and packaging, and then to take corrective action on performance and yield early in the design process.
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Momentum EM Simulation Accuracy and speed pays off
Industrie’s first 64-bit 3D planar EM solver
Improved thick conductor modeling:Now includes the addition of horizontal current modeling on the metal interconnects sidewalls as well as the vertical currents.
Adding a new Krylov Iterative Solver:Momentum now hosts three unique solvers to address the varying degrees of EM modeling complexity and extend EM modeling efficiencies across a much wider application coverage area.
Presenter
Presentation Notes
The Momentum simulator is the industry’s first 64-bit, 3D planar EM solver, and it includes a new Krylov iterative solver. It hosts three unique solvers to address the varying degrees of EM modeling complexity and extend EM modeling efficiencies across a much wider application coverage area. As a result, you can solve bigger problems, previously not solvable, much faster. The full-wave and quasi-static solvers and adaptive mesh reduction available with Momentum cover EM analysis needs from microwave frequencies down to DC. This is especially important to MMIC designers because it allows fast design explorations without sacrificing accuracy. Momentum also features improved thick-conductor modeling capabilities. Horizontal current modeling on the metal interconnect sidewalls, as well as vertical currents, accurately predict loss or Q calculations at high frequencies. To add, Momentum in ADS 2008 Update 2……
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LNA Layout & Momentum Simulation on the OMN of our one Stage LNA
Presenter
Presentation Notes
Here, back to our Ku band LNA demo example, We took the Output Matching Network (OMN) and performed Momentum simulation on it and simulated the Momentum results along with the rest of the amplifier in order to see the effect of the OMN with its two Spiral inductors.
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Momentum
No Change in NF
Circuit model
LNA Simulation Results with Momentum Simulation on the OMN of LNA
Presenter
Presentation Notes
Notice how Momentum has accurately simulated the gain and output return loss of the output matching network. Notice how our Response now has shifted down in Frequency using Momentum. Therefore it is very important now to bring the result back to its right frequency by using the Momentum Optimization tool in ADS.
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Momentum Optimization on LNA OMN
Presenter
Presentation Notes
Here we are using Momentum Optimization in order to bring the response back to Ku Band. The variables that we want to optimize are chosen, and a Layout-look-alike parameterized component is built automatically and can be used on the schematic page as shown on the next page.
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Meshing during Momentum dimulation and optimization
Output matching metwork parameterized layout look-alike component for EM simulation and optimization
Momentum Optimization on LNA OMN
Presenter
Presentation Notes
Here, you can see the Parameterized Layout look-alike Component being used on the schematic page and is ready to be used for Momentum optimization. As the optimizer runs, it launches Momentum in the background and keep searching for a better optimized solution.
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Results achieved by reduction in linelengths and the series spiral inductor
Momentum Optimized Results
Presenter
Presentation Notes
You can see here how the Momentum Optimizer has brought back the results to the right Ku band frequencies. A second optimization run could be launched to improve the results further and center it around 12 GHz.
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EMDS is now SeamlesslyIntegrated in ADSFollows the Momentum Model
3D Featuresincludes 3DJDEC Bond Wire
EMDS Integration into ADS
Presenter
Presentation Notes
As I said before, just as the planar Momentum simulator is integrated in ADS, the 3D Electromagnetic Design System (EMDS) finite element simulator is also fully and tightly integrated into ADS 2008 and can be accessed in the same design environment, allowing you to verify the proximity effect of chip area compaction, as well as effects of bond wires and packaging, and then to take corrective action on performance and yield early in the design process. EMDS is integrated into ADS. Its features include a 3D viewer and a bond wire modeling capability with JEDEC parameter entry. Momentum and EMDS eliminate the need to leave the design environment to perform EM analysis. With ADS and its integrated EM analysis capabilities, designers can perform full front-to-back design and EM verification all in the ADS environment. After an MMIC is designed, it is packaged and mounted onto a board, and package effects must be considered in the overall design performance. ADS can simulate not only the IC, but also the package and test board as well, so that you can accurately predict in-circuit performance. ADS assures MMIC performance both before and after you insert it into its package and attach input and output wire bonds.
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Advanced 3D EM Simulation with EMDS Co-simulation of a balanced MMIC Amp inside a 10-pin packageEfficient approach to package modeling is to Co-simulate the MMIC circuit design inside the package using EMDS in ADS.
EMDS accurately models package parasitic and its effects on the MMIC Chip Performance.
Co-Simulation / Optimization automatically adjusts the design’s parameters and brings back its performance by counteracting the effect of the package parasitic
Presenter
Presentation Notes
An efficient approach to package modeling is to co-simulate the MMIC circuit design inside the package and then tweak unlocked parameters to achieve best design performance. EMDS accurately models package parasitic and its effects on the MMIC Chip Performance. The process of Co-Simulation and Optimization automatically adjusts the design’s parameters and brings back its performance by counteracting the effect of the package parasitic in the same identical way as what Momentum C0-simulation and optimization did to our LNA to bring it back to meet the specs. For example, the figure shows a MMIC circuit, with embedded layout parasitics, inside of the package on a schematic page readily available for design co-simulation and co-optimization.
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3D View
True MMIC Verification prior to Manufacturing Our LNA Example
True MMIC design verification prior to manufacturing is done by co-simulating the MMIC inside the package and with bond wires using EMDS in ADS
Presenter
Presentation Notes
Back to our LNA demo. Here we have embedded the LNA inside a 3X3 QFN package. The design has been simulated in EMDS and with bond wires attached at the input and output. Let me share with you next the results of the package and bond wires effects on the LNA.
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True MMIC Verification Before Manufacturing
You can co-simulate and optimize theresponse in the same way as in Momentum.
Presenter
Presentation Notes
The dark blue curve shows the original circuit response at Ku Band. The light blue curve shows how the response shift down in frequency when inserted and simulated inside a package. The red curve shows the response of the MMIC inside the package and with bond wires attached at the input and output. We see that the Package and Bond wires affected the results and brought them down in Freq. Now, we can co-simulate the MMIC with the package and Bond wire using EMDS and we can Optimize the design in the same exact way as we did earlier using Momentum. Remember, EMDS is fully integrated in ADS exactly as Momentum is and they both have very similar use models.
DRC - Rapid, Automatic Conformance Check Design Rule Checker (DRC) is a simple, foundry-proven method for rapidly and automatically checking layout conformance to foundry process design rules. ADS features an enhanced version of its DRC tool that allows you to verify that your physical layouts conform to process rules. Now you can find all the errors and their exact x-y coordinate locations easily. You can sort the errors according to name or location to help you fix them. Once you invoke the DRC tool, all you have to do is to load the Rules file then and push on “Run”. What you will get is shown on the next page
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Users now can Load, Run, Compile, and View Results in one mouse click.Users can sort errors and can choose to view any error first.DRC provides exact error coordinates and lets you pan and zoom.
DRC - Rapid, Automatic Conformance Check The output lists all the DRC errors in order with their exact x,y co-ordinates locations. Once you click on an error, the DRC tool pans and zooms on that error and highlights it for a clearer view of that error.
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3D Pre-Viewer with Z-scale Expansion
Scale up substrate thicknesses to easily visualize a complex 3D layout
ADS 3D View Up-scaled View
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Presentation Notes
ADS 3-D EM tool comes with a 3D viewer with many useful features. Allow me to share some of these features with you. This feature (The Z-scale Expansion) allows you to scale and expand your z-axis up and down easier and better visualization of a complex 3 D layout.
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3D Previewer with Cut Plane
• Cut through the layout to easily visualize a complex 3D layout• 3 cut planes on XY, YZ, and XZ plane• Flip Cut – positive or negative cut
No Cut Plane Enabled YZ Cut Plane Enabled
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Presentation Notes
This feature (3D viewer Cut Plane) allows you to cut any of the x, y, or z planes and move them forward and backward in order to see all of the interconnects going through the substrate and inspect if everything is connected the way it is intended.
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New Drag and Drop From Project View Window
Drag and drop existing designs to the current design• Both for Schematic and Layout• Drag and drop designs directly from the Project View window• No need to browse the library browser
Drag and Drop
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2D view
3D view
Trace With Automatic Via Insertion
Easier to change trace layers with hot keys, comma(,) and period(.)
Automatically inserts the via when changing layers.
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Presentation Notes
Trace with Automatic Via Insertion allows you to insert cross traces of different layers over other traces automatically. With the “Period” key and the “comma” key, you can automatically insert the proper via between the specified layers and continue drawing your interconnect microstrip line. In this picture, you can see an example of a line drawn on the “Metal 2” layer crossing a vertical line on the “Metal 1” layer.
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ADS Data Display is Another Design Tool Post Processing and Data Display
RF specific functionality and flexibility to post-process and display data, for better insight to the circuit behavior.
A design tool helps achieve faster design cycles
Presenter
Presentation Notes
Finally, I don’t want to forget to mention the ADS data display. This data display tool is considered by many as another design tool. The Data Display tool in ADS is oriented toward the needs of MMIC designers, and provides flexibility to display the data in many ways that offer the most insight into circuit behavior. Its post processing capabilities allows designers to extract many useful information on the design
