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Fundamentals of LDOs: Part Ib
Jose Silva-Martinez
Department of ECE
Texas A&M University
May 2017
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Outline• Introduction and Motivation• Design Issues
o System Architecture and Challengeso Loop Bandwidth and StabilityoNoise and PSRo Transient ResponseoDigital LDOs
• Summary and Future Work
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Power Management is everywhere
Mobile DevicesMedicalImaging
Sensing and Biometrics
Automotive
AvionicsWearables
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Power Management: Wireless Phones
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Power Management: Automotive
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Power Management: Automotive
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Power Management: Automotive
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Power Management: Automotive
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Applications of LDOs
Power Management of typical cell phone
INTEGRATED PMU
BATTERY CHARGINGUNIT AND CONTROL
3.1V….4.6V
LDO2 LDOn
RF High Voltage
Analog OscillatorsAnalog
LDO1
2.5 V 2.8 V2.8 V
BUCK 1.8 V Digital
Boost10-20 V
LED drivers
LDO1.5 V RF Low
voltage
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Typical Biasing Schemeover 10 LDOs could be needed in large SOCs
Switching Regulator Battery LDO
Regulator
Unregulated 3.1-4.6 V
Regulated noisy 2 V
2V 1.85V 1.85V
Ideal Real
Post regulated 1.85V
Circuit Blocks
Insufficient Filtering (PSR)Switching noise10KHz to 3MHz
1. Increasing switching frequencies in SMPS2. Limited PSR of LDOs at high frequencies
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Understanding Linear Regulators
+-
Error Amp Rf1
Rf2Cout
Z load
Vout
VinVref
Iout
Vout
The LDO is “just” a multi‐stage amplifier, usually three stages! Large DC loop gain is needed to minimize
the error voltage
Gm_in stands for Vin transconductance gain
_
In principle the problem is not quite complex, but the practical requirements are very demanding:
While output current can be >100mA, it is highly desirable to maintain amplifier’s quiescent current in the range of A. (David versus Goliath)
The system must be stable for all current loading conditions { standby till full load}
Excellent voltage accuracy under all possible loading conditions (outstanding load regulation)
Must tolerate large Vin variations while maintaining accurate output (large rejection to supply variations and supply noise)
Very fast reaction to maintain the glitches within 100mV when the loading changes between standby and full loading (Quasi glitch free topology)
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Understanding Linear Regulators
1st stage
Vout
Vout
VRef
Vout
Vin
MP
2nd stage
ZLR1
R2
Gm2Gm1
I L
1st stage
Vout
Vout
VRef
VOut
Vin
MP
2nd stage
ZLR1
R2
Gm2Gm1
Current Budget <1A <1A >100mA
David vs Goliath: Load current is larger than pre‐amplifier
current by 4‐5 orders of magnitude. Width of MP is in the range of 10,000 m
while transistors in preamp are in the order of 10m or less.
Gm2/CP is quite small; pole at low‐medium frequency.
Fast charging of capacitors at the gate of the pass transistor is difficult: IB2/CP .
Vout
VRef
VOut
VinMP
ZLR1
R2
Gm1 Gm2
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Stability Issues
Gain (dB)
f
P1
RHP zero
Load dependentmovement of P2
0
>50
4 poles and a RHP zero. Two most relevant poles move a lot due to load variationsRHP zero is another fact that limits system stabilityESR helps, adding a LHP zero
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Typical loop transfer function: Cap-less LDO
Gain variations can be >10dB for min‐max load variations Dominant Pole at the output of second stage changes by (close to) a decade. Output pole also changes by a decade. Stability is more critical for minimum loading case
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Understanding Linear Regulators
David vs Goliath: continuation The loop shows at least 4 poles in the case of a 3‐stage loop. Although the pole at the output of Gm1 can be placed beyond loop’s unity gain
frequency, the other poles may clash each other. CP changes a lot with load current variations due to miller effects Pole at the output varies a lot due to rdsp variations with load current variations ESR will a zero that helps with loop stabilization RHP zero complicates further loop’s frequency compensation
VoutVin
VOut
MP
RLR1
R2
Gm1 Gm2
r01 C01r02 CP
Ci1CoutBreak
the loop
rdsp
XXXX Re
ImComplex
Plane
ESRzero
Dominant poles
RHPzero
Non-Dominant poles
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Feedback Network
• Medium frequency zero for improving stability• Zero frequency < pole frequency• RF2 << RF1
)//(1
1)()(
211
11
21
2
FFF
FF
FF
F
S
X
RRCsRCs
RRR
sVsv
)//(1
211 FFFf RRC
p 11
1
FFf RC
z
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Understanding Linear Regulators
Noise present in the reference voltage is not attenuated by loop gain.
Actually Vref noise (as well as input referred noise of Gm1) is amplified!
≅
Since current flowing through the gate of the input stage is quite small, then RC filtering is advisable for noise reduction on vn, provided that KT/C is smaller than the integrated noise produced by vn2
Input referred noise of Gm2 is shaped by the gain of the first stage and noise of MP is shaped by first and second amplifiers; overall output referred spot noise is then computed as:
Noisy Voltage reference
≅
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Understanding Linear Regulators: PSR
David vs Goliath: continuation Vin supply is noisy and is coming from a power efficient (yet noisy) switching regulator. The loop must be able to reject the power supply noise, often more than 50dB. Supply noise that appears at the output of the first stage is critical. Noise leakage due to Gm2 may not be very critical. However noise due to Mp may dominate system’s PSR performance.
High gain in the first two stages definitely helps reducing PSR noise Reducing leakage paths is especially effective; e.g. making vgsP=0 for power
supply noise; Vin noise will be injected through rdsP only.
≅
Assuming that each amplification stage shows the supply noise leakage depicted in the figure, then
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Power supply noise: where does it comes from?
2
1 2 1 2
1 1
11
m dsout
fbds ds eddm ds
fb fb L fb fb
e
g rVRr r Av g r sR R Z R R
gsdd
gs p
Cv
C C
High Frequency noise contribution is mainly due to pass transistor
(1 )
gs
gs p
dOL m dd
CC C
i g v
IL
rds
MP Vout
Rfb1
EA-
+
Vref 2
Cgs
CP
3
Rfb2
4
VDD+vdd
Cout
1
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Transient response main issue
0mA Full loadFull load 0mA
Slow and slew rate limited Path
Gate voltage of the pass transistor must be manipulated as quick as possible.Copy VDD noise into the gate of the pass transistor to make Vsg=0; then id=gmvgs=0.
More creative solutions are needed to minimize the effects of Rds! Wider bandwidth and more loop gain helps, but remember David‐Goliath limitations
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Linear Regulators: Transient Response
The load changes from full load to standby conditions in less than 1 sec
Worst case variations: 0Imax and Imax0 in 100nsecs.
Glitches should not exceed 100mV Worst case conditions when loading is
modeled as a current source Pass transistor is in deep subthreshold
region when IL=0 Gate voltage should instantaneously
change by around 1V
Large output compensation capacitor helps, but an additional pin per capacitor is needed.
External Cap‐less solution is more attractive but large glitches result when going from 0Imax
>1.5VDeep triode region
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+-
Error Amp
vgMp
Rf1
Rf2Cout
I load
Vout
vin
VrefID
Cout I load
Vout
ID
Vin
Pass transistor
If the load changes from standby to full load conditions, then Instantaneous current is taken from the capacitor; slope is given by Iload/Cout.
Iload/Cout.=100mA/1F= 100mV/Sec; ID must be close to Iload after 1 SecIload/Cout.=100mA/100pF= 100mV/nSec; ID must be close to Iload after 0.1nSec
Gate capacitance will exceed 10pF; the second stage of error amp must provide current in the range of Iout2 0.5*10‐11/10‐10 =50mA for moving the gate voltage by 500mV in 0.1sSec!
But this is David! Adaptive schemes, class AB (or even class B) solutions, etc.
Linear Regulators: Transient Response
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Cf detects output variations (differentiation) and it indicates how strong the variation is. A fast Class‐B current amplifier increases the current to the levels required to manipulate
Vg into the proper direction. Static power must be minimized but high current must be delivered: Class AB operation,
but very close to class B Loop helps with frequency stabilization since a 2nd loop with 2 poles and 1 LHP zero is
added.
+-
Error Amp Vg
Mp
Rf1
Rf2
Coutiload
Vout
Vin
Vref
iD
Current amplifier
Cf
ifAi if
0Zini C
CG
DifferentiatoroutZ
Load steps force the instantaneous current to flow through or into Cout.
Cf samples the load current variation (in parallel with Cout), then the fast path react immediately if the current amplifier is fast
Linear Regulators: Transient Response
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Compensation Circuitry
M1
Cout
(on-chip load
capacitance
0-100 pF)
Rf
Cf
Mf1Mf2
Rf2
Rf1
ME
Vout
ME
M0eM0eM1
M2M2
M4
M5 M6
Mp
Vref
Vfb
Cf2
Vfb
Error Amplifier
IB1 IB2
Cf3
Circuit Realization: Cap-less LDO
Very symmetric 1st stage due to M2; Fully differential to single ended stage with good PSRR Glitch compensation due to Cf, Rf and other circuitry “Current‐amplifier gain” = Gmf2Rf
Cf3 compensates for parasitic capacitors at gate of Mf1
R. Milliken, TCAS‐I, 2017
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Fast path response: Magnitude and Phase
Magnitude and phase response of the current amplifier Frequency is limited by
pole at the input of the integrator; positive feedback helps increasing this frequency
Decent performance up to 500KHz.
Main pole can be moved to higher frequencies if needed
2nd pole is not an issue
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Loop response: Magnitude and Phase
Loop response Check loop
stability for zero bias current;
In standyconditions, load current should be zero to maximize power savings
Use phase margin as well as gain margin figures
ROOT LOCUS!
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Loop response: Magnitude and Phase
Z1Z2 Pdom
P3
P2P4P6P5
Z3
S-plane
=1
=1
Re
Im
Z1Z2Pdom
P4 P6P5 Z3
S-plane
Re
Im
mA50I:FmA25I:EmA10I:D
mA1I:CA100I:B
A1I:A
out
out
out
out
out
out
A P3
C
DEF
B
A P2
C
DEF
B
Design Issues: Be careful with the pole‐zero constellations; consider zero and full loading Root locus is quite useful
Several poles before zero could be catastrophic RHP zero attracts poles Consider the very worst case
Open loop: Pole‐zero constellation Closed loop: Poles movement as function of
C1R1
+Verror
-
Vref
Vout
V01
gm1 Verror C2R2
V02
gm2 V01 C4R3
Vout
gm3 V01
CL
RESR
ZL
C3
Undesired!desirable!
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Last lesson: Make it as real as possible
Design Issues: IL is in the range {0 – 150mA} DC current in standby should be under 1A High power efficiency, low drop‐out voltage; e.g. Vin‐Vout < 200mV Fast transient response; peak voltages under transient < 100mV Stable under all conditions Small voltage variations when load current changes from 0 up tp Ilmax Minimize the external components: Cap‐less solutions
+
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Digital LDO: Y. Okuma, et.al., CICC‐2010
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Digital LDO: Wen‐Jie Tsou, ISSCC‐2017
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