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© 2006 Microchip Technology Inc. DS51537F
PIC18 CONFIGURATIONSETTINGS ADDENDUM
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS OR WAR-RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,WRITTEN OR ORAL, STATUTORY OR OTHERWISE,RELATED TO THE INFORMATION, INCLUDING BUT NOTLIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,MERCHANTABILITY OR FITNESS FOR PURPOSE.Microchip disclaims all liability arising from this information andits use. Use of Microchip devices in life support and/or safetyapplications is entirely at the buyer’s risk, and the buyer agreesto defend, indemnify and hold harmless Microchip from any andall damages, claims, suits, or expenses resulting from suchuse. No licenses are conveyed, implicitly or otherwise, underany Microchip intellectual property rights.
DS51537F-page ii
Trademarks
The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.
© 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
© 2006 Microchip Technology Inc.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
PIC18 CONFIGURATIONSETTINGS ADDENDUM
© 2006 Microchip Technology Inc. DS51537F-page iii
Table of Contents
PIC18C242............................................................................................................ 1
PIC18C252............................................................................................................ 2
PIC18C442............................................................................................................ 3
PIC18C452............................................................................................................ 4
PIC18C601............................................................................................................ 5
PIC18C658............................................................................................................ 6
PIC18C801............................................................................................................ 7
PIC18C858............................................................................................................ 8
PIC18F1220 .......................................................................................................... 9
PIC18F1230 ........................................................................................................ 11
PIC18F1231 ........................................................................................................ 14
PIC18F1320 ........................................................................................................ 17
PIC18F1330 ........................................................................................................ 20
PIC18F1331 ........................................................................................................ 23
PIC18F2220 ........................................................................................................ 26
PIC18F2221 ........................................................................................................ 29
PIC18F2320 ........................................................................................................ 32
PIC18F2321 ........................................................................................................ 35
PIC18F2331 ........................................................................................................ 38
PIC18F2410 ........................................................................................................ 41
PIC18F242 .......................................................................................................... 44
PIC18F2420 ........................................................................................................ 46
PIC18F2423 ........................................................................................................ 49
PIC18F2431 ........................................................................................................ 52
PIC18F2439 ........................................................................................................ 55
PIC18F2450 ........................................................................................................ 57
PIC18F2455 ........................................................................................................ 61
PIC18F248 .......................................................................................................... 65
PIC18F2480 ........................................................................................................ 67
PIC18F24J10 ...................................................................................................... 70
PIC18F2510 ........................................................................................................ 71
PIC18F2515 ........................................................................................................ 75
PIC18F252 .......................................................................................................... 78
PIC18 Configuration Settings Addendum
DS51537F-page iv © 2006 Microchip Technology Inc.
PIC18F2520 ........................................................................................................ 81
PIC18F2523 ........................................................................................................ 85
PIC18F2525 ........................................................................................................ 88
PIC18F2539 ........................................................................................................ 91
PIC18F2550 ........................................................................................................ 94
PIC18F258 .......................................................................................................... 98
PIC18F2580 ...................................................................................................... 101
PIC18F2585 ...................................................................................................... 104
PIC18F25J10 .................................................................................................... 107
PIC18F25K20.................................................................................................... 109
PIC18F2610 ...................................................................................................... 112
PIC18F2620 ...................................................................................................... 116
PIC18F2680 ...................................................................................................... 119
PIC18F2685 ...................................................................................................... 123
PIC18F4220 ...................................................................................................... 127
PIC18F4221 ...................................................................................................... 130
PIC18F4320 ...................................................................................................... 133
PIC18F4321 ...................................................................................................... 136
PIC18F4331 ...................................................................................................... 139
PIC18F4410 ...................................................................................................... 143
PIC18F442 ........................................................................................................ 146
PIC18F4420 ...................................................................................................... 148
PIC18F4423 ...................................................................................................... 151
PIC18F4431 ...................................................................................................... 154
PIC18F4439 ...................................................................................................... 158
PIC18F4450 ...................................................................................................... 160
PIC18F4455 ...................................................................................................... 163
PIC18F448 ........................................................................................................ 167
PIC18F4480 ...................................................................................................... 169
PIC18F44J10 .................................................................................................... 172
PIC18F4510 ...................................................................................................... 174
PIC18F4515 ...................................................................................................... 178
PIC18F452 ........................................................................................................ 181
PIC18F4520 ...................................................................................................... 184
PIC18F4523 ...................................................................................................... 188
PIC18F4525 ...................................................................................................... 191
PIC18F4539 ...................................................................................................... 194
PIC18F4550 ...................................................................................................... 197
PIC18F458 ........................................................................................................ 201
© 2006 Microchip Technology Inc. DS51537F-page v
PIC18F4580 ...................................................................................................... 204
PIC18F4585 ...................................................................................................... 207
PIC18F45J10 .................................................................................................... 210
PIC18F45K20.................................................................................................... 212
PIC18F4610 ...................................................................................................... 215
PIC18F4620 ...................................................................................................... 219
PIC18F4680 ...................................................................................................... 222
PIC18F4685 ...................................................................................................... 226
PIC18F6310 ...................................................................................................... 230
PIC18F6390 ...................................................................................................... 232
PIC18F63J90 .................................................................................................... 234
PIC18F6410 ...................................................................................................... 235
PIC18F6490 ...................................................................................................... 237
PIC18F64J90 .................................................................................................... 239
PIC18F6520 ...................................................................................................... 241
PIC18F6525 ...................................................................................................... 243
PIC18F6527 ...................................................................................................... 246
PIC18F6585 ...................................................................................................... 250
PIC18F65J10 .................................................................................................... 253
PIC18F65J15 .................................................................................................... 254
PIC18F65J90 .................................................................................................... 255
PIC18F6620 ...................................................................................................... 257
PIC18F6621 ...................................................................................................... 260
PIC18F6622 ...................................................................................................... 263
PIC18F6627 ...................................................................................................... 267
PIC18F6680 ...................................................................................................... 271
PIC18F66J10 .................................................................................................... 274
PIC18F66J15 .................................................................................................... 275
PIC18F66J60 .................................................................................................... 277
PIC18F66J65 .................................................................................................... 278
PIC18F6720 ...................................................................................................... 279
PIC18F6722 ...................................................................................................... 283
PIC18F67J10 .................................................................................................... 288
PIC18F67J60 .................................................................................................... 289
PIC18F8310 ...................................................................................................... 290
PIC18F8390 ...................................................................................................... 293
PIC18F83J90 .................................................................................................... 295
PIC18F8410 ...................................................................................................... 296
PIC18F8490 ...................................................................................................... 299
PIC18 Configuration Settings Addendum
DS51537F-page vi © 2006 Microchip Technology Inc.
PIC18F84J90 .................................................................................................... 301
PIC18F8520 ...................................................................................................... 302
PIC18F8525 ...................................................................................................... 305
PIC18F8527 ...................................................................................................... 308
PIC18F8585 ...................................................................................................... 312
PIC18F85J10 .................................................................................................... 315
PIC18F85J15 .................................................................................................... 317
PIC18F85J90 .................................................................................................... 319
PIC18F8620 ...................................................................................................... 320
PIC18F8621 ...................................................................................................... 323
PIC18F8622 ...................................................................................................... 326
PIC18F8627 ...................................................................................................... 331
PIC18F8680 ...................................................................................................... 336
PIC18F86J10 .................................................................................................... 339
PIC18F86J15 .................................................................................................... 341
PIC18F86J60 .................................................................................................... 343
PIC18F86J65 .................................................................................................... 344
PIC18F8720 ...................................................................................................... 346
PIC18F8722 ...................................................................................................... 350
PIC18F87J10 .................................................................................................... 355
PIC18F87J60 .................................................................................................... 357
PIC18F96J60 .................................................................................................... 358
PIC18F96J65 .................................................................................................... 361
PIC18F97J60 .................................................................................................... 363
PIC18 CONFIGURATIONSETTINGS ADDENDUM
© 2006 Microchip Technology Inc. DS51537F-page 1
Configuration Settings
This addendum lists the configuration settings available for each of the PIC18 devices for use with MPLAB® C18's #pragma config directive and MPASM™ assembler's CONFIG directive.
PIC18C242
Code Protect:
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
CP = ON Enabled
CP = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 2
Watchdog Postscaler:
CCP2 MUX:
Stack Overflow Reset:
PIC18C252
Code Protect:
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
CCP2MUX = OFF Disable (RB3)
CCP2MUX = ON Enable (RC1)
STVR = OFF Disabled
STVR = ON Enabled
CP = ON Enabled
CP = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 3
Watchdog Timer:
Watchdog Postscaler:
CCP2 MUX:
Stack Overflow Reset:
PIC18C442
Code Protect:
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
CCP2MUX = OFF Disable (RB3)
CCP2MUX = ON Enable (RC1)
STVR = OFF Disabled
STVR = ON Enabled
CP = ON Enabled
CP = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 4
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
CCP2 MUX:
Stack Overflow Reset:
PIC18C452
Code Protect:
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
CCP2MUX = OFF Disable (RB3)
CCP2MUX = ON Enable (RC1)
STVR = OFF Disabled
STVR = ON Enabled
CP = ON Enabled
CP = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 5
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
CCP2 MUX:
Stack Overflow Reset:
PIC18C601
Oscillator Selection:
Power-up Timer:
External Bus Data Width:
Watchdog Timer:
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
CCP2MUX = OFF Disable (RB3)
CCP2MUX = ON Enable (RC1)
STVR = OFF Disabled
STVR = ON Enabled
OSC = LP LP Oscillator
OSC = EC EC Oscillator
OSC = HS HS Oscillator
OSC = RC RC Oscillator
PWRT = ON Enable
PWRT = OFF Disable
BW = 8 8-bit External Bus mode
BW = 16 16-bit External Bus mode
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 6
Watchdog Timer Postscale Selection:
Stack Full/Underflow Reset:
PIC18C658
Code Protect:
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
CP = ON Enabled
CP = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 7
Watchdog Postscaler:
Stack Overflow Reset:
PIC18C801
Oscillator Selection:
Power-up Timer:
External Bus Data Width:
Watchdog Timer:
Watchdog Timer Postscale Selection:
Stack Full/Underflow Reset:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
OSC = LP LP Oscillator
OSC = EC EC Oscillator
OSC = HS HS Oscillator
OSC = RC RC Oscillator
PWRT = ON Enable
PWRT = OFF Disable
BW = 8 8-bit External Bus mode
BW = 16 16-bit External Bus mode
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 8
PIC18C858
Code Protect:
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
Stack Overflow Reset:
CP = ON Enabled
CP = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 9
PIC18F1220
Oscillator Selection:
Fail-Safe Clock Monitor:
Internal External Switch Over mode:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = EC External Clock on OSC1, OSC2 as FOSC/4
OSC = ECIO External Clock on OSC1, OSC2 as RA6
OSC = HSPLL HS + PLL
OSC = RCIO External RC on OSC1, OSC2 as RA6
OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6
OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4
OSC = RC External RC on OSC1, OSC2 as FOSC/4
FSCM = OFF Fail-Safe Clock Monitor disabled
FSCM = ON Fail-Safe Clock Monitor enabled
IESO = OFF Internal External Switch Over mode disabled
IESO = ON Internal External Switch Over mode enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 10
Watchdog Postscaler:
MCLR Enable:
Stack Full/Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 11
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F1230
Oscillator Selection:
Fail-Safe Clock Monitor:
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = EC External Clock on OSC1, OSC2 as FOSC/4
OSC = ECIO External Clock on OSC1, OSC2 as RA6
OSC = HSPLL HS + PLL
OSC = RCIO External RC on OSC1, OSC2 as RA6
OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6
OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4
OSC = RC External RC on OSC1, OSC2 as FOSC/4
FSCM = OFF Fail-Safe Clock Monitor disabled
FSCM = ON Fail-Safe Clock Monitor enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 12
Internal External Switch Over mode:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
High-Side Transistors Polarity:
Low-Side Transistors Polarity:
IESO = OFF Internal External Switch Over mode disabled
IESO = ON Internal External Switch Over mode enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
HPOL = LOW Active low
HPOL = HIGH Active high
LPOL = LOW Active low
LPOL = HIGH Active high
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 13
PWM output pins Reset state control:
FLTA MUX Bit:
T1OSC MUX bit:
MCLR Enable:
Stack Overflow Reset Enable Bit:
Dedicated In-Circuit Port Enable Bit:
Boot Block Size Select Bits:
Extended Instruction Set Enable bit:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
PWMPIN = ON Enabled
PWMPIN = OFF Disabled
FLTAMX = RA7 Multiplexed with RA7
FLTAMX = RA5 Multiplexed with RA5
T1OSCMX = LOW T1OSC pins reside on RB2 and RB3
T1OSCMX = HIGH T1OSC pins reside on RA6 and RA7
MCLRE = OFF Disabled
MCLRE = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
ENICPORT = OFF Disabled
ENICPORT = ON Enabled
BBSIZ = BB256 256 W Boot Block Size
BBSIZ = BB512 512 W Boot Block Size
XINST = OFF Disabled
XINST = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 14
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F1231
Oscillator Selection:
Fail-Safe Clock Monitor:
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = EC External Clock on OSC1, OSC2 as FOSC/4
OSC = ECIO External Clock on OSC1, OSC2 as RA6
OSC = HSPLL HS + PLL
OSC = RCIO External RC on OSC1, OSC2 as RA6
OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6
OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4
OSC = RC External RC on OSC1, OSC2 as FOSC/4
FSCM = OFF Fail-Safe Clock Monitor disabled
FSCM = ON Fail-Safe Clock Monitor enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 15
Internal External Switch Over mode:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
High-Side Transistors Polarity:
Low-Side Transistors Polarity:
IESO = OFF Internal External Switch Over mode disabled
IESO = ON Internal External Switch Over mode enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
HPOL = LOW Active low
HPOL = HIGH Active high
LPOL = LOW Active low
LPOL = HIGH Active high
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 16
PWM output pins Reset state control:
FLTA MUX Bit:
T1OSC MUX bit:
MCLR Enable:
Stack Overflow Reset Enable Bit:
Dedicated In-Circuit Port Enable Bit:
Boot Block Size Select Bits:
Extended Instruction Set Enable bit:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
PWMPIN = ON Enabled
PWMPIN = OFF Disabled
FLTAMX = RA7 Multiplexed with RA7
FLTAMX = RA5 Multiplexed with RA5
T1OSCMX = LOW T1OSC pins reside on RB2 and RB3
T1OSCMX = HIGH T1OSC pins reside on RA6 and RA7
MCLRE = OFF Disabled
MCLRE = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
ENICPORT = OFF Disabled
ENICPORT = ON Enabled
BBSIZ = BB256 256 W Boot Block Size
BBSIZ = BB512 512 W Boot Block Size
XINST = OFF Disabled
XINST = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 17
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F1320
Oscillator Selection:
Fail-Safe Clock Monitor:
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = EC External Clock on OSC1, OSC2 as FOSC/4
OSC = ECIO External Clock on OSC1, OSC2 as RA6
OSC = HSPLL HS + PLL
OSC = RCIO External RC on OSC1, OSC2 as RA6
OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6
OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4
OSC = RC External RC on OSC1, OSC2 as FOSC/4
FSCM = OFF Fail-Safe Clock Monitor disabled
FSCM = ON Fail-Safe Clock Monitor enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 18
Internal External Switch Over mode:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
Stack Full/Overflow Reset:
Low Voltage ICSP:
IESO = OFF Internal External Switch Over mode disabled
IESO = ON Internal External Switch Over mode enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 19
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 20
PIC18F1330
Oscillator Selection:
Fail-Safe Clock Monitor:
Internal External Switch Over mode:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = EC External Clock on OSC1, OSC2 as FOSC/4
OSC = ECIO External Clock on OSC1, OSC2 as RA6
OSC = HSPLL HS + PLL
OSC = RCIO External RC on OSC1, OSC2 as RA6
OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6
OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4
OSC = RC External RC on OSC1, OSC2 as FOSC/4
FSCM = OFF Fail-Safe Clock Monitor disabled
FSCM = ON Fail-Safe Clock Monitor enabled
IESO = OFF Internal External Switch Over mode disabled
IESO = ON Internal External Switch Over mode enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 21
Watchdog Postscaler:
High-Side Transistors Polarity:
Low-Side Transistors Polarity:
PWM output pins Reset state control:
FLTA MUX Bit:
T1OSC MUX bit:
MCLR Enable:
Stack Overflow Reset Enable Bit:
Dedicated In-Circuit Port Enable Bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
HPOL = LOW Active low
HPOL = HIGH Active high
LPOL = LOW Active low
LPOL = HIGH Active high
PWMPIN = ON Enabled
PWMPIN = OFF Disabled
FLTAMX = RA7 Multiplexed with RA7
FLTAMX = RA5 Multiplexed with RA5
T1OSCMX = LOW T1OSC pins reside on RB2 and RB3
T1OSCMX = HIGH T1OSC pins reside on RA6 and RA7
MCLRE = OFF Disabled
MCLRE = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
ENICPORT = OFF Disabled
ENICPORT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 22
Boot Block Size Select Bits:
Extended Instruction Set Enable bit:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
BBSIZ = BB256 256 W Boot Block Size
BBSIZ = BB512 512 W Boot Block Size
BBSIZ = BB1K 1 KW Boot Block Size
XINST = OFF Disabled
XINST = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 23
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F1331
Oscillator Selection:
Fail-Safe Clock Monitor:
Internal External Switch Over mode:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = EC External Clock on OSC1, OSC2 as FOSC/4
OSC = ECIO External Clock on OSC1, OSC2 as RA6
OSC = HSPLL HS + PLL
OSC = RCIO External RC on OSC1, OSC2 as RA6
OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6
OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4
OSC = RC External RC on OSC1, OSC2 as FOSC/4
FSCM = OFF Fail-Safe Clock Monitor disabled
FSCM = ON Fail-Safe Clock Monitor enabled
IESO = OFF Internal External Switch Over mode disabled
IESO = ON Internal External Switch Over mode enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 24
Watchdog Postscaler:
High-Side Transistors Polarity:
Low-Side Transistors Polarity:
PWM output pins Reset state control:
FLTA MUX Bit:
T1OSC MUX bit:
MCLR Enable:
Stack Overflow Reset Enable Bit:
Dedicated In-Circuit Port Enable Bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
HPOL = LOW Active low
HPOL = HIGH Active high
LPOL = LOW Active low
LPOL = HIGH Active high
PWMPIN = ON Enabled
PWMPIN = OFF Disabled
FLTAMX = RA7 Multiplexed with RA7
FLTAMX = RA5 Multiplexed with RA5
T1OSCMX = LOW T1OSC pins reside on RB2 and RB3
T1OSCMX = HIGH T1OSC pins reside on RA6 and RA7
MCLRE = OFF Disabled
MCLRE = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
ENICPORT = OFF Disabled
ENICPORT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 25
Boot Block Size Select Bits:
Extended Instruction Set Enable bit:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
BBSIZ = BB256 256 W Boot Block Size
BBSIZ = BB512 512 W Boot Block Size
BBSIZ = BB1K 1 KW Boot Block Size
XINST = OFF Disabled
XINST = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 26
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F2220
Oscillator Selection:
Fail-Safe Clock Monitor:
Internal External Switch Over mode:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = EC External Clock on OSC1, OSC2 as FOSC/4
OSC = ECIO External Clock on OSC1, OSC2 as RA6
OSC = HSPLL HS + PLL
OSC = RCIO External RC on OSC1, OSC2 as RA6
OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6
OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4
OSC = RC External RC on OSC1, OSC2 as FOSC/4
FSCM = OFF Fail-Safe Clock Monitor disabled
FSCM = ON Fail-Safe Clock Monitor enabled
IESO = OFF Internal External Switch Over mode disabled
IESO = ON Internal External Switch Over mode enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 27
Watchdog Postscaler:
MCLR Enable:
PORTB A/D Enable:
CCP2 Pin Function:
Stack Full/Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
PBAD = DIG Digital
PBAD = ANA Analog
CCP2MX = B3 RB3
CCP2MX = OFF RB3
CCP2MX = C1 RC1
CCP2MX = ON RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 28
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 29
PIC18F2221
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO2 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO1 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOR = OFF Brown-out Reset disabled in hardware and software
BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOR = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 30
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Boot Block Size Select bits:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = DIG PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ANA PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = RB3 CCP2 input/output is multiplexed with RB3
CCP2MX = RC1 CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
BBSIZ = BB256 256 Word
BBSIZ = BB512 512 Word
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 31
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Configuration Register Write Protection bit:
Boot Block Write Protection bit:
Data EEPROM Write Protection bit:
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 code-protected
CP0 = OFF Block 0 not code-protected
CP1 = ON Block 1 code-protected
CP1 = OFF Block 1 not code-protected
CPB = ON Boot block code-protected
CPB = OFF Boot block not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 write-protected
WRT0 = OFF Block 0 not write-protected
WRT1 = ON Block 1 write-protected
WRT1 = OFF Block 1 not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTB = ON Boot block write-protected
WRTB = OFF Boot block not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 32
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Boot Block Table Read Protection bit:
PIC18F2320
Oscillator Selection:
Fail-Safe Clock Monitor:
Internal External Switch Over mode:
Power-up Timer:
Brown-out Reset:
EBTR0 = ON Block 0 protected from table reads executed in other blocks
EBTR0 = OFF Block 0 not protected from table reads executed in other blocks
EBTR1 = ON Block 1 protected from table reads executed in other blocks
EBTR1 = OFF Block 1 not protected from table reads executed in other blocks
EBTRB = ON Boot block protected from table reads executed in other blocks
EBTRB = OFF Boot block not protected from table reads executed in other blocks
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = EC External Clock on OSC1, OSC2 as FOSC/4
OSC = ECIO External Clock on OSC1, OSC2 as RA6
OSC = HSPLL HS + PLL
OSC = RCIO External RC on OSC1, OSC2 as RA6
OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6
OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4
OSC = RC External RC on OSC1, OSC2 as FOSC/4
FSCM = OFF Fail-Safe Clock Monitor disabled
FSCM = ON Fail-Safe Clock Monitor enabled
IESO = OFF Internal External Switch Over mode disabled
IESO = ON Internal External Switch Over mode enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 33
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
PORTB A/D Enable:
CCP2 Pin Function:
Stack Full/Overflow Reset:
Low Voltage ICSP:
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
PBAD = DIG Digital
PBAD = ANA Analog
CCP2MX = B3 RB3
CCP2MX = OFF RB3
CCP2MX = C1 RC1
CCP2MX = ON RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 34
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 35
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F2321
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO2 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO1 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 36
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
BOR = OFF Brown-out Reset disabled in hardware and software
BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOR = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = DIG PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ANA PORTB<4:0> pins are configured as analog input channels on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 37
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Boot Block Size Select bits:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
CCP2MX = RB3 CCP2 input/output is multiplexed with RB3
CCP2MX = RC1 CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
BBSIZ = BB256 256 Word
BBSIZ = BB512 512 Word
BBSIZ = BB1K 1024 Word
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 code-protected
CP0 = OFF Block 0 not code-protected
CP1 = ON Block 1 code-protected
CP1 = OFF Block 1 not code-protected
CPB = ON Boot block code-protected
CPB = OFF Boot block not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 write-protected
WRT0 = OFF Block 0 not write-protected
WRT1 = ON Block 1 write-protected
WRT1 = OFF Block 1 not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 38
Configuration Register Write Protection bit:
Boot Block Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Boot Block Table Read Protection bit:
PIC18F2331
Oscillator Selection:
Fail-Safe Clock Monitor Enable:
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTB = ON Boot block write-protected
WRTB = OFF Boot block not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 protected from table reads executed in other blocks
EBTR0 = OFF Block 0 not protected from table reads executed in other blocks
EBTR1 = ON Block 1 protected from table reads executed in other blocks
EBTR1 = OFF Block 1 not protected from table reads executed in other blocks
EBTRB = ON Boot block protected from table reads executed in other blocks
EBTRB = OFF Boot block not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC2 External RC, RA6 is CLKOUT
OSC = EC EC, RA6 is CLKOUT
OSC = ECIO EC, RA6 is I/O
OSC = HSPLL HS-PLL Enabled
OSC = RCIO External RC, RA6 is I/O
OSC = IRCIO Internal RC, RA6 & RA7 are I/O
OSC = IRC Internal RC, RA6 is CLKOUT, RA7 is I/O
OSC = RC1 External RC, RA6 is CLKOUT
OSC = RC External RC, RA6 is CLKOUT
FCMEN = OFF Disabled
FCMEN = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 39
Internal/External Switch-Over:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Timer Enable Window:
Watchdog Postscaler:
Timer1 Oscillator MUX:
High-Side Transistors Polarity:
IESO = OFF Disabled
IESO = ON Enabled
PWRTEN = ON Enabled
PWRTEN = OFF Disabled
BOREN = OFF Disabled
BOREN = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDTEN = OFF Disabled
WDTEN = ON Enabled
WINEN = ON Enabled
WINEN = OFF Disabled
WDPS = 1 1:1
WDPS = 2 1:2
WDPS = 4 1:4
WDPS = 8 1:8
WDPS = 16 1:16
WDPS = 32 1:32
WDPS = 64 1:64
WDPS = 128 1:128
WDPS = 256 1:256
WDPS = 512 1:512
WDPS = 1024 1:1024
WDPS = 2048 1:2048
WDPS = 4096 1:4096
WDPS = 8192 1:8192
WDPS = 16384 1:16384
WDPS = 32768 1:32768
T1OSCMX = OFF Active
T1OSCMX = ON Inactive
HPOL = LOW Active low
HPOL = HIGH Active high
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 40
Low-Side Transistors Polarity:
PWM output pins Reset state control:
MCLR Enable:
Stack Overflow Reset:
Low Voltage Programming:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
LPOL = LOW Active low
LPOL = HIGH Active high
PWMPIN = ON Enabled
PWMPIN = OFF Disabled
MCLRE = OFF Disabled
MCLRE = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 41
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F2410
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 42
Brown-out Reset Enable bits:
Brown-out Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF MCLR pin enabled; RE3 input pin disabled
MCLRE = ON RE3 input pin enabled; MCLR disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 43
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Boot Block Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 44
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Boot Block Table Read Protection bit:
PIC18F242
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 45
Watchdog Postscaler:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
CCP2MUX = OFF Disable (RB3)
CCP2MUX = ON Enable (RC1)
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 46
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F2420
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 47
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 48
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Boot Block Write Protection bit:
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 49
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Boot Block Table Read Protection bit:
PIC18F2423
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 50
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 51
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Low Voltage ICSP:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection bit:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = PORTB CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Disabled
LVP = ON Enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 52
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection bit:
PIC18F2431
Oscillator Selection:
Fail-Safe Clock Monitor Enable:
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC2 External RC, RA6 is CLKOUT
OSC = EC EC, RA6 is CLKOUT
OSC = ECIO EC, RA6 is I/O
OSC = HSPLL HS-PLL Enabled
OSC = RCIO External RC, RA6 is I/O
OSC = IRCIO Internal RC, RA6 & RA7 are I/O
OSC = IRC Internal RC, RA6 is CLKOUT, RA7 is I/O
OSC = RC1 External RC, RA6 is CLKOUT
OSC = RC External RC, RA6 is CLKOUT
FCMEN = OFF Disabled
FCMEN = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 53
Internal/External Switch-Over:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Timer Enable Window:
Watchdog Postscaler:
Timer1 Oscillator MUX:
High-Side Transistors Polarity:
IESO = OFF Disabled
IESO = ON Enabled
PWRTEN = ON Enabled
PWRTEN = OFF Disabled
BOREN = OFF Disabled
BOREN = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDTEN = OFF Disabled
WDTEN = ON Enabled
WINEN = ON Enabled
WINEN = OFF Disabled
WDPS = 1 1:1
WDPS = 2 1:2
WDPS = 4 1:4
WDPS = 8 1:8
WDPS = 16 1:16
WDPS = 32 1:32
WDPS = 64 1:64
WDPS = 128 1:128
WDPS = 256 1:256
WDPS = 512 1:512
WDPS = 1024 1:1024
WDPS = 2048 1:2048
WDPS = 4096 1:4096
WDPS = 8192 1:8192
WDPS = 16384 1:16384
WDPS = 32768 1:32768
T1OSCMX = OFF Active
T1OSCMX = ON Inactive
HPOL = LOW Active low
HPOL = HIGH Active high
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 54
Low-Side Transistors Polarity:
PWM output pins Reset state control:
MCLR Enable:
Stack Overflow Reset:
Low Voltage Programming:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
LPOL = LOW Active low
LPOL = HIGH Active high
PWMPIN = ON Enabled
PWMPIN = OFF Disabled
MCLRE = OFF Disabled
MCLRE = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 55
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F2439
Oscillator Selection:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 56
Watchdog Postscaler:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 57
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F2450
96 MHz PLL Prescaler:
CPU System Clock Postscaler:
Full-Speed USB Clock Source Selection:
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
PLLDIV = 1 No divide (4 MHz input)
PLLDIV = 2 Divide by 2 (8 MHz input)
PLLDIV = 3 Divide by 3 (12 MHz input)
PLLDIV = 4 Divide by 4 (16 MHz input)
PLLDIV = 5 Divide by 5 (20 MHz input)
PLLDIV = 6 Divide by 6 (24 MHz input)
PLLDIV = 10 Divide by 10 (40 MHz input)
PLLDIV = 12 Divide by 12 (48 MHz input)
CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
USBDIV = 1 Clock source from OSC1/OSC2
USBDIV = 2 Clock source from 96 MHz PLL/2
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 58
Oscillator Selection bits:
Fail-Safe Clock Monitor:
Internal/External Switch Over:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
USB Voltage Regulator Enable:
Watchdog Timer:
FOSC = XT_XT XT oscillator, XT used by USB
FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB
FOSC = ECIO_EC External clock, port function on RA6, EC used by USB
FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB
FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB
FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB
FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB
FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB
FOSC = INTOSC_XT Internal oscillator, XT used by USB
FOSC = INTOSC_HS Internal oscillator, HS used by USB
FOSC = HS HS oscillator, HS used by USB
FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB
FCMEM = OFF Disabled
FCMEM = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = SOFT Controlled by SBOREN
BOR = ON_ACTIVE Enabled when the device is not in Sleep, SBOREN bit is disabled
BOR = ON Enabled, SBOREN bit is disabled
BORV = 46 4.6V
BORV = 43 4.3V
BORV = 28 2.8V
BORV = 21 2.1V
VREGEN = OFF Disabled
VREGEN = ON Enabled
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 59
Watchdog Postscaler:
MCLR Enable:
Low Power Timer1 Oscillator Enable:
PORTB A/D Enable:
Stack Overflow Reset:
Low Voltage ICSP:
Boot Block Size Select Bit:
Dedicated In-Circuit Debug/Programming Enable:
Extended Instruction Set Enable:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Timer1 oscillator configured for high power
LPT1OSC = ON Timer1 oscillator configured for low power
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input on Reset
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
BBSIZ = BB2K 2KW Boot Block Size
BBSIZ = BB1K 1KW Boot Block Size
ICPRT = OFF Disabled
ICPRT = ON Enabled
XINST = OFF Disabled
XINST = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 60
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 61
PIC18F2455
PLL Prescaler Selection bits:
CPU System Clock Postscaler:
USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1):
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly)
PLLDIV = 2 Divide by 2 (8 MHz oscillator input)
PLLDIV = 3 Divide by 3 (12 MHz oscillator input)
PLLDIV = 4 Divide by 4 (16 MHz oscillator input)
PLLDIV = 5 Divide by 5 (20 MHz oscillator input)
PLLDIV = 6 Divide by 6 (24 MHz oscillator input)
PLLDIV = 10 Divide by 10 (40 MHz oscillator input)
PLLDIV = 12 Divide by 12 (48 MHz oscillator input)
CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale
USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2
FOSC = XT_XT XT oscillator, XT used by USB
FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB
FOSC = ECIO_EC External clock, port function on RA6, EC used by USB
FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB
FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB
FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB
FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB
FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB
FOSC = INTOSC_XT Internal oscillator, XT used by USB
FOSC = INTOSC_HS Internal oscillator, HS used by USB
FOSC = HS HS oscillator, HS used by USB
FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB
FCMEM = OFF Fail-Safe Clock Monitor disabled
FCMEM = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 62
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
USB Voltage Regulator Enable bit:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOR = OFF Brown-out Reset disabled in hardware and software
BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
VREGEN = OFF USB voltage regulator disabled
VREGEN = ON USB voltage regulator enabled
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 63
Low-Power Timer 1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = OFF CCP2 input/output is multiplexed with RB3
CCP2MX = ON CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CP2 = ON Block 2 (004000-005FFFh) code-protected
CP2 = OFF Block 2 (004000-005FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 64
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Boot Block Table Read Protection:
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRT2 = ON Block 2 (004000-005FFFh) write-protected
WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
WRTB = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTB = OFF Configuration registers (300000-3000FFh) not write-protected
WRTC = ON Boot block (000000-0007FFh) write-protected
WRTC = OFF Boot block (000000-0007FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 65
PIC18F248
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
Stack Overflow Reset:
Low Voltage ICSP:
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 66
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 67
PIC18F2480
Oscillator Selection bits:
Fail-Safe Clock Monitor:
Internal External Osc. Switch:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC External RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO External RC with OSC2 as RA6
OSC = IRCIO67 Internal RC with OSC2 as RA6 and OSC1 as RA7
OSC = IRCIO7 Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out
OSC = ERC1 External RC with OSC2 as divide by 4 clock out
OSC = ERC External RC with OSC2 as divide by 4 clock out
FCMENB = OFF Disabled
FCMENB = ON Enabled
IESOB = OFF Disabled
IESOB = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 68
Watchdog Postscaler:
MCLR Enable:
Low Power Timer1 Oscillator:
PORTB Pins Configured for A/D:
BackGround Debug:
Extended Instruction Set CPU:
Boot Block Size:
Low Voltage Programming:
Stack Overflow/Underflow Reset:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Timer1 Low Power Oscillator Disabled
LPT1OSC = ON Timer1 Low Power Oscillator Active
PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset
PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
BBSIZ = 1024 1K words (2K bytes) Boot Block
BBSIZ = 2048 2K words (4K bytes) Boot Block
LVP = OFF Disabled
LVP = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 69
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 70
PIC18F24J10
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLKO function on OSC2
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 71
Watchdog Timer Postscale Select bits:
CCP2 MUX bit:
PIC18F2510
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE CCP2 is multiplexed with RB3
CCP2MX = DEFAULT CCP2 is multiplexed with RC1
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 72
Brown-out Reset Enable bits:
Brown-out Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF MCLR pin enabled; RE3 input pin disabled
MCLRE = ON RE3 input pin enabled; MCLR disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 73
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
Boot Block Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CP2 = ON Block 2 (004000-005FFFh) code-protected
CP2 = OFF Block 2 (004000-005FFFh) not code-protected
CP3 = ON Block 3 (006000-007FFFh) code-protected
CP3 = OFF Block 3 (006000-007FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 74
Write Protection bit Block 2:
Write Protection bit Block 3:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Boot Block Table Read Protection bit:
WRT2 = ON Block 2 (004000-005FFFh) write-protected
WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
WRT3 = ON Block 3 (006000-007FFFh) write-protected
WRT3 = OFF Block 3 (006000-007FFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 75
PIC18F2515
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 76
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF MCLR pin enabled; RE3 input pin disabled
MCLRE = ON RE3 input pin enabled; MCLR disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 77
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Boot Block Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Table Read Protection bit Block 0:
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-003FFFh) code-protected
CP0 = OFF Block 0 (000800-003FFFh) not code-protected
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
WRT0 = ON Block 0 (000800-003FFFh) write-protected
WRT0 = OFF Block 0 (000800-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 78
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Boot Block Table Read Protection bit:
PIC18F252
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 79
Watchdog Postscaler:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
CCP2MUX = OFF Disable (RB3)
CCP2MUX = ON Enable (RC1)
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 80
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 81
PIC18F2520
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 82
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 83
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Write Protection bit Block 3:
Boot Block Write Protection bit:
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CP2 = ON Block 2 (004000-005FFFh) code-protected
CP2 = OFF Block 2 (004000-005FFFh) not code-protected
CP3 = ON Block 3 (006000-007FFFh) code-protected
CP3 = OFF Block 3 (006000-007FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRT2 = ON Block 2 (004000-005FFFh) write-protected
WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
WRT3 = ON Block 3 (006000-007FFFh) write-protected
WRT3 = OFF Block 3 (006000-007FFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 84
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Boot Block Table Read Protection bit:
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 85
PIC18F2523
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 86
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Low Voltage ICSP:
Extended Instruction Set Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = PORTB CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Disabled
LVP = ON Enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 87
Background Debugger Enable bit:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection bit:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection bit:
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CP2 = ON Block 2 (004000-005FFFh) code-protected
CP2 = OFF Block 2 (004000-005FFFh) not code-protected
CP3 = ON Block 3 (006000-007FFFh) code-protected
CP3 = OFF Block 3 (006000-007FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRT2 = ON Block 2 (004000-005FFFh) write-protected
WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
WRT3 = ON Block 3 (006000-007FFFh) write-protected
WRT3 = OFF Block 3 (006000-007FFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 88
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection bit:
PIC18F2525
Oscillator Selection:
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO6 EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO6 RC-OSC2 as RA6
OSC = INTIO67 INTRC-OSC2 as RA6, OSC1 as RA7
OSC = INTIO7 INTRC-OSC2 as Clock Out, OSC1 as RA7
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 89
Fail-Safe Clock Monitor:
Internal External Osc. Switch Over:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOREN = OFF Disabled
BOREN = ON SBOREN Enabled
BOREN = NOSLP Enabled except Sleep, SBOREN Disabled
BOREN = SBORDIS Enabled, SBOREN Disabled
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 90
T1 Oscillator Enable:
PORTB A/D Enable:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
XINST Enable:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
LPT1OSC = OFF Disabled
LPT1OSC = ON Enabled
PBADEN = OFF PORTB<4:0> digital on Reset
PBADEN = ON PORTB<4:0> analog on Reset
CCP2MX = PORTBE Multiplexed with RB3
CCP2MX = PORTC Multiplexed with RC1
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
XINST = OFF Disabled
XINST = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 91
Write Protection Block 1:
Write Protection Block 2:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Boot Block Table Read Protection:
PIC18F2539
Oscillator Selection:
Power-up Timer:
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
PWRT = ON Enabled
PWRT = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 92
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Boot Block Code Protection:
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 93
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Boot Block Table Read Protection:
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 94
PIC18F2550
PLL Prescaler Selection bits:
CPU System Clock Postscaler:
USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1):
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly)
PLLDIV = 2 Divide by 2 (8 MHz oscillator input)
PLLDIV = 3 Divide by 3 (12 MHz oscillator input)
PLLDIV = 4 Divide by 4 (16 MHz oscillator input)
PLLDIV = 5 Divide by 5 (20 MHz oscillator input)
PLLDIV = 6 Divide by 6 (24 MHz oscillator input)
PLLDIV = 10 Divide by 10 (40 MHz oscillator input)
PLLDIV = 12 Divide by 12 (48 MHz oscillator input)
CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale
USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2
FOSC = XT_XT XT oscillator, XT used by USB
FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB
FOSC = ECIO_EC External clock, port function on RA6, EC used by USB
FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB
FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB
FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB
FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB
FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB
FOSC = INTOSC_XT Internal oscillator, XT used by USB
FOSC = INTOSC_HS Internal oscillator, HS used by USB
FOSC = HS HS oscillator, HS used by USB
FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB
FCMEM = OFF Fail-Safe Clock Monitor disabled
FCMEM = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 95
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
USB Voltage Regulator Enable bit:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOR = OFF Brown-out Reset disabled in hardware and software
BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
VREGEN = OFF USB voltage regulator disabled
VREGEN = ON USB voltage regulator enabled
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 96
Low-Power Timer 1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
Boot Block Code Protection bit:
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = OFF CCP2 input/output is multiplexed with RB3
CCP2MX = ON CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CP2 = ON Block 2 (004000-005FFFh) code-protected
CP2 = OFF Block 2 (004000-005FFFh) not code-protected
CP3 = ON Block 3 (006000-007FFFh) code-protected
CP3 = OFF Block 3 (006000-007FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 97
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Write Protection bit Block 3:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRT2 = ON Block 2 (004000-005FFFh) write-protected
WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
WRT3 = ON Block 3 (006000-007FFFh) write-protected
WRT3 = OFF Block 3 (006000-007FFFh) not write-protected
WRTB = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTB = OFF Configuration registers (300000-3000FFh) not write-protected
WRTC = ON Boot block (000000-0007FFh) write-protected
WRTC = OFF Boot block (000000-0007FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 98
Table Read Protection bit Block 3:
Boot Block Table Read Protection:
PIC18F258
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 99
Watchdog Postscaler:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 100
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 101
PIC18F2580
Oscillator Selection bits:
Fail-Safe Clock Monitor:
Internal External Osc. Switch:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC External RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO External RC with OSC2 as RA6
OSC = IRCIO67 Internal RC with OSC2 as RA6 and OSC1 as RA7
OSC = IRCIO7 Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out
OSC = ERC1 External RC with OSC2 as divide by 4 clock out
OSC = ERC External RC with OSC2 as divide by 4 clock out
FCMENB = OFF Disabled
FCMENB = ON Enabled
IESOB = OFF Disabled
IESOB = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 102
Watchdog Postscaler:
MCLR Enable:
Low Power Timer1 Oscillator:
PORTB Pins Configured for A/D:
BackGround Debug:
Extended Instruction Set CPU:
Boot Block Size:
Low Voltage Programming:
Stack Overflow/Underflow Reset:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Timer1 Low Power Oscillator Disabled
LPT1OSC = ON Timer1 Low Power Oscillator Active
PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset
PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
BBSIZ = 1024 1K words (2K bytes) Boot Block
BBSIZ = 2048 2K words (4K bytes) Boot Block
LVP = OFF Disabled
LVP = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 103
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 104
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F2585
Oscillator Selection bits:
Fail-Safe Clock Monitor:
Internal External Osc. Switch:
Power-up Timer:
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC External RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO External RC with OSC2 as RA6
OSC = IRCIO67 Internal RC with OSC2 as RA6 and OSC1 as RA7
OSC = IRCIO7 Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out
OSC = ERC1 External RC with OSC2 as divide by 4 clock out
OSC = ERC External RC with OSC2 as divide by 4 clock out
FCMENB = OFF Disabled
FCMENB = ON Enabled
IESOB = OFF Disabled
IESOB = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 105
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
Low Power Timer1 Oscillator:
PORTB Pins Configured for A/D:
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Timer1 Low Power Oscillator Disabled
LPT1OSC = ON Timer1 Low Power Oscillator Active
PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset
PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 106
BackGround Debug:
Extended Instruction Set CPU:
Boot Block Size:
Low Voltage Programming:
Stack Overflow/Underflow Reset:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
BBSIZ = 1024 1K words (2K bytes) Boot Block
BBSIZ = 2048 2K words (4K bytes) Boot Block
BBSIZ = 4096 4K words (8K bytes) Boot Block
LVP = OFF Disabled
LVP = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 107
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F25J10
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 108
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
Watchdog Timer Postscale Select bits:
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLKO function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 109
CCP2 MUX bit:
PIC18F25K20
Oscillator Selection:
Fail Safe Clock Monitor:
Internal External Osc. Switch Over:
Power Up Timer:
Brown Out Reset:
Brown Out Voltage:
Watchdog Timer:
CCP2MX = ALTERNATE CCP2 is multiplexed with RB3
CCP2MX = DEFAULT CCP2 is multiplexed with RC1
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO6 EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO6 RC-OSC2 as RA6
OSC = INTIO67 INTRC-OSC2 as RA6, OSC1 as RA7
OSC = INTIO7 INTRC-OSC2 as Clock Out, OSC1 as RA7
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOREN = OFF Disabled
BOREN = ON SBOREN Enabled
BOREN = NOSLP Enabled except SLEEP, SBOREN Disabled
BOREN = SBORDIS Enabled, SBOREN Disabled
BORV = 46 3.0V
BORV = 43 2.7V
BORV = 28 2.2V
BORV = 21 1.8
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 110
Watchdog Postscaler:
MCLR Enable:
T1 Oscillator Enable:
Port B A/D Enable:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
XINST Enable:
Background Debugger Enable:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Disabled
LPT1OSC = ON Enabled
PBADEN = OFF Port B<4:0> digital on RESET
PBADEN = ON Port B<4:0> analog on RESET
CCP2MX = PORTBE Multiplexed with RB3
CCP2MX = PORTC Multiplexed with RC1
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
XINST = OFF Disabled
XINST = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 111
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 112
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F2610
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 113
Brown-out Reset Enable bits:
Brown-out Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF MCLR pin enabled; RE3 input pin disabled
MCLRE = ON RE3 input pin enabled; MCLR disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 114
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
Boot Block Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-003FFFh) code-protected
CP0 = OFF Block 0 (000800-003FFFh) not code-protected
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
CP3 = ON Block 3 (00C000-00FFFFh) code-protected
CP3 = OFF Block 3 (00C000-00FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
WRT0 = ON Block 0 (000800-003FFFh) write-protected
WRT0 = OFF Block 0 (000800-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 115
Write Protection bit Block 2:
Write Protection bit Block 3:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Boot Block Table Read Protection bit:
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
WRT3 = ON Block 3 (00C000-00FFFFh) write-protected
WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 116
PIC18F2620
Oscillator Selection:
Fail-Safe Clock Monitor:
Internal External Osc. Switch Over:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO6 EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO6 RC-OSC2 as RA6
OSC = INTIO67 INTRC-OSC2 as RA6, OSC1 as RA7
OSC = INTIO7 INTRC-OSC2 as Clock Out, OSC1 as RA7
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOREN = OFF Disabled
BOREN = ON SBOREN Enabled
BOREN = NOSLP Enabled except Sleep, SBOREN Disabled
BOREN = SBORDIS Enabled, SBOREN Disabled
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 117
Watchdog Postscaler:
MCLR Enable:
T1 Oscillator Enable:
PORTB A/D Enable:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
XINST Enable:
Background Debugger Enable:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Disabled
LPT1OSC = ON Enabled
PBADEN = OFF PORTB<4:0> digital on Reset
PBADEN = ON PORTB<4:0> analog on Reset
CCP2MX = PORTBE Multiplexed with RB3
CCP2MX = PORTC Multiplexed with RC1
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
XINST = OFF Disabled
XINST = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 118
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 119
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F2680
Oscillator Selection bits:
Fail-Safe Clock Monitor:
Internal External Osc. Switch:
Power-up Timer:
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC External RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO External RC with OSC2 as RA6
OSC = IRCIO67 Internal RC with OSC2 as RA6 and OSC1 as RA7
OSC = IRCIO7 Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out
OSC = ERC1 External RC with OSC2 as divide by 4 clock out
OSC = ERC External RC with OSC2 as divide by 4 clock out
FCMENB = OFF Disabled
FCMENB = ON Enabled
IESOB = OFF Disabled
IESOB = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 120
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
Low Power Timer1 Oscillator:
PORTB Pins Configured for A/D:
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Timer1 Low Power Oscillator Disabled
LPT1OSC = ON Timer1 Low Power Oscillator Active
PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset
PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 121
BackGround Debug:
Extended Instruction Set CPU:
Boot Block Size:
Low Voltage Programming:
Stack Overflow/Underflow Reset:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
BBSIZ = 1024 1K words (2K bytes) Boot Block
BBSIZ = 2048 2K words (4K bytes) Boot Block
BBSIZ = 4096 4K words (8K bytes) Boot Block
LVP = OFF Disabled
LVP = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 122
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 123
PIC18F2685
Oscillator Selection bits:
Fail-Safe Clock Monitor:
Internal External Osc. Switch:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC External RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO External RC with OSC2 as RA6
OSC = IRCIO67 Internal RC with OSC2 as RA6 and OSC1 as RA7
OSC = IRCIO7 Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out
OSC = ERC1 External RC with OSC2 as divide by 4 clock out
OSC = ERC External RC with OSC2 as divide by 4 clock out
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOREN = OFF Disabled
BOREN = SBORENCTRL Controlled by SBOREN
BOREN = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOREN = BOHW Enabled in HW, SBOREN Disabled
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 124
Watchdog Postscaler:
MCLR Enable:
Low Power Timer1 Oscillator:
PORTB Pins Configured for A/D:
BackGround Debug:
Extended Instruction Set CPU:
Boot Block Size:
Low Voltage Programming:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Disabled
LPT1OSC = ON Enabled
PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset
PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
BBSIZ = 1024 1K words (2K bytes) Boot Block
BBSIZ = 2048 2K words (4K bytes) Boot Block
BBSIZ = 4096 4K words (8K bytes) Boot Block
LVP = OFF Disabled
LVP = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 125
Stack Overflow/Underflow Reset:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Code Protection Block 4:
Code Protection Block 5:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
STVREN = OFF Disabled
STVREN = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CP4 = ON Enabled
CP4 = OFF Disabled
CP5 = ON Enabled
CP5 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 126
Write Protection Block 4:
Write Protection Block 5:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Table Read Protection Block 4:
Table Read Protection Block 5:
Boot Block Table Read Protection:
WRT4 = ON Enabled
WRT4 = OFF Disabled
WRT5 = ON Enabled
WRT5 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTR4 = ON Enabled
EBTR4 = OFF Disabled
EBTR5 = ON Enabled
EBTR5 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 127
PIC18F4220
Oscillator Selection:
Fail-Safe Clock Monitor:
Internal External Switch Over mode:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = EC External Clock on OSC1, OSC2 as FOSC/4
OSC = ECIO External Clock on OSC1, OSC2 as RA6
OSC = HSPLL HS + PLL
OSC = RCIO External RC on OSC1, OSC2 as RA6
OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6
OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4
OSC = RC External RC on OSC1, OSC2 as FOSC/4
FSCM = OFF Fail-Safe Clock Monitor disabled
FSCM = ON Fail-Safe Clock Monitor enabled
IESO = OFF Internal External Switch Over mode disabled
IESO = ON Internal External Switch Over mode enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 128
Watchdog Postscaler:
MCLR Enable:
PORTB A/D Enable:
CCP2 Pin Function:
Stack Full/Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
PBAD = DIG Digital
PBAD = ANA Analog
CCP2MX = B3 RB3
CCP2MX = OFF RB3
CCP2MX = C1 RC1
CCP2MX = ON RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 129
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 130
PIC18F4221
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO2 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO1 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOR = OFF Brown-out Reset disabled in hardware and software
BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOR = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 131
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit:
Boot Block Size Select bits:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = DIG PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ANA PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = RB3 CCP2 input/output is multiplexed with RB3
CCP2MX = RC1 CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
ICPORT = OFF ICPORT disabled
ICPORT = ON ICPORT enabled
BBSIZ = BB256 256 Word
BBSIZ = BB512 512 Word
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 132
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Configuration Register Write Protection bit:
Boot Block Write Protection bit:
Data EEPROM Write Protection bit:
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 code-protected
CP0 = OFF Block 0 not code-protected
CP1 = ON Block 1 code-protected
CP1 = OFF Block 1 not code-protected
CPB = ON Boot block code-protected
CPB = OFF Boot block not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 write-protected
WRT0 = OFF Block 0 not write-protected
WRT1 = ON Block 1 write-protected
WRT1 = OFF Block 1 not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTB = ON Boot block write-protected
WRTB = OFF Boot block not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 133
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Boot Block Table Read Protection bit:
PIC18F4320
Oscillator Selection:
Fail-Safe Clock Monitor:
Internal External Switch Over mode:
Power-up Timer:
Brown-out Reset:
EBTR0 = ON Block 0 protected from table reads executed in other blocks
EBTR0 = OFF Block 0 not protected from table reads executed in other blocks
EBTR1 = ON Block 1 protected from table reads executed in other blocks
EBTR1 = OFF Block 1 not protected from table reads executed in other blocks
EBTRB = ON Boot block protected from table reads executed in other blocks
EBTRB = OFF Boot block not protected from table reads executed in other blocks
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = EC External Clock on OSC1, OSC2 as FOSC/4
OSC = ECIO External Clock on OSC1, OSC2 as RA6
OSC = HSPLL HS + PLL
OSC = RCIO External RC on OSC1, OSC2 as RA6
OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6
OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4
OSC = RC External RC on OSC1, OSC2 as FOSC/4
FSCM = OFF Fail-Safe Clock Monitor disabled
FSCM = ON Fail-Safe Clock Monitor enabled
IESO = OFF Internal External Switch Over mode disabled
IESO = ON Internal External Switch Over mode enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 134
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
PORTB A/D Enable:
CCP2 Pin Function:
Stack Full/Overflow Reset:
Low Voltage ICSP:
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
PBAD = DIG Digital
PBAD = ANA Analog
CCP2MX = B3 RB3
CCP2MX = OFF RB3
CCP2MX = C1 RC1
CCP2MX = ON RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 135
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 136
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F4321
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO2 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO1 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 137
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
BOR = OFF Brown-out Reset disabled in hardware and software
BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOR = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = DIG PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ANA PORTB<4:0> pins are configured as analog input channels on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 138
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit:
Boot Block Size Select bits:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
CCP2MX = RB3 CCP2 input/output is multiplexed with RB3
CCP2MX = RC1 CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
ICPORT = OFF ICPORT disabled
ICPORT = ON ICPORT enabled
BBSIZ = BB256 256 Word
BBSIZ = BB512 512 Word
BBSIZ = BB1K 1024 Word
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 code-protected
CP0 = OFF Block 0 not code-protected
CP1 = ON Block 1 code-protected
CP1 = OFF Block 1 not code-protected
CPB = ON Boot block code-protected
CPB = OFF Boot block not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 write-protected
WRT0 = OFF Block 0 not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 139
Write Protection bit Block 1:
Configuration Register Write Protection bit:
Boot Block Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Boot Block Table Read Protection bit:
PIC18F4331
Oscillator Selection:
WRT1 = ON Block 1 write-protected
WRT1 = OFF Block 1 not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTB = ON Boot block write-protected
WRTB = OFF Boot block not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 protected from table reads executed in other blocks
EBTR0 = OFF Block 0 not protected from table reads executed in other blocks
EBTR1 = ON Block 1 protected from table reads executed in other blocks
EBTR1 = OFF Block 1 not protected from table reads executed in other blocks
EBTRB = ON Boot block protected from table reads executed in other blocks
EBTRB = OFF Boot block not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC2 External RC, RA6 is CLKOUT
OSC = EC EC, RA6 is CLKOUT
OSC = ECIO EC, RA6 is I/O
OSC = HSPLL HS-PLL Enabled
OSC = RCIO External RC, RA6 is I/O
OSC = IRCIO Internal RC, RA6 & RA7 are I/O
OSC = IRC Internal RC, RA6 is CLKOUT, RA7 is I/O
OSC = RC1 External RC, RA6 is CLKOUT
OSC = RC External RC, RA6 is CLKOUT
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 140
Fail-Safe Clock Monitor Enable:
Internal/External Switch-Over:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Timer Enable Window:
Watchdog Postscaler:
Timer1 Oscillator MUX:
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
PWRTEN = ON Enabled
PWRTEN = OFF Disabled
BOREN = OFF Disabled
BOREN = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDTEN = OFF Disabled
WDTEN = ON Enabled
WINEN = ON Enabled
WINEN = OFF Disabled
WDPS = 1 1:1
WDPS = 2 1:2
WDPS = 4 1:4
WDPS = 8 1:8
WDPS = 16 1:16
WDPS = 32 1:32
WDPS = 64 1:64
WDPS = 128 1:128
WDPS = 256 1:256
WDPS = 512 1:512
WDPS = 1024 1:1024
WDPS = 2048 1:2048
WDPS = 4096 1:4096
WDPS = 8192 1:8192
WDPS = 16384 1:16384
WDPS = 32768 1:32768
T1OSCMX = OFF Active
T1OSCMX = ON Inactive
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 141
High-Side Transistors Polarity:
Low-Side Transistors Polarity:
PWM output pins Reset state control:
MCLR Enable:
External clock MUX bit:
PWM4 MUX bit:
SSP I/O MUX bit:
FLTA MUX bit:
Stack Overflow Reset:
Low Voltage Programming:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
HPOL = LOW Active low
HPOL = HIGH Active high
LPOL = LOW Active low
LPOL = HIGH Active high
PWMPIN = ON Enabled
PWMPIN = OFF Disabled
MCLRE = OFF Disabled
MCLRE = ON Enabled
EXCLKMX = RD0 Multiplexed with RD0
EXCLKMX = RC3 Multiplexed with RC3
PWM4MX = RD5 Multiplexed with RD5
PWM4MX = RB5 Multiplexed with RB5
SSPMX = RD1 SDO output is multiplexed with RD1
SSPMX = RC7 SD0 output is multiplexed with RC7
FLTAMX = RD4 Multiplexed with RD4
FLTAMX = RC1 Multiplexed with RC1
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 142
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 143
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F4410
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 144
Brown-out Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF MCLR pin enabled; RE3 input pin disabled
MCLRE = ON RE3 input pin enabled; MCLR disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 145
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Boot Block Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Table Read Protection bit Block 0:
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 146
Table Read Protection bit Block 1:
Boot Block Table Read Protection bit:
PIC18F442
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 147
Watchdog Postscaler:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
CCP2MUX = OFF Disable (RB3)
CCP2MUX = ON Enable (RC1)
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 148
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F4420
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 149
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 150
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Boot Block Write Protection bit:
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 151
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Boot Block Table Read Protection bit:
PIC18F4423
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 152
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 153
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Low Voltage ICSP:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection bit:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = PORTB CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Disabled
LVP = ON Enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 154
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection bit:
PIC18F4431
Oscillator Selection:
Fail-Safe Clock Monitor Enable:
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC2 External RC, RA6 is CLKOUT
OSC = EC EC, RA6 is CLKOUT
OSC = ECIO EC, RA6 is I/O
OSC = HSPLL HS-PLL Enabled
OSC = RCIO External RC, RA6 is I/O
OSC = IRCIO Internal RC, RA6 & RA7 are I/O
OSC = IRC Internal RC, RA6 is CLKOUT, RA7 is I/O
OSC = RC1 External RC, RA6 is CLKOUT
OSC = RC External RC, RA6 is CLKOUT
FCMEN = OFF Disabled
FCMEN = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 155
Internal/External Switch-Over:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Timer Enable Window:
Watchdog Postscaler:
Timer1 Oscillator MUX:
High-Side Transistors Polarity:
IESO = OFF Disabled
IESO = ON Enabled
PWRTEN = ON Enabled
PWRTEN = OFF Disabled
BOREN = OFF Disabled
BOREN = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDTEN = OFF Disabled
WDTEN = ON Enabled
WINEN = ON Enabled
WINEN = OFF Disabled
WDPS = 1 1:1
WDPS = 2 1:2
WDPS = 4 1:4
WDPS = 8 1:8
WDPS = 16 1:16
WDPS = 32 1:32
WDPS = 64 1:64
WDPS = 128 1:128
WDPS = 256 1:256
WDPS = 512 1:512
WDPS = 1024 1:1024
WDPS = 2048 1:2048
WDPS = 4096 1:4096
WDPS = 8192 1:8192
WDPS = 16384 1:16384
WDPS = 32768 1:32768
T1OSCMX = OFF Active
T1OSCMX = ON Inactive
HPOL = LOW Active low
HPOL = HIGH Active high
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 156
Low-Side Transistors Polarity:
PWM output pins Reset state control:
MCLR Enable:
External clock MUX bit:
PWM4 MUX bit:
SSP I/O MUX bit:
FLTA MUX bit:
Stack Overflow Reset:
Low Voltage Programming:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
LPOL = LOW Active low
LPOL = HIGH Active high
PWMPIN = ON Enabled
PWMPIN = OFF Disabled
MCLRE = OFF Disabled
MCLRE = ON Enabled
EXCLKMX = RD0 Multiplexed with RD0
EXCLKMX = RC3 Multiplexed with RC3
PWM4MX = RD5 Multiplexed with RD5
PWM4MX = RB5 Multiplexed with RB5
SSPMX = RD1 SDO output is multiplexed with RD1
SSPMX = RC7 SD0 output is multiplexed with RC7
FLTAMX = RD4 Multiplexed with RD4
FLTAMX = RC1 Multiplexed with RC1
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 157
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 158
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F4439
Oscillator Selection:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
Stack Overflow Reset:
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 159
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 160
Boot Block Table Read Protection:
PIC18F4450
96 MHz PLL Prescaler:
CPU System Clock Postscaler:
Full-Speed USB Clock Source Selection:
Oscillator Selection bits:
Fail-Safe Clock Monitor:
EBTRB = ON Enabled
EBTRB = OFF Disabled
PLLDIV = 1 No divide (4 MHz input)
PLLDIV = 2 Divide by 2 (8 MHz input)
PLLDIV = 3 Divide by 3 (12 MHz input)
PLLDIV = 4 Divide by 4 (16 MHz input)
PLLDIV = 5 Divide by 5 (20 MHz input)
PLLDIV = 6 Divide by 6 (24 MHz input)
PLLDIV = 10 Divide by 10 (40 MHz input)
PLLDIV = 12 Divide by 12 (48 MHz input)
CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
USBDIV = 1 Clock source from OSC1/OSC2
USBDIV = 2 Clock source from 96 MHz PLL/2
FOSC = XT_XT XT oscillator, XT used by USB
FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB
FOSC = ECIO_EC External clock, port function on RA6, EC used by USB
FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB
FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB
FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB
FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB
FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB
FOSC = INTOSC_XT Internal oscillator, XT used by USB
FOSC = INTOSC_HS Internal oscillator, HS used by USB
FOSC = HS HS oscillator, HS used by USB
FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB
FCMEM = OFF Disabled
FCMEM = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 161
Internal/External Switch Over:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
USB Voltage Regulator Enable:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
IESO = OFF Disabled
IESO = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = SOFT Controlled by SBOREN
BOR = ON_ACTIVE Enabled when the device is not in Sleep, SBOREN bit is disabled
BOR = ON Enabled, SBOREN bit is disabled
BORV = 46 4.6V
BORV = 43 4.3V
BORV = 28 2.8V
BORV = 21 2.1V
VREGEN = OFF Disabled
VREGEN = ON Enabled
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 162
Low Power Timer1 Oscillator Enable:
PORTB A/D Enable:
Stack Overflow Reset:
Low Voltage ICSP:
Boot Block Size Select Bit:
Dedicated In-Circuit Debug/Programming Enable:
Extended Instruction Set Enable:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Write Protection Block 0:
Write Protection Block 1:
LPT1OSC = OFF Timer1 oscillator configured for high power
LPT1OSC = ON Timer1 oscillator configured for low power
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input on Reset
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
BBSIZ = BB2K 2KW Boot Block Size
BBSIZ = BB1K 1KW Boot Block Size
ICPRT = OFF Disabled
ICPRT = ON Enabled
XINST = OFF Disabled
XINST = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 163
Boot Block Write Protection:
Configuration Register Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F4455
PLL Prescaler Selection bits:
CPU System Clock Postscaler:
USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1):
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly)
PLLDIV = 2 Divide by 2 (8 MHz oscillator input)
PLLDIV = 3 Divide by 3 (12 MHz oscillator input)
PLLDIV = 4 Divide by 4 (16 MHz oscillator input)
PLLDIV = 5 Divide by 5 (20 MHz oscillator input)
PLLDIV = 6 Divide by 6 (24 MHz oscillator input)
PLLDIV = 10 Divide by 10 (40 MHz oscillator input)
PLLDIV = 12 Divide by 12 (48 MHz oscillator input)
CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale
USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 164
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
USB Voltage Regulator Enable bit:
FOSC = XT_XT XT oscillator, XT used by USB
FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB
FOSC = ECIO_EC External clock, port function on RA6, EC used by USB
FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB
FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB
FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB
FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB
FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB
FOSC = INTOSC_XT Internal oscillator, XT used by USB
FOSC = INTOSC_HS Internal oscillator, HS used by USB
FOSC = HS HS oscillator, HS used by USB
FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB
FCMEM = OFF Fail-Safe Clock Monitor disabled
FCMEM = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOR = OFF Brown-out Reset disabled in hardware and software
BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
VREGEN = OFF USB voltage regulator disabled
VREGEN = ON USB voltage regulator enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 165
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer 1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit:
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = OFF CCP2 input/output is multiplexed with RB3
CCP2MX = ON CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
ICPRT = OFF ICPORT disabled
ICPRT = ON ICPORT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 166
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CP2 = ON Block 2 (004000-005FFFh) code-protected
CP2 = OFF Block 2 (004000-005FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRT2 = ON Block 2 (004000-005FFFh) write-protected
WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
WRTB = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTB = OFF Configuration registers (300000-3000FFh) not write-protected
WRTC = ON Boot block (000000-0007FFh) write-protected
WRTC = OFF Boot block (000000-0007FFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 167
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Boot Block Table Read Protection:
PIC18F448
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 168
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 169
Write Protection Block 1:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Boot Block Table Read Protection:
PIC18F4480
Oscillator Selection bits:
Fail-Safe Clock Monitor:
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC External RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO External RC with OSC2 as RA6
OSC = IRCIO67 Internal RC with OSC2 as RA6 and OSC1 as RA7
OSC = IRCIO7 Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out
OSC = ERC1 External RC with OSC2 as divide by 4 clock out
OSC = ERC External RC with OSC2 as divide by 4 clock out
FCMENB = OFF Disabled
FCMENB = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 170
Internal External Osc. Switch:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
Low Power Timer1 Oscillator:
IESOB = OFF Disabled
IESOB = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Timer1 Low Power Oscillator Disabled
LPT1OSC = ON Timer1 Low Power Oscillator Active
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 171
PORTB Pins Configured for A/D:
BackGround Debug:
Extended Instruction Set CPU:
Boot Block Size:
Low Voltage Programming:
Stack Overflow/Underflow Reset:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset
PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
BBSIZ = 1024 1K words (2K bytes) Boot Block
BBSIZ = 2048 2K words (4K bytes) Boot Block
LVP = OFF Disabled
LVP = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 172
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F44J10
Background Debugger Enable bit:
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 173
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLKO function on OSC2
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 174
Watchdog Timer Postscale Select bits:
CCP2 MUX bit:
PIC18F4510
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE CCP2 is multiplexed with RB3
CCP2MX = DEFAULT CCP2 is multiplexed with RC1
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 175
Brown-out Reset Enable bits:
Brown-out Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF MCLR pin enabled; RE3 input pin disabled
MCLRE = ON RE3 input pin enabled; MCLR disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 176
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
Boot Block Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CP2 = ON Block 2 (004000-005FFFh) code-protected
CP2 = OFF Block 2 (004000-005FFFh) not code-protected
CP3 = ON Block 3 (006000-007FFFh) code-protected
CP3 = OFF Block 3 (006000-007FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 177
Write Protection bit Block 2:
Write Protection bit Block 3:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Boot Block Table Read Protection bit:
WRT2 = ON Block 2 (004000-005FFFh) write-protected
WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
WRT3 = ON Block 3 (006000-007FFFh) write-protected
WRT3 = OFF Block 3 (006000-007FFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 178
PIC18F4515
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 179
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF MCLR pin enabled; RE3 input pin disabled
MCLRE = ON RE3 input pin enabled; MCLR disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 180
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Boot Block Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Table Read Protection bit Block 0:
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-003FFFh) code-protected
CP0 = OFF Block 0 (000800-003FFFh) not code-protected
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
WRT0 = ON Block 0 (000800-003FFFh) write-protected
WRT0 = OFF Block 0 (000800-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 181
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Boot Block Table Read Protection bit:
PIC18F452
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 182
Watchdog Postscaler:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
CCP2MUX = OFF Disable (RB3)
CCP2MUX = ON Enable (RC1)
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 183
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 184
PIC18F4520
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 185
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 186
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Write Protection bit Block 3:
Boot Block Write Protection bit:
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CP2 = ON Block 2 (004000-005FFFh) code-protected
CP2 = OFF Block 2 (004000-005FFFh) not code-protected
CP3 = ON Block 3 (006000-007FFFh) code-protected
CP3 = OFF Block 3 (006000-007FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRT2 = ON Block 2 (004000-005FFFh) write-protected
WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
WRT3 = ON Block 3 (006000-007FFFh) write-protected
WRT3 = OFF Block 3 (006000-007FFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 187
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Boot Block Table Read Protection bit:
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 188
PIC18F4523
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 189
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Low Voltage ICSP:
Extended Instruction Set Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = PORTB CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Disabled
LVP = ON Enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 190
Background Debugger Enable bit:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection bit:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection bit:
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CP2 = ON Block 2 (004000-005FFFh) code-protected
CP2 = OFF Block 2 (004000-005FFFh) not code-protected
CP3 = ON Block 3 (006000-007FFFh) code-protected
CP3 = OFF Block 3 (006000-007FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRT2 = ON Block 2 (004000-005FFFh) write-protected
WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
WRT3 = ON Block 3 (006000-007FFFh) write-protected
WRT3 = OFF Block 3 (006000-007FFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 191
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection bit:
PIC18F4525
Oscillator Selection:
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO6 EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO6 RC-OSC2 as RA6
OSC = INTIO67 INTRC-OSC2 as RA6, OSC1 as RA7
OSC = INTIO7 INTRC-OSC2 as Clock Out, OSC1 as RA7
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 192
Fail-Safe Clock Monitor:
Internal External Osc. Switch Over:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOREN = OFF Disabled
BOREN = ON SBOREN Enabled
BOREN = NOSLP Enabled except Sleep, SBOREN Disabled
BOREN = SBORDIS Enabled, SBOREN Disabled
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 193
T1 Oscillator Enable:
PORTB A/D Enable:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
XINST Enable:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
LPT1OSC = OFF Disabled
LPT1OSC = ON Enabled
PBADEN = OFF PORTB<4:0> digital on Reset
PBADEN = ON PORTB<4:0> analog on Reset
CCP2MX = PORTBE Multiplexed with RB3
CCP2MX = PORTC Multiplexed with RC1
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
XINST = OFF Disabled
XINST = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 194
Write Protection Block 1:
Write Protection Block 2:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Boot Block Table Read Protection:
PIC18F4539
Oscillator Selection:
Power-up Timer:
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
PWRT = ON Enabled
PWRT = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 195
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Boot Block Code Protection:
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 196
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Boot Block Table Read Protection:
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 197
PIC18F4550
PLL Prescaler Selection bits:
CPU System Clock Postscaler:
USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1):
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly)
PLLDIV = 2 Divide by 2 (8 MHz oscillator input)
PLLDIV = 3 Divide by 3 (12 MHz oscillator input)
PLLDIV = 4 Divide by 4 (16 MHz oscillator input)
PLLDIV = 5 Divide by 5 (20 MHz oscillator input)
PLLDIV = 6 Divide by 6 (24 MHz oscillator input)
PLLDIV = 10 Divide by 10 (40 MHz oscillator input)
PLLDIV = 12 Divide by 12 (48 MHz oscillator input)
CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale
USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2
FOSC = XT_XT XT oscillator, XT used by USB
FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB
FOSC = ECIO_EC External clock, port function on RA6, EC used by USB
FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB
FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB
FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB
FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB
FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB
FOSC = INTOSC_XT Internal oscillator, XT used by USB
FOSC = INTOSC_HS Internal oscillator, HS used by USB
FOSC = HS HS oscillator, HS used by USB
FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB
FCMEM = OFF Fail-Safe Clock Monitor disabled
FCMEM = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 198
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
USB Voltage Regulator Enable bit:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOR = OFF Brown-out Reset disabled in hardware and software
BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
VREGEN = OFF USB voltage regulator disabled
VREGEN = ON USB voltage regulator enabled
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RE3 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RE3 input pin disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 199
Low-Power Timer 1 Oscillator Enable bit:
PORTB A/D Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
CCP2MX = OFF CCP2 input/output is multiplexed with RB3
CCP2MX = ON CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
ICPRT = OFF ICPORT disabled
ICPRT = ON ICPORT enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-001FFFh) code-protected
CP0 = OFF Block 0 (000800-001FFFh) not code-protected
CP1 = ON Block 1 (002000-003FFFh) code-protected
CP1 = OFF Block 1 (002000-003FFFh) not code-protected
CP2 = ON Block 2 (004000-005FFFh) code-protected
CP2 = OFF Block 2 (004000-005FFFh) not code-protected
CP3 = ON Block 3 (006000-007FFFh) code-protected
CP3 = OFF Block 3 (006000-007FFFh) not code-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 200
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Write Protection bit Block 3:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800-001FFFh) write-protected
WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
WRT1 = ON Block 1 (002000-003FFFh) write-protected
WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
WRT2 = ON Block 2 (004000-005FFFh) write-protected
WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
WRT3 = ON Block 3 (006000-007FFFh) write-protected
WRT3 = OFF Block 3 (006000-007FFFh) not write-protected
WRTB = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTB = OFF Configuration registers (300000-3000FFh) not write-protected
WRTC = ON Boot block (000000-0007FFh) write-protected
WRTC = OFF Boot block (000000-0007FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 201
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Boot Block Table Read Protection:
PIC18F458
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 202
Watchdog Postscaler:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 203
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 204
PIC18F4580
Oscillator Selection bits:
Fail-Safe Clock Monitor:
Internal External Osc. Switch:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC External RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO External RC with OSC2 as RA6
OSC = IRCIO67 Internal RC with OSC2 as RA6 and OSC1 as RA7
OSC = IRCIO7 Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out
OSC = ERC1 External RC with OSC2 as divide by 4 clock out
OSC = ERC External RC with OSC2 as divide by 4 clock out
FCMENB = OFF Disabled
FCMENB = ON Enabled
IESOB = OFF Disabled
IESOB = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 205
Watchdog Postscaler:
MCLR Enable:
Low Power Timer1 Oscillator:
PORTB Pins Configured for A/D:
BackGround Debug:
Extended Instruction Set CPU:
Boot Block Size:
Low Voltage Programming:
Stack Overflow/Underflow Reset:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Timer1 Low Power Oscillator Disabled
LPT1OSC = ON Timer1 Low Power Oscillator Active
PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset
PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
BBSIZ = 1024 1K words (2K bytes) Boot Block
BBSIZ = 2048 2K words (4K bytes) Boot Block
LVP = OFF Disabled
LVP = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 206
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 207
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F4585
Oscillator Selection bits:
Fail-Safe Clock Monitor:
Internal External Osc. Switch:
Power-up Timer:
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC External RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO External RC with OSC2 as RA6
OSC = IRCIO67 Internal RC with OSC2 as RA6 and OSC1 as RA7
OSC = IRCIO7 Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out
OSC = ERC1 External RC with OSC2 as divide by 4 clock out
OSC = ERC External RC with OSC2 as divide by 4 clock out
FCMENB = OFF Disabled
FCMENB = ON Enabled
IESOB = OFF Disabled
IESOB = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 208
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
Low Power Timer1 Oscillator:
PORTB Pins Configured for A/D:
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Timer1 Low Power Oscillator Disabled
LPT1OSC = ON Timer1 Low Power Oscillator Active
PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset
PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 209
BackGround Debug:
Enhanced Instruction Set CPU:
Boot Block Size:
Low Voltage Programming:
Stack Overflow/Underflow Reset:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
BBSIZ = 1024 1K words (2K bytes) Boot Block
BBSIZ = 2048 2K words (4K bytes) Boot Block
BBSIZ = 4096 4K words (8K bytes) Boot Block
LVP = OFF Disabled
LVP = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 210
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F45J10
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 211
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
Watchdog Timer Postscale Select bits:
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLKO function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 212
CCP2 MUX bit:
PIC18F45K20
Oscillator Selection:
Fail Safe Clock Monitor:
Internal External Osc. Switch Over:
Power Up Timer:
Brown Out Reset:
Brown Out Voltage:
Watchdog Timer:
CCP2MX = ALTERNATE CCP2 is multiplexed with RB3
CCP2MX = DEFAULT CCP2 is multiplexed with RC1
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO6 EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO6 RC-OSC2 as RA6
OSC = INTIO67 INTRC-OSC2 as RA6, OSC1 as RA7
OSC = INTIO7 INTRC-OSC2 as Clock Out, OSC1 as RA7
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOREN = OFF Disabled
BOREN = ON SBOREN Enabled
BOREN = NOSLP Enabled except SLEEP, SBOREN Disabled
BOREN = SBORDIS Enabled, SBOREN Disabled
BORV = 46 3.0V
BORV = 43 2.7V
BORV = 28 2.2V
BORV = 21 1.8
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 213
Watchdog Postscaler:
MCLR Enable:
T1 Oscillator Enable:
Port B A/D Enable:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
XINST Enable:
Background Debugger Enable:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Disabled
LPT1OSC = ON Enabled
PBADEN = OFF Port B<4:0> digital on RESET
PBADEN = ON Port B<4:0> analog on RESET
CCP2MX = PORTBE Multiplexed with RB3
CCP2MX = PORTC Multiplexed with RC1
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
XINST = OFF Disabled
XINST = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 214
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 215
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F4610
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 216
Brown-out Reset Enable bits:
Brown-out Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
PORTB A/D Enable bit:
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF MCLR pin enabled; RE3 input pin disabled
MCLRE = ON RE3 input pin enabled; MCLR disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 217
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
Boot Block Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800-003FFFh) code-protected
CP0 = OFF Block 0 (000800-003FFFh) not code-protected
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
CP3 = ON Block 3 (00C000-00FFFFh) code-protected
CP3 = OFF Block 3 (00C000-00FFFh) not code-protected
CPB = ON Boot block (000000-0007FFh) code-protected
CPB = OFF Boot block (000000-0007FFh) not code-protected
WRT0 = ON Block 0 (000800-003FFFh) write-protected
WRT0 = OFF Block 0 (000800-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 218
Write Protection bit Block 2:
Write Protection bit Block 3:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Boot Block Table Read Protection bit:
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
WRT3 = ON Block 3 (00C000-00FFFFh) write-protected
WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected
WRTB = ON Boot block (000000-0007FFh) write-protected
WRTB = OFF Boot block (000000-0007FFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 219
PIC18F4620
Oscillator Selection:
Fail-Safe Clock Monitor:
Internal External Osc. Switch Over:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO6 EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO6 RC-OSC2 as RA6
OSC = INTIO67 INTRC-OSC2 as RA6, OSC1 as RA7
OSC = INTIO7 INTRC-OSC2 as Clock Out, OSC1 as RA7
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOREN = OFF Disabled
BOREN = ON SBOREN Enabled
BOREN = NOSLP Enabled except Sleep, SBOREN Disabled
BOREN = SBORDIS Enabled, SBOREN Disabled
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 220
Watchdog Postscaler:
MCLR Enable:
T1 Oscillator Enable:
PORTB A/D Enable:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
XINST Enable:
Background Debugger Enable:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Disabled
LPT1OSC = ON Enabled
PBADEN = OFF PORTB<4:0> digital on Reset
PBADEN = ON PORTB<4:0> analog on Reset
CCP2MX = PORTBE Multiplexed with RB3
CCP2MX = PORTC Multiplexed with RC1
STVREN = OFF Disabled
STVREN = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
XINST = OFF Disabled
XINST = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 221
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 222
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F4680
Oscillator Selection bits:
Fail-Safe Clock Monitor:
Internal External Osc. Switch:
Power-up Timer:
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC External RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO External RC with OSC2 as RA6
OSC = IRCIO67 Internal RC with OSC2 as RA6 and OSC1 as RA7
OSC = IRCIO7 Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out
OSC = ERC1 External RC with OSC2 as divide by 4 clock out
OSC = ERC External RC with OSC2 as divide by 4 clock out
FCMENB = OFF Disabled
FCMENB = ON Enabled
IESOB = OFF Disabled
IESOB = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 223
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
Low Power Timer1 Oscillator:
PORTB Pins Configured for A/D:
BOR = OFF Disabled
BOR = SBORENCTRL Controlled by SBOREN
BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOR = BOHW Enabled in HW, SBOREN Disabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Timer1 Low Power Oscillator Disabled
LPT1OSC = ON Timer1 Low Power Oscillator Active
PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset
PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 224
BackGround Debug:
Enhanced Instruction Set CPU:
Boot Block Size:
Low Voltage Programming:
Stack Overflow/Underflow Reset:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
BBSIZ = 1024 1K words (2K bytes) Boot Block
BBSIZ = 2048 2K words (4K bytes) Boot Block
BBSIZ = 4096 4K words (8K bytes) Boot Block
LVP = OFF Disabled
LVP = ON Enabled
STVREN = OFF Disabled
STVREN = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 225
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 226
PIC18F4685
Oscillator Selection bits:
Fail-Safe Clock Monitor:
Internal External Osc. Switch:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC External RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO External RC with OSC2 as RA6
OSC = IRCIO67 Internal RC with OSC2 as RA6 and OSC1 as RA7
OSC = IRCIO7 Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out
OSC = ERC1 External RC with OSC2 as divide by 4 clock out
OSC = ERC External RC with OSC2 as divide by 4 clock out
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOREN = OFF Disabled
BOREN = SBORENCTRL Controlled by SBOREN
BOREN = BOACTIVE Enabled whenever Part is Active - SBOREN Dis-abled
BOREN = BOHW Enabled in HW, SBOREN Disabled
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 227
Watchdog Postscaler:
MCLR Enable:
Low Power Timer1 Oscillator:
PORTB Pins Configured for A/D:
BackGround Debug:
Enhanced Instruction Set CPU:
Boot Block Size:
Low Voltage Programming:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
LPT1OSC = OFF Disabled
LPT1OSC = ON Enabled
PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset
PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
BBSIZ = 1024 1K words (2K bytes) Boot Block
BBSIZ = 2048 2K words (4K bytes) Boot Block
BBSIZ = 4096 4K words (8K bytes) Boot Block
LVP = OFF Disabled
LVP = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 228
Stack Overflow/Underflow Reset:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Code Protection Block 4:
Code Protection Block 5:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
STVREN = OFF Disabled
STVREN = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CP4 = ON Enabled
CP4 = OFF Disabled
CP5 = ON Enabled
CP5 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 229
Write Protection Block 4:
Write Protection Block 5:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Table Read Protection Block 4:
Table Read Protection Block 5:
Boot Block Table Read Protection:
WRT4 = ON Enabled
WRT4 = OFF Disabled
WRT5 = ON Enabled
WRT5 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTR4 = ON Enabled
EBTR4 = OFF Disabled
EBTR5 = ON Enabled
EBTR5 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 230
PIC18F6310
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 231
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer 1 Oscillator Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
CCP2MX = PORTE CCP2 input/output is multiplexed with RE7
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP = ON Program memory block code-protected
CP = OFF Program memory block not code-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 232
PIC18F6390
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown Out Voltage:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 233
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer 1 Oscillator Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP = ON Program memory block (000000-003FFFh) code-protected
CP = OFF Program memory block (000000-003FFFh) not code-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 234
PIC18F63J90
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Fail-Safe Clock Monitor Enable bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 235
Watchdog Timer Postscaler Select bits:
ECCP2 MUX bit:
PIC18F6410
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontrol-ler mode or with RB3 in Extended Microcontroller mode
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 236
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer 1 Oscillator Enable bit:
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 237
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit:
PIC18F6490
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
CCP2MX = PORTE CCP2 input/output is multiplexed with RE7
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP = ON Program memory block code-protected
CP = OFF Program memory block not code-protected
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 238
Brown-out Reset Enable bits:
Brown Out Voltage:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer 1 Oscillator Enable bit:
CCP2 MUX bit:
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 239
Stack Full/Underflow Reset Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit:
PIC18F64J90
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP = ON Program memory block (000000-003FFFh) code-protected
CP = OFF Program memory block (000000-003FFFh) not code-protected
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 240
Fail-Safe Clock Monitor Enable bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
Watchdog Timer Postscaler Select bits:
ECCP2 MUX bit:
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontrol-ler mode or with RB3 in Extended Microcontroller mode
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 241
PIC18F6520
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
CCP2 MUX:
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC-OSC2 as Clock Out
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
CCP2MUX = OFF Uses RE7
CCP2MUX = RE7 Uses RE7
CCP2MUX = ON Uses RC1
CCP2MUX = RC1 Uses RC1
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 242
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 243
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F6525
Oscillator Selection:
Osc. Switch Enable:
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSC = ECIOPLL EC-OSC2 as RA6 and PLL
OSC = ECIOSWPLL EC-OSC2 as RA6 and SW PLL
OSC = HSSWPLL HS with SW PLL
OSCS = ON Enabled
OSCS = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 244
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
CCP2MX = PORTBE Multiplexed with RB3 or RE7
CCP2MX = PORTC Multiplexed with RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 245
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 246
Table Read Protection Block 1:
Table Read Protection Block 2:
Boot Block Table Read Protection:
PIC18F6527
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 247
Brown-out Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
CCP2MX = PORTE ECCP2 input/output is multiplexed with RE7
CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 248
Boot Block Size Select bits:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size
BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size
BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected
CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
CPB = ON Boot Block (000000-0007FFh) code-protected
CPB = OFF Boot Block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected
WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 249
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Boot Block Table Read Protection bit:
WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) pro-tected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 250
PIC18F6585
Oscillator Selection bits:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO RC with OSC2 as RA6
OSC = ECIOPLL EC with OSC2 as RA6 and HW enabled 4xPLL
OSC = ECIOSWPLL EC with OSC2 as RA6 and SW enabled 4xPLL
OSC = HSSWPLL HS with SW enabled 4xPLL
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 251
Watchdog Postscaler:
MCLR Enable:
CCP2 MUX bit:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
CCP2MX = OFF CCP2 input/output is multiplexed with RE7
CCP2MX = ON CCP2 input/output is multiplexed with RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 252
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Boot Block Table Read Protection:
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 253
PIC18F65J10
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 254
Watchdog Timer Postscaler Select bits:
ECCP2 MUX bit:
PIC18F65J15
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 255
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
Watchdog Timer Postscaler Select bits:
ECCP2 MUX bit:
PIC18F65J90
Background Debugger Enable bit:
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 256
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Fail-Safe Clock Monitor Enable bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 257
Watchdog Timer Postscaler Select bits:
ECCP2 MUX bit:
PIC18F6620
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontrol-ler mode or with RB3 in Extended Microcontroller mode
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 258
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
CCP2MUX = OFF Disabled
CCP2MUX = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 259
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 260
Boot Block Table Read Protection:
PIC18F6621
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSC = ECIOPLL EC-OSC2 as RA6 and PLL
OSC = ECIOSWPLL EC-OSC2 as RA6 and SW PLL
OSC = HSSWPLL HS with SW PLL
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 261
Watchdog Postscaler:
MCLR Enable:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
CCP2MX = PORTBE Multiplexed with RB3 or RE7
CCP2MX = PORTC Multiplexed with RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 262
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 263
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F6622
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 264
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Boot Block Size Select bits:
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
CCP2MX = PORTE ECCP2 input/output is multiplexed with RE7
CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size
BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size
BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 265
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected
CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
CP3 = ON Block 3 (00C000-00FFFFh) code-protected
CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected
CPB = ON Boot Block (000000-0007FFh) code-protected
CPB = OFF Boot Block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected
WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 266
Write Protection bit Block 3:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Boot Block Table Read Protection bit:
WRT3 = ON Block 3 (00C000-00FFFFh) write-protected
WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected
WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) pro-tected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 267
PIC18F6627
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 268
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Boot Block Size Select bits:
Extended Instruction Set Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
CCP2MX = PORTE ECCP2 input/output is multiplexed with RE7
CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size
BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size
BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 269
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
Code Protection bit Block 4:
Code Protection bit Block 5:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected
CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
CP3 = ON Block 3 (00C000-00FFFFh) code-protected
CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected
CP4 = ON Block 4 (010000-013FFFh) code-protected
CP4 = OFF Block 4 (010000-013FFFh) not code-protected
CP5 = ON Block 5 (014000-017FFFh) code-protected
CP5 = OFF Block 5 (014000-017FFFh) not code-protected
CPB = ON Boot Block (000000-0007FFh) code-protected
CPB = OFF Boot Block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected
WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 270
Write Protection bit Block 3:
Write Protection bit Block 4:
Write Protection bit Block 5:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
WRT3 = ON Block 3 (00C000-00FFFFh) write-protected
WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected
WRT4 = ON Block 4 (010000-013FFFh) write-protected
WRT4 = OFF Block 4 (010000-013FFFh) not write-protected
WRT5 = ON Block 5 (014000-017FFFh) write-protected
WRT5 = OFF Block 5 (014000-017FFFh) not write-protected
WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) pro-tected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 271
Table Read Protection bit Block 4:
Table Read Protection bit Block 5:
Boot Block Table Read Protection bit:
PIC18F6680
Oscillator Selection bits:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks
EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks
EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO RC with OSC2 as RA6
OSC = ECIOPLL EC with OSC2 as RA6 and HW enabled 4xPLL
OSC = ECIOSWPLL EC with OSC2 as RA6 and SW enabled 4xPLL
OSC = HSSWPLL HS with SW enabled 4xPLL
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 272
Watchdog Timer:
Watchdog Postscaler:
MCLR Enable:
CCP2 MUX bit:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF Disabled
MCLRE = ON Enabled
CCP2MX = OFF CCP2 input/output is multiplexed with RE7
CCP2MX = ON CCP2 input/output is multiplexed with RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 273
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 274
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F66J10
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 275
Oscillator Selection bits:
Watchdog Timer Postscaler Select bits:
ECCP2 MUX bit:
PIC18F66J15
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 276
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
Watchdog Timer Postscaler Select bits:
ECCP2 MUX bit:
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 277
PIC18F66J60
Background Debugger Enable:
Extended Instruction Set Enable:
Stack Overflow Reset:
Watchdog Timer:
Code Protection:
Fail-Safe Clock Monitor:
Internal/External Switch Over:
Default/Reset System Clock Select Bit:
Oscillator Selection bits:
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
WDT = OFF Disabled
WDT = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
FOSC2 = OFF INTRC as system clock when OSCCON<1:0> = 00
FOSC2 = ON FOSC<1:0> selects system clock for OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, Software Controlled PLL
FOSC = EC External Clock
FOSC = ECPLL External Clock, Software Controlled PLL
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 278
Watchdog Postscaler:
Ethernet LED Enable:
PIC18F66J65
Background Debugger Enable:
Extended Instruction Set Enable:
Stack Overflow Reset:
Watchdog Timer:
Code Protection:
Fail-Safe Clock Monitor:
Internal/External Switch Over:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
ETHLED = OFF Disabled
ETHLED = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
WDT = OFF Disabled
WDT = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 279
Default/Reset System Clock Select Bit:
Oscillator Selection bits:
Watchdog Postscaler:
Ethernet LED Enable:
PIC18F6720
Oscillator Selection:
Osc. Switch Enable:
FOSC2 = OFF INTRC as system clock when OSCCON<1:0> = 00
FOSC2 = ON FOSC<1:0> selects system clock for OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, Software Controlled PLL
FOSC = EC External Clock
FOSC = ECPLL External Clock, Software Controlled PLL
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
ETHLED = OFF Disabled
ETHLED = ON Enabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 280
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
CCP2MUX = OFF Disabled
CCP2MUX = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 281
Code Protection Block 2:
Code Protection Block 3:
Code Protection Block 4:
Code Protection Block 5:
Code Protection Block 6:
Code Protection Block 7:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Write Protection Block 4:
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CP4 = ON Enabled
CP4 = OFF Disabled
CP5 = ON Enabled
CP5 = OFF Disabled
CP6 = ON Enabled
CP6 = OFF Disabled
CP7 = ON Enabled
CP7 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRT4 = ON Enabled
WRT4 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 282
Write Protection Block 5:
Write Protection Block 6:
Write Protection Block 7:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Table Read Protection Block 4:
Table Read Protection Block 5:
Table Read Protection Block 6:
WRT5 = ON Enabled
WRT5 = OFF Disabled
WRT6 = ON Enabled
WRT6 = OFF Disabled
WRT7 = ON Enabled
WRT7 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTR4 = ON Enabled
EBTR4 = OFF Disabled
EBTR5 = ON Enabled
EBTR5 = OFF Disabled
EBTR6 = ON Enabled
EBTR6 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 283
Table Read Protection Block 7:
Boot Block Table Read Protection:
PIC18F6722
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
EBTR7 = ON Enabled
EBTR7 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 284
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Boot Block Size Select bits:
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
CCP2MX = PORTE ECCP2 input/output is multiplexed with RE7
CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size
BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size
BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 285
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
Code Protection bit Block 4:
Code Protection bit Block 5:
Code Protection bit Block 6:
Code Protection bit Block 7:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected
CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
CP3 = ON Block 3 (00C000-00FFFFh) code-protected
CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected
CP4 = ON Block 4 (010000-013FFFh) code-protected
CP4 = OFF Block 4 (010000-013FFFh) not code-protected
CP5 = ON Block 5 (014000-017FFFh) code-protected
CP5 = OFF Block 5 (014000-017FFFh) not code-protected
CP6 = ON Block 6 (01BFFF-018000h) code-protected
CP6 = OFF Block 6 (01BFFF-018000h) not code-protected
CP7 = ON Block 7 (01C000-01FFFFh) code-protected
CP7 = OFF Block 7 (01C000-01FFFFh) not code-protected
CPB = ON Boot Block (000000-0007FFh) code-protected
CPB = OFF Boot Block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 286
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Write Protection bit Block 3:
Write Protection bit Block 4:
Write Protection bit Block 5:
Write Protection bit Block 6:
Write Protection bit Block 7:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected
WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
WRT3 = ON Block 3 (00C000-00FFFFh) write-protected
WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected
WRT4 = ON Block 4 (010000-013FFFh) write-protected
WRT4 = OFF Block 4 (010000-013FFFh) not write-protected
WRT5 = ON Block 5 (014000-017FFFh) write-protected
WRT5 = OFF Block 5 (014000-017FFFh) not write-protected
WRT6 = ON Block 6 (01BFFF-018000h) write-protected
WRT6 = OFF Block 6 (01BFFF-018000h) not write-protected
WRT7 = ON Block 7 (01C000-01FFFFh) write-protected
WRT7 = OFF Block 7 (01C000-01FFFFh) not write-protected
WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 287
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Table Read Protection bit Block 4:
Table Read Protection bit Block 5:
Table Read Protection bit Block 6:
Table Read Protection bit Block 7:
Boot Block Table Read Protection bit:
EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) pro-tected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks
EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks
EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
EBTR6 = ON Block 6 (018000-01BFFFh) protected from table reads executed in other blocks
EBTR6 = OFF Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks
EBTR7 = ON Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks
EBTR7 = OFF Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 288
PIC18F67J10
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 289
Watchdog Timer Postscaler Select bits:
ECCP2 MUX bit:
PIC18F67J60
Background Debugger Enable:
Extended Instruction Set Enable:
Stack Overflow Reset:
Watchdog Timer:
Code Protection:
Fail-Safe Clock Monitor:
Internal/External Switch Over:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
WDT = OFF Disabled
WDT = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 290
Default/Reset System Clock Select Bit:
Oscillator Selection bits:
Watchdog Postscaler:
Ethernet LED Enable:
PIC18F8310
Oscillator Selection bits:
FOSC2 = OFF INTRC as system clock when OSCCON<1:0> = 00
FOSC2 = ON FOSC<1:0> selects system clock for OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, Software Controlled PLL
FOSC = EC External Clock
FOSC = ECPLL External Clock, Software Controlled PLL
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
ETHLED = OFF Disabled
ETHLED = ON Enabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 291
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 292
Processor Data Memory Mode Select bits:
External Bus Data Width Select bit:
External Bus Data Wait Enable bit:
MCLR Pin Enable bit:
Low-Power Timer 1 Oscillator Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit:
Table Read Protection bit:
PM = EM Extended Microcontroller mode
PM = MPB Microprocessor with Boot Block mode
PM = MP Microprocessor mode
PM = MC Microcontroller mode
BW = 8 8-bit External Bus Data Width
BW = 16 16-bit External Bus Data Width
WAIT = ON Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>)
WAIT = OFF Wait selections unavailable, device will not wait
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
CCP2MX = PORTBE CCP2 is multiplexed with RB3 in Extended Microcon-troller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode.
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP = ON Program memory block code-protected
CP = OFF Program memory block not code-protected
EBTR = ON Internal program memory block protected from table reads executed from external memory block
EBTR = OFF Internal program memory block not protected from table reads executed from external memory block
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 293
PIC18F8390
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown Out Voltage:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 294
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer 1 Oscillator Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP = ON Program memory block (000000-003FFFh) code-protected
CP = OFF Program memory block (000000-003FFFh) not code-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 295
PIC18F83J90
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Fail-Safe Clock Monitor Enable bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 296
Watchdog Timer Postscaler Select bits:
ECCP2 MUX bit:
PIC18F8410
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontrol-ler mode or with RB3 in Extended Microcontroller mode
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 297
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Reset Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
Processor Data Memory Mode Select bits:
External Bus Data Width Select bit:
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
PM = EM Extended Microcontroller mode
PM = MPB Microprocessor with Boot Block mode
PM = MP Microprocessor mode
PM = MC Microcontroller mode
BW = 8 8-bit External Bus Data Width
BW = 16 16-bit External Bus Data Width
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 298
External Bus Data Wait Enable bit:
MCLR Pin Enable bit:
Low-Power Timer 1 Oscillator Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit:
Table Read Protection bit:
WAIT = ON Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>)
WAIT = OFF Wait selections unavailable, device will not wait
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
CCP2MX = PORTBE CCP2 is multiplexed with RB3 in Extended Microcon-troller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode.
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP = ON Program memory block code-protected
CP = OFF Program memory block not code-protected
EBTR = ON Internal program memory block protected from table reads executed from external memory block
EBTR = OFF Internal program memory block not protected from table reads executed from external memory block
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 299
PIC18F8490
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown Out Voltage:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
OSC = RCIO External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Oscillator Switchover mode disabled
IESO = ON Oscillator Switchover mode enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum Setting
BORV = 1
BORV = 2
BORV = 3 Minimum Setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 300
Watchdog Timer Postscale Select bits:
MCLR Pin Enable bit:
Low-Power Timer 1 Oscillator Enable bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7
CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP = ON Program memory block (000000-003FFFh) code-protected
CP = OFF Program memory block (000000-003FFFh) not code-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 301
PIC18F84J90
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Fail-Safe Clock Monitor Enable bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 302
Watchdog Timer Postscaler Select bits:
ECCP2 MUX bit:
PIC18F8520
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontrol-ler mode or with RB3 in Extended Microcontroller mode
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC-OSC2 as Clock Out
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 303
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
Processor Mode Selection:
External Bus Data Wait:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
MODE = EM Extended Microcontroller mode
MODE = MPB Microprocessor with Boot Block mode
MODE = MP Microprocessor mode
MODE = MC Microcontroller mode
WAIT = ON Enabled
WAIT = OFF Disabled
CCP2MUX = OFF Uses RE7
CCP2MUX = RE7 Uses RE7
CCP2MUX = ON Uses RC1
CCP2MUX = RC1 Uses RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 304
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 305
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F8525
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSC = ECIOPLL EC-OSC2 as RA6 and PLL
OSC = ECIOSWPLL EC-OSC2 as RA6 and SW PLL
OSC = HSSWPLL HS with SW PLL
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 306
Watchdog Timer:
Watchdog Postscaler:
Processor Mode Selection:
External Bus Data Wait:
MCLR Enable:
ECCP MUX:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MODE = EM Extended Microcontroller mode
MODE = MPB Microprocessor with Boot Block mode
MODE = MP Microprocessor mode
MODE = MC Microcontroller mode
WAIT = ON Enabled
WAIT = OFF Disabled
MCLRE = OFF Disabled
MCLRE = ON Enabled
ECCPMX = PORTH Multiplexed with RH7:4
ECCPMX = PORTE Multiplexed with RE6:3
CCP2MX = PORTBE Multiplexed with RB3 or RE7
CCP2MX = PORTC Multiplexed with RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 307
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 308
Table Read Protection Block 1:
Table Read Protection Block 2:
Boot Block Table Read Protection:
PIC18F8527
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 309
Brown-out Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
Processor Data Memory Mode Select bits:
Address Bus Width Select bits:
Data Bus Width Select bit:
External Bus Data Wait Enable bit:
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MODE = EM Extended Microcontroller mode
MODE = MPB Microprocessor with Boot Block mode
MODE = MP Microprocessor mode
MODE = MC Microcontroller mode
ADDRBW = ADDR8BIT 8-bit Address Bus
ADDRBW = ADDR12BIT 12-bit Address Bus
ADDRBW = ADDR16BIT 16-bit Address Bus
ADDRBW = ADDR20BIT 20-bit Address Bus
DATABW = DATA8BIT 8-bit External Bus mode
DATABW = DATA16BIT 16-bit External Bus mode
WAIT = ON Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits
WAIT = OFF Wait selections are unavailable for table reads and table writes
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 310
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
ECCP MUX bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Boot Block Size Select bits:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
ECCPMX = PORTH ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively
ECCPMX = PORTE ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively
CCP2MX = PORTBE ECCP2 is multiplexed with RB3 in Extended Micro-controller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode.
CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size
BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size
BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected
CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 311
Code Protection bit Block 1:
Code Protection bit Block 2:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
CPB = ON Boot Block (000000-0007FFh) code-protected
CPB = OFF Boot Block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected
WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) pro-tected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 312
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Boot Block Table Read Protection bit:
PIC18F8585
Oscillator Selection bits:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO RC with OSC2 as RA6
OSC = ECIOPLL EC with OSC2 as RA6 and HW enabled 4xPLL
OSC = ECIOSWPLL EC with OSC2 as RA6 and SW enabled 4xPLL
OSC = HSSWPLL HS with SW enabled 4xPLL
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 313
Watchdog Timer:
Watchdog Postscaler:
Processor Mode Selection:
External Bus Data Wait:
MCLR Enable:
CCP2 MUX bit:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MODE = EM Extended Microcontroller mode
MODE = MPB Microprocessor with Boot Block mode
MODE = MP Microprocessor mode
MODE = MC Microcontroller mode
WAIT = ON Enabled
WAIT = OFF Disabled
MCLRE = OFF Disabled
MCLRE = ON Enabled
CCP2MX = OFF CCP2 input/output is multiplexed with RE7
CCP2MX = ON CCP2 input/output is multiplexed with RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 314
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 315
Table Read Protection Block 2:
Boot Block Table Read Protection:
PIC18F85J10
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 316
Oscillator Selection bits:
Watchdog Timer Postscaler Select bits:
External Bus Wait Enable bit:
Data Bus Width Select bit:
Processor Mode Selection:
External Address Bus Shift Enable bit:
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
WAIT = ON Wait states for operations on external memory bus enabled
WAIT = OFF Wait states for operations on external memory bus disabled
BW = 8 8-bit external bus mode
BW = 16 16-bit external bus mode
MODE = MM Microcontroller mode - External bus disabled
MODE = XM12 Extended Microcontroller mode, 12-bit Address mode
MODE = XM16 Extended Microcontroller mode, 16-bit Address mode
MODE = XM20 Extended Microcontroller mode, 20-bit Address mode
EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value
EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 317
ECCPx MUX bit:
ECCP2 MUX bit:
PIC18F85J15
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4
ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontrol-ler mode or with RB3 in Extended Microcontroller mode
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 318
Oscillator Selection bits:
Watchdog Timer Postscaler Select bits:
External Bus Wait Enable bit:
Data Bus Width Select bit:
Processor Mode Selection:
External Address Bus Shift Enable bit:
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
WAIT = ON Wait states for operations on external memory bus enabled
WAIT = OFF Wait states for operations on external memory bus disabled
BW = 8 8-bit external bus mode
BW = 16 16-bit external bus mode
MODE = MM Microcontroller mode - External bus disabled
MODE = XM12 Extended Microcontroller mode, 12-bit Address mode
MODE = XM16 Extended Microcontroller mode, 16-bit Address mode
MODE = XM20 Extended Microcontroller mode, 20-bit Address mode
EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value
EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 319
ECCPx MUX bit:
ECCP2 MUX bit:
PIC18F85J90
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Fail-Safe Clock Monitor Enable bit:
Default/Reset System Clock Select bit:
ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4
ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontrol-ler mode or with RB3 in Extended Microcontroller mode
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 320
Oscillator Selection bits:
Watchdog Timer Postscaler Select bits:
ECCP2 MUX bit:
PIC18F8620
Oscillator Selection:
Osc. Switch Enable:
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontrol-ler mode or with RB3 in Extended Microcontroller mode
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 321
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
Processor Mode Selection:
External Bus Data Wait:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
MODE = EM Extended Microcontroller mode
MODE = MPB Microprocessor with Boot Block mode
MODE = MP Microprocessor mode
MODE = MC Microcontroller mode
WAIT = ON Enabled
WAIT = OFF Disabled
CCP2MUX = OFF Disabled
CCP2MUX = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 322
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 323
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F8621
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSC = ECIOPLL EC-OSC2 as RA6 and PLL
OSC = ECIOSWPLL EC-OSC2 as RA6 and SW PLL
OSC = HSSWPLL HS with SW PLL
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 324
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
Processor Mode Selection:
External Bus Data Wait:
MCLR Enable:
ECCP MUX:
CCP2 MUX:
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MODE = EM Extended Microcontroller mode
MODE = MPB Microprocessor with Boot Block mode
MODE = MP Microprocessor mode
MODE = MC Microcontroller mode
WAIT = ON Enabled
WAIT = OFF Disabled
MCLRE = OFF Disabled
MCLRE = ON Enabled
ECCPMX = PORTH Multiplexed with RH7:4
ECCPMX = PORTE Multiplexed with RE6:3
CCP2MX = PORTBE Multiplexed with RB3 or RE7
CCP2MX = PORTC Multiplexed with RC1
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 325
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 326
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F8622
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 327
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
Watchdog Timer Enable bit:
Watchdog Timer Postscale Select bits:
Processor Data Memory Mode Select bits:
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MODE = EM Extended Microcontroller mode
MODE = MPB Microprocessor with Boot Block mode
MODE = MP Microprocessor mode
MODE = MC Microcontroller mode
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 328
Address Bus Width Select bits:
Data Bus Width Select bit:
External Bus Data Wait Enable bit:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
ECCP MUX bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Boot Block Size Select bits:
ADDRBW = ADDR8BIT 8-bit Address Bus
ADDRBW = ADDR12BIT 12-bit Address Bus
ADDRBW = ADDR16BIT 16-bit Address Bus
ADDRBW = ADDR20BIT 20-bit Address Bus
DATABW = DATA8BIT 8-bit External Bus mode
DATABW = DATA16BIT 16-bit External Bus mode
WAIT = ON Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits
WAIT = OFF Wait selections are unavailable for table reads and table writes
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
ECCPMX = PORTH ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively
ECCPMX = PORTE ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively
CCP2MX = PORTBE ECCP2 is multiplexed with RB3 in Extended Micro-controller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode.
CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size
BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size
BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 329
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
Code Protection bit Block 3:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected
CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
CP3 = ON Block 3 (00C000-00FFFFh) code-protected
CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected
CPB = ON Boot Block (000000-0007FFh) code-protected
CPB = OFF Boot Block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected
WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 330
Write Protection bit Block 3:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Boot Block Table Read Protection bit:
WRT3 = ON Block 3 (00C000-00FFFFh) write-protected
WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected
WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) pro-tected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 331
PIC18F8627
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 332
Watchdog Timer Postscale Select bits:
Processor Data Memory Mode Select bits:
Address Bus Width Select bits:
Data Bus Width Select bit:
External Bus Data Wait Enable bit:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MODE = EM Extended Microcontroller mode
MODE = MPB Microprocessor with Boot Block mode
MODE = MP Microprocessor mode
MODE = MC Microcontroller mode
ADDRBW = ADDR8BIT 8-bit Address Bus
ADDRBW = ADDR12BIT 12-bit Address Bus
ADDRBW = ADDR16BIT 16-bit Address Bus
ADDRBW = ADDR20BIT 20-bit Address Bus
DATABW = DATA8BIT 8-bit External Bus mode
DATABW = DATA16BIT 16-bit External Bus mode
WAIT = ON Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits
WAIT = OFF Wait selections are unavailable for table reads and table writes
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 333
ECCP MUX bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Boot Block Size Select bits:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
ECCPMX = PORTH ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively
ECCPMX = PORTE ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively
CCP2MX = PORTBE ECCP2 is multiplexed with RB3 in Extended Micro-controller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode.
CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size
BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size
BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected
CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 334
Code Protection bit Block 3:
Code Protection bit Block 4:
Code Protection bit Block 5:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Write Protection bit Block 3:
Write Protection bit Block 4:
Write Protection bit Block 5:
Boot Block Write Protection bit:
CP3 = ON Block 3 (00C000-00FFFFh) code-protected
CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected
CP4 = ON Block 4 (010000-013FFFh) code-protected
CP4 = OFF Block 4 (010000-013FFFh) not code-protected
CP5 = ON Block 5 (014000-017FFFh) code-protected
CP5 = OFF Block 5 (014000-017FFFh) not code-protected
CPB = ON Boot Block (000000-0007FFh) code-protected
CPB = OFF Boot Block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected
WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
WRT3 = ON Block 3 (00C000-00FFFFh) write-protected
WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected
WRT4 = ON Block 4 (010000-013FFFh) write-protected
WRT4 = OFF Block 4 (010000-013FFFh) not write-protected
WRT5 = ON Block 5 (014000-017FFFh) write-protected
WRT5 = OFF Block 5 (014000-017FFFh) not write-protected
WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 335
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Table Read Protection bit Block 4:
Table Read Protection bit Block 5:
Boot Block Table Read Protection bit:
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) pro-tected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks
EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks
EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 336
PIC18F8680
Oscillator Selection bits:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC with OSC2 as divide by 4 clock out
OSC = EC EC with OSC2 as divide by 4 clock out
OSC = ECIO EC with OSC2 as RA6
OSC = HSPLL HS with HW enabled 4xPLL
OSC = RCIO RC with OSC2 as RA6
OSC = ECIOPLL EC with OSC2 as RA6 and HW enabled 4xPLL
OSC = ECIOSWPLL EC with OSC2 as RA6 and SW enabled 4xPLL
OSC = HSSWPLL HS with SW enabled 4xPLL
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 337
Watchdog Postscaler:
Processor Mode Selection:
External Bus Data Wait:
MCLR Enable:
CCP2 MUX bit:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MODE = EM Extended Microcontroller mode
MODE = MPB Microprocessor with Boot Block mode
MODE = MP Microprocessor mode
MODE = MC Microcontroller mode
WAIT = ON Enabled
WAIT = OFF Disabled
MCLRE = OFF Disabled
MCLRE = ON Enabled
CCP2MX = OFF CCP2 input/output is multiplexed with RE7
CCP2MX = ON CCP2 input/output is multiplexed with RC1
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 338
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Boot Block Write Protection:
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 339
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Boot Block Table Read Protection:
PIC18F86J10
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 340
Default/Reset System Clock Select bit:
Oscillator Selection bits:
Watchdog Timer Postscaler Select bits:
External Bus Wait Enable bit:
Data Bus Width Select bit:
Processor Mode Selection:
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
WAIT = ON Wait states for operations on external memory bus enabled
WAIT = OFF Wait states for operations on external memory bus disabled
BW = 8 8-bit external bus mode
BW = 16 16-bit external bus mode
MODE = MM Microcontroller mode - External bus disabled
MODE = XM12 Extended Microcontroller mode, 12-bit Address mode
MODE = XM16 Extended Microcontroller mode, 16-bit Address mode
MODE = XM20 Extended Microcontroller mode, 20-bit Address mode
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 341
External Address Bus Shift Enable bit:
ECCPx MUX bit:
ECCP2 MUX bit:
PIC18F86J15
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value
EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h
ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4
ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontrol-ler mode or with RB3 in Extended Microcontroller mode
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 342
Default/Reset System Clock Select bit:
Oscillator Selection bits:
Watchdog Timer Postscaler Select bits:
External Bus Wait Enable bit:
Data Bus Width Select bit:
Processor Mode Selection:
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
WAIT = ON Wait states for operations on external memory bus enabled
WAIT = OFF Wait states for operations on external memory bus disabled
BW = 8 8-bit external bus mode
BW = 16 16-bit external bus mode
MODE = MM Microcontroller mode - External bus disabled
MODE = XM12 Extended Microcontroller mode, 12-bit Address mode
MODE = XM16 Extended Microcontroller mode, 16-bit Address mode
MODE = XM20 Extended Microcontroller mode, 20-bit Address mode
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 343
External Address Bus Shift Enable bit:
ECCPx MUX bit:
ECCP2 MUX bit:
PIC18F86J60
Background Debugger Enable:
Extended Instruction Set Enable:
Stack Overflow Reset:
Watchdog Timer:
Code Protection:
Fail-Safe Clock Monitor:
Internal/External Switch Over:
Default/Reset System Clock Select Bit:
EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value
EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h
ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4
ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontrol-ler mode or with RB3 in Extended Microcontroller mode
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
WDT = OFF Disabled
WDT = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
FOSC2 = OFF INTRC as system clock when OSCCON<1:0> = 00
FOSC2 = ON FOSC<1:0> selects system clock for OSCCON<1:0> = 00
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 344
Oscillator Selection bits:
Watchdog Postscaler:
Ethernet LED Enable:
ECCP MUX:
CCP2 MUX:
PIC18F86J65
Background Debugger Enable:
Extended Instruction Set Enable:
Stack Overflow Reset:
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, Software Controlled PLL
FOSC = EC External Clock
FOSC = ECPLL External Clock, Software Controlled PLL
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
ETHLED = OFF Disabled
ETHLED = ON Enabled
ECCPMX = OFF Disabled
ECCPMX = ON Enabled
CCP2MX = OFF Disabled
CCP2MX = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 345
Watchdog Timer:
Code Protection:
Fail-Safe Clock Monitor:
Internal/External Switch Over:
Default/Reset System Clock Select Bit:
Oscillator Selection bits:
Watchdog Postscaler:
Ethernet LED Enable:
WDT = OFF Disabled
WDT = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
FOSC2 = OFF INTRC as system clock when OSCCON<1:0> = 00
FOSC2 = ON FOSC<1:0> selects system clock for OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, Software Controlled PLL
FOSC = EC External Clock
FOSC = ECPLL External Clock, Software Controlled PLL
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
ETHLED = OFF Disabled
ETHLED = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 346
ECCP MUX:
CCP2 MUX:
PIC18F8720
Oscillator Selection:
Osc. Switch Enable:
Power-up Timer:
Brown-out Reset:
Brown-out Voltage:
Watchdog Timer:
Watchdog Postscaler:
ECCPMX = OFF Disabled
ECCPMX = ON Enabled
CCP2MX = OFF Disabled
CCP2MX = ON Enabled
OSC = LP LP
OSC = XT XT
OSC = HS HS
OSC = RC RC
OSC = EC EC-OSC2 as Clock Out
OSC = ECIO EC-OSC2 as RA6
OSC = HSPLL HS-PLL Enabled
OSC = RCIO RC-OSC2 as RA6
OSCS = ON Enabled
OSCS = OFF Disabled
PWRT = ON Enabled
PWRT = OFF Disabled
BOR = OFF Disabled
BOR = ON Enabled
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 25 2.5V
WDT = OFF Disabled
WDT = ON Enabled
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 347
Processor Mode Selection:
External Bus Data Wait:
CCP2 MUX:
Stack Overflow Reset:
Low Voltage ICSP:
Background Debugger Enable:
Code Protection Block 0:
Code Protection Block 1:
Code Protection Block 2:
Code Protection Block 3:
Code Protection Block 4:
Code Protection Block 5:
MODE = EM Extended Microcontroller mode
MODE = MPB Microprocessor with Boot Block mode
MODE = MP Microprocessor mode
MODE = MC Microcontroller mode
WAIT = ON Enabled
WAIT = OFF Disabled
CCP2MUX = OFF Disabled
CCP2MUX = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
LVP = OFF Disabled
LVP = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
CP0 = ON Enabled
CP0 = OFF Disabled
CP1 = ON Enabled
CP1 = OFF Disabled
CP2 = ON Enabled
CP2 = OFF Disabled
CP3 = ON Enabled
CP3 = OFF Disabled
CP4 = ON Enabled
CP4 = OFF Disabled
CP5 = ON Enabled
CP5 = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 348
Code Protection Block 6:
Code Protection Block 7:
Boot Block Code Protection:
Data EEPROM Code Protection:
Write Protection Block 0:
Write Protection Block 1:
Write Protection Block 2:
Write Protection Block 3:
Write Protection Block 4:
Write Protection Block 5:
Write Protection Block 6:
Write Protection Block 7:
Boot Block Write Protection:
CP6 = ON Enabled
CP6 = OFF Disabled
CP7 = ON Enabled
CP7 = OFF Disabled
CPB = ON Enabled
CPB = OFF Disabled
CPD = ON Enabled
CPD = OFF Disabled
WRT0 = ON Enabled
WRT0 = OFF Disabled
WRT1 = ON Enabled
WRT1 = OFF Disabled
WRT2 = ON Enabled
WRT2 = OFF Disabled
WRT3 = ON Enabled
WRT3 = OFF Disabled
WRT4 = ON Enabled
WRT4 = OFF Disabled
WRT5 = ON Enabled
WRT5 = OFF Disabled
WRT6 = ON Enabled
WRT6 = OFF Disabled
WRT7 = ON Enabled
WRT7 = OFF Disabled
WRTB = ON Enabled
WRTB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 349
Configuration Register Write Protection:
Data EEPROM Write Protection:
Table Read Protection Block 0:
Table Read Protection Block 1:
Table Read Protection Block 2:
Table Read Protection Block 3:
Table Read Protection Block 4:
Table Read Protection Block 5:
Table Read Protection Block 6:
Table Read Protection Block 7:
Boot Block Table Read Protection:
WRTC = ON Enabled
WRTC = OFF Disabled
WRTD = ON Enabled
WRTD = OFF Disabled
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
EBTR1 = ON Enabled
EBTR1 = OFF Disabled
EBTR2 = ON Enabled
EBTR2 = OFF Disabled
EBTR3 = ON Enabled
EBTR3 = OFF Disabled
EBTR4 = ON Enabled
EBTR4 = OFF Disabled
EBTR5 = ON Enabled
EBTR5 = OFF Disabled
EBTR6 = ON Enabled
EBTR6 = OFF Disabled
EBTR7 = ON Enabled
EBTR7 = OFF Disabled
EBTRB = ON Enabled
EBTRB = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 350
PIC18F8722
Oscillator Selection bits:
Fail-Safe Clock Monitor Enable bit:
Internal/External Oscillator Switchover bit:
Power-up Timer Enable bit:
Brown-out Reset Enable bits:
Brown-out Voltage bits:
Watchdog Timer Enable bit:
OSC = LP LP oscillator
OSC = XT XT oscillator
OSC = HS HS oscillator
OSC = RC External RC oscillator, CLKO function on RA6
OSC = EC EC oscillator, CLKO function on RA6
OSC = ECIO6 EC oscillator, port function on RA6
OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
OSC = RCIO6 External RC oscillator, port function on RA6
OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
PWRT = ON PWRT enabled
PWRT = OFF PWRT disabled
BOREN = OFF Brown-out Reset disabled in hardware and software
BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN = NOSLP Brown-out Reset enabled in hardware only and dis-abled in Sleep mode (SBOREN is disabled)
BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = 0 Maximum setting
BORV = 1
BORV = 2
BORV = 3 Minimum setting
WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
WDT = ON WDT enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 351
Watchdog Timer Postscale Select bits:
Processor Data Memory Mode Select bits:
Address Bus Width Select bits:
Data Bus Width Select bit:
External Bus Data Wait Enable bit:
MCLR Pin Enable bit:
Low-Power Timer1 Oscillator Enable bit:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MODE = EM Extended Microcontroller mode
MODE = MPB Microprocessor with Boot Block mode
MODE = MP Microprocessor mode
MODE = MC Microcontroller mode
ADDRBW = ADDR8BIT 8-bit Address Bus
ADDRBW = ADDR12BIT 12-bit Address Bus
ADDRBW = ADDR16BIT 16-bit Address Bus
ADDRBW = ADDR20BIT 20-bit Address Bus
DATABW = DATA8BIT 8-bit External Bus mode
DATABW = DATA16BIT 16-bit External Bus mode
WAIT = ON Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits
WAIT = OFF Wait selections are unavailable for table reads and table writes
MCLRE = OFF RG5 input pin enabled; MCLR disabled
MCLRE = ON MCLR pin enabled; RG5 input pin disabled
LPT1OSC = OFF Timer1 configured for higher power operation
LPT1OSC = ON Timer1 configured for low-power operation
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 352
ECCP MUX bit:
CCP2 MUX bit:
Stack Full/Underflow Reset Enable bit:
Single-Supply ICSP Enable bit:
Boot Block Size Select bits:
Extended Instruction Set Enable bit:
Background Debugger Enable bit:
Code Protection bit Block 0:
Code Protection bit Block 1:
Code Protection bit Block 2:
ECCPMX = PORTH ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively
ECCPMX = PORTE ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively
CCP2MX = PORTBE ECCP2 is multiplexed with RB3 in Extended Micro-controller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode.
CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1
STVREN = OFF Stack full/underflow will not cause Reset
STVREN = ON Stack full/underflow will cause Reset
LVP = OFF Single-Supply ICSP disabled
LVP = ON Single-Supply ICSP enabled
BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size
BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size
BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled, RB6 and RB7 con-figured as general purpose I/O pins
CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected
CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
CP1 = ON Block 1 (004000-007FFFh) code-protected
CP1 = OFF Block 1 (004000-007FFFh) not code-protected
CP2 = ON Block 2 (008000-00BFFFh) code-protected
CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 353
Code Protection bit Block 3:
Code Protection bit Block 4:
Code Protection bit Block 5:
Code Protection bit Block 6:
Code Protection bit Block 7:
Boot Block Code Protection bit:
Data EEPROM Code Protection bit:
Write Protection bit Block 0:
Write Protection bit Block 1:
Write Protection bit Block 2:
Write Protection bit Block 3:
Write Protection bit Block 4:
Write Protection bit Block 5:
CP3 = ON Block 3 (00C000-00FFFFh) code-protected
CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected
CP4 = ON Block 4 (010000-013FFFh) code-protected
CP4 = OFF Block 4 (010000-013FFFh) not code-protected
CP5 = ON Block 5 (014000-017FFFh) code-protected
CP5 = OFF Block 5 (014000-017FFFh) not code-protected
CP6 = ON Block 6 (01BFFF-018000h) code-protected
CP6 = OFF Block 6 (01BFFF-018000h) not code-protected
CP7 = ON Block 7 (01C000-01FFFFh) code-protected
CP7 = OFF Block 7 (01C000-01FFFFh) not code-protected
CPB = ON Boot Block (000000-0007FFh) code-protected
CPB = OFF Boot Block (000000-0007FFh) not code-protected
CPD = ON Data EEPROM code-protected
CPD = OFF Data EEPROM not code-protected
WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected
WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
WRT1 = ON Block 1 (004000-007FFFh) write-protected
WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
WRT2 = ON Block 2 (008000-00BFFFh) write-protected
WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
WRT3 = ON Block 3 (00C000-00FFFFh) write-protected
WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected
WRT4 = ON Block 4 (010000-013FFFh) write-protected
WRT4 = OFF Block 4 (010000-013FFFh) not write-protected
WRT5 = ON Block 5 (014000-017FFFh) write-protected
WRT5 = OFF Block 5 (014000-017FFFh) not write-protected
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 354
Write Protection bit Block 6:
Write Protection bit Block 7:
Boot Block Write Protection bit:
Configuration Register Write Protection bit:
Data EEPROM Write Protection bit:
Table Read Protection bit Block 0:
Table Read Protection bit Block 1:
Table Read Protection bit Block 2:
Table Read Protection bit Block 3:
Table Read Protection bit Block 4:
WRT6 = ON Block 6 (01BFFF-018000h) write-protected
WRT6 = OFF Block 6 (01BFFF-018000h) not write-protected
WRT7 = ON Block 7 (01C000-01FFFFh) write-protected
WRT7 = OFF Block 7 (01C000-01FFFFh) not write-protected
WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
WRTC = ON Configuration registers (300000-3000FFh) write-pro-tected
WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
WRTD = ON Data EEPROM write-protected
WRTD = OFF Data EEPROM not write-protected
EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) pro-tected from table reads executed in other blocks
EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks
EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 355
Table Read Protection bit Block 5:
Table Read Protection bit Block 6:
Table Read Protection bit Block 7:
Boot Block Table Read Protection bit:
PIC18F87J10
Background Debugger Enable bit:
Extended Instruction Set Enable bit:
Stack Overflow/Underflow Reset Enable bit:
Watchdog Timer Enable bit:
Code Protection bit:
Fail-Safe Clock Monitor Enable bit:
EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks
EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
EBTR6 = ON Block 6 (018000-01BFFFh) protected from table reads executed in other blocks
EBTR6 = OFF Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks
EBTR7 = ON Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks
EBTR7 = OFF Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks
EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
DEBUG = OFF Background debugger disabled; RB6 and RB7 con-figured as general purpose I/O pins
XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST = ON Instruction set extension and Indexed Addressing mode enabled
STVREN = OFF Reset on stack overflow/underflow disabled
STVREN = ON Reset on stack overflow/underflow enabled
WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
WDTEN = ON WDT enabled
CP0 = ON Program memory is code-protected
CP0 = OFF Program memory is not code-protected
FCMEN = OFF Fail-Safe Clock Monitor disabled
FCMEN = ON Fail-Safe Clock Monitor enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 356
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
Default/Reset System Clock Select bit:
Oscillator Selection bits:
Watchdog Timer Postscaler Select bits:
External Bus Wait Enable bit:
Data Bus Width Select bit:
IESO = OFF Two-Speed Start-up disabled
IESO = ON Two-Speed Start-up enabled
FOSC2 = OFF INTRC enabled as system clock when OSC-CON<1:0> = 00
FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, PLL enabled and under software con-trol
FOSC = EC EC oscillator, CLKO function on OSC2
FOSC = ECPLL EC oscillator, PLL enabled and under software con-trol, CLK function on OSC2
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
WAIT = ON Wait states for operations on external memory bus enabled
WAIT = OFF Wait states for operations on external memory bus disabled
BW = 8 8-bit external bus mode
BW = 16 16-bit external bus mode
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 357
Processor Mode Selection:
External Address Bus Shift Enable bit:
ECCPx MUX bit:
ECCP2 MUX bit:
PIC18F87J60
Background Debugger Enable:
Extended Instruction Set Enable:
Stack Overflow Reset:
Watchdog Timer:
Code Protection:
Fail-Safe Clock Monitor:
MODE = MM Microcontroller mode - External bus disabled
MODE = XM12 Extended Microcontroller mode, 12-bit Address mode
MODE = XM16 Extended Microcontroller mode, 16-bit Address mode
MODE = XM20 Extended Microcontroller mode, 20-bit Address mode
EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value
EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h
ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4
ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3
CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontrol-ler mode or with RB3 in Extended Microcontroller mode
CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
WDT = OFF Disabled
WDT = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
FCMEN = OFF Disabled
FCMEN = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 358
Internal/External Switch Over:
Default/Reset System Clock Select Bit:
Oscillator Selection bits:
Watchdog Postscaler:
Ethernet LED Enable:
ECCP MUX:
CCP2 MUX:
PIC18F96J60
Background Debugger Enable:
IESO = OFF Disabled
IESO = ON Enabled
FOSC2 = OFF INTRC as system clock when OSCCON<1:0> = 00
FOSC2 = ON FOSC<1:0> selects system clock for OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, Software Controlled PLL
FOSC = EC External Clock
FOSC = ECPLL External Clock, Software Controlled PLL
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
ETHLED = OFF Disabled
ETHLED = ON Enabled
ECCPMX = OFF Disabled
ECCPMX = ON Enabled
CCP2MX = OFF Disabled
CCP2MX = ON Enabled
DEBUG = ON Enabled
DEBUG = OFF Disabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 359
Extended Instruction Set Enable:
Stack Overflow Reset:
Watchdog Timer:
Code Protection:
Fail-Safe Clock Monitor:
Internal/External Switch Over:
Default/Reset System Clock Select Bit:
Oscillator Selection bits:
XINST = OFF Disabled
XINST = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
WDT = OFF Disabled
WDT = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
FOSC2 = OFF INTRC as system clock when OSCCON<1:0> = 00
FOSC2 = ON FOSC<1:0> selects system clock for OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, Software Controlled PLL
FOSC = EC External Clock
FOSC = ECPLL External Clock, Software Controlled PLL
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 360
Watchdog Postscaler:
External Bus Data Wait:
Data Bus Width Select:
Processor Mode Selection:
External Address Bus Shift Enable:
Ethernet LED Enable:
ECCP MUX:
CCP2 MUX:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
WAIT = ON Enabled
WAIT = OFF Disabled
BW = 8 8-bit external bus
BW = 16 16-bit external bus
MODE = MM Microcontroller mode - External bus disabled
MODE = XM12 Extended Microcontroller mode - 12-bit Address mode
MODE = XM16 Extended Microcontroller mode - 16-bit Address mode
MODE = XM20 Extended Microcontroller mode - 20-bit Address mode
EASHFT = OFF External bus reflects PC value
EASHFT = ON External bus starts at 000000h
ETHLED = OFF Disabled
ETHLED = ON Enabled
ECCPMX = OFF Disabled
ECCPMX = ON Enabled
CCP2MX = OFF Disabled
CCP2MX = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 361
PIC18F96J65
Background Debugger Enable:
Extended Instruction Set Enable:
Stack Overflow Reset:
Watchdog Timer:
Code Protection:
Fail-Safe Clock Monitor:
Internal/External Switch Over:
Default/Reset System Clock Select Bit:
Oscillator Selection bits:
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
WDT = OFF Disabled
WDT = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
FOSC2 = OFF INTRC as system clock when OSCCON<1:0> = 00
FOSC2 = ON FOSC<1:0> selects system clock for OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, Software Controlled PLL
FOSC = EC External Clock
FOSC = ECPLL External Clock, Software Controlled PLL
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 362
Watchdog Postscaler:
External Bus Data Wait:
Data Bus Width Select:
Processor Mode Selection:
External Address Bus Shift Enable:
Ethernet LED Enable:
ECCP MUX:
CCP2 MUX:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
WAIT = ON Enabled
WAIT = OFF Disabled
BW = 8 8-bit external bus
BW = 16 16-bit external bus
MODE = MM Microcontroller mode - External bus disabled
MODE = XM12 Extended Microcontroller mode - 12-bit Address mode
MODE = XM16 Extended Microcontroller mode - 16-bit Address mode
MODE = XM20 Extended Microcontroller mode - 20-bit Address mode
EASHFT = OFF External bus reflects PC value
EASHFT = ON External bus starts at 000000h
ETHLED = OFF Disabled
ETHLED = ON Enabled
ECCPMX = OFF Disabled
ECCPMX = ON Enabled
CCP2MX = OFF Disabled
CCP2MX = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 363
PIC18F97J60
Background Debugger Enable:
Extended Instruction Set Enable:
Stack Overflow Reset:
Watchdog Timer:
Code Protection:
Fail-Safe Clock Monitor:
Internal/External Switch Over:
Default/Reset System Clock Select Bit:
Oscillator Selection bits:
DEBUG = ON Enabled
DEBUG = OFF Disabled
XINST = OFF Disabled
XINST = ON Enabled
STVR = OFF Disabled
STVR = ON Enabled
WDT = OFF Disabled
WDT = ON Enabled
CP0 = ON Enabled
CP0 = OFF Disabled
FCMEN = OFF Disabled
FCMEN = ON Enabled
IESO = OFF Disabled
IESO = ON Enabled
FOSC2 = OFF INTRC as system clock when OSCCON<1:0> = 00
FOSC2 = ON FOSC<1:0> selects system clock for OSCCON<1:0> = 00
FOSC = HS HS oscillator
FOSC = HSPLL HS oscillator, Software Controlled PLL
FOSC = EC External Clock
FOSC = ECPLL External Clock, Software Controlled PLL
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 364
Watchdog Postscaler:
External Bus Data Wait:
Data Bus Width Select:
Processor Mode Selection:
External Address Bus Shift Enable:
Ethernet LED Enable:
ECCP MUX:
CCP2 MUX:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
WAIT = ON Enabled
WAIT = OFF Disabled
BW = 8 8-bit external bus
BW = 16 16-bit external bus
MODE = MM Microcontroller mode - External bus disabled
MODE = XM12 Extended Microcontroller mode - 12-bit Address mode
MODE = XM16 Extended Microcontroller mode - 16-bit Address mode
MODE = XM20 Extended Microcontroller mode - 20-bit Address mode
EASHFT = OFF External bus reflects PC value
EASHFT = ON External bus starts at 000000h
ETHLED = OFF Disabled
ETHLED = ON Enabled
ECCPMX = OFF Disabled
ECCPMX = ON Enabled
CCP2MX = OFF Disabled
CCP2MX = ON Enabled
Configuration Settings
© 2006 Microchip Technology Inc. DS51537F-page 365
NOTES:
DS51537F-page 366 © 2006 Microchip Technology Inc.
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10/31/05