Future nanoelectronic device technologies - high-k, nanowire andalternative channel

January 13, 2010

Hiroshi Iwai1

IEEE AP & ED Joint MQ@IIT Bombay

Frontier Research CenterTokyo Institute of Technology

By Dr. Lu Terman, at IEDM 2009

Last year is a great year for Electron/Opt Devices!

Three IEEE Fellows Win 2009 Nobel Prize in Physics

“. . .for breakthroughs involving the transmission of light in fiber optics and inventing an imaging semiconductor circuit, the three scientists created the technology behind digital photography and helped link the world through fiber‐optic networks.”

(l-r)Dr. Charles K. Kao Dr. Willard S. Boyle Dr. George E. Smith

Nobel Prizes in Electron Devices1956 – The Transistor

William Shockley, John Bardeen, and Walter Brattain1973 – Tunneling Diode

Leo Esaki, Ivar Giaever– Josephson Junction

Brian David Josephson

2000 – Integrated CircuitJack Kilby

– Semiconductor Heterojunction DevicesZohres Alferov and Herbert Kroemer

2007 – Giant Magnetoresistive Effect (GMR)Albert Fert and Peter Grunberg

2009 – Charge Coupled DevicesGeorge Smith and Willard Boyle

– Fiber Optic TechnologyCharles Kao By Dr. Lu Terman, at IEDM 2009

By Dr. Lu Terman, at IEDM 2009

Global Internet 2009

By Dr. Lu Terman, at IEDM 2009

By Dr. Lu Terman, at IEDM 2009

By Dr. Lu Terman, at IEDM 2009

Sir Isaac Newton“If I can see so far, it is because I stand on the shoulders of giants”

By Dr. Lu Terman, at IEDM 2009

1010

1. Scaling

1900 1950 1960 1970 2000

VacuumTube

Transistor IC LSI ULSI

10 cm cm mm 10 µm 100 nm

In 100 years, the size reduced by one million times.There have been many devices from stone age.We have never experienced such a tremendous reduction of devices in human history.

10-1m 10-2m 10-3m 10-5m 10-7m

Downsizing of the components has been the driving force for circuit evolution

11

Downsizing1. Reduce Capacitance

Reduce switching time of MOSFETsIncrease clock frequency

Increase circuit operation speed2. Increase number of Transistors

Parallel processingIncrease circuit operation speed

Thus, downsizing of Si devices is the most important and critical issue.12

Downsizing contribute to the performance increase in double ways

1313

Drive current

Power per chip

Integration (# of Tr)

Scaling    K :   K=0.7 for example

Id = vsatWgCo (Vg‐Vth)

N

K‐1(αK‐2)K (K1 )2= α

Switching  speed KK/K= K

Id per unit Wg = Id / Wg= 1

Wg (tox –1)(Vg‐Vth)= Wgtox 

‐1(Vg‐Vth)= KK‐1K=Kin saturation

Co: gate C per unit area

Cg = εoεoxLgWg/tox

Id per unit Wg

Clock frequency

K

1

τ

Id

K

Id/µm

f 1/K f = 1/τ = 1/K

N α/K2

P α

Gate  capacitance Cg K

Chip area Achip α

Lg, WgTox, Vdd

Geometry &Supply voltage

K

KK/K = K

τ= CgVdd/Id

α: Scaling factor

α/K2

fNCV2/2

= 1/K2 , when α=1

= 1, when α=1

Downscaling merit: Beautiful!

In the past, α>1 for most cases

k= 0.72 =0.5if we keep the chip area the same for scaling

Single MOFET

Chip

Vdd 0.5Lg 0.5Id 0.5Cg 0.5P (Power)/Clock

0.53 = 0.125 τ (Switching time) 0.5

N (# of Tr) 1/0.52 = 4

P (Power)1/0.5 = 2f (Clock)1

2 Generationsscaling

Scaling down approach is very beautiful and imprtant

14

1515

10 -3

10 -2

10 -1

10 0

10 1

10 2

1970 1980 1990 2000

MPU Lg (µm)X

j (µm)

Minimum logic Vdd (V)

Id/µm(mA/µm)

tox (µm)

10 -3

10 -1

10 1

10 3

1970 1980 1990 2000

chip size （mm2）

Number of tr

ansistors

power (W

)

MIPSclock frequency (MHz)

Id/µm

Id

1 101

10‐1K (10 –2) f 1/K(10 2) 103

P α(10 1) 105

N α/K2(10 5) 104Achip α 101

Change in 30 years

Lg K 10 ‐2tox K(10 –2) 10‐2

Vdd K(10 –2) 10‐1

Idealscaling

RealChange

Idealscaling

RealChange

Idealscaling

RealChange

= fαNCV2

Past 30 years scaling

N, f increaseMerit:

Demerit: P increase

Vdd scaling insufficient

Additional significantincrease inId, f, P

Actual past downscaling trend until year 2000

Vd scaling insufficient, α increased N, Id, f, P increased significantly

Source. Iwai and S. Ohmi, Microelectronics Reliability 42 (2002), pp.1251-1268

- However, down-scaling of CMOS is still the‘royal road’* for high performance and low power.

- The concerns for limits of down-scaling havebeen announced for every generation.

- Effort for the down-scaling has to be continuedby all means.

17

1818

ITRS figure edited by Iwai

5.5nm?*

3 important innovations

-There will be still 4~6 generations left untilwe reach 11 ~ 5.5 nm technologies, at which we will reach down-scaling limit, in some year between 2020-30 (H. Iwai, IWJT2008).

-Even After reaching the down-scaling limit, we could still continueR & D, seeking sufficiently higher Id-sat under low Vdd.-Three important technologies

3. Alternative channel MOSFETs (III-V, Ge), maybe nanowire 2. Si Nanowire MOSFETs

- Other Beyond CMOS devices are still in the cloud.

1. High-k/metal gate stack with <0.5nm EOT, Silcide S/D

19

Before reaching the scaling limit, we need to pursuit the down scaling limit with conventional planar, or FINFET, introducing new materials such as (1) high-k/metal gate <0.5 nm EOT, and silicide S/D.

Then, (2) Si-nanowire FET

and then, (3) Alternative channel (III-V and Ge) .

20

Si Nanowire FET

F.-L.Yang, VLSI2004

FinFET to Nanowire

Ion/Ioff=230000Ion/Ioff=52200

Channel conductance is well controlled by Gateeven at L=5nm

21

22

Si nanowire FET as a strong candidateafter CMOS limitation1. Compatibility with

current CMOS process2. Good controllability of IOFF

3. High drive current

1D ballisticconduction

Multi quantumChannel High integration

of wires

k

E

量子チャネル

量子チャネル量子チャネル量子チャネル

バンド図

Quantum channelQuantum channel

Quantum channelQuantum channel

k

E

量子チャネル

量子チャネル量子チャネル量子チャネル

バンド図

Quantum channelQuantum channel

Quantum channelQuantum channel

Off電流のカットオフ

Gate:OFFDrain Source

cut-off

Gate: OFFdrainsource

Off電流のカットオフ

Gate:OFFDrain Source

cut-off

Gate: OFFdrainsource

by the courtesy of Professor H. Iwai

1

10

100

1000

10000

0 1000 2000 3000 4000

bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)

Bulk

DG

dia~3nm

dia~10nm

ITRS (SOI)

ITRS (DG)

ITRS(Bulk)

Si Nanowire

Ion (uA/um)

Ioff

(nA

/um

)

1

10

100

1000

10000

0 1000 2000 3000 4000

bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)

1

10

100

1000

10000

0 1000 2000 3000 4000

bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)

Bulk

DG

dia~3nm

dia~10nm

ITRS (SOI)

ITRS (DG)

ITRS(Bulk)

Si Nanowire

Ion (uA/um)

Ioff

(nA

/um

)Off Current

23

1D conduction per one quantum channel:G = 2e2/h = 77.8 µS/wire or tuberegardless of gate length and channel material

That is 77.8 microA/wire at 1V supply

This an extremely high value

However, already 40-50 micro A/wire was obtained by our experiments

Increase the Number of quantum channels

Energy band of Bulk Si

Eg

By Prof. Shiraishi of Tsukuba univ.

Energy band of 3 x 3 Si wire

4 channels can be used

Eg

25

Maximum number of wires per 1 µm

Surrounded gate type MOS

Front gate type MOS 165 wires /µm

33 wires/µm

High-k gate insulator (4nm)Si Nano wire (Diameter 2nm)

Metal gate electrode(10nm)

Surrounded gate MOS

30nm

6nm6nm pitchBy nano-imprint method

30nm pitch: EUV lithograpy

26

SiSiGe

SiSiGe

...

Selective EtchingDry EtchingSi/SiGe multistacked wafer

H2 Annealing

SiSiGeSi

(c) Selective Etching

(b) Dry Etching(a) Si/SiGe/Siepitaxial wafer

(d) H2 Annealing

(e) Gate Oxide (f) Gate, S/D Formation

SiSiGeSi

(c) Selective Etching

(b) Dry Etching(a) Si/SiGe/Siepitaxial wafer

(d) H2 Annealing

(e) Gate Oxide (f) Gate, S/D Formation

Increase the number of wires towards vertical dimension

27

Theoretical model of SiNW FET

Landauer Formalism for Ballistic FETPotential Energy

µS

µD

xO xmax xmin

From xmax to xmin

[ ][ ]∑

⎭⎬⎫

⎩⎨⎧

−+−+

⎟⎟⎠

⎞⎜⎜⎝

⎛=

i BiD

BiSi

BD TkE

TkEgqTkGI

/)(exp1/)(exp1ln

0

00 µ

µ

k

Energy

µSµD

E0

E1

E2min

E2max

qVD

E2min

Qf

Qb

Carrier Density obtained from E-k Band

=+= bf QQQ

)(exp1)(exp1

min

min

⎥⎥⎥⎥⎥

⎦

⎤

⎭⎬⎫

⎩⎨⎧ −

++

⎢⎢⎢⎢⎢

⎣

⎡

⎭⎬⎫

⎩⎨⎧ −

+= ∫∫∑

∞−

∞ i

i

k

B

Dik

B

Sii

i

TkkE

dk

TkkE

dkgqµµπ

µS

µD

xO xmax xmin

Qf

Qb

qVD

φG

Qb Qf

μS

Nanowire InsulatorGate

Energy

Position

qVG

0Fo

re

Cha

nnel

Bac

k C

hann

el

μDμ0

qVsub

φp

Insulator

ϕ1ϕ2

ϕ3

ϕ4

Substrate

CGCp

)( 0

qVV

CQ S

tGG

µµα −−−=

G

P

CC

+= 1α

Carrier Density obtained from Band Diagram

0

5

10

15

20

25

30

35

40

0 0.1 0.2 0.3 0.4 0.5

Drain Bias (V)

Current (uA)

IV Characteristics of Ballistic SiNW FET

T=1KT=300K

Vg-Vt=1.0 V

0.7 V

0.3 V

0.05 V

Small temperature dependency35µA/wire for 4 quantum channels

Model of Carrier Scattering

ChannelOpticalPhonon

Initial ElasticZone

Optical PhononEmission Zone

ε~kBT

ε*

Source

TransmissionProbability : Ti

Elastic Backscatt.Elastic Backscatt.＋（Optical Phonon Emission）

x00x

V(x)

F(0)

G(0)

Linear Potential Approx. ： Electric Field E

TransmissionProbability to Drain

To Drain

0Drain fromInjection )0()0()0()(

=⎟⎟⎠

⎞−=

FGFT ε

Résumé of the Compact Model

.)( 0

G

bfStG C

QQ

qVV

+=

−−−

µµα

.

22

ln

2

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

−+

++=

oxox

oxox

oxG

ttrttr

Cεπ

0 1 1 ( ( ))( ) ( ) ( )1 exp 1 exp 1 exp

f b i i ii i S i S i D

B B B

q dkQ Q g T k dkk k kk T k T k T

επ ε µ ε µ ε µ

∞

−∞ −∞

⎤⎡ ⎧ ⎫⎥⎢ ⎪ ⎪

⎪ ⎪ ⎥⎢+ = − −⎨ ⎬ ⎥⎢ ⎧ ⎫ ⎧ ⎫ ⎧ ⎫− − −⎪ ⎪+ + + ⎥⎢ ⎨ ⎬ ⎨ ⎬ ⎨ ⎬⎪ ⎪⎢ ⎥⎩ ⎭ ⎩ ⎭ ⎩ ⎭⎣ ⎩ ⎭ ⎦

∑ ∫ ∫

.ln

2

⎟⎠⎞

⎜⎝⎛ +

=

rtr

Cox

oxG

επDDS qV=− µµ

Unknowns are ID, (µS-µ0), (µD-µ0),および (Qf+Qb)

[ ]( , ) ( , )i s D ii

qI g f f T dε µ ε µ επ

= −∑ ∫h

( )0

00 0 0 0 0

2( )

2 ln

D qET

qExB D D qE mD Bε

εε

=+⎛ ⎞+ + + ⎜ ⎟

⎝ ⎠

PlanarGate

GAA

(Electrostatics requirement)

(Carrier distributionin Subbands)

I-VD Characteritics (RT)

Electric current ２０～25 µANo satruration at Large VD

0

5

10

15

20

25

30

35

40

45

0 0.1 0.2 0.3 0.4 0.5 0.6

Drain Bias [V]

Current [uA]

VG-Vt=0.1V,Bal.

VG-Vt=0.1V,Qbal

VG-Vt=0.4V,Bal.

VG-Vt=0.4V,Qbal.

VG-Vt=0.7V,Bal.

VG-Vt=0.7V,Qbal.

VG-Vt=1.0V,Bal.

VG-Vt=1.0V,Qbal.

Cross section of Si NW

[001] [011] [111]D=1.96nm D=1.94nm D=1.93nm

First principal calculation, TAPP

Si nanowire FET with 1D Transport[001] [011] [111]0.86 0.94 0.89

OrientationDiameter (nm)

[001] [011] [111]3.00 3.94 1.93

OrientationDiameter (nm)

ZG G GZ ZWave Number

ZG G GZ ZWave Number

Ener

gy (e

V)

0

-1

0

1

Ener

gy (e

V)

0

-1

0

1

(a)

(b)

Small mass with [011]

Large number of quantum channels with [001]

0

0.5

1

1.5

2

2.5

3

0 1 2 3 4 5 6Diamreter (nm)

Effe

ctiv

e m

ass

of h

ole

(m0)

[100][110][111]

0

0.1

0.2

0.3

0.4

0.5

0 1 2 3 4 5 6Diameter (nm)

Effe

ctiv

e m

ass

of e

lect

ron

(m0)

[100][110][111]

Effective mass

Lighter effective masses make conductance higher

[110] [111]>>[100]

[110][111] >[100]Electron

Hole

Electron Hole

lighter

0

2

4

6

8

10

0 1 2 3 4 5 6Diameter (nm)

Num

ber o

f qua

ntum

chan

nels

for V

B

[100][110][111]

0

2

4

6

8

10

0 1 2 3 4 5 6Diameter (nm)

Num

ber o

f qua

ntum

chan

nels

for C

B

[100][110][111]

Numbers of Quantum Channels

Quantum channels increase in large wire

Quantum channels denote subband edges within 0.1 eV from CBM and VBM

CB VB

[110][111] < [100]

[110] < [100]CB

VB <[111]

Quantum channel Passage for transport

more

4

3

2

1

0

-1

-2

(eV

)

1.0

0.8

0.6

0.4

0.2

0.0DO

S ( S

tate

s / e

V a

tom

)

-12 -10 -8 -6 -4 -2 0 2(eV)

d=1nm, Si21H20 (41 atoms), Eg=2.60 eV

2.0

1.5

1.0

0.5

0.0

-0.5

-1.0

(eV

)

1.0

0.8

0.6

0.4

0.2

0.0DO

S ( S

tate

s / e

V a

tom

)

-12 -10 -8 -6 -4 -2 0 2(eV)

2.0

1.5

1.0

0.5

0.0

-0.5

-1.0

(eV

)

1.0

0.8

0.6

0.4

0.2

0.0DO

S ( S

tate

s / e

V a

tom

)

-12 -10 -8 -6 -4 -2 0 2(eV)

d=4nm, Si341H84 (425 atoms), Eg=0.81 eV

d=8nm, Si1361H164 (1525 atoms), Eg=0.61 eV

T2K-TsukubaTheoretical Peak Performance : 95 TFLOPSCPU : Quad-core Opteron 2.3GHz (×4 CPUs×648 nodes)

PACS-CSTheoretical Peak Performance : 14 TFLOPSCPU : LV Xeon 2.8GHz (×1 CPU×2560 nodes)

10 nm diameter Si nanowired with 14,366-atom model

Collboration with Prof. Oshiyama and Iwata of Univ. of Tokyo

SiNW FET Fabrication

S/D&Fin Patterining(ArF Lithography and RIE Etching)

Sacrificial Oxidation & Oxide Removal (not completely released from BOX layer)

Sidewall Formation (oxide support protector)

SALISIDE Process

S/D&Fin Patterining(ArF

(not completely released from BOX layer)

Nanowire

Gate Oxidation (5nm) & Poly-Si Deposition (75nm)

Gate Lithography & RIE Etching

Ni

Gate Sidewall Formation

S/D&Fin Patterining(ArF Lithography and RIE Etching)

Sacrificial Oxidation & Oxide Removal (not completely released from BOX layer)

Sidewall Formation (oxide support protector)

SALISIDE Process

S/D&Fin Patterining(ArF

(not completely released from BOX layer)

Nanowire

Gate Oxidation (5nm) & Poly-Si Deposition (75nm)

Gate Lithography & RIE Etching

Ni

Gate Sidewall Formation

Brief process flow of Si Nanowire FET

42

Nanowire Sidewall(SiN)

Si channel

Nanowire Sidewall(SiN)

Si channel

(a) Fin structure formed on BOX layer. (b)XTEM image of fin shown in (a) (c) XTEM image after sacrificial oxidation (d) Cross sectional SEM image after partial removal of sacrificial oxide (e) XTEM after nanowire sidewall formation

43

SiNW FET Fabrication

Sacrificial Oxidation

SiN sidewall support formation

Ni SALISIDE Process (Ni 9nm / TiN 10nm)

S/D & Fin Patterning

Gate Oxidation & Poly-Si DepositionGate Lithography & RIE EtchingGate Sidewall Formation

30nm

30nm

30nm

Oixde etch back

Standard recipe for gate stack formationBackend

(a) SEM image of Si NW FET (Lg = 200nm) (b) high magnification observation of gate and its sidewall.

45

Fabricated SiNW FET

30nm

Poly-Si

SiN

Nanow

ire

SiN support

SiNW

IdVg and IdVd Characteristics

Ion/Ioff ratio of ~107, high Ion of 49.6 µA/wire

0

10

20

30

40

50

0.0 0.2 0.4 0.6 0.8 1.0Drain Voltage (V)

Driv

e C

urre

nt (

µA)

Vg-Vth=1.0V

Vg-Vth=0.8V

Vg-Vth=0.6V

Vg-Vth=0.4V

1.0 -0.5 0.0 0.5 1.0Gate Voltage (V)

102

100

10-2

10-4

10-6

Driv

e C

urre

nt (µ

A)

VD=0.05V

VD=1.0V

S.S.= 71mV/dec Vth=-0.36VLg=200nm

35nm

25nm

35nm

25nm

(a)

-1.0 -0.5 0.0 0.5 1.0Gate Voltage (V)

102

100

10-2

10-4

10-6

Driv

e C

urre

nt (µ

A)

VD=0.05V

VD=1.0V

S.S.= 71mV/dec Vth=-0.36VLg=200nm

35nm

25nm

35nm

25nm

(a)

-

ION

0

200

400

600

800

0.E+00 5.E+12 1.E+13 2.E+13

Effective mobility extraction

Lg=500nmNumber of NWs :64

Effe

ctiv

e el

ectr

on m

obili

ty (c

m2 /V

s)

Univ. curve Si (100)

measured at RT

SourceDrain

5µm

Inversion Carrier Density (cm-2)

0

10

20

30

40

50

60

0 10 20 30 40 50D (nm)

I ON(µ

A)

(500)(400)(300)

(250)

(200)

(350)

(5) (650)

(8)

(30)

(15)(25)

(490)

(15)

(350)

(25)(30)

(Vg-Vth=1.0V)

nMOSpMOS

smallLg

our result

0

10

20

30

40

50

60

0 10 20 30 40 50D (nm)

I ON(µ

A)

(500)(400)(300)

(250)

(200)

(350)

(5) (650)

(8)

(30)

(15)(25)

(490)

(15)

(350)

(25)(30)

(Vg-Vth=1.0V)

nMOSpMOS

smallLg

our result

Comparison of Si NW FET being already reported with Si NW FETs in this work

49

10nm

10nm 18nm 25nm

wire formation(a)

(b)

BOX

sub.

(A) (B) (C)

10nm 10nm

??

Output characteristics of 10x10cm2

SiNW FET

Gate voltage (V)-1.0 -0.5 0 0.5 1.0

Vd=1.0V

Vd=50mV

Lg=160nmTox=3nm

(A)10x10nm2

10-15

10-13

10-11

10-9

10-5

10-3

10-7

Dra

in c

urre

nt (A

)

0 0.2 0.4 0.6 0.8 1.0

40353025201510

50

Dra

in c

urre

nt (µ

A)

Drain voltage (V)

Vg-Vth=1.2V(step 0.2V)

0 0.2 0.4 0.6 0.8 1.0

40353025201510

50

Dra

in c

urre

nt (µ

A)

Drain voltage (V)

Vg-Vth=1.2V(step 0.2V)

05

10152025303540

1 10 100 1000Gate Length (nm)

ION

(µA

)

(8.5)

(10)

(10)

(8)

(8)(8)

(10)(3)(3)

(19)

(30)

10x25nm2

our workNMOS PMOS

10x18nm210x10nm2

Obtained Ion with reported data

Even with large Lg, fairly nice ION have been achieved

D

S

W

Si nanowire

G

Si nanowireD

S

W

Si nanowire

G

Si nanowireD

S

W

Planer

G

D

S

W

Planer

G

D

S

W

Si nanowire

G

Si nanowireD

S

W

Si nanowire

G

Si nanowireD

S

W

Planer

G

D

S

W

Planer

G

Occupying area of Si bulk planar FET and Si NW FET. Drive current should be compared with the same width, W

53

Year half-pitch (nm), P

2010 452014 282018 182022 11

(based on ITRS2008update)

SOI

wire

S S SS S

Numbers of wires are determined by the lithographic technology

1000(nm)

(at D>P/2)

#N= Por 1000(nm)

D+P/2(at D<P/2)

D

On current evaluation base on gate width

2010 2014 2018 20220

500

1000

1500

2000

2500

3000

3500I O

N(µ

A/µ

m)

YearSample (A) Lg=160nm, 10x10nm2

bulkSOI

DGITRS 75µA/wire

50µA/wire

25µA/wireTox scaling from3nm to 1.5nm

Lg scaling from160nm to 80nm

x2

x1.5

Performance of SiNW FET in ITRS

With device scaling in Tox and Lg, SiNW FET can exceed the required performance in ITRS

Relationship between mobility and high-k interface propertiesin advanced Si and SiGe nanowiresK. Tachi,, M. Casse, D. Jang2, C. Dupré, A. Hubert, N. Vulliet, V. Maffini-Alvaro,C. Vizioz1,C. Carabasse1, V. Delaye, J. M. Hartmann, G. Ghibaudo,H. Iwai4, S. Cristoloveanu, O. Faynot, and T. Ernst1

Joint work with LETI

Si Nanowire FET

1. Good I-off control2. High I-on

3. Fully compatible to Si-LSI process

Most promising candidate for16 or 11 nm CMOS and beyond

Many things to do for Si nanowire FETs

1. No optimum diameter/orientation/,

both from theory and experiments

2. No compact model for I-V exists,with diameter, orientation, cross-sectionshape, gate length as a parameter.

cross-section shape are known,

3. So many unknown things;

Mobility, Oxidation, Strain, etc.

2015 2020 2025 2030 20352015 2020 2025 2030 2035

Cloud

Beyond the horizon

2010

?More Moore

ITRS Beyond CMOS

? ? ?? ? ? More Moore ??

ITRS

PJT(2007~2012)

2007

Horizon

Extended CMOS: More Moore + CMOS logic

Ribbon

Tube

Extended CMOS

Si Fin, Tri-gate

Si Nano wire

III-V Ge Nano wire

製品段階

開発段階

研究段階

Production

Research

Development

Natural direction of downsizing

Diameter = 2nm

Si Channel

Nanowire

Tube, Ribbon

Selection

-

Problem：Mechanical Stress, Roughness

1D - High conduction

More perfect crystal

CNT

Graphene

Diameter = 10nm Problem：Hiigh-k gate oxides, etching of III-V wire

Further higher conductionBy multi quantum channel Selection

Our new roadmap

High conductionBy 1D conduction

60

61

10-5

10-4

10-3

10-2

10-1

100

101

102

1970 1990 2010 2030 2050Year

MPU LgJunction depthGate oxide thickness

Direct-tunneling limit in SiO2

ITRS Roadmap(at introduction)

Wave length of electron

Distance between Si atomsSize

(µm

), V

olta

ge(V

)

Min. V supply

10 nm3 nm

0.3 nm

ULTIMATELIMIT

10-5

10-4

10-3

10-2

10-1

100

101

102

1970 1990 2010 2030 205010-5

10-4

10-3

10-2

10-1

100

101

102

1970 1990 2010 2030 2050Year

MPU LgJunction depthGate oxide thickness

Direct-tunneling limit in SiO2

ITRS Roadmap(at introduction)

Wave length of electron

Distance between Si atomsSize

(µm

), V

olta

ge(V

)

Min. V supply

10 nm3 nm

0.3 nm

ULTIMATELIMIT

Scaling Limit in MOSFET

By Robert Chau, IWGI 2003

62

High‐k Thin Film for Gate InsulatorMOSFET

p-type substrate

n+ channel n+source SiO2

gatedrain

p-type substrate

n+ channel n+source

High-k

gate

drain

63Source: 2007 ITRS Winter Public Conf.

Gate oxide scaling is very important also for suppressing the variation.

Nor

mal

ized

σVt

hRandom Variability Reduction Scenarioin ITRS 2007

64

Historical trend of high-k R& D

1st FET LSIPMOS NMOS CMOS

IC

Gate insulator

Gate electrode

1960 1970 1980 1990 2000 05

MOSFETGate Stackin production

SiO2 SiOxNy

DoublePoly SiAl N+Poly Si

Silicide above Poly Si electrode TiSi2 CoSi2WSi2MoSi2 NiSi

MOSFET

DRAM Capacitor

NV Memory

Analog/RF

Al2O3, ZrO2

Ni3Si4 Stack NO(Ni3Si4/SiO2)

R&D for high-k

NO, AO (Al2O3/SiO2)

Recent new high-kPure Si Period

(O)NO, Ni3Si4

(O)NO, Ni3Si4Ta2O5 , Al2O3,

Ta2O5 ,

65

R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)

●

● Gas or liquidat 1000 K

●H

○Radio activeHe

● ● ● ● ● ●Li Be B C N O F Ne① ● ● ● ●Na Mg Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ① ● ● ● ●K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ① ① ① ① ● ●Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe● ③ ① ① ① ① ① ● ● ● ● ① ① ○ ○ ○Cs Ba ★ Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn○ ○ ○ ○ ○ ○ ○ ○Fr Ra ☆ Rf Ha Sg Ns Hs Mt

○La Ce Pr Nd PmSmEu GdTb Dy Ho Er TmYｂ Lu○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr

★

☆

Candidates

● ●Na Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ● ● ● ●K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ①

○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr

★

☆

②

③

Unstable at Si interfaceSi + MOX M + SiO2①

Si + MOX MSiX + SiO2

Si + MOX M + MSiXOY

Choice of High-k

HfO2 based dielectrics are selected as the first generation materials, because of their merit in1) band-offset, 2) dielectric constant3) thermal stability

La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer

66

0 V

1.1 V

V > 1 Ve

V > 1 Vh

OxideSi

CB

VB

-6

-4

-2

0

2

4

6

Ene

rgy

(eV

)

SiO2

4.4

3.5

1.1

2.4

1.8

0.3

3.0

-0.1

2.3

Si3N4Ta2O5

SrTiO3

BaZrO3

ZrO2

Al2O3

Y2O3

La2O3

ZrSiO4HfSiO4

4.9

2.82.3

2.6 3.4

1.51.5

3.43.3

1.4

3.4

0.8

Si HfO2

1.9

2.1

LaAlO3

J Robertson, J Vac Sci Technol B 18 1785 (2000)

Band Offsets Calculated value

Dielectric constantSiO2; 4Si3N4: ~ 7Al2O3: ~ 9

Y2O3; ~10Gd2O3: ~10

HfO2; ~23La2O3: ~27

HfO2 was chosen for the 1st generationLa2O3 is more difficult material to treat

0 10 20 30 40 50Dielectric Constant

4

2

0

-2

-4

-6

SiO2

Ban

d D

isco

ntin

uity

[eV]

Si

kB *φ : Figure of Merit of High-k

T. Hattori, INFOS , 2003

SiO2 3.9AlxSiyOz(Ba,Sr)TiO3 200-300BeAl2O4 8.3-9.43CeO2 16.6-26CeHfO4 10-20CoTiO3/Si3N4EuAlO3 22.5HfO2 26-30Hf silicate 11La2O3 20.8LaScO3 30La2SiO5MgAl2O4

NdAlO3 22.5PrAlO3 25Si3N4 7SmAlO3 19SrTiO3 150-250Ta2O5 25-24Ta2O5-TiO2TiO2 86-95TiO2/Si3N4Y2O3 8-11.6YxSiyOzZrO2 22.2-28Zr-Al-OZr silicate(Zr,Sn)TiO4 40-60

C.A. Billmann et al.,, MRS Spring Symp., 1999,R.D.Shannon, J. Appl. Phys., 73, 348, 1993S. De Gebdt, IEDM Short Coyuse, 2004

Dielectric constant value vs. Band offset (Measured)

68

Too large high-k cause significant short channel effect

SiO2

Too largehigh-k

Gate

DrainSource

Substrate

ε r = 3.9

Gate

DrainSource

Substrate

ε r = 3.9

DrainSource

Substrate

Gateε r = 390

-2 0 2 40

0.01

0.02

0.03

0.04

0.05I d

(mA

)

Vg (V)

Lg =0.04μmVd = 0.1VEOT = 2nm

K = 3.9SiO2

K = 390Too largeHigh-k

gate

ε r = 3.9

Oxidefilm

Magnified100 timesin vertical direction

Vg= 0V, Vd=0.5V

Source Drain

gate

outsideε r = 3.9

oxide

filmε r = 390

Vg= 0V, Vd=0.5VToo largehigh-kSiO2

Penetration of lateral field from Drain through high-k causes significant short channel effects

The oxides become hydroxide and carbonate in H2O and CO2 ambient.

Ln2O3

n-Si(100)

Ln2O3

n-Si(100)

Ln2(CO3)3

Ln2O3 + H2O → Ln2O3・H2O

Ln2O3 + H2O → 2(LnOOH)

2Ln(OH) + H2O → 3Ln2(OH)3

Ln2O3

n-Si(100)

Ln2(OH)3

n-Si(100)

Ln2O3 + CO2→ Ln2O2(CO3)

hydroxide carbonate

※Ln：Lanthanide

Absorption of moisture and CO2

70

Hygroscopic Properties of La2O3

After 30 hours in clean room (temperature & humidity controlled)

Ln2O3

n-Si(100)

Ln2O3 + H2O → Ln2O3・H2O

Ln2O3・H2O → 2(LnOOH)

LnOOH + H2O → Ln(OH)3

Ln(OH)3

n-Si(100)

Ln2O3

n-Si(100)

Ln2O3 + H2O → Ln2O3・H2O

Ln2O3・H2O → 2(LnOOH)

LnOOH + H2O → Ln(OH)3

Ln(OH)3

n-Si(100)

Ln2O3

n-Si(100)

Ln2(CO3)3Ln2O3

n-Si(100)Ln2O3 + 2CO2→ Ln2(CO3)3

Ln2O3

n-Si(100)

Ln2(CO3)3Ln2O3

n-Si(100)Ln2O3 + 2CO2→ Ln2(CO3)3

Temperature: ~20oCHumidity: 80%Humidification time:

0 ~120 hrs

ThermometerHygrometer

Samples

Ultra pure water

acryl(PMMA)or glass(PYREX)

*PMMA : CH2C(CH)3COOCH3

glass(PYREX)

acryl(PMMA)

Experimental apparatus

1

Yb 2O

3G

d 2O3

Dy 2O

3Zr

O2

SiO

21

2Lu

2O3

Eu2O

3Sm

2O3

Pr2O

3La

2O3

CET

120h

rs/C

ETfr

esh CET120hrs/CETFresh

Change of CET for all studied

n-Si(100)

Al electrode

High-k film

moisture

with electrode C-V

n-Si(100)High-k film

～ ～～

0

0.5

1

1.5

-2 -1 0 1

Fresh24hrs (with electrode)

Cap

acita

nce

(µF/

cm2 )

Voltage (V)

Pr2O3 / n-Si(100)

R.T.-depo

RTA : N2600oC

Absorption test in case of acryl apparatusafter the Al electrode formation

Moisture absorption is protected

74

R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)

●

● Gas or liquidat 1000 K

●H

○Radio activeHe

● ● ● ● ● ●Li Be B C N O F Ne① ● ● ● ●Na Mg Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ① ● ● ● ●K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ① ① ① ① ● ●Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe● ③ ① ① ① ① ① ● ● ● ● ① ① ○ ○ ○Cs Ba ★ Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn○ ○ ○ ○ ○ ○ ○ ○Fr Ra ☆ Rf Ha Sg Ns Hs Mt

○La Ce Pr Nd PmSmEu GdTb Dy Ho Er TmYｂ Lu○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr

★

☆

Candidates

● ●Na Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ● ● ● ●K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ①

○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr

★

☆

②

③

Unstable at Si interfaceSi + MOX M + SiO2①

Si + MOX MSiX + SiO2

Si + MOX M + MSiXOY

Choice of High-k

HfO2 based dielectrics are selected as the first generation materials, because of their merit in1) band-offset, 2) dielectric constant3) thermal stability

La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer

Remote scattering is dominant

High-κHigh-κ

Poly-Si gate

SiO2SiO2

- - -

-+

source draine-

channel

Fixed charge

Phase separation Crystallization

Remote surface roughness

Remote phonon

+-

Interfacial dipole

Hf+4

O-2

Mobility degradation causes for High-k MOSFETs (HfO2, Al2O3 based oxide)

S. Saito et al., IEDM 2003, S. Saito et al., ECS Symp. on ULSI Process Integration

76

PMOS

High‐k gate insulator MOSFETs for Intel:  EOT=1nm

EOT: Equivalent Oxide Thickness

77

0

100

200

300

400

500

0 1 2 3

EOT ( nm )

µef

f ( c

m2 /V

s )

HfO2HfSiONHfAlO(N)HfONHfTaOTiO2/HfO2

[6]

[2] D2 anneal

[1] D2 anneal

[3] low temp. process

[4]

[5]

[1] [2] [3] [5]

Y. Nara, Selete Sypm.

[4]

Present Status of  high‐k Research

HfSiON：- High effective mobility even at EOT=1nm- Thermal stability- IL of 0.5~0.7nm is essential for high µ- Difficult to achieve EOT<0.7nm ?

EOT [nm]

[A/c

m2 ] H

fO2 , H

fSiON

, HfA

lON

SiO 2

10 1

0 0.5 1 1.5 2

10 -1

10 -4

ゲート電極HfO 2,HfSiONHfAlON

界面層(SiON , SiO 2)

EOT [nm]

Cur

rent

Den

sity

[A/c

m2 ] H

fO2 , H

fSiON

, HfA

lON

SiO 2

10 1

0 0.5 1 1.5 2

10 -1

10 -4

GateHfO 2,HfSiONHfAlON

IL(SiON , SiO 2)

Reported Gate Leakage Curent

[1]C. Choi, VLSII05[2]R. Choi, IEDM02[3]Y. Akasaka, VLSI05[4]S. J. Rhee, IEDM04[5] L. A. Rangersson, VLSI05[6]C. H. Choi, IEDM02[7]S. J. Rhee, VLSI05

78Year

Pow

er p

er M

OSF

ET (P

)

P∝L

g 3

(Scaling)

EOT Limit0.7~0.8 nm

EOT=0.5nm

TodayEOT=1.0nm

Now

45nm nodeLg=22nm

One order of Magnitude

Si

HfO2

Metal

SiO2/SiON

Si

High-k

Metal

Direct ContactOf high-k and Si

Si

MetalSiO2/SiON

0.5～0.7nm

Introduction of High-kStill SiO2 or SiONIs used at Si interface

For the past 45 yearsSiO2 and SiON

For gate insulator

EOT can be reduced further beyond 0.5 nm by using direct contact to SiBy choosing appropriate materials and processes.

79

Si

High-k High-k High-k

SiOx interfacial layer (typ.0.5~0.7nm)

Scaling in EOTlimit

excess gate leakage

High-k for Further Scaling

0

0.2

0.4

0.6

0.8

1

1.2

2007 2012 2017 2022

ITRS2007

Bulk

SOIDG

Year

EOT

(nm

)

EOT=0.5nm

SiO2 interfacial layer inserted or re-grown for- recovery of degraded mobility- interface state, reliability (TDDB, BTI), etc.SiO2-IL free structure (direct contact of high-k/Si)

is required for EOT=0.5nm

Hf based oxide

EOT scaling is expected down to 0.5 nm in ITRS

80

1837184018431846Binding energy (eV)

Inte

nsity

(a.u

)

Si sub.

Hf SilicateSiO2

500 oC

1837184018431846Binding energy (eV)

Inte

nsity

(a.u

)

Si sub.

Hf SilicateSiO2

500 oC

SiOx-IL

HfO2

W

1 nm

k=4

k=16

SiOx-IL growth at HfO2/Si Interface

HfO2 + Si + O2→ HfO2 + Si + 2O*→HfO2+SiO2

Phase separator

SiOx-IL is formed after annealingOxygen control is required for optimizing the reaction

Oxygen supplied from W gate electrode

XPS Si1s spectrum

D.J.Lichtenwalner, Tans. ECS 11, 319

TEM image 500 oC 30min

H. Shimizu, JJAP, 44, pp. 6131

81

La-Silicate Reaction at La2O3/Si

La2O3

La-silicate

W

500 oC, 30 min

1 nm

k=8~14

k=23

1837184018431846Binding energy (eV)

Inte

nsity

(a.u

)

as depo.

300 oC

La-silicate

Si sub.

500 oC

1837184018431846Binding energy (eV)

Inte

nsity

(a.u

)

as depo.

300 oC

La-silicate

Si sub.

500 oC

La2O3 + Si + nO2→ La2SiO5, La2Si2O7,

La9.33Si6O26, La10(SiO4)6O3, etc.

La2O3 can achieve direct contact of high-k/Si

XPS Si1s spectraTEM image

Direct contact high-k/Si is possible

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

0 0.5 1 1.5 2 2.5 3

EOT ( nm )

Cur

rent

den

sity

( A

/cm

2 )Al2O3HfAlO(N)HfO2HfSiO(N)HfTaOLa2O3Nd2O3Pr2O3PrSiOPrTiOSiON/SiNSm2O3SrTiO3Ta2O5TiO2ZrO2(N)ZrSiOZrAlO(N)

Gate Leakage vs EOT, (Vg=|1|V)

La2O3

HfO2

82

83

Quantum Effect in Gate Stack

Si sub.

High-k

Gate

Gate oxidecapacitance

Charge layercapacitance

Inversion layer capacitance

Poly-Si(1020cm-3): 0.3 nmMetal : 0.1 nm

0.5 ~ 0.6 nm

High-k (EOT)

metal

channel

A question if the performance improvement can be obtained with EOT<0.5nm

Thickness shown in EOT

Total parasitic capacitance ~ 0.6nm of EOT

K. Natori, SSDM (2005)

S. Takagi, TED, 46. pp.1446 (1999)

Is EOT<0.5nm achievable?

depending on Eeff

EOT = 0.48 nm

Transistor with La2O3 gate insulator

Our results

84

85

Electrical Characterization of thin La2O3 MOSFET EOT<0.5nm

86

EOT<0.5nm with Gain in Drive Current

14% of Id increase is observed even at saturation region

EOT below 0.4nm is still useful for scaling

0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1

Dra

in c

urre

nt (m

A) 3.5

2

1

0

3

(a) EOT=0.37nm (b) EOT=0.43nm (c) EOT=0.48nm

W/L=2.5/50µmPMA 300oC (30min)

Vth=-0.04V Vth=-0.03V Vth=-0.02V

14%up4%up

0 0.2 0.4 0.6 0.8 1Drain voltage (V)

0 0.2 0.4 0.6 0.8 1Drain voltage (V)

0 0.2 0.4 0.6 0.8 1Drain voltage (V)

compensation regioninsufficient

W/L=50/2.5µm

87

Mobility concerns

88

W/La2O3/nFET, 500oC anneal

Electrical characteristics of W/La2O3 nFET annealed at 500 oC

0.0E+00

5.0E-05

1.0E-04

1.5E-04

2.0E-04

2.5E-04

3.0E-04

3.5E-04

4.0E-04

-0.8 -0.4 0.0 0.4 0.8 1.2 1.61.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

0.0E+00

1.0E-03

2.0E-03

3.0E-03

4.0E-03

5.0E-03

6.0E-03

0 0.2 0.4 0.6 0.8 1

00.20.40.60.811.2

Ids

(A)

Vd (V) Vg (V)

Ids

(A)

EOT=1.26 nmVth=-0.08 VSS=66.4mV/dec

0

0.5

1

1.5

2

2.5

-2.5 -1.5 -0.5 0.5 1.5

Cgc

, Cgb

(µF/

cm2 )

Hysteresisin Cgb

CgcCgb

Vg (V)

Split-CV

0

50100

150200

250

300350

400

0 0.2 0.4 0.6 0.8 1Eeff(MV/cm)

µ eff(

cm2 /V

s)

universal

Improvement in electrical characteristicsSS=66mV/dec, µeff=300cm2/Vs

EOT grows from 0.5 to 1.3nm

L/W=2.5/50µm

89

Schematic illustration of µeff reduction at small EOT

metal

Si sub.

EOTlim

density defects

effectivedistance

interface trap generation

high-kVo defect

metal defect metal

Vo

EOTlim

EOT

µeff

Spatial distribution of metal gate induced defects approaches to high-k/Si interface with small EOT

Some of the defects generates interfacial states

90

µeff of W/La2O3 and W/HfO2 nFET on EOT

W/La2O3 exhibits higher µeff than W/HfO2µeff start degrades below EOT=1.4nm

W/HfO2

µ eff

(cm

2 /Vs)

EOT (nm)

500 oC annealed

0.4 1.0 1.6

350

250

50

150

100

200

300

0W/La2O3 @300oC

W/La2O3Open: peak mobilityFill: 0.8MV/cm

EOT=0.5nm

1.41.20.80.6

500 oC annealed

91

FET characteristics of W/La2O3 on EOT

All characteristics start to degrade or shift below EOT=1.4nm

Nfix=7x1012 cm-2

Aggressive Nfix generationat EOT<1.2nm

-1.4-1.2

-1-0.8-0.6-0.4-0.2

00.2

EOT (nm)

W/Lg=50µm/2.5µm

1011

1012

Dit

(eV-

1 cm

-2)

507090

110130150170

S.S

(mV/

dec)

V fb,

V th

(V)

Vd=50mV

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2

CP@1MHz

Si sub.

metal

Nfix and Dit

92

Vfb

(V)

-0.5-0.4-0.3-0.2-0.1

00.10.2

0.8 1.0 1.2 1.4 1.6 1.8 2.0

w/ Mg

w/o Mg

PMA500oC

EOT (nm)

W

Si

La

W

Si 2nm

a.u.

Mg

TEM EDX

Gate Metal Induced Defects Compensation

Suppression of aggressive shift in Vfb

Metal GateMgO

La2O3Si

93

µ eff( c

m2 /V

s)

050

100150200250300350

0 0.2 0.4 0.6 0.8 1.0

w/ Mg (EOT=1.09nm)

w/o Mg (EOT=1.04nm)

universalµ ef

f( c

m2 /V

s)

050

100150200250300350

0 0.2 0.4 0.6 0.8 1.0

w/ Mg (EOT=1.09nm)

w/o Mg (EOT=1.04nm)

universal

PMA500oC

Mobility Improvement with Mg Incorporation

Recovery of µeff mainly at low Eeff

94

Material selection against EOT growth

1. metal selection2. high-k selection

95

La-silicatereaction

30min in F.G.

183718391841184318451847Binding energy [eV]

Nor

mal

ized

Inte

nsity

[a.u

.]

La-silicate

SiO2

Bulk Si

PMA700oCPMA500oCPMA300oCw/o annealing

PMA700oCPMA500oCPMA300oCw/o annealing

PMA700oCPMA500oCPMA300oCw/o annealing

La-silicate

EOT growth of W/La2O3on annealing temperature

Silicate reaction further proceeds with the annealing temperature

XPS Si1s spectrum

La2O3 + Si + nO2→ La2SiO5, La2Si2O7,

La9.33Si6O26, La10(SiO4)6O3, etc.

96

0

0.2

0.4

0.6

0.8

1

1.2

no interfacereaction

500as depo. 300

EOT

(nm

)

Annealing temperature (oC)

W/La2O3

TaSi2/W/La2O3

silicateformation

0.0

1.0

2.0

3.0

4.0

5.0

-0.5 0 0.5 1 1.5Gate voltage (V)C

apac

itanc

e de

nsity

(µF/

cm2 )

500oC 30minEOT=0.50nm

TaSi2/W/La2O3

as depo.EOT=0.49nm

0.0

1.0

2.0

3.0

4.0

5.0

-0.5 0 0.5 1 1.5Gate voltage (V)C

apac

itanc

e de

nsity

(µF/

cm2 )

500oC 30minEOT=0.50nm

TaSi2/W/La2O3

as depo.EOT=0.49nm

Suppression of Silicate Reaction

Oxygen control is the key technology in achieving small EOT with high temperature annealing

Si

La2O3

W(5nm)TaSi2

Oxygen blockO

Limited silicate reaction

Barrier for Ta diffusion

La2O3 + Si + nO2→ La2SiO5, La2Si2O7,

La9.33Si6O26, La10(SiO4)6O3, etc.

30min

97

SiRE silicate

La2O3

tungsten

La-silicateCe-silicatePr-silicate

with and w/o SrO

Leakage current suppression

Cap effect of SrO

Selection of rare earth silicate for interface layerFind out the effect of SrO capping

98

0

0.5

1

1.5

40% down

50% down

15% down

EOT

(nm

)

with SrO cappingw/o SrO cappingLa2O3(1nm) on RE-silicate

La-silicate Ce-silicate Pr-silicate

La2O3

RE-silicate

SrO Diffusion of Sr to enhance the dielectric constant of RE-silicate

500 oC anneal (30min)

SrO capping for achieving small EOT

0.5nm EOT can be achieved with Ce-silicatecapped with SrO which enhances the k-value

99

0 0.001 0.002 0.003 0.004 0.005

1nm

W Si

0 1 2 3 4 (nm)

Cou

nt (a

. u.)

SiCeSr

EDX Analysis of the Distribution of Sr

Sr is diffused into Ce-silicate and possibly down to Si interface

100

1.00E-01

1.00E+00

1.00E+01

1.00E+02

1.00E+03

1.00E+04

0.3 0.5 0.7 0.9

EOT (nm)0.5 0.7 0.9

10-1

0.3

100

101

102

103

104

J g@

Vg=

1 V

(A/c

m2 )

La2O3/Ce-Silicate

La2O3/La-silicateLa2O3/Ce-SilicateLa2O3/Pr-silicate

La2O3/La-silicateLa2O3/Ce-SilicateLa2O3/Pr-silicate

Ref [4]

Open : w/o SrO capClose : w/ SrO cap

SrO(1.5 nm)

SrO(1.0 nm)

SrO effect on Current Density

Further EOT scaling is possible

101

A guideline for material selection: direct contact of high-k with Si structure