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Future Works in LLVM Register Allocation 1
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Page 1: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Future Works in LLVM Register Allocation

1

Page 2: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Talk Overview

1. Introduction

2. Upcoming Changes

3. PBQP

2

Page 3: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Register Allocation in LLVM

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

3

Page 4: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

Lower PHI-instructions to copies

Register Allocation in LLVM

4

Page 5: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

PHI Lowering

BB1: %x1 = .

BB3:%x3 = phi [%x1, BB1], [%x2, BB2]

BB2: %x2 = .

5

Page 6: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

PHI Lowering

BB1: %x1 = .

BB3:%x3 = %xP

BB2: %x2 = .

6

Page 7: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

PHI Lowering

BB1: %x1 = . %xP = %x1

BB3:%x3 = %xP

BB2: %x2 = . %xP = %x2

7

Page 8: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

Lower PHI-instructions to copies

Register Allocation in LLVM

8

Page 9: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

Register Allocation in LLVM

Lower Three-Address Instructions

9

Page 10: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Two-Address Instructions

10

Page 11: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Two-Address Instructions

x3 = x2 + x1

10

Page 12: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Two-Address Instructions

x3 = x2 + x1

x3 = x2x3 += x1

10

Page 13: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

Register Allocation in LLVM

Lower three-address instructions

11

Page 14: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Register Allocation in LLVM

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

Construct live intervals

12

Page 15: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Live Intervals

BB:%x1 = ...

.

.

.%x2 = %x1

.

.

. ... = %x2

13

Page 16: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Live Intervals

BB:%x1 = ...

.

.

.%x2 = %x1

.

.

. ... = %x2

%x1

13

Page 17: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Live Intervals

BB:%x1 = ...

.

.

.%x2 = %x1

.

.

. ... = %x2

%x1 %x2

13

Page 18: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Register Allocation in LLVM

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

Construct Live Intervals

14

Page 19: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Register Allocation in LLVM

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

Aggressively eliminate copies

15

Page 20: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

BB:%x1 = ...

.

.

.%x2 = %x1

.

.

. ... = %x2

Coalescing

%x1 %x2

16

Page 21: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

BB:%x1 = ...

.

.

.

.

.

. ... = %x1

Coalescing

%x1

16

Page 22: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Register Allocation in LLVM

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

Aggressively eliminate copies

17

Page 23: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Register Allocation in LLVM

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

Compute register assignment

18

Page 24: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Register Allocation in LLVM

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

Apply register assignment

19

Page 25: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Register Allocation in LLVM

PHI Elimination Two-Address

Coalescing Allocator

Liveness

Rewriter

20

Page 26: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Improvements

• New and better optimizations

• New allocators

• Cleaner infrastructure

21

Page 27: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

1. Optimizations

22

Page 28: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Rematerialization

23

Page 29: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

. // stuff

... =

. // more stuff

... =

<expr>

vr1

vr1

vr1

Rematerialization

=

23

Page 30: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

. // stuff

... =

. // more stuff

... =

<expr>

vr1

vr1

vr1

Rematerialization

=

23

Page 31: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

. // stuff

... =

. // more stuff

... =

<expr>

vr1

vr1

vr1

[M]

[M]

[M]

Rematerialization

=

23

Page 32: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

. // stuff

... =

. // more stuff

... =

<expr>

vr1

vr1

vr1

Rematerialization

=

23

Page 33: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

. // stuff

... =

. // more stuff

... =

<expr>

<expr>

Rematerialization

23

Page 34: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Splitting

24

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Splitting

24

Page 36: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Splitting

24

Page 37: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Splitting

24

Page 38: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Splitting

Spill

24

Page 39: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Spills introducedin to other loops

Splitting

Spill

24

Page 40: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Splitting

Register

Spill

24

Page 41: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

2. New Allocators

25

Page 42: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

New Allocators

26

Page 43: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

New Allocators

• “Linear Scan” is not, in fact, linear

26

Page 44: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

New Allocators

• “Linear Scan” is not, in fact, linear

• We want something faster

26

Page 45: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

New Allocators

• “Linear Scan” is not, in fact, linear

• We want something faster

• Priority coloring?

26

Page 46: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

New Allocators

• “Linear Scan” is not, in fact, linear

• We want something faster

• Priority coloring?

• Linear Scan?

26

Page 47: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

New Allocators

• “Linear Scan” is not, in fact, linear

• We want something faster

• Priority coloring?

• Linear Scan?

• Need to tidy the infrastructure

26

Page 48: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

3. Cleaner Infrastructure

27

Page 49: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Currently...

28

Page 50: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Currently...

Liveness Analysis

28

Page 51: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Currently...

Liveness Analysis Allocator

28

Page 52: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Currently...

Liveness Analysis Allocator

VirtualRegister Map

28

Page 53: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Currently...

Liveness Analysis Allocator

VirtualRegister Map

28

Page 54: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Currently...

Liveness Analysis Allocator

VirtualRegister Map

28

Page 55: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Currently...

Liveness Analysis Allocator

VirtualRegister Map

28

Page 56: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Currently...

Liveness Analysis Allocator Rewriter

VirtualRegister Map

28

Page 57: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Rewrite In Place

29

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Rewrite In Place

Liveness Analysis

29

Page 59: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Rewrite In Place

Liveness Analysis

Live Intervals

29

Page 60: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Rewrite In Place

Liveness Analysis Allocator

Live Intervals

29

Page 61: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Rewrite In Place

Liveness Analysis Allocator

Live Intervals

Modify code in-place

29

Page 62: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Rewrite In Place

Liveness Analysis Allocator

Live Intervals

Modify code in-place

Live intervalskept up-to-date

29

Page 63: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Rewrite In Place

Liveness Analysis Allocator

Live IntervalsLive intervals remain valid post-alloc

Modify code in-place

Live intervalskept up-to-date

29

Page 64: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Improvements

• New and better optimizations

• New allocators

• Cleaner infrastructure

30

Page 65: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Upcoming Changes

31

Page 66: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Upcoming Changes

• Live index renumbering

• Improved splitting

• Better def/kill tracking for values

32

Page 67: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Live Indexes

33

Page 68: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

BB: . . %x2 = %x1 add %x3, %x2 . .

Live Indexes

33

Page 69: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

BB: . . %x2 = %x1 add %x3, %x2 . .

Live Indexes

123456

33

Page 70: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

%x3 = ...

BB: . . %x2 = %x1

add %x3, %x2 . .

Live Indexes

123

456

33

Page 71: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

%x3 = ...

BB: . . %x2 = %x1

add %x3, %x2 . .

Live Indexes

123

456

?

33

Page 72: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

BB: . . %x2 = %x1 %x3 = ... add %x3, %x2 . .

Live Indexes

P1P2P3

P4P5P6

34

Page 73: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

BB: . . %x2 = %x1 %x3 = ... add %x3, %x2 . .

Live Indexes

P1P2P3

P4P5P6

P1 ≺ P2 ≺ P3 ≺ P4 ≺ P5 ≺ P634

Page 74: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

BB: . . %x2 = %x1 %x3 = ... add %x3, %x2 . .

Live Indexes

P1P2P3

P4P5P6

P7

P1 ≺ P2 ≺ P3 ≺ P4 ≺ P5 ≺ P634

Page 75: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

BB: . . %x2 = %x1 %x3 = ... add %x3, %x2 . .

Live Indexes

P1P2P3

P4P5P6

P7

P1 ≺ P2 ≺ P3 ≺ P4 ≺ P5 ≺ P6P7 ≺34

Page 76: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Live Indexes

• unsigned ➙ LiveIndex

• Index Renumbering

✓⌚

35

Page 77: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Improved Splitting

36

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Improved Splitting

• Break multi-value intervals into component values.

36

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Improved Splitting

• Break multi-value intervals into component values.

• Each value gets a 2nd chance at allocation.

36

Page 80: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Improved Splitting

• Break multi-value intervals into component values.

• Each value gets a 2nd chance at allocation.

• ... but not a 3rd.

36

Page 81: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Improved Splitting

• Break multi-value intervals into component values.

• Each value gets a 2nd chance at allocation.

• ... but not a 3rd.

• 13% reduction in static memory references on test case (a pathological SSE kernel).

36

Page 82: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Better Def/Kill Tracking

37

Page 83: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Better Def/Kill Tracking

• Defined by a PHI - Track the def block.

For Values

37

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Better Def/Kill Tracking

• Defined by a PHI - Track the def block.

• Killed by a PHI - Track the appropriate predecessor.

For Values

37

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Future Work

• Better value def/kill tracking

• LiveIndex renumbering

• Improved splitting

• Rewrite-in-place

• New allocators

⌚⌚⌚⌚

38

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PBQP

39

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PBQP

• Discrete optimization problems

• NP-complete

• Subclass solvable in linear time

Partitioned Boolean Quadratic Problems

40

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Irregular Architectures

• Multiple register classes.

• Register aliasing.

• Register pairing.

• ...

41

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PBQP Example

42

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PBQP Example

ZX

Y

42

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PBQP Example

901

436

702

ZX

Y

42

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PBQP Example

901

436

702

ZX

Y

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

Y

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

Y

Solution [3,2,1]:

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

Y

Solution [3,2,1]:

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

Y

Solution [3,2,1]:

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

Y

Solution [3,2,1]:

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

YNode Costs: 6+0+9 = 15

Solution [3,2,1]:

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

YNode Costs: 6+0+9 = 15

Solution [3,2,1]:

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

YNode Costs: 6+0+9 = 15

Solution [3,2,1]:

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

YNode Costs: 6+0+9 = 15

Solution [3,2,1]:

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

YNode Costs: 6+0+9 = 15Edge Costs: 2+6+9 = 17

Solution [3,2,1]:

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

YNode Costs: 6+0+9 = 15Edge Costs: 2+6+9 = 17

Total: 32

Solution [3,2,1]:

42

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PBQP Example

901

436

702

3 8 18 5 35 2 7

5 2 26 7 31 4 8

1 9 34 5 39 7 6

ZX

YNode Costs: 6+0+9 = 15Edge Costs: 2+6+9 = 17

Total: 32

Solution [3,2,1]:

Solution [1,2,3]: 19

42

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PBQP Example

900

400

700

0 0 00 ∞ 00 0 ∞

0 0 00 ∞ 00 0 ∞

0 0 00 ∞ 00 0 ∞

ZX

Y

Nodes represent virtual registers.

Options reflect storage locations.

Option costs:

Typically zero cost for registers,spill cost estimate for stack slot.

Edge costs:

Depends on the constraint.

For Register Allocation:

43

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Example 1

X Y

Interference on a Regular Architecture

44

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Example 1

400

X Y

Interference on a Regular Architecture

Sp

r0

r1

44

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Example 1

400

700

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

44

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Example 1

400

700

0 0 00 ∞ 00 0 ∞

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

44

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Example 1

400

700

0 0 00 ∞ 00 0 ∞

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

44

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Example 1

400

700

0 0 00 ∞ 00 0 ∞

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

Cost (Sp, Sp) = 1144

Page 112: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Example 1

400

700

0 0 00 ∞ 00 0 ∞

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

Cost (r0, Sp) = 745

Page 113: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Example 1

400

700

0 0 00 ∞ 00 0 ∞

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

Cost (Sp, r0) = 446

Page 114: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Example 1

400

700

0 0 00 ∞ 00 0 ∞

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

Cost (r0, r1) = 047

Page 115: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Example 1

400

700

0 0 00 ∞ 00 0 ∞

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

Cost (r0, r1) = 0 ✓47

Page 116: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

0 0 00 ∞ 00 0 ∞

Example 1

400

700

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

Cost (r0, r1) = 0 ✓48

Page 117: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Example 1

400

700

0 0 00 ∞ 00 0 ∞

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

Cost (r0, r1) = 0 ✓49

Page 118: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Example 1

400

700

0 0 00 ∞ 00 0 ∞

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

Cost (r0, r0) = ∞50

Page 119: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Example 1

400

700

0 0 00 ∞ 00 0 ∞

X Y

Interference on a Regular Architecture

Sp

r0

r1

Sp

r0

r1

Cost (r0, r0) = ✗∞50

Page 120: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Example 1

0 0 00 ∞ 00 0 ∞

Interference on a Regular Architecture

50

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Example 2

0 0 0 0 00 ∞ ∞ 0 00 0 0 ∞ 0

Interference on an Irregular Architecture

Sp

AX

BX

Sp AL AH BL CL

51

Page 122: Future Works in LLVM Register Allocationllvm.org/devmtg/2009-10/RegisterAllocationFutureWorks.pdf0 -c 0 0 0 -c Coalescing Sp AX BX Sp AX BX 52. Example 4 Register Pairing (R i, R i+1)

Example 3

0 0 00 -c 00 0 -c

Coalescing

Sp

AX

BX

Sp AX BX

52

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Example 4

Register Pairing (Ri, Ri+1)

Sp

s0

s1

Sp s0 s1 s2 s3

s2

0 0 0 0 00 ∞ 0 ∞ ∞0 ∞ ∞ 0 ∞0 ∞ ∞ ∞ 0

53

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The PBQP Allocator

solution = solve pbqpsolution -> allocation

regalloc -> pbqp

54

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The PBQP Allocator

solution = solve pbqpsolution -> allocation

regalloc -> pbqp

54

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The PBQP Allocator

solution = solve pbqpsolution -> allocation

regalloc -> pbqp

54

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The PBQP Allocator

llvm/lib/CodeGen/RegAllocPBQP.cpp

solution = solve pbqpsolution -> allocation

regalloc -> pbqp

54

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How does it work?

Solver uses a graph reduction algorithm.

Reduce problem to the empty graph with reduction rules, then reconstruct it.

55

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PBQP

56

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PBQP

PROS CONS

• Ideal for Irregularity

• Very Simple

• Reasonable quality

• Slooooooow

56

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PBQP

PROS CONS

• Ideal for Irregularity

• Very Simple

• Reasonable quality

• Slooooooow

56

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PBQP

PROS CONS

• Ideal for Irregularity

• Very Simple

• Reasonable quality

• Slooooooow

• Perfect opportunity

for a coffee

56

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57

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• Improved Optimizations.

• New Allocators.

• Cleaner Architecture.

• PBQP.

57

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the end.

58


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